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marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ddr/ddr2spax.vhd | 1 | 8,952 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spax
-- File: ddr2spax.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: DDR2 memory controller with asynch AHB interface
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
library techmap;
use techmap.gencomp.ddr2phy_has_datavalid;
use techmap.gencomp.ddr2phy_ptctrl;
entity ddr2spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
-- dqsgating : integer := 0;
nosync : integer := 0;
dqsgating : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
hwidth : in std_ulogic
);
end ddr2spax;
architecture rtl of ddr2spax is
constant REVISION : integer := 1;
constant ramwt: integer := 0;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
function pick(choice: boolean; t,f: integer) return integer is
begin
if choice then return t; else return f; end if;
end;
constant xahbw: integer := pick(ft/=0 and ahbbits<64, 64, ahbbits);
constant l2ahbw: integer := log2(xahbw);
-- For non-FT, write buffer has room for two write bursts and is addressable
-- down to 32-bit level on write (AHB) side.
-- For FT, the write buffer has room for one write burst and is addressable
-- down to 64-bit level on write side.
-- Write buffer dimensions
constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw;
constant wbuf_rabits_r: integer := wbuf_rabits_s-FT;
constant wbuf_rdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits);
constant wbuf_wabits: integer := pick(ft/=0, l2blen-6, 1+l2blen-5);
constant wbuf_wdbits: integer := pick(ft/=0, xahbw+xahbw/2, xahbw);
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw;
constant rbuf_rdbits: integer := wbuf_wdbits;
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits);
signal request : ddr_request_type;
signal start_tog : std_logic;
signal response : ddr_response_type;
signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0);
signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0);
signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0);
signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0);
signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0);
signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0);
signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0);
signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0);
signal wbwrite,wbwritebig,rbwrite: std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of rbwdata : signal is true;
attribute syn_keep of rbwdata : signal is true;
attribute syn_preserve of rbwdata : signal is true;
signal vcc: std_ulogic;
signal sdox: ddrctrl_out_type;
signal ce: std_logic;
begin
vcc <= '1';
gft0: if ft=0 generate
ahbc : ddr2spax_ahb
generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
nosync => nosync, burstlen => burstlen, ahbbits => xahbw, revision => revision,
ddrbits => ddrbits, regarea => 0)
port map (ahb_rst, clk_ahb, ahbsi, ahbso, request, start_tog, response,
wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, hwidth, FTFE_BEID_DDR2);
ce <= '0';
end generate;
gft1: if ft/=0 generate
ftc: ft_ddr2spax_ahb
generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
nosync => nosync, burstlen => burstlen, ahbbits => xahbw, bufbits => xahbw+xahbw/2,
ddrbits => ddrbits, hwidthen => hwidthen, devid => GAISLER_DDR2SP, revision => revision)
port map (ahb_rst, clk_ahb, ahbsi, ahbso, ce, request, start_tog, response,
wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, hwidth, '0', open, open, FTFE_BEID_DDR2);
end generate;
ddrc : ddr2spax_ddr
generic map (ddrbits => ddrbits,
pwron => pwron, MHz => MHz, TRFC => TRFC, col => col, Mbyte => Mbyte,
readdly => readdly, odten => odten, octen => octen, dqsgating => dqsgating,
nosync => nosync, eightbanks => eightbanks, dqsse => dqsse, burstlen => burstlen,
chkbits => ft*ddrbits/2, bigmem => bigmem, raspipe => raspipe,
hwidthen => hwidthen, phytech => phytech, hasdqvalid => ddr2phy_has_datavalid(phytech),
rstdel => rstdel, phyptctrl => ddr2phy_ptctrl(phytech), scantest => scantest,
ddr_syncrst => ddr_syncrst)
port map (ddr_rst, clk_ddr, request, start_tog, response, sdi, sdox,
wbraddr, wbrdata, rbwaddr, rbwdata, rbwrite, hwidth,
'0', ddr_request_none, open, ahbsi.testen, ahbsi.testrst, ahbsi.testoen);
sdoproc: process(sdox,ce)
variable o: ddrctrl_out_type;
begin
o := sdox;
o.ce := ce;
sdo <= o;
end process;
wbuf: ddr2buf
generic map (tech => memtech, wabits => wbuf_wabits, wdbits => wbuf_wdbits,
rabits => wbuf_rabits_r, rdbits => wbuf_rdbits,
sepclk => 1, wrfst => ramwt)
port map ( rclk => clk_ddr, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0),
dataout => wbrdata, wclk => clk_ahb, write => wbwrite,
writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata);
rbuf: ddr2buf
generic map (tech => memtech, wabits => rbuf_wabits, wdbits => rbuf_wdbits,
rabits => rbuf_rabits, rdbits => rbuf_rdbits,
sepclk => 1, wrfst => ramwt)
port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr,
dataout => rbrdata,
wclk => clk_ddr, write => rbwrite,
writebig => '0', waddress => rbwaddr, datain => rbwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddr2spa: DDR2 controller rev " &
tost(REVISION) & ", " & tost(ddrbits) & " bit width, " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| gpl-2.0 | 8631380f4f74c7008dbfec7e048e9138 | 0.599531 | 3.893867 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_PaintMask_32_0_1080_1920_s.vhd | 2 | 24,811 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_PaintMask_32_0_1080_1920_s is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_mask_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_mask_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_mask_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_mask_data_stream_V_empty_n : IN STD_LOGIC;
p_mask_data_stream_V_read : OUT STD_LOGIC;
p_dst_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_dst_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of image_filter_PaintMask_32_0_1080_1920_s is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_st6_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_23 : BOOLEAN;
signal p_4_reg_194 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_bdd_71 : BOOLEAN;
signal exitcond4_fu_210_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_83 : BOOLEAN;
signal i_V_fu_215_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_280 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond_fu_225_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_reg_285 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_94 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_sig_bdd_111 : BOOLEAN;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppstg_exitcond_reg_285_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_125 : BOOLEAN;
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal j_V_fu_230_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_39_fu_242_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_39_reg_294 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_40_fu_250_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_40_reg_299 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_41_fu_258_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_41_reg_304 : STD_LOGIC_VECTOR (7 downto 0);
signal p_s_reg_183 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_st6_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_158 : BOOLEAN;
signal p_cast_fu_206_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_4_cast_fu_221_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_37_fu_236_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond4_fu_210_p2 = ap_const_lv1_0)))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_fu_225_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond4_fu_210_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and (exitcond_fu_225_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond4_fu_210_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_fu_225_p2 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond4_fu_210_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- p_4_reg_194 assign process. --
p_4_reg_194_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and (exitcond_fu_225_p2 = ap_const_lv1_0))) then
p_4_reg_194 <= j_V_fu_230_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond4_fu_210_p2 = ap_const_lv1_0))) then
p_4_reg_194 <= ap_const_lv11_0;
end if;
end if;
end process;
-- p_s_reg_183 assign process. --
p_s_reg_183_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_71))) then
p_s_reg_183 <= ap_const_lv11_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_3)) then
p_s_reg_183 <= i_V_reg_280;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
ap_reg_ppstg_exitcond_reg_285_pp0_it1 <= exitcond_reg_285;
exitcond_reg_285 <= exitcond_fu_225_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
i_V_reg_280 <= i_V_fu_215_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
tmp_39_reg_294 <= tmp_39_fu_242_p3;
tmp_40_reg_299 <= tmp_40_fu_250_p3;
tmp_41_reg_304 <= tmp_41_fu_258_p3;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_71, exitcond4_fu_210_p2, exitcond_fu_225_p2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_71)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((exitcond4_fu_210_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_pp0_stg0_fsm_2 =>
if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_fu_225_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_fu_225_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
ap_NS_fsm <= ap_ST_st6_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_st6_fsm_3 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, exitcond4_fu_210_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond4_fu_210_p2 = ap_const_lv1_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(exitcond4_fu_210_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond4_fu_210_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_111 assign process. --
ap_sig_bdd_111_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_mask_data_stream_V_empty_n, exitcond_reg_285)
begin
ap_sig_bdd_111 <= (((p_src_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_reg_285 = ap_const_lv1_0)) or ((exitcond_reg_285 = ap_const_lv1_0) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_reg_285 = ap_const_lv1_0) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_reg_285 = ap_const_lv1_0) and (p_mask_data_stream_V_empty_n = ap_const_logic_0)));
end process;
-- ap_sig_bdd_125 assign process. --
ap_sig_bdd_125_assign_proc : process(p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_reg_ppstg_exitcond_reg_285_pp0_it1)
begin
ap_sig_bdd_125 <= (((p_dst_data_stream_0_V_full_n = ap_const_logic_0) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1)) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)));
end process;
-- ap_sig_bdd_158 assign process. --
ap_sig_bdd_158_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_158 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_23 assign process. --
ap_sig_bdd_23_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_71 assign process. --
ap_sig_bdd_71_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_71 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_83 assign process. --
ap_sig_bdd_83_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_83 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_94 assign process. --
ap_sig_bdd_94_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_94 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_94)
begin
if (ap_sig_bdd_94) then
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_83)
begin
if (ap_sig_bdd_83) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_3 assign process. --
ap_sig_cseq_ST_st6_fsm_3_assign_proc : process(ap_sig_bdd_158)
begin
if (ap_sig_bdd_158) then
ap_sig_cseq_ST_st6_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_3 <= ap_const_logic_0;
end if;
end process;
exitcond4_fu_210_p2 <= "1" when (p_cast_fu_206_p1 = p_dst_rows_V_read) else "0";
exitcond_fu_225_p2 <= "1" when (p_4_cast_fu_221_p1 = p_dst_cols_V_read) else "0";
i_V_fu_215_p2 <= std_logic_vector(unsigned(p_s_reg_183) + unsigned(ap_const_lv11_1));
j_V_fu_230_p2 <= std_logic_vector(unsigned(p_4_reg_194) + unsigned(ap_const_lv11_1));
p_4_cast_fu_221_p1 <= std_logic_vector(resize(unsigned(p_4_reg_194),12));
p_cast_fu_206_p1 <= std_logic_vector(resize(unsigned(p_s_reg_183),12));
p_dst_data_stream_0_V_din <= tmp_39_reg_294;
-- p_dst_data_stream_0_V_write assign process. --
p_dst_data_stream_0_V_write_assign_proc : process(ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_reg_285_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
p_dst_data_stream_0_V_write <= ap_const_logic_1;
else
p_dst_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_1_V_din <= tmp_40_reg_299;
-- p_dst_data_stream_1_V_write assign process. --
p_dst_data_stream_1_V_write_assign_proc : process(ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_reg_285_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
p_dst_data_stream_1_V_write <= ap_const_logic_1;
else
p_dst_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_2_V_din <= tmp_41_reg_304;
-- p_dst_data_stream_2_V_write assign process. --
p_dst_data_stream_2_V_write_assign_proc : process(ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_reg_285_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
p_dst_data_stream_2_V_write <= ap_const_logic_1;
else
p_dst_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
-- p_mask_data_stream_V_read assign process. --
p_mask_data_stream_V_read_assign_proc : process(exitcond_reg_285, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
p_mask_data_stream_V_read <= ap_const_logic_1;
else
p_mask_data_stream_V_read <= ap_const_logic_0;
end if;
end process;
-- p_src_data_stream_0_V_read assign process. --
p_src_data_stream_0_V_read_assign_proc : process(exitcond_reg_285, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
p_src_data_stream_0_V_read <= ap_const_logic_1;
else
p_src_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
-- p_src_data_stream_1_V_read assign process. --
p_src_data_stream_1_V_read_assign_proc : process(exitcond_reg_285, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
p_src_data_stream_1_V_read <= ap_const_logic_1;
else
p_src_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
-- p_src_data_stream_2_V_read assign process. --
p_src_data_stream_2_V_read_assign_proc : process(exitcond_reg_285, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then
p_src_data_stream_2_V_read <= ap_const_logic_1;
else
p_src_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
tmp_37_fu_236_p2 <= "1" when (p_mask_data_stream_V_dout = ap_const_lv8_0) else "0";
tmp_39_fu_242_p3 <=
p_src_data_stream_0_V_dout when (tmp_37_fu_236_p2(0) = '1') else
ap_const_lv8_FF;
tmp_40_fu_250_p3 <=
p_src_data_stream_1_V_dout when (tmp_37_fu_236_p2(0) = '1') else
ap_const_lv8_0;
tmp_41_fu_258_p3 <=
p_src_data_stream_2_V_dout when (tmp_37_fu_236_p2(0) = '1') else
ap_const_lv8_0;
end behav;
| gpl-3.0 | 09aa2528412bd867f2e26924ad26401d | 0.589618 | 2.652732 | false | false | false | false |
IamVNIE/Hardware-Security | Interfaces/UART_Version_3/Uart_working/hex2LED - Copy.vhd | 2 | 892 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Dec2LED is
Port ( CLK: in STD_LOGIC; X : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC_VECTOR (7 downto 0));
end Dec2LED;
architecture Behavioral of Dec2LED is
begin
process (CLK)
begin
case X is
when "0000" => Y <= "11000000";
when "0001" => Y <= "11111001";
when "0010" => Y <= "10100100";
when "0011" => Y <= "10110000";
when "0100" => Y <= "10011001";
when "0101" => Y <= "10010010";
when "0110" => Y <= "10000010";
when "0111" => Y <= "11111000";
when "1000" => Y <= "10000000";
when "1001" => Y <= "10010000";
when "1010" => Y <= "10001000";
when "1011" => Y <= "10000011";
when "1100" => Y <= "11000110";
when "1101" => Y <= "10100001";
when "1110" => Y <= "10000110";
when others => Y <= "10001110";
end case;
end process;
end Behavioral;
| mit | a0ee1fdfb33ffeb3debce43ab38f932b | 0.60426 | 2.915033 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep3c25/config.vhd | 1 | 5,550 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (10);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (8);
constant CFG_DDRSP_RSKEW : integer := (2500);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 9dfa70dde1b0f3908099bb4c7986790a | 0.643063 | 3.66095 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_mm2s_cntrl_strm.vhd | 3 | 21,779 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
library lib_fifo_v1_0;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => CNTRL_FIFO_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty
and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1 : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_dma_v7_1.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
-- C_DEPTH => CNTRL_FIFO_DEPTH ,
-- C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_mm2s_stop_d1 <= '0';
p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1 <= mm2s_stop;
p_mm2s_stop_d1 <= mm2s_stop_reg;
p_mm2s_stop_d2 <= p_mm2s_stop_d1;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
| gpl-3.0 | bfdaa33c68264a55e07eeb409439c4a6 | 0.438863 | 4.364529 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-avnet-3s1500/config.vhd | 1 | 6,387 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- board options
constant CFG_ADS_DAU_MEZZ : integer := 1;
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (3);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000013#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 1;
constant CFG_CANIO : integer := 16#C00#;
constant CFG_CANIRQ : integer := (13);
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 2;
constant CFG_PCIVID : integer := 16#1AC8#;
constant CFG_PCIDID : integer := 16#0054#;
constant CFG_PCIDEPTH : integer := 16;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | c5f6f5ac8f0664d76c9a5bd43044123e | 0.644747 | 3.610514 | false | false | false | false |
CogPy/cog | xUnit/vhdl/somedir/Cents.vhd | 1 | 1,889 | -------------------------------------------------------------------------------
-- Title : Cents
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity Cents is
port (
Clk : in std_logic;
Clr : in std_logic;
Cents_A : in std_logic_vector(3 downto 0);
Cents_B : in std_logic_vector(3 downto 0);
Cents_AB : out std_logic_vector(4 downto 0)
);
end entity Cents;
-------------------------------------------------------------------------------
architecture str of Cents is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal AB : unsigned(Cents_AB'range);
begin -- architecture str
-----------------------------------------------------------------------------
-- Output assignments
-----------------------------------------------------------------------------
Cents_AB <= std_logic_vector(AB);
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
p_addAandB: process (Clk) is
begin -- process p_addAandB
if Clk'event and Clk = '1' then -- rising clock edge
if Clr = '1' then
AB <= to_unsigned(0, AB'length);
else
AB <= resize(unsigned(Cents_A), AB'length) + resize(unsigned(Cents_B), AB'length);
end if;
end if;
end process p_addAandB;
end architecture str;
-------------------------------------------------------------------------------
| lgpl-3.0 | 589f674f3575e10aa715fae99ea149a2 | 0.31657 | 5.830247 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/ctrl_types_pkg.vhd | 1 | 9,750 | --------------------------------------------------------------------------------
--
-- Title : ctrl_types_pkg.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Main types and components
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ctrl_types_pkg is
type data8x8 is array (7 downto 0) of std_logic_vector(7 downto 0);
type data3x8 is array (7 downto 0) of std_logic_vector(2 downto 0);
type array8x1 is array (7 downto 0) of std_logic;
type array8x8 is array (7 downto 0) of array8x1;
type key_data is record
WSAD : std_logic_vector(3 downto 0);
ENTER : std_logic;
SPACE : std_logic;
ESC : std_logic;
kY : std_logic;
kN : std_logic;
end record;
component ctrl_key_decoder is
port(
-- system signals
clk : in std_logic; -- System clock
-- keyboard in:
ps2_clk : in std_logic; -- PS/2 CLK
ps2_data: in std_logic; -- PS/2 DATA
-- keyboard out:
keys_out : out key_data; -- Key data
new_key : out std_logic -- Detect new key
);
end component;
component vga_ctrl640x480 is
port(
clk : in std_logic; -- Pixel clk - DCM should generate 25 MHz freq;
reset : in std_logic; -- Asycnchronous reset
h_sync : out std_logic; -- Horiztonal sync pulse
v_sync : out std_logic; -- Vertical sync pulse
disp : out std_logic; -- Display enable '1'
x_out : out std_logic_vector(9 downto 0); -- x axis
y_out : out std_logic_vector(8 downto 0) -- y axis
);
end component;
component ctrl_game_block is
generic(
constant yend : std_logic_vector(4 downto 0); -- Y end area
constant ystart : std_logic_vector(4 downto 0); -- Y start area
constant xend : std_logic_vector(6 downto 0); -- X end area
constant xstart : std_logic_vector(6 downto 0) -- X start area
);
port(
-- system signals:
clk : in std_logic; -- clock
reset : in std_logic; -- system reset
-- keyboard:
push_keys : in key_data; -- ps/2 keys
-- vga XoY coordinates:
display : in std_logic; -- display enable
x_char : in std_logic_vector(9 downto 0); -- X line: 0:79
y_char : in std_logic_vector(8 downto 0); -- Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0); -- RGB data
leds : out std_logic_vector(8 downto 1) -- 8 LEDs
);
end component;
component rtl_game_int is
port(
-- system signals
reset : in std_logic; -- System reset
clk : in std_logic; -- Pixel CLK ~25 MHz;
-- ps/2 signals
ps2_clk : in std_logic; -- PS/2 CLOCK
ps2_data : in std_logic; -- PS/2 SERIAL DATA
-- vga output signals
h_vga : out std_logic; -- Horizontal
v_vga : out std_logic; -- Vertical
rgb : out std_logic_vector(2 downto 0); -- RBG
-- test leds signals
leds : out std_logic_vector(8 downto 1) -- LEDs
);
end component;
component rtl_ds1302 is
generic (
TD : in time; -- simulation time;
DIV_SCL : in integer -- Clock division for SCL: clk50m/DIV_SCL
);
port(
-- global ports
clk50m : in std_logic; -- System frequency (50 MHz)
rstn : in std_logic; -- '0' - negative reset
-- main interface
enable : in std_logic; -- I2c start (S)
addr_i : in std_logic_vector(7 downto 0); -- Address Tx: 7 bit - always '1', 0 bit - R/W ('0' - write, '1' - read)
data_i : in std_logic_vector(7 downto 0); -- Data Tx
data_o : out std_logic_vector(7 downto 0); -- Data Rx
data_v : out std_logic; -- Valid Rx
ready : out std_logic; -- Ready
-- serial interface
--ds_data : inout std_logic; -- serial data
ds_data_i : in std_logic; -- Serial data input
ds_data_o : out std_logic; -- Serial data output
ds_data_t : out std_logic; -- Serial data enable
ds_clk : out std_logic; -- Serial clock
ds_ena : out std_logic -- Clock enable for i2c
);
end component;
component rtl_lcd1602 is
generic (
TD : in time; -- Simulation time;
DIV_SCL : in integer -- Clock division for SCL: clk50m/DIV_SCL
);
port(
-- global ports
clk50m : in std_logic; -- System frequency (50 MHz)
rstn : in std_logic; -- '0' - negative reset
-- main interface
start : in std_logic; -- Start
data_ena : in std_logic; -- Data enable (S)
data_int : in std_logic_vector(7 downto 0); -- Data Tx
data_sel : in std_logic; -- Select: '0' - data, '1' - command
data_rw : in std_logic; -- Data write: write - '0', read - '1'
lcd_ready : out std_logic; -- Ready for data
lcd_init : out std_logic; -- Lcd initialization complete
-- lcd1602 interface
lcd_dt : out std_logic_vector(7 downto 0); -- Lcd data
lcd_en : out std_logic; -- Lcd clock enable
lcd_rw : out std_logic; -- Lcd r/w: write - '0', read - '1'
lcd_rs : out std_logic -- Lcd set: command - '0', data - '1'
);
end component;
component cl_lcd_data is
generic (
TD : in time -- Simulation time;
);
port(
reset : in std_logic; -- System reset
clk : in std_logic; -- Clock 50 MHz
test_mode : in std_logic; -- select mode: test message or timer message
load_ena : in std_logic; -- Load new data
load_dat : in std_logic_vector(7 downto 0); -- New data;
load_addr : in std_logic_vector(4 downto 0); -- New address;
disp_data : out std_logic_vector(7 downto 0); -- Data to display
disp_ena : out std_logic; -- Enable for data
disp_init : in std_logic; -- Ready for data
disp_rdyt : in std_logic -- Valid pulse for data
);
end component;
component ctrl_leds is
port(
-- system signals:
clk : in std_logic; -- Clock
clk_dv : in std_logic; -- Clock/2
reset : in std_logic; -- System reset
pwm_ena : in std_logic; -- Enable PWM
-- buttons:
cbut : in std_logic_vector(5 downto 1); -- Buttons
-- leds vectors:
led_x : out std_logic_vector(7 downto 0); -- LED X
led_y : out std_logic_vector(7 downto 0) -- LED y
);
end component;
component cl_timer_data is
generic (
TIME_SECS : in integer range 0 to 59:=12; -- Seconds
TIME_MINS : in integer range 0 to 59:=35; -- Minutes
TIME_HRS : in integer range 0 to 23:=17; -- Hours
TIME_DTS : in integer range 0 to 30:=13; -- Dates
TIME_MTHS : in integer range 0 to 11:=07; -- Months
TIME_DAYS : in integer range 0 to 59:=17; -- Days
TIME_YRS : in integer range 0 to 99:=86; -- Years
TD : in time -- simulation time
);
port(
---- Global signals ----
reset : in std_logic; -- asycnchronous reset
clk : in std_logic; -- clock 50 MHz
restart : in std_logic; -- restart timer
---- DS1302 signals ----
addr : out std_logic_vector(7 downto 0); -- address for timer
data_o : out std_logic_vector(7 downto 0); -- input data (to timer)
data_i : in std_logic_vector(7 downto 0); -- output data (from timer)
data_v : in std_logic; -- valid data (from timer)
ready : in std_logic; -- timer is ready for data
enable : out std_logic; -- timer enable
---- LCD1602 signals ----
load_ena : out std_logic; -- enable writing to LCD RAM
load_dat : out std_logic_vector(7 downto 0); -- data to LCD RAM
load_addr : out std_logic_vector(4 downto 0) -- address to LCD RAM
);
end component;
component ctrl_fanout is
generic(
FD_WIDTH : in integer -- data width
);
port(
clk : in std_logic; -- clock
data_in : in std_logic; -- input
data_out : out std_logic_vector(FD_WIDTH-1 downto 0) -- output
);
end component;
end ctrl_types_pkg; | mit | 99e8cc3ce696fd214f53e2543db03a14 | 0.469436 | 3.225273 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/digit/simulation/digit_synth.vhd | 1 | 6,814 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: digit_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY digit_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE digit_synth_ARCH OF digit_synth IS
COMPONENT digit_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: digit_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | 7acbca544a9f1b43fd01694c310e4943 | 0.579689 | 3.810962 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-clock-gate/testbench.vhd | 1 | 19,873 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.jtagtst.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART1 tx data
rxd2 : in std_logic; -- UART1 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic;
can_rxd : in std_logic;
can_stb : out std_logic;
spw_clk : in std_logic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_logic;
tdo : out std_logic
);
end component;
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdog : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal gtx_clk : std_logic := '0';
signal emdc, emdio: std_logic;
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic;
signal can_rxd : std_logic;
signal can_stb : std_logic;
signal spw_clk : std_logic := '0';
signal spw_rxd : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxs : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txd : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txs : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal tck, tms, tdi, tdo : std_logic;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_SD64 : integer := CFG_SDCTRL_SD64 + CFG_MCTRL_SD64;
begin
-- clock and reset
spw_clk <= not spw_clk after 20 ns;
spw_rxd(0) <= spw_txd(0); spw_rxdn(0) <= spw_txdn(0);
spw_rxs(0) <= spw_txs(0); spw_rxsn(0) <= spw_txsn(0);
spw_rxd(1) <= spw_txd(1); spw_rxdn(1) <= spw_txdn(1);
spw_rxs(1) <= spw_txs(1); spw_rxsn(1) <= spw_txsn(1);
spw_rxd(2) <= spw_txd(0); spw_rxdn(2) <= spw_txdn(2);
spw_rxs(2) <= spw_txs(0); spw_rxsn(2) <= spw_txsn(2);
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
--## can_rxd <= '1';
can_rxd <= can_txd; -- CAN LOOP BACK ##
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, sdclk, error, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,
dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, emddis, epwrdwn, ereset, esleep, epause,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd, can_stb, spw_clk, spw_rxd, spw_rxdn, spw_rxs,
spw_rxsn, spw_txd, spw_txdn, spw_txs, spw_txsn, tck, tms, tdi, tdo);
-- optional sdram
sd0 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if (CFG_SDEN /= 0) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_SD64 /= 0) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sbanks : for k in 0 to srambanks-1 generate
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8),
ramsn(k), rwen(i), ramoen(k));
end generate;
end generate;
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
-- wait;
wait for 355000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#0F#, 16#DD#, 16#94#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
jtagproc : process
begin
wait;
jtagcom(tdo, tck, tms, tdi, 100, 20, 16#40000000#, true);
wait;
end process;
end;
| gpl-2.0 | a3e7389b24c5a5f4cc222320783d521d | 0.572838 | 3.018836 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/ptf/pt_pci_arb.vhd | 1 | 4,003 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pt_pci_arb
-- File: pt_pci_arb.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: PCI arbiter
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.pt_pkg.all;
entity pt_pci_arb is
generic (
slots : integer := 5;
tval : time := 7 ns);
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end pt_pci_arb;
architecture tb of pt_pci_arb is
type queue_type is array (0 to slots-1) of integer range 0 to slots;
signal queue : queue_type;
signal queue_nr : integer range 0 to slots;
signal wfbus : boolean;
begin
arb : process(systclk)
variable i, slotgnt : integer;
variable set : boolean;
variable bus_idle : boolean;
variable vqueue_nr : integer range 0 to slots;
variable gnt,req : std_logic_vector(slots-1 downto 0);
begin
set := false; vqueue_nr := queue_nr;
if (ifcin.frame and ifcin.irdy) = '1' then bus_idle := true; else bus_idle := false; end if;
gnt := to_x01(arbin.gnt(slots-1 downto 0));
req := to_x01(arbin.req(slots-1 downto 0));
if systclk.rst = '0' then
gnt := (others => '1');
wfbus <= false;
for i in 0 to slots-1 loop
queue(i) <= 0;
end loop;
queue_nr <= 0;
elsif rising_edge(systclk.clk) then
for i in 0 to slots-1 loop
if (gnt(i) or req(i)) = '0' then
if (bus_idle or wfbus) then
set := true;
end if;
end if;
end loop;
for i in 0 to slots-1 loop
if (gnt(i) and not req(i)) = '1' then
if queue(i) = 0 then
vqueue_nr := vqueue_nr+1;
queue(i) <= vqueue_nr;
elsif (queue(i) = 1 and set = false) then
gnt := (others => '1'); gnt(i) := '0';
queue(i) <= 0;
if not bus_idle then wfbus <= true; end if;
if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif queue(i) >= 2 then
if (set = false or vqueue_nr <= 1) then
queue(i) <= queue(i)-1;
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
elsif (req(i) and not gnt(i)) = '1' then
queue(i) <= 0; gnt(i) := '1';
-- if vqueue_nr > 0 then vqueue_nr := vqueue_nr-1; end if;
elsif (req(i) and gnt(i)) = '1' then
if (queue(i) > 0 and set = false) then
queue(i) <= queue(i)-1;
if (vqueue_nr > 0 and queue(i) = 1) then vqueue_nr := vqueue_nr-1; end if;
end if;
end if;
end loop;
end if;
if bus_idle then wfbus <= false; end if;
queue_nr <= vqueue_nr;
arbout.req <= (others => 'Z');
arbout.gnt <= (others => 'Z');
arbout.gnt(slots-1 downto 0) <= gnt;
end process;
end;
-- pragma translate_on
| gpl-2.0 | 1a7941117737f7f15019fb214a73953e | 0.553835 | 3.49607 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/umc18/memory_umc18.vhd | 1 | 9,424 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_umc_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for UMC rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library umc18;
use umc18.SRAM_2048wx32b;
use umc18.SRAM_1024wx32b;
use umc18.SRAM_512wx32b;
use umc18.SRAM_256wx32b;
use umc18.SRAM_128wx32b;
use umc18.SRAM_64wx32b;
use umc18.SRAM_32wx32b;
use umc18.SRAM_2048wx40b;
use umc18.SRAM_1024wx40b;
use umc18.SRAM_512wx40b;
use umc18.SRAM_256wx40b;
use umc18.SRAM_128wx40b;
use umc18.SRAM_64wx40b;
use umc18.SRAM_32wx40b;
-- pragma translate_on
entity umc_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector(abits -1 downto 0);
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of umc_syncram is
component SRAM_2048wx32b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_1024wx32b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_512wx32b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_256wx32b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_128wx32b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_64wx32b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_32wx32b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(31 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(31 downto 0);
clk : in std_logic
);
end component;
component SRAM_2048wx40b is
port (
a : in std_logic_vector(10 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_1024wx40b is
port (
a : in std_logic_vector(9 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_512wx40b is
port (
a : in std_logic_vector(8 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_256wx40b is
port (
a : in std_logic_vector(7 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_128wx40b is
port (
a : in std_logic_vector(6 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_64wx40b is
port (
a : in std_logic_vector(5 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
component SRAM_32wx40b is
port (
a : in std_logic_vector(4 downto 0);
data : in std_logic_vector(39 downto 0);
csn : in std_logic;
wen : in std_logic;
oen : in std_logic;
q : out std_logic_vector(39 downto 0);
clk : in std_logic
);
end component;
signal d, q, gnd : std_logic_vector(41 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc, csn, wen : std_ulogic;
constant synopsys_bug : std_logic_vector(41 downto 0) := (others => '0');
begin
csn <= not enable; wen <= not write;
gnd <= (others => '0'); vcc <= '1';
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a(17 downto abits) <= synopsys_bug(17 downto abits);
d(41 downto dbits) <= synopsys_bug(41 downto dbits);
dataout <= q(dbits -1 downto 0);
-- q(41 downto dbits) <= synopsys_bug(41 downto dbits);
d32 : if (dbits <= 32) generate
a5d32 : if (abits <= 5) generate
id0 : SRAM_32wx32b port map (a(4 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a6d32 : if (abits = 6) generate
id0 : SRAM_64wx32b port map (a(5 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a7d32 : if (abits = 7) generate
id0 : SRAM_128wx32b port map (a(6 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a8d32 : if (abits = 8) generate
id0 : SRAM_256wx32b port map (a(7 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a9d32 : if (abits = 9) generate
id0 : SRAM_512wx32b port map (a(8 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a10d32 : if (abits = 10) generate
id0 : SRAM_1024wx32b port map (a(9 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
a11d32 : if (abits = 11) generate
id0 : SRAM_2048wx32b port map (a(10 downto 0), d(31 downto 0), csn,
wen, gnd(0), q(31 downto 0), clk);
end generate;
end generate;
d40 : if (dbits > 32) and (dbits <= 40) generate
a5d40 : if (abits <= 5) generate
id0 : SRAM_32wx40b port map (a(4 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a6d40 : if (abits = 6) generate
id0 : SRAM_64wx40b port map (a(5 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a7d40 : if (abits = 7) generate
id0 : SRAM_128wx40b port map (a(6 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a8d40 : if (abits = 8) generate
id0 : SRAM_256wx40b port map (a(7 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a9d40 : if (abits = 9) generate
id0 : SRAM_512wx40b port map (a(8 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a10d40 : if (abits = 10) generate
id0 : SRAM_1024wx40b port map (a(9 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
a11d40 : if (abits = 11) generate
id0 : SRAM_2048wx40b port map (a(10 downto 0), d(39 downto 0), csn,
wen, gnd(0), q(39 downto 0), clk);
end generate;
end generate;
-- pragma translate_off
a_to_high : if (abits > 11) or (dbits > 40) generate
x : process
begin
assert false
report "Unsupported memory size (umc18)"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
| gpl-2.0 | 4469c29a2ce79c695f09a1bbaf488cf7 | 0.606324 | 2.90954 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/digit/simulation/bmg_stim_gen.vhd | 1 | 12,583 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (11 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0):= hex_to_std_logic_vector("0",12);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (10239 downto 0) of std_logic_vector(11 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"digit.mif",
DEFAULT_DATA,
12,
10240);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>10240 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(13 DOWNTO 0) <= READ_ADDR(13 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 10240 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit | f461114db447910d46fbe44ee75c70a0 | 0.547882 | 3.687866 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml510/testbench.vhd | 1 | 16,125 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2008 Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library cypress;
use cypress.components.all;
library hynix;
use hynix.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal sysace_fpga_clk : std_ulogic := '0';
signal flash_we_b : std_ulogic;
signal flash_wait : std_ulogic;
signal flash_reset_b : std_ulogic;
signal flash_oe_b : std_ulogic;
signal flash_d : std_logic_vector(15 downto 0);
signal flash_clk : std_ulogic;
signal flash_ce_b : std_ulogic;
signal flash_adv_b : std_logic;
signal flash_a : std_logic_vector(21 downto 0);
signal sram_bw : std_ulogic;
signal sim_d : std_logic_vector(15 downto 0);
signal iosn : std_ulogic;
signal dimm1_ddr2_we_b : std_ulogic;
signal dimm1_ddr2_s_b : std_logic_vector(1 downto 0);
signal dimm1_ddr2_ras_b : std_ulogic;
signal dimm1_ddr2_pll_clkin_p : std_ulogic;
signal dimm1_ddr2_pll_clkin_n : std_ulogic;
signal dimm1_ddr2_odt : std_logic_vector(1 downto 0);
signal dimm1_ddr2_dqs_p : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dqs_n : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dqm : std_logic_vector(8 downto 0);
signal dimm1_ddr2_dq : std_logic_vector(71 downto 0);
signal dimm1_ddr2_dq2 : std_logic_vector(71 downto 0);
signal dimm1_ddr2_cke : std_logic_vector(1 downto 0);
signal dimm1_ddr2_cas_b : std_ulogic;
signal dimm1_ddr2_ba : std_logic_vector(2 downto 0);
signal dimm1_ddr2_a : std_logic_vector(13 downto 0);
signal dimm0_ddr2_we_b : std_ulogic;
signal dimm0_ddr2_s_b : std_logic_vector(1 downto 0);
signal dimm0_ddr2_ras_b : std_ulogic;
signal dimm0_ddr2_pll_clkin_p : std_ulogic;
signal dimm0_ddr2_pll_clkin_n : std_ulogic;
signal dimm0_ddr2_odt : std_logic_vector(1 downto 0);
signal dimm0_ddr2_dqs_p : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dqs_n : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dqm : std_logic_vector(8 downto 0);
signal dimm0_ddr2_dq : std_logic_vector(71 downto 0);
signal dimm0_ddr2_dq2 : std_logic_vector(71 downto 0);
signal dimm0_ddr2_cke : std_logic_vector(1 downto 0);
signal dimm0_ddr2_cas_b : std_ulogic;
signal dimm0_ddr2_ba : std_logic_vector(2 downto 0);
signal dimm0_ddr2_a : std_logic_vector(13 downto 0);
signal phy0_txer : std_ulogic;
signal phy0_txd : std_logic_vector(3 downto 0);
signal phy0_txctl_txen : std_ulogic;
signal phy0_txclk : std_ulogic;
signal phy0_rxer : std_ulogic;
signal phy0_rxd : std_logic_vector(3 downto 0);
signal phy0_rxctl_rxdv : std_ulogic;
signal phy0_rxclk : std_ulogic;
signal phy0_reset : std_ulogic;
signal phy0_mdio : std_logic;
signal phy0_mdc : std_ulogic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_mpd : std_logic_vector(15 downto 0);
signal dbg_led : std_logic_vector(3 downto 0);
signal opb_bus_error : std_ulogic;
signal plb_bus_error : std_ulogic;
signal dvi_xclk_p : std_ulogic;
signal dvi_xclk_n : std_ulogic;
signal dvi_v : std_ulogic;
signal dvi_reset_b : std_ulogic;
signal dvi_h : std_ulogic;
signal dvi_gpio1 : std_logic;
signal dvi_de : std_ulogic;
signal dvi_d : std_logic_vector(11 downto 0);
signal pci_p_trdy_b : std_logic;
signal pci_p_stop_b : std_logic;
signal pci_p_serr_b : std_logic;
signal pci_p_rst_b : std_logic;
signal pci_p_req_b : std_logic_vector(0 to 4);
signal pci_p_perr_b : std_logic;
signal pci_p_par : std_logic;
signal pci_p_lock_b : std_logic;
signal pci_p_irdy_b : std_logic;
signal pci_p_intd_b : std_logic;
signal pci_p_intc_b : std_logic;
signal pci_p_intb_b : std_logic;
signal pci_p_inta_b : std_logic;
signal pci_p_gnt_b : std_logic_vector(0 to 4);
signal pci_p_frame_b : std_logic;
signal pci_p_devsel_b : std_logic;
signal pci_p_clk5_r : std_ulogic;
signal pci_p_clk5 : std_ulogic;
signal pci_p_clk4_r : std_ulogic;
signal pci_p_clk3_r : std_ulogic;
signal pci_p_clk1_r : std_ulogic;
signal pci_p_clk0_r : std_ulogic;
signal pci_p_cbe_b : std_logic_vector(3 downto 0);
signal pci_p_ad : std_logic_vector(31 downto 0);
--signal pci_fpga_idsel : std_ulogic;
signal sbr_pwg_rsm_rstj : std_logic;
signal sbr_nmi_r : std_ulogic;
signal sbr_intr_r : std_ulogic;
signal sbr_ide_rst_b : std_logic;
signal iic_sda_dvi : std_logic;
signal iic_scl_dvi : std_logic;
signal fpga_sda : std_logic;
signal fpga_scl : std_logic;
signal iic_therm_b : std_ulogic;
signal iic_reset_b : std_ulogic;
signal iic_irq_b : std_ulogic;
signal iic_alert_b : std_ulogic;
signal spi_data_out : std_logic;
signal spi_data_in : std_logic;
signal spi_data_cs_b : std_ulogic;
signal spi_clk : std_ulogic;
signal uart1_txd : std_ulogic;
signal uart1_rxd : std_ulogic;
signal uart1_rts_b : std_ulogic;
signal uart1_cts_b : std_ulogic;
signal uart0_txd : std_ulogic;
signal uart0_rxd : std_ulogic;
signal uart0_rts_b : std_ulogic;
--signal uart0_cts_b : std_ulogic;
--signal test_mon_vrefp : std_ulogic;
signal test_mon_vp0_p : std_ulogic;
signal test_mon_vn0_n : std_ulogic;
--signal test_mon_avdd : std_ulogic;
signal data : std_logic_vector(31 downto 0);
signal phy0_rxdl : std_logic_vector(7 downto 0);
signal phy0_txdl : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
sysace_fpga_clk <= not sysace_fpga_clk after 15 ns;
pci_p_clk5 <= pci_p_clk5_r;
flash_wait <= 'L';
phy0_txdl <= "0000" & phy0_txd; phy0_rxd <= phy0_rxdl(3 downto 0);
sysace_mpd <= (others => 'H'); sysace_mpirq <= 'L';
dbg_led <= (others => 'H');
dvi_gpio1 <= 'H';
pci_p_trdy_b <= 'H'; pci_p_stop_b <= 'H';
pci_p_serr_b <= 'H'; pci_p_rst_b <= 'H';
pci_p_req_b <= (others => 'H'); pci_p_perr_b <= 'H';
pci_p_par <= 'H'; pci_p_lock_b <= 'H';
pci_p_irdy_b <= 'H'; pci_p_intd_b <= 'H';
pci_p_intc_b <= 'H'; pci_p_intb_b <= 'H';
pci_p_inta_b <= 'H'; pci_p_gnt_b <= (others => 'H');
pci_p_frame_b <= 'H'; pci_p_devsel_b <= 'H';
pci_p_cbe_b <= (others => 'H'); pci_p_ad <= (others => 'H');
-- pci_fpga_idsel <= 'H';
sbr_pwg_rsm_rstj <= 'H'; sbr_nmi_r <= 'H';
sbr_intr_r <= 'L'; sbr_ide_rst_b <= 'H';
iic_sda_dvi <= 'H'; iic_scl_dvi <= 'H';
fpga_sda <= 'H'; fpga_scl <= 'H';
iic_therm_b <= 'L'; iic_irq_b <= 'L'; iic_alert_b <= 'L';
spi_data_out <= 'H';
uart1_rxd <= 'H'; uart1_cts_b <= uart1_rts_b;
uart0_rxd <= 'H'; --uart0_cts_b <= uart0_rts_b;
test_mon_vp0_p <= 'H'; test_mon_vn0_n <= 'H';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map (sys_rst_in, sys_clk, sysace_fpga_clk,
-- Flash
flash_we_b, flash_wait, flash_reset_b, flash_oe_b,
flash_d, flash_clk, flash_ce_b, flash_adv_b, flash_a,
sram_bw, sim_d, iosn,
-- DDR2 slot 1
dimm1_ddr2_we_b, dimm1_ddr2_s_b, dimm1_ddr2_ras_b,
dimm1_ddr2_pll_clkin_p, dimm1_ddr2_pll_clkin_n,
dimm1_ddr2_odt, dimm1_ddr2_dqs_p, dimm1_ddr2_dqs_n,
dimm1_ddr2_dqm, dimm1_ddr2_dq, dimm1_ddr2_cke,
dimm1_ddr2_cas_b, dimm1_ddr2_ba, dimm1_ddr2_a,
-- DDR2 slot 0
dimm0_ddr2_we_b, dimm0_ddr2_s_b, dimm0_ddr2_ras_b,
dimm0_ddr2_pll_clkin_p, dimm0_ddr2_pll_clkin_n,
dimm0_ddr2_odt, dimm0_ddr2_dqs_p, dimm0_ddr2_dqs_n,
dimm0_ddr2_dqm, dimm0_ddr2_dq, dimm0_ddr2_cke,
dimm0_ddr2_cas_b, dimm0_ddr2_ba, dimm0_ddr2_a,
open,
-- Ethernet PHY
phy0_txer, phy0_txd, phy0_txctl_txen, phy0_txclk,
phy0_rxer, phy0_rxd, phy0_rxctl_rxdv, phy0_rxclk,
phy0_reset, phy0_mdio, phy0_mdc,
-- System ACE MPU
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_mpd,
-- GPIO/Green LEDs
dbg_led,
-- Red/Green LEDs
opb_bus_error, plb_bus_error,
-- LCD
-- fpga_lcd_rw, fpga_lcd_rs, fpga_lcd_e, fpga_lcd_db,
-- DVI
dvi_xclk_p, dvi_xclk_n, dvi_v, dvi_reset_b, dvi_h,
dvi_gpio1, dvi_de, dvi_d,
-- PCI
pci_p_trdy_b, pci_p_stop_b, pci_p_serr_b, pci_p_rst_b,
pci_p_req_b, pci_p_perr_b, pci_p_par, pci_p_lock_b,
pci_p_irdy_b, pci_p_intd_b, pci_p_intc_b, pci_p_intb_b,
pci_p_inta_b, pci_p_gnt_b, pci_p_frame_b, pci_p_devsel_b,
pci_p_clk5_r, pci_p_clk5, pci_p_clk4_r, pci_p_clk3_r,
pci_p_clk1_r, pci_p_clk0_r, pci_p_cbe_b, pci_p_ad,
-- pci_fpga_idsel,
sbr_pwg_rsm_rstj, sbr_nmi_r, sbr_intr_r, sbr_ide_rst_b,
-- IIC/SMBus and sideband signals
iic_sda_dvi, iic_scl_dvi, fpga_sda, fpga_scl, iic_therm_b,
iic_reset_b, iic_irq_b, iic_alert_b,
-- SPI
spi_data_out, spi_data_in, spi_data_cs_b, spi_clk,
-- UARTs
uart1_txd, uart1_rxd, uart1_rts_b, uart1_cts_b,
uart0_txd, uart0_rxd, uart0_rts_b--, --uart0_cts_b
-- System monitor
-- test_mon_vp0_p, test_mon_vn0_n
);
ddr2mem0: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => true, PUSCheckFlag => false,
index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH,
fname => sdramfile, fdelay => 0)
port map (DQ => dimm0_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)),
LDQS => dimm0_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
LDQSB => dimm0_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
UDQS => dimm0_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
UDQSB => dimm0_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
LDM => dimm0_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
WEB => dimm0_ddr2_we_b, CASB => dimm0_ddr2_cas_b,
RASB => dimm0_ddr2_ras_b, CSB => dimm0_ddr2_s_b(0),
BA => dimm0_ddr2_ba(1 downto 0), ADDR => dimm0_ddr2_a(12 downto 0),
CKE => dimm0_ddr2_cke(0), CLK => dimm0_ddr2_pll_clkin_p,
CLKB => dimm0_ddr2_pll_clkin_n,
UDM => dimm0_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)));
end generate;
ddr2mem1: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => true, PUSCheckFlag => false,
index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH,
fname => sdramfile, fdelay => 0)
port map (DQ => dimm1_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)),
LDQS => dimm1_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
LDQSB => dimm1_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
UDQS => dimm1_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
UDQSB => dimm1_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)),
LDM => dimm1_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)),
WEB => dimm1_ddr2_we_b, CASB => dimm1_ddr2_cas_b,
RASB => dimm1_ddr2_ras_b, CSB => dimm1_ddr2_s_b(0),
BA => dimm1_ddr2_ba(1 downto 0), ADDR => dimm1_ddr2_a(12 downto 0),
CKE => dimm1_ddr2_cke(0), CLK => dimm1_ddr2_pll_clkin_p,
CLKB => dimm1_ddr2_pll_clkin_n,
UDM => dimm1_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)));
end generate;
ddr2delay0 : delay_wire
generic map(data_width => dimm0_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 2.5)
port map(a => dimm0_ddr2_dq, b => dimm0_ddr2_dq2);
ddr2delay1 : delay_wire
generic map(data_width => dimm1_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 2.5)
port map(a => dimm1_ddr2_dq, b => dimm1_ddr2_dq2);
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (flash_a(romdepth-1 downto 0), flash_d(15 downto 0),
gnd, gnd, flash_ce_b, flash_we_b, flash_oe_b);
phy0_mdio <= 'H';
p0: phy
generic map (address => 7)
port map(phy0_reset, phy0_mdio, phy0_txclk, phy0_rxclk, phy0_rxdl,
phy0_rxctl_rxdv, phy0_rxer, open, open, phy0_txdl,
phy0_txctl_txen, phy0_txer, phy0_mdc, '0');
i0: i2c_slave_model
port map (iic_scl_dvi, iic_sda_dvi);
i1: i2c_slave_model
port map (fpga_scl, fpga_sda);
iuerr : process
begin
wait for 5000 ns;
if to_x01(opb_bus_error) = '0' then wait on opb_bus_error; end if;
assert (to_x01(opb_bus_error) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= flash_d & sim_d;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, opb_bus_error, flash_a(20 downto 1), data,
iosn, flash_oe_b, sram_bw, open);
flash_d <= buskeep(flash_d), (others => 'H') after 250 ns;
data <= buskeep(data), (others => 'H') after 250 ns;
end ;
| gpl-2.0 | e0bf2ee659a88f8ddb54116ad4723933 | 0.584186 | 2.879464 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/keyboard/ps2_keyboard.vhd | 1 | 5,215 | --------------------------------------------------------------------------------
--
-- FileName: ps2_keyboard.vhd
-- Dependencies: debounce.vhd
-- Design Software: Quartus II 32-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/25/2013 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity ps2_keyboard is
generic(
clk_freq : integer; --! system clock frequency in Hz
db_cnt_size : integer --! set such that (2^size)/clk_freq = 5us (size = 8 for 50MHz)
);
port(
clk : in std_logic; --! system clock
ps2_clk : in std_logic; --! clock signal from PS/2 keyboard
ps2_data : in std_logic; --! data signal from PS/2 keyboard
ps2_code_new : out std_logic; --! new PS/2 code is available
ps2_code : out std_logic_vector(7 downto 0) --! code received from PS/2
);
end ps2_keyboard;
architecture ps2_keyboard of ps2_keyboard is
signal sync_ffs : std_logic_vector(1 downto 0); -- synchronizer flip-flops for ps/2 signals
signal ps2_clk_int : std_logic; -- debounced clock signal from ps/2 keyboard
signal ps2_data_int : std_logic; -- debounced data signal from ps/2 keyboard
signal ps2_word : std_logic_vector(10 downto 0); -- stores the ps2 data word
signal error : std_logic; -- validate parity, start, and stop bits
signal count_idle : integer range 0 to clk_freq/18_000; -- counter to determine ps/2 is idle
--declare debounce component for debouncing PS2 input signals
component debounce is
generic(
counter_size : integer -- Counter size (19 bits gives 10.5ms with 50MHz clock)
);
port(
clk : in std_logic; -- Input clock
button : in std_logic; -- Input signal to be debounced
result : out std_logic -- Debounced signal
);
end component;
begin
--synchronizer flip-flops
pr_clk: process(clk)
begin
if (clk'event and clk = '1') then -- rising edge of system clock
sync_ffs(0) <= ps2_clk; -- synchronize ps/2 clock signal
sync_ffs(1) <= ps2_data; -- synchronize ps/2 data signal
end if;
end process;
--debounce PS2 input signals
debounce_ps2_clk: debounce
generic map(counter_size => db_cnt_size)
port map(clk => clk, button => sync_ffs(0), result => ps2_clk_int);
debounce_ps2_data: debounce
generic map(counter_size => db_cnt_size)
port map(clk => clk, button => sync_ffs(1), result => ps2_data_int);
--input PS2 data
pr_int: process(ps2_clk_int)
begin
if (ps2_clk_int'event and ps2_clk_int = '0') then --falling edge of ps2 clock
ps2_word <= ps2_data_int & ps2_word(10 downto 1); --shift in ps2 data bit
end if;
end process;
--verify that parity, start, and stop bits are all correct
error <= NOT (NOT ps2_word(0) AND ps2_word(10) AND (ps2_word(9) XOR ps2_word(8) XOR
ps2_word(7) XOR ps2_word(6) XOR ps2_word(5) XOR ps2_word(4) XOR ps2_word(3) XOR
ps2_word(2) XOR ps2_word(1)));
--determine if PS2 port is idle (i.e. last transaction is finished) and output result
pr_ps2: process(clk)
begin
if (clk'event and clk = '1') then --rising edge of system clock
if (ps2_clk_int = '0') then --low ps2 clock, ps/2 is active
count_idle <= 0; --reset idle counter
elsif(count_idle /= clk_freq/18_000) then --ps2 clock has been high less than a half clock period (<55us)
count_idle <= count_idle + 1; --continue counting
end if;
if(count_idle = clk_freq/18_000 and error = '0') then --idle threshold reached and no errors detected
ps2_code_new <= '1'; --set flag that new ps/2 code is available
ps2_code <= ps2_word(8 downto 1); --output new ps/2 code
else --ps/2 port active or error detected
ps2_code_new <= '0'; --set flag that ps/2 transaction is in progress
end if;
end if;
end process;
end ps2_keyboard; | mit | 911b7157a1f57deb99c3809950853f2e | 0.571429 | 3.78447 | false | false | false | false |
laurocruz/snakes_vhdl | src/snake_lib/size_counter.vhd | 1 | 1,037 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std;
LIBRARY snake_lib;
USE snake_lib.snake_pack.all;
-- tamanho da cobra
ENTITY size_counter IS
-- DImensões do mapa
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
PORT (reset : IN STD_LOGIC;
food_pos : IN INTEGER RANGE -20 TO 255;
--food_pos : IN INTEGER RANGE 0 TO N*M-1;
snake_head : IN INTEGER RANGE -20 TO 255;
snake_size : OUT INTEGER RANGE 0 TO N*M;
eaten : OUT STD_LOGIC);
END size_counter;
ARCHITECTURE Behavior OF size_counter IS
SIGNAL size : INTEGER RANGE 0 TO N*M := INITIAL_SIZE;
SIGNAL eatens : STD_LOGIC := '0';
BEGIN
eatens <= '1' WHEN food_pos = snake_head ELSE '0';
PROCESS(eatens,reset)
BEGIN
IF (reset = '1') THEN
size <= INITIAL_SIZE;
ELSIF (eatens'EVENT and eatens = '1') THEN
size <= size + 1;
END IF;
END PROCESS;
snake_size <= size;
eaten <= eatens;
END Behavior;
| mit | c2360553793e0a364021116d66cd601c | 0.593629 | 3.092537 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma_sg_wrap.vhd | 1 | 97,825 | -------------------------------------------------------------------------------
-- axi_cdma_sg_wrap
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
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-- laws.
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-- CRITICAL APPLICATIONS
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-- PART OF THIS FILE AT ALL TIMES.
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_sg_wrap.vhd
--
-- Description:
--
-- This file is the module wrapper for the AXI CDMA core when parameterized
-- for only Simple Mode DMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- VHDL Libraries
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg;
library axi_cdma_v4_1;
use axi_cdma_v4_1.axi_cdma_pkg.all;
use axi_cdma_v4_1.axi_cdma_reset;
use axi_cdma_v4_1.axi_cdma_reg_module;
use axi_cdma_v4_1.axi_cdma_simple_cntlr;
use axi_cdma_v4_1.axi_cdma_sg_cntlr;
use axi_cdma_v4_1.axi_cdma_sf;
-------------------------------------------------------------------------------
entity axi_cdma_sg_wrap is
generic(
-----------------------------------------------------------------------
-- AXI Lite Register Interface Parameters
-----------------------------------------------------------------------
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 6;
-- Address width of the AXI Lite Interface (bits)
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface (bits)
C_AXI_LITE_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the AXI Lite Register interface needs to
-- be asynchronous to the CDMA data transport path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special AXI Lite clock for the axi lite interface
-----------------------------------------------------------------------
-- DataMover Memory Map Master Interface Parameters
-----------------------------------------------------------------------
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
-- DataMover Master AXI Memory Map Address Width (bits)
C_M_AXI_DATA_WIDTH : integer range 32 to 1024 := 32;
-- DataMover Master AXI Memory Map Data Width (bits)
C_M_AXI_MAX_BURST_LEN : integer range 2 to 256 := 16;
-- DataMover Maximum burst length to use for AXI MMAP requests
-- Allowed values are 16, 32, 64, 128, and 256 (data beats)
C_INCLUDE_DRE : integer range 0 to 1 := 0;
-- Include or exclude DataMover Data Realignment (DRE)
-- NOTE: DRE is only available for 32 and 64 bit data widths
-- 0 = Exclude DRE
-- 1 = Include DRE
C_USE_DATAMOVER_LITE : integer range 0 to 1 := 0;
-- Enable DataMover Lite mode
-- NOTE: Data widths limited to 32 and 64 bits, max burst
-- limited to 16, 32, and 64 data beats, no DRE, 4K address
-- guarding must be done by SW programmer.
-- 0 = Normal DataMover mode
-- 1 = Lite dataMover mode
C_READ_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter specifies the depth of the DataMover
-- read address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4 Read
-- Address Channel will be the value assigned plus 2.
C_WRITE_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter specifies the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channel. The effective address pipelining on the AXI4 Write
-- Address Channel will be the value assigned plus 2.
-----------------------------------------------------------------------
-- Store and Forward Parameters
-----------------------------------------------------------------------
C_INCLUDE_SF : integer range 0 to 1 := 1;
-- This parameter includes includes/omits Store and Forward.
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 128 ;
-- This parameter sets the depth of the Store and Forward FIFO.
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather
-- R/W Port (bits)
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather
-- R/W Port (bits)
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in clock ticks of axi_aclk
-----------------------------------------------------------------------
-- Soft Reset Assertion Time
-----------------------------------------------------------------------
C_SOFT_RST_TIME_CLKS : integer range 1 to 64 := 8;
-- Specifies the time of the soft reset assertion in
-- axi_aclk clock periods.
-----------------------------------------------------------------------
-- Target FPGA Family Parameter
-----------------------------------------------------------------------
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-----------------------------------------------------------------------
-- Primary Clock
-----------------------------------------------------------------------
axi_aclk : in std_logic ;
-----------------------------------------------------------------------
-- Primary Reset Input (active low synchronous to axi_aclk)
-----------------------------------------------------------------------
axi_resetn : in std_logic ;
-----------------------------------------------------------------------
-- AXI Lite clock
-----------------------------------------------------------------------
axi_lite_aclk : in std_logic ;
-----------------------------------------------------------------------
-- AXI Lite reset (active low synchronous to axi_lite_aclk)
-----------------------------------------------------------------------
axi_lite_resetn : in std_logic ;
-----------------------------------------------------------------------
-- Interrupt output
-----------------------------------------------------------------------
cdma_introut : out std_logic ;
-----------------------------------------------------------------------
-- Error Discrete output
-----------------------------------------------------------------------
cdma_error_out : out std_logic ;
---------------------------------------------------------------------------------
-- AXI Lite Register Access Interface
---------------------------------------------------------------------------------
-- AXI Lite Write Address Channel -- AXI4-Lite
s_axi_lite_awready : out std_logic ;-- AXI4-Lite
s_axi_lite_awvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_awaddr : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Data Channel -- AXI4-Lite
s_axi_lite_wready : out std_logic ;-- AXI4-Lite
s_axi_lite_wvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_wdata : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Response Channel -- AXI4-Lite
s_axi_lite_bready : in std_logic ;-- AXI4-Lite
s_axi_lite_bvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Read Address Channel -- AXI4-Lite
s_axi_lite_arready : out std_logic ;-- AXI4-Lite
s_axi_lite_arvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_araddr : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Read Data Channel -- AXI4-Lite
s_axi_lite_rready : in std_logic ;-- AXI4-Lite
s_axi_lite_rvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_rdata : out std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
----------------------------------------------------------------------------
-- AXI DataMover Read Channel
----------------------------------------------------------------------------
-- DataMover MMap Read Address Channel -- AXI4
m_axi_arready : in std_logic ;-- AXI4
m_axi_arvalid : out std_logic ;-- AXI4
m_axi_araddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_arlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_arsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_arprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- DataMover MMap Read Data Channel -- AXI4
m_axi_rready : out std_logic ;-- AXI4
m_axi_rvalid : in std_logic ;-- AXI4
m_axi_rdata : in std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ;-- AXI4
m_axi_rresp : in std_logic_vector(1 downto 0) ;-- AXI4
m_axi_rlast : in std_logic ;-- AXI4
-----------------------------------------------------------------------------
-- AXI DataMover Write Channel
-----------------------------------------------------------------------------
-- DataMover Write Address Channel -- AXI4
m_axi_awready : in std_logic ;-- AXI4
m_axi_awvalid : out std_logic ;-- AXI4
m_axi_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_awlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_awsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_awburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_awprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_awcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- DataMover Write Data Channel -- AXI4
m_axi_wready : in std_logic ;-- AXI4
m_axi_wvalid : out std_logic ;-- AXI4
m_axi_wdata : out std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ;-- AXI4
m_axi_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_DATA_WIDTH/8)-1 downto 0);-- AXI4
m_axi_wlast : out std_logic ;-- AXI4
-- AXI4
-- DataMover Write Response Channel -- AXI4
m_axi_bready : out std_logic ;-- AXI4
m_axi_bvalid : in std_logic ;-- AXI4
m_axi_bresp : in std_logic_vector(1 downto 0) ;-- AXI4
----------------------------------------------------------------------------
-- AXI Scatter Gather Interface
----------------------------------------------------------------------------
-- Scatter Gather Write Address Channel -- AXI4
m_axi_sg_awready : in std_logic ;-- AXI4
m_axi_sg_awvalid : out std_logic ;-- AXI4
m_axi_sg_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- Scatter Gather Write Data Channel -- AXI4
m_axi_sg_wready : in std_logic ;-- AXI4
m_axi_sg_wvalid : out std_logic ;-- AXI4
m_axi_sg_wdata : out std_logic_vector -- AXI4
(C_M_AXI_SG_DATA_WIDTH-1 downto 0);-- AXI4
m_axi_sg_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0);-- AXI4
m_axi_sg_wlast : out std_logic ;-- AXI4
-- AXI4
-- Scatter Gather Write Response Channel -- AXI4
m_axi_sg_bready : out std_logic ;-- AXI4
m_axi_sg_bvalid : in std_logic ;-- AXI4
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ;-- AXI4
-- AXI4
-- Scatter Gather Read Address Channel -- AXI4
m_axi_sg_arready : in std_logic ;-- AXI4
m_axi_sg_arvalid : out std_logic ;-- AXI4
m_axi_sg_araddr : out std_logic_vector -- AXI4
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- Scatter Gather Read Data Channel -- AXI4
m_axi_sg_rready : out std_logic ;-- AXI4
m_axi_sg_rvalid : in std_logic ;-- AXI4
m_axi_sg_rdata : in std_logic_vector -- AXI4
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ;-- AXI4
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ;-- AXI4
m_axi_sg_rlast : in std_logic ;-- AXI4
-- Debug test vector (Xilinx use only)
axi_cdma_tstvec : out std_logic_vector(31 downto 0)
);
-----------------------------------------------------------------
-- End of PSFUtil MPD attributes
-----------------------------------------------------------------
end axi_cdma_sg_wrap;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_sg_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- General Use
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- AXI CDMA Build Mode (This Wrapper is with SG); 1 = Scatter Gather Enabled
constant CDMA_BUILD_MODE : integer := 1;
-- Indicates that ACLK is synchronous to ch1_aclk and ch2_aclk
Constant ACLK_IS_SYNC : integer := 0;
-- SG Channel 1 Include/omit
Constant INCLUDE_CH1 : integer := 1;
-- SG Channel 2 Include/omit
Constant OMIT_CH2 : integer := 0;
-- SG Include Update Engine
Constant INCLUDE_UPDATE_ENG : integer := 1;
-- SG Include Interrupt Controller
Constant INCLUDE_IRPT_CNTLR : integer := 1;
-- SG Include Delay Timer
Constant INCLUDE_DLY_TIMER : integer := 1;
-- SG Fetch Master Stream Width
Constant M_AXIS_SG_TDATA_WIDTH : integer := 32;
-- SG Pointer Update Stream Width
Constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32;
-- SG Status Update Stream Width
Constant C_S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33;
-- SG Update Slave Stream Width
Constant S_AXIS_SG_DATA_WIDTH : integer := 34;
-- SG Fetch Descriptor Queue Depth
Constant SG_FTCH_DESC2QUEUE : integer := 4;
-- SG Update Descriptor Queue Depth
--Constant SG_UPDT_DESC2QUEUE : integer := 8;
Constant SG_UPDT_DESC2QUEUE : integer := 4;
-- SG Ch1 number of descriptor words to fetch
Constant SG_CH1_WORDS_TO_FETCH : integer := 8;
-- SG Ch1 number of descriptor words to update
Constant SG_CH1_WORDS_TO_UPDATE : integer := 1;
-- SG Ch1 First Update word offset from desctiptor start
Constant SG_CH1_FIRST_UPDATE_WORD : integer := 7;
-- SG Ch1 Stale Descriptor Error enable
Constant SG_CH1_ENBL_STALE_ERROR : integer := 1;
-- SG Ch2 words to fetch (Not used in CDMA application)
Constant SG_CH2_WORDS_TO_FETCH : integer := 4;
-- SG Ch2 words to update (Not used in CDMA application)
Constant SG_CH2_WORDS_TO_UPDATE : integer := 1;
-- SG Ch2 First Update word offset from desctiptor start (Not used in CDMA application)
Constant SG_CH2_FIRST_UPDATE_WORD : integer := 0;
-- SG Ch2 Stale Descriptor Error enable (Not used in CDMA application)
Constant SG_CH2_ENBL_STALE_ERROR : integer := 0;
-- AXI DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- AXI DataMover Command / Status FIFO Depth
constant DM_SG_CMDSTS_FIFO_DEPTH : integer := 1;
-- AXI MM2S DataMover Full mode value
constant MM2S_FULL_MODE : integer := 1;
-- AXI MM2S DataMover Lite mode value
constant MM2S_LITE_MODE : integer := 2;
-- AXI S2MM DataMover Full mode value
constant S2MM_FULL_MODE : integer := 1;
-- AXI S2MM DataMover LITE mode value
constant S2MM_LITE_MODE : integer := 4;
-- AXI DataMover clocking mode
constant DM_USE_SYNC_CLOCKS : integer := 0;
-- AXI DataMover BTT Used width (Set the to the max allowed)
constant DM_BTT_WIDTH : integer := 23;
-- AXI DataMover S2MM DRE Enable (set to disabled)
constant DM_S2MM_DRE_DISABLED : integer := 0;
-- AXI DataMover Include Store and Forward
constant DM_OMIT_S2MM_STORE_FORWARD : integer := 0;
constant DM_ENABLE_S2MM_STORE_FORWARD : integer := 1;
Constant STORE_FORWARD_CNTL : integer := DM_OMIT_S2MM_STORE_FORWARD;
-- AXI DataMover Stream Backend width
constant DM_STREAM_DWIDTH : integer := C_M_AXI_DATA_WIDTH;
-- AXI DataMover Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- AXI DataMover S2MM status stream data width delta
-- if Store and Forward enabled
Constant SF_ADDED_STS_WIDTH : integer := 24;
-- AXI DataMover status stream data width (S2MM is based on mode of operation)
constant DM_MM2S_STATUS_WIDTH : integer := BASE_STATUS_WIDTH;
constant DM_S2MM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH +
(STORE_FORWARD_CNTL *
SF_ADDED_STS_WIDTH);
-- DataMover Command Stream data Width in bits
constant DM_CMD_WIDTH : integer := 72;
-- constant DM_CMD_WIDTH : integer := 104;
-- SG Delay and Threshold field widths
Constant DLY_THRESH_WIDTH : integer := 8;
-- SG Delay and Threshold zero values
Constant IRQ_DLY_THRESH_ZEROS : std_logic_vector(DLY_THRESH_WIDTH-1 downto 0) := (others => '0');
-- SG Address zero value
Constant SG_ADDR_ZEROS : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- SG Descriptor Fetch data width
Constant SG_FETCH_DWIDTH : integer := M_AXIS_SG_TDATA_WIDTH;
-- SG Descriptor Update data width
Constant SG_UPDATE_DWIDTH : integer := S_AXIS_SG_DATA_WIDTH;
-- SG Pointer Update data value of zeroes
Constant SG_UPDPTR_DATA_ZEROS : std_logic_vector(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- SG Status Update data value of zeroes
Constant SG_UPDSTS_DATA_ZEROS : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
-- AXI DataMover pipeline depth constants
Constant DM_READ_ADDR_PIPE_DEPTH : integer := C_READ_ADDR_PIPE_DEPTH;
Constant DM_WRITE_ADDR_PIPE_DEPTH : integer := C_WRITE_ADDR_PIPE_DEPTH;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_max (value_in_1 : integer;
value_in_2 : integer)
return integer is
Variable max_value : Integer := 0;
begin
If (value_in_1 > value_in_2) Then
max_value := value_in_1;
else
max_value := value_in_2;
End if;
Return (max_value);
end function funct_get_max;
-------------------------------------------------------------------
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(funct_get_max(4, 4)+2)
* C_M_AXI_MAX_BURST_LEN;
-- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Reset Module signals
signal sig_rst2lite_bside_reset : std_logic := '0';
signal sig_rst2lite_cside_reset : std_logic := '0';
signal sig_rst2reg_reset : std_logic := '0';
signal sig_rst2cntlr_reset : std_logic := '0';
signal sig_rst2sgcntlr_reset : std_logic := '0';
signal sig_rst2sg_resetn : std_logic := '0';
signal sig_rst2dm_resetn : std_logic := '0';
signal sig_rst2cntlr_halt : std_logic := '0';
signal sig_cntlr2rst_halt_cmplt : std_logic := '0';
signal sig_dm_mm2s_halt : std_logic := '0';
signal sig_dm_mm2s_halt_cmplt : std_logic := '0';
signal sig_dm_s2mm_halt : std_logic := '0';
signal sig_dm_s2mm_halt_cmplt : std_logic := '0';
-- Register Module Signals
signal sig_reg2cntlr_src_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2cntlr_dest_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2cntlr_btt : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2cntlr_go : std_logic := '0';
signal sig_cntlr2reg_idle_set : std_logic := '0';
signal sig_cntlr2reg_idle_clr : std_logic := '0';
signal sig_cntlr2reg_decerr_set : std_logic := '0';
signal sig_cntlr2reg_slverr_set : std_logic := '0';
signal sig_cntlr2reg_interr_set : std_logic := '0';
signal sig_cntlr2reg_ioc_set : std_logic := '0';
signal sig_cntlr2reg_iocirpt_set : std_logic := '0';
signal sig_reg2rst_soft_reset : std_logic := '0';
signal sig_rst2reg_soft_reset_clr : std_logic := '0';
signal sig_reg2cntlr_sg_mode : std_logic := '0';
-- DataMover MM2S error discrete
signal sig_dm_mm2s_err : std_logic := '0';
-- DataMover MM2S command Stream
signal sig_cntl2mm2s_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s2cntl_cmd_tready : std_logic := '0';
signal sig_cntl2mm2s_cmd_tvalid : std_logic := '0';
-- DataMover MM2S status Stream
signal sig_mm2s2cntl_sts_tdata : std_logic_vector(DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s2cntl_sts_tstrb : std_logic_vector((DM_MM2S_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s2cntl_sts_tvalid : std_logic := '0';
signal sig_cntl2mm2s_sts_tready : std_logic := '0';
-- DataMover S2MM error discrete
signal sig_dm_s2mm_err : std_logic := '0';
-- DataMover S2MM command Stream
signal sig_cntl2s2mm_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cntl2s2mm_cmd_tvalid : std_logic := '0';
signal sig_s2mm2cntl_cmd_tready : std_logic := '0';
-- DataMover S2MM status Stream
signal sig_s2mm2cntl_sts_tdata : std_logic_vector(DM_S2MM_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm2cntl_sts_tstrb : std_logic_vector((DM_S2MM_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm2cntl_sts_tvalid : std_logic := '0';
signal sig_cntl2s2mm_sts_tready : std_logic := '0';
-- DataMover stream loopback hookup
signal sig_mm2s_axis_tdata : std_logic_vector(DM_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_axis_tkeep : std_logic_vector((DM_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_axis_tlast : std_logic := '0';
signal sig_mm2s_axis_tvalid : std_logic := '0';
signal sig_mm2s_axis_tready : std_logic := '0';
-- SG/Register signals
signal sig_reg2sg_dmacr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2sg_dmasr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2sg_curdesc : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2sg_taildesc : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2sgcntlr_currdesc_updated : std_logic := '0';
signal sig_reg2sg_tailpntr_updated : std_logic := '0';
signal sig_reg2sg_irqdelay_wren : std_logic := '0';
signal sig_reg2sg_irqthresh_wren : std_logic := '0';
signal sig_sg2reg_ftch_interr_set : std_logic := '0';
signal sig_sg2reg_ftch_slverr_set : std_logic := '0';
signal sig_sg2reg_ftch_decerr_set : std_logic := '0';
signal sig_sg2reg_updt_interr_set : std_logic := '0';
signal sig_sg2reg_updt_slverr_set : std_logic := '0';
signal sig_sg2reg_updt_decerr_set : std_logic := '0';
signal sig_sg2sgcntlr_ftch_error : std_logic := '0';
signal sig_sg2reg_ftch_error_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_sg2sgcntlr_updt_error : std_logic := '0';
signal sig_sg2reg_updt_error_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_sg2reg_irqdelay_status : std_logic_vector(DLY_THRESH_WIDTH-1 downto 0) := (others => '0');
signal sig_sg2reg_irqthresh_status : std_logic_vector(DLY_THRESH_WIDTH-1 downto 0) := (others => '0');
-- SG Controller signals
signal sig_rst2sgcntl_halt : std_logic := '0';
signal sig_sgcntl2rst_halt_cmplt : std_logic := '0';
signal sig_sgcntl2reg_idle_set : std_logic := '0';
signal sig_sgcntl2reg_idle_clr : std_logic := '0';
signal sig_sgcntl2sg_pkt_sof : std_logic := '0';
signal sig_sgcntl2sg_pkt_eof : std_logic := '0';
signal sig_sg2sgcntl_ioc_irq_set : std_logic := '0';
signal sig_sg2sgcntl_dly_irq_set : std_logic := '0';
signal sig_sgcntl2reg_ioc_irq_set : std_logic := '0';
signal sig_sgcntl2reg_dly_irq_set : std_logic := '0';
signal sig_sg2sgcntlr_ftch_tdata : std_logic_vector(SG_FETCH_DWIDTH-1 downto 0) := (others => '0');
signal sig_sg2sgcntlr_ftch_tdata_new : std_logic_vector(127 downto 0) := (others => '0');
signal sig_sg2sgcntlr_ftch_tvalid : std_logic := '0';
signal sig_sg2sgcntlr_ftch_tvalid_new : std_logic := '0';
signal sig_sgcntl2sg_ftch_tready : std_logic := '0';
signal sig_sg2sgcntlr_ftch_tlast : std_logic := '0';
signal sig_sg2sgcntlr_ftch_desc_available : std_logic := '0';
signal sig_sg2sgcntlr_updptr_tready : std_logic := '0';
signal sig_sgcntl2sg_updptr_tvalid : std_logic := '0';
signal sig_sgcntl2sg_updptr_tdata : std_logic_vector(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sgcntl2sg_updptr_tlast : std_logic := '0';
signal sig_sg2sgcntlr_updsts_tready : std_logic := '0';
signal sig_sgcntl2sg_updsts_tvalid : std_logic := '0';
signal sig_sgcntl2sg_updsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sgcntl2sg_updsts_tlast : std_logic := '0';
signal sig_sgcntlr2sg_run_stop : std_logic := '0';
signal sig_sgcntlr2sg_desc_flush : std_logic := '0';
signal sig_sg2sgcntlr_ftch_idle : std_logic := '0';
signal sig_sg2sgcntlr_ftch_err_early : std_logic := '0';
signal sig_sg2sgcntlr_ftch_stale_desc : std_logic := '0';
signal sig_sg2sgcntlr_updt_idle : std_logic := '0';
signal sig_sg2sgcntlr_updt_ioc_irq_set : std_logic := '0';
signal sig_sg2sgcntlr_dma_interr_set : std_logic := '0';
signal sig_sg2sgcntlr_dma_slverr_set : std_logic := '0';
signal sig_sg2sgcntlr_dma_decerr_set : std_logic := '0';
signal sig_sgcntlr2reg_dma_interr_set : std_logic := '0';
signal sig_sgcntlr2reg_dma_slverr_set : std_logic := '0';
signal sig_sgcntlr2reg_dma_decerr_set : std_logic := '0';
signal sig_sgcntlr2reg_new_curdesc_wren : std_logic := '0';
signal sig_sgcntlr2reg_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Shared SG and Simple Mode register IF signals
signal sig_composite_idle_set : std_logic := '0';
signal sig_composite_idle_clr : std_logic := '0';
signal sig_composite_iocirpt_set : std_logic := '0';
signal sig_composite_dm_decerr_set : std_logic := '0';
signal sig_composite_dm_slverr_set : std_logic := '0';
signal sig_composite_dm_interr_set : std_logic := '0';
-- DataMover input signals multiplexed between Simple and SG Mode controllers
signal sig_dm_mm2s_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_dm_mm2s_cmd_tvalid : std_logic := '0';
signal sig_dm_mm2s_sts_tready : std_logic := '0';
signal sig_dm_s2mm_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_dm_s2mm_cmd_tvalid : std_logic := '0';
signal sig_dm_s2mm_sts_tready : std_logic := '0';
-- DataMover output signals shared between the Simple and SG Contorllers
signal sig_dm_mm2s_cmd_tready : std_logic := '0';
signal sig_dm_mm2s_sts_tvalid : std_logic := '0';
signal sig_dm_mm2s_sts_tdata : std_logic_vector(DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_dm_mm2s_sts_tkeep : std_logic_vector((DM_MM2S_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dm_s2mm_cmd_tready : std_logic := '0';
signal sig_dm_s2mm_sts_tvalid : std_logic := '0';
-- SG DataMover Interface signals
-- DataMover MM2S error discrete
signal sig_mm2s2sgcntl_err : std_logic := '0';
-- DataMover MM2S command Stream
signal sig_sgcntl2mm2s_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_sgcntl2mm2s_cmd_tvalid : std_logic := '0';
signal sig_mm2s2sgcntl_cmd_tready : std_logic := '0';
-- DataMover MM2S status Stream
signal sig_mm2s2sgcntl_sts_tdata : std_logic_vector(DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s2sgcntl_sts_tstrb : std_logic_vector((DM_MM2S_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s2sgcntl_sts_tvalid : std_logic := '0';
signal sig_sgcntl2mm2s_sts_tready : std_logic := '0';
-- DataMover S2MM error discrete
signal sig_s2mm2sgcntl_err : std_logic := '0';
-- DataMover S2MM command Stream
signal sig_sgcntl2s2mm_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_sgcntl2s2mm_cmd_tvalid : std_logic := '0';
signal sig_s2mm2sgcntl_cmd_tready : std_logic := '0';
-- DataMover S2MM status Stream
signal sig_s2mm2sgcntl_sts_tdata : std_logic_vector(BASE_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm2sgcntl_sts_tstrb : std_logic_vector((BASE_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm2sgcntl_sts_tvalid : std_logic := '0';
signal sig_sgcntl2s2mm_sts_tready : std_logic := '0';
-- DataMover halt control
signal sig_rst2mm2s_halt : std_logic := '0';
signal sig_rst2s2mm_halt : std_logic := '0';
signal sig_sgcntl2mm2s_halt : std_logic := '0';
signal sig_sgcntl2s2mm_halt : std_logic := '0';
-- DataMover Input Stream
signal sig_s2mm_axis_tready : std_logic := '0';
signal sig_s2mm_axis_tvalid : std_logic := '0';
signal sig_s2mm_axis_tdata : std_logic_vector(DM_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_axis_tkeep : std_logic_vector((DM_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_axis_tlast : std_logic := '0';
signal sig_dm_s2mm_sts_tdata : std_logic_vector(DM_S2MM_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_dm_s2mm_sts_tkeep : std_logic_vector((DM_S2MM_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
-- DataMover Address Pipe Controls
signal sig_mm2s_allow_addr_req : std_logic := '0';
signal sig_mm2s_addr_req_posted : std_logic := '0';
signal sig_mm2s_rd_xfer_cmplt : std_logic := '0';
signal sig_s2mm_allow_addr_req : std_logic := '0';
signal sig_s2mm_addr_req_posted : std_logic := '0';
signal sig_s2mm_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
-- store and Forward module Reset
signal sig_sf_reset : std_logic := '0';
signal dma_keyhole_write : std_logic;
signal dma_keyhole_read : std_logic;
signal dma_cyclic : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- AXI CDMA Test Vector (For Xilinx Internal Use Only)
-------------------------------------------------------------------------------
-- Simple Mode (bits 7 downto 0)
axi_cdma_tstvec(0) <= sig_reg2cntlr_go ;
axi_cdma_tstvec(1) <= sig_cntlr2reg_idle_set ;
axi_cdma_tstvec(2) <= sig_cntlr2reg_idle_clr ;
axi_cdma_tstvec(3) <= sig_cntlr2reg_iocirpt_set ;
axi_cdma_tstvec(4) <= sig_cntlr2reg_decerr_set ;
axi_cdma_tstvec(5) <= sig_cntlr2reg_slverr_set ;
axi_cdma_tstvec(6) <= sig_cntlr2reg_interr_set ;
axi_cdma_tstvec(7) <= '0' ;
-- SG Mode bits 31 downto 8)
axi_cdma_tstvec(8) <= sig_sgcntlr2sg_run_stop ;
axi_cdma_tstvec(9) <= sig_sgcntl2sg_pkt_sof ;
axi_cdma_tstvec(10) <= sig_sgcntl2sg_pkt_eof ;
axi_cdma_tstvec(11) <= sig_sgcntl2reg_ioc_irq_set ;
axi_cdma_tstvec(12) <= sig_sgcntl2reg_dly_irq_set ;
axi_cdma_tstvec(13) <= sig_sg2sgcntlr_ftch_error ;
axi_cdma_tstvec(14) <= sig_sg2sgcntlr_ftch_stale_desc ;
axi_cdma_tstvec(15) <= sig_sg2reg_ftch_interr_set ;
axi_cdma_tstvec(16) <= sig_sg2reg_ftch_slverr_set ;
axi_cdma_tstvec(17) <= sig_sg2reg_ftch_decerr_set ;
axi_cdma_tstvec(18) <= sig_sg2sgcntlr_updt_error ;
axi_cdma_tstvec(19) <= sig_sg2reg_updt_interr_set ;
axi_cdma_tstvec(20) <= sig_sg2reg_updt_slverr_set ;
axi_cdma_tstvec(21) <= sig_sg2reg_updt_decerr_set ;
axi_cdma_tstvec(22) <= sig_sgcntlr2reg_dma_interr_set ;
axi_cdma_tstvec(23) <= sig_sgcntlr2reg_dma_slverr_set ;
axi_cdma_tstvec(24) <= sig_sgcntlr2reg_dma_decerr_set ;
axi_cdma_tstvec(31 downto 25) <= (others => '0') ;
-- Create a postive reset for the Store and Forward module
-- from the inverted DataMover active low reset.
-- CR591254 change
-- sig_sf_reset <= not(sig_rst2dm_resetn) ;
sig_sf_reset <= sig_rst2cntlr_reset ;
-------------------------------------------------------------------------------
-- Module Instances
-------------------------------------------------------------------------------
------------------------------------------------------------
-- Instance: I_RST_MODULE
--
-- Description:
-- Instance for the Reset Module used with Simple Mode
-- operation. It manages both hard and soft reset generation.
--
------------------------------------------------------------
I_RST_MODULE : entity axi_cdma_v4_1.axi_cdma_reset
generic map(
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_SOFT_RST_TIME_CLKS => C_SOFT_RST_TIME_CLKS
)
port map(
-- Primary Clock and Reset Sources
axi_aclk => axi_aclk ,
axi_resetn => axi_resetn ,
-- AXI Lite Clock and Reset Sources
axi_lite_aclk => axi_lite_aclk ,
axi_lite_resetn => axi_lite_resetn ,
-- CDMA Module hard reset outputs
rst2lite_bside_reset => sig_rst2lite_bside_reset ,
rst2lite_cside_reset => sig_rst2lite_cside_reset ,
rst2reg_reset => sig_rst2reg_reset ,
rst2cntlr_reset => sig_rst2cntlr_reset ,
rst2sgcntlr_reset => sig_rst2sgcntlr_reset ,
rst2sg_resetn => sig_rst2sg_resetn ,
rst2dm_resetn => sig_rst2dm_resetn ,
-- Soft Reset Request from Register module
reg2rst_soft_reset_in => sig_reg2rst_soft_reset ,
rst2reg_soft_reset_clr => sig_rst2reg_soft_reset_clr ,
-- CDMA Simple Controller halt
rst2cntlr_halt => sig_rst2cntlr_halt ,
cntlr2rst_halt_cmplt => sig_cntlr2rst_halt_cmplt ,
-- CDMA SG Controller halt
rst2sg_halt => sig_rst2sgcntl_halt ,
sg2rst_halt_cmplt => sig_sgcntl2rst_halt_cmplt ,
-- CDMA DatMover MM2S Halt
rst2dm_mm2s_halt => sig_rst2mm2s_halt ,
dm2rst_mm2s_halt_cmplt => sig_dm_mm2s_halt_cmplt ,
-- CDMA DatMover S2MM Halt
rst2dm_s2mm_halt => sig_rst2s2mm_halt ,
dm2rst_s2mm_halt_cmplt => sig_dm_s2mm_halt_cmplt
);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: REG_IF_MUX
--
-- Process Description:
-- This process implements a mux for Register Module input
-- signals that are shared between the Simple DMA mode and
-- SG mode operations.
--
-------------------------------------------------------------
REG_IF_MUX : process (sig_reg2cntlr_sg_mode,
sig_sgcntl2reg_idle_set ,
sig_sgcntl2reg_idle_clr ,
sig_sgcntl2reg_ioc_irq_set ,
sig_sgcntlr2reg_dma_decerr_set ,
sig_sgcntlr2reg_dma_slverr_set ,
sig_sgcntlr2reg_dma_interr_set ,
sig_cntlr2reg_idle_set ,
sig_cntlr2reg_idle_clr ,
sig_cntlr2reg_iocirpt_set ,
sig_cntlr2reg_decerr_set ,
sig_cntlr2reg_slverr_set ,
sig_cntlr2reg_interr_set
)
begin
case sig_reg2cntlr_sg_mode is
when '1' => -- SG Mode Enabled
sig_composite_idle_set <= sig_sgcntl2reg_idle_set ;
sig_composite_idle_clr <= sig_sgcntl2reg_idle_clr ;
sig_composite_iocirpt_set <= sig_sgcntl2reg_ioc_irq_set ;
sig_composite_dm_decerr_set <= sig_sgcntlr2reg_dma_decerr_set ;
sig_composite_dm_slverr_set <= sig_sgcntlr2reg_dma_slverr_set ;
sig_composite_dm_interr_set <= sig_sgcntlr2reg_dma_interr_set ;
when others => -- Simple DMA Enabled
sig_composite_idle_set <= sig_cntlr2reg_idle_set ;
sig_composite_idle_clr <= sig_cntlr2reg_idle_clr ;
sig_composite_iocirpt_set <= sig_cntlr2reg_iocirpt_set ;
sig_composite_dm_decerr_set <= sig_cntlr2reg_decerr_set ;
sig_composite_dm_slverr_set <= sig_cntlr2reg_slverr_set ;
sig_composite_dm_interr_set <= sig_cntlr2reg_interr_set ;
end case;
end process REG_IF_MUX;
------------------------------------------------------------
-- Instance: I_HYBRID_REG_MODULE
--
-- Description:
-- Instance for the Register Module used with Simple and
-- SG Mode operations.
--
------------------------------------------------------------
I_HYBRID_REG_MODULE : entity axi_cdma_v4_1.axi_cdma_reg_module
generic map(
C_CDMA_BUILD_MODE => CDMA_BUILD_MODE ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH
)
port map(
-- AXI Lite Clock and Reset
axi_lite_aclk => axi_lite_aclk ,
axi_lite_reset => sig_rst2lite_bside_reset ,
-- AXI Lite Core side Reset
axi_lite_cside_reset => sig_rst2lite_cside_reset ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
-- AXI Lite Read Data Channel
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- Register Clock and Reset
axi_aclk => axi_aclk ,
axi_reg_reset => sig_rst2reg_reset ,
-- Composite Interrupt Output
reg_introut => cdma_introut ,
-- Composite error Output
reg_error_out => cdma_error_out ,
-- Soft Reset Control
reg_soft_reset_request => sig_reg2rst_soft_reset ,
reg_soft_reset_clr => sig_rst2reg_soft_reset_clr ,
-- Simple DMA Go Control
reg_dma_go => sig_reg2cntlr_go ,
-- SG Mode control
reg_dma_sg_mode => sig_reg2cntlr_sg_mode ,
-- Key Hole write
dma_keyhole_write => dma_keyhole_write ,
-- Key Hole read
dma_keyhole_read => dma_keyhole_read ,
-- Key Hole read
dma_cyclic => dma_cyclic ,
-- CDMASR Control inputs
reg_idle_set => sig_composite_idle_set ,
reg_idle_clr => sig_composite_idle_clr ,
reg_ioc_irq_set => sig_composite_iocirpt_set ,
reg_dly_irq_set => sig_sgcntl2reg_dly_irq_set ,
-- Status from SG indicating current Delay and Thresh cntr values
reg_irqdelay_status => sig_sg2reg_irqdelay_status ,
reg_irqthresh_status => sig_sg2reg_irqthresh_status ,
-- Controls to SG to load new DMACR Delay and Thresh values
reg_irqthresh_wren => sig_reg2sg_irqthresh_wren ,
reg_irqdelay_wren => sig_reg2sg_irqdelay_wren ,
-- DataMover Errors
reg_dma_decerr_set => sig_composite_dm_decerr_set ,
reg_dma_slverr_set => sig_composite_dm_slverr_set ,
reg_dma_interr_set => sig_composite_dm_interr_set ,
-- SG Descriptor Fetch errors
reg_ftch_interr_set => sig_sg2reg_ftch_interr_set ,
reg_ftch_slverr_set => sig_sg2reg_ftch_slverr_set ,
reg_ftch_decerr_set => sig_sg2reg_ftch_decerr_set ,
reg_ftch_error_addr => sig_sg2reg_ftch_error_addr ,
-- SG Descriptor Update errors
reg_updt_interr_set => sig_sg2reg_updt_interr_set ,
reg_updt_slverr_set => sig_sg2reg_updt_slverr_set ,
reg_updt_decerr_set => sig_sg2reg_updt_decerr_set ,
reg_updt_error_addr => sig_sg2reg_updt_error_addr ,
-- From SG Controller CURDESC Update
reg_new_curdesc_wren => sig_sgcntlr2reg_new_curdesc_wren ,
reg_new_curdesc => sig_sgcntlr2reg_new_curdesc ,
-- To SG TAILDESC Update (also used to start SG operations in SGMode)
reg_tailpntr_updated => sig_reg2sg_tailpntr_updated ,
reg_currdesc_updated => sig_reg2sgcntlr_currdesc_updated,
-- Register State Out
reg_dmacr => sig_reg2sg_dmacr ,
reg_dmasr => sig_reg2sg_dmasr ,
reg_curdesc => sig_reg2sg_curdesc ,
reg_taildesc => sig_reg2sg_taildesc ,
reg_src_addr => sig_reg2cntlr_src_addr ,
reg_dest_addr => sig_reg2cntlr_dest_addr ,
reg_btt => sig_reg2cntlr_btt
);
------------------------------------------------------------
-- Instance: I_SIMPLE_DMA_CNTLR
--
-- Description:
--
-- Control Logic module for the Simple Mode CDMA operation.
--
------------------------------------------------------------
I_SIMPLE_DMA_CNTLR : entity axi_cdma_v4_1.axi_cdma_simple_cntlr
generic map(
C_DM_CMD_WIDTH => DM_CMD_WIDTH ,
C_DM_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_DM_MM2S_STATUS_WIDTH => DM_MM2S_STATUS_WIDTH ,
C_DM_S2MM_STATUS_WIDTH => BASE_STATUS_WIDTH ,
C_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_BTT_WIDTH => DM_BTT_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Clock and reset
axi_aclk => axi_aclk ,
axi_reset => sig_rst2cntlr_reset ,
-- Halt request
rst2cntlr_halt => sig_rst2cntlr_halt ,
cntlr2rst_halt_cmplt => sig_cntlr2rst_halt_cmplt ,
-- Register Module Start and Mode Controls
reg2cntlr_go => sig_reg2cntlr_go ,
reg2cntlr_sg_mode => sig_reg2cntlr_sg_mode ,
burst_type_read => dma_keyhole_read ,
burst_type_write => dma_keyhole_write ,
-- Register Module command qualifiers
reg2cntlr_src_addr => sig_reg2cntlr_src_addr ,
reg2cntlr_dest_addr => sig_reg2cntlr_dest_addr ,
reg2cntlr_btt => sig_reg2cntlr_btt(DM_BTT_WIDTH-1
downto 0) ,
-- General Status Bit controls
cntlr2reg_idle_set => sig_cntlr2reg_idle_set ,
cntlr2reg_idle_clr => sig_cntlr2reg_idle_clr ,
cntlr2reg_iocirpt_set => sig_cntlr2reg_iocirpt_set ,
-- DataMover Error Status bit controls
cntlr2reg_decerr_set => sig_cntlr2reg_decerr_set ,
cntlr2reg_slverr_set => sig_cntlr2reg_slverr_set ,
cntlr2reg_interr_set => sig_cntlr2reg_interr_set ,
-- DataMover MM2S Command Interface Ports (AXI Stream)
mm2s2cntl_cmd_tready => sig_mm2s2cntl_cmd_tready ,
cntl2mm2s_cmd_tvalid => sig_cntl2mm2s_cmd_tvalid ,
cntl2mm2s_cmd_tdata => sig_cntl2mm2s_cmd_tdata ,
-- DataMover MM2S Status Interface Ports (AXI Stream)
cntl2mm2s_sts_tready => sig_cntl2mm2s_sts_tready ,
mm2s2cntl_sts_tvalid => sig_mm2s2cntl_sts_tvalid ,
mm2s2cntl_sts_tdata => sig_dm_mm2s_sts_tdata ,
mm2s2cntl_sts_tstrb => sig_dm_mm2s_sts_tkeep ,
-- DataMover MM2S error discrete
mm2s2cntl_err => sig_dm_mm2s_err ,
-- DataMover S2MM Command Interface Ports (AXI Stream)
cntl2s2mm_cmd_tdata => sig_cntl2s2mm_cmd_tdata ,
cntl2s2mm_cmd_tvalid => sig_cntl2s2mm_cmd_tvalid ,
s2mm2cntl_cmd_tready => sig_s2mm2cntl_cmd_tready ,
-- DataMover S2MM Status Interface Ports (AXI Stream)
s2mm2cntl_sts_tdata => sig_s2mm2sgcntl_sts_tdata ,
s2mm2cntl_sts_tstrb => sig_s2mm2sgcntl_sts_tstrb ,
s2mm2cntl_sts_tvalid => sig_s2mm2cntl_sts_tvalid ,
cntl2s2mm_sts_tready => sig_cntl2s2mm_sts_tready ,
-- DataMover S2MM error discrete
s2mm2cntl_err => sig_dm_s2mm_err
);
------------------------------------------------------------
-- Instance: I_SG_CNTLR
--
-- Description:
--
-- Control Logic module for the Scatter Gather Mode CDMA
-- operation.
--
------------------------------------------------------------
I_SG_CNTLR : entity axi_cdma_v4_1.axi_cdma_sg_cntlr
generic map(
C_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_SG_FETCH_DWIDTH => SG_FETCH_DWIDTH ,
C_SG_PTR_UPDATE_DWIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_SG_STS_UPDATE_DWIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_DM_CMD_WIDTH => DM_CMD_WIDTH ,
C_DM_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_DM_MM2S_STATUS_WIDTH => DM_MM2S_STATUS_WIDTH ,
C_DM_S2MM_STATUS_WIDTH => BASE_STATUS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Clock and reset
axi_aclk => axi_aclk ,
axi_reset => sig_rst2sgcntlr_reset ,
-- Halt request
rst2sgcntl_halt => sig_rst2sgcntl_halt ,
sgcntl2rst_halt_cmplt => sig_sgcntl2rst_halt_cmplt ,
sgcntlr2sg_desc_flush => sig_sgcntlr2sg_desc_flush ,
-- MM2S Type of Burst, 1 is increment, 0 is fixed
burst_type_read => dma_keyhole_read ,
-- S2MM Type of Burst, 1 is increment, 0 is fixed
burst_type_write => dma_keyhole_write ,
-- Register Module Start and Mode Controls
reg2sgcntl_sg_mode => sig_reg2cntlr_sg_mode ,
reg2sgcntl_tailpntr_updated => sig_reg2sg_tailpntr_updated ,
reg2sgcntl_currdesc_updated => sig_reg2sgcntlr_currdesc_updated ,
-- Misc Controls to SG
sgcntlr2sg_run_stop => sig_sgcntlr2sg_run_stop ,
-- Idle bit control to Register
sgcntl2reg_idle_set => sig_sgcntl2reg_idle_set ,
sgcntl2reg_idle_clr => sig_sgcntl2reg_idle_clr ,
-- SOF/EOF control to SG
sgcntl2sg_pkt_sof => sig_sgcntl2sg_pkt_sof ,
sgcntl2sg_pkt_eof => sig_sgcntl2sg_pkt_eof ,
-- Interrupt status from SG
sg2sgcntl_ioc_irq_set => sig_sg2sgcntl_ioc_irq_set ,
sg2sgcntl_dly_irq_set => sig_sg2sgcntl_dly_irq_set ,
-- Interrupt control to Register
sgcntl2reg_ioc_irq_set => sig_sgcntl2reg_ioc_irq_set ,
sgcntl2reg_dly_irq_set => sig_sgcntl2reg_dly_irq_set ,
-- Descriptor Fetch Stream from SG
sgcntl2sg_ftch_tready => sig_sgcntl2sg_ftch_tready ,
sg2sgcntlr_ftch_tvalid => sig_sg2sgcntlr_ftch_tvalid ,
sg2sgcntlr_ftch_tvalid_new => sig_sg2sgcntlr_ftch_tvalid_new ,
sg2sgcntlr_ftch_tdata => sig_sg2sgcntlr_ftch_tdata ,
sg2sgcntlr_ftch_tdata_new => sig_sg2sgcntlr_ftch_tdata_new ,
sg2sgcntlr_ftch_tlast => sig_sg2sgcntlr_ftch_tlast ,
sig_sg2sgcntlr_ftch_desc_available => sig_sg2sgcntlr_ftch_desc_available ,
-- Descriptor Pointer Update Stream to SG
sg2sgcntlr_updptr_tready => sig_sg2sgcntlr_updptr_tready ,
sgcntl2sg_updptr_tvalid => sig_sgcntl2sg_updptr_tvalid ,
sgcntl2sg_updptr_tdata => sig_sgcntl2sg_updptr_tdata ,
sgcntl2sg_updptr_tlast => sig_sgcntl2sg_updptr_tlast ,
-- Descriptor Status Update Stream to SG
sg2sgcntlr_updsts_tready => sig_sg2sgcntlr_updsts_tready ,
sgcntl2sg_updsts_tvalid => sig_sgcntl2sg_updsts_tvalid ,
sgcntl2sg_updsts_tdata => sig_sgcntl2sg_updsts_tdata ,
sgcntl2sg_updsts_tlast => sig_sgcntl2sg_updsts_tlast ,
-- Descriptor Fetch status from SG
sg2sgcntlr_ftch_idle => sig_sg2sgcntlr_ftch_idle ,
sg2sgcntlr_ftch_err_early => sig_sg2sgcntlr_ftch_err_early ,
sg2sgcntlr_ftch_stale_desc => sig_sg2sgcntlr_ftch_stale_desc ,
sg2sgcntlr_ftch_error => sig_sg2sgcntlr_ftch_error ,
-- Descriptor Update status from SG
sg2sgcntlr_updt_idle => sig_sg2sgcntlr_updt_idle ,
sg2sgcntlr_updt_ioc_irq_set => sig_sg2sgcntlr_updt_ioc_irq_set ,
sg2sgcntlr_updt_error => sig_sg2sgcntlr_updt_error ,
-- Echo of Main DataMover detected errors from SG
sg2sgcntlr_dma_interr_set => sig_sg2sgcntlr_dma_interr_set ,
sg2sgcntlr_dma_slverr_set => sig_sg2sgcntlr_dma_slverr_set ,
sg2sgcntlr_dma_decerr_set => sig_sg2sgcntlr_dma_decerr_set ,
-- Main DM Error bit controls to Register
sgcntlr2reg_dma_interr_set => sig_sgcntlr2reg_dma_interr_set ,
sgcntlr2reg_dma_slverr_set => sig_sgcntlr2reg_dma_slverr_set ,
sgcntlr2reg_dma_decerr_set => sig_sgcntlr2reg_dma_decerr_set ,
-- Current DEscriptor Update control to Register
sgcntlr2reg_new_curdesc_wren => sig_sgcntlr2reg_new_curdesc_wren ,
sgcntlr2reg_new_curdesc => sig_sgcntlr2reg_new_curdesc ,
-- DataMover MM2S Command Interface Ports (AXI Stream)
mm2s2sgcntl_cmd_tready => sig_mm2s2sgcntl_cmd_tready ,
sgcntl2mm2s_cmd_tvalid => sig_sgcntl2mm2s_cmd_tvalid ,
sgcntl2mm2s_cmd_tdata => sig_sgcntl2mm2s_cmd_tdata ,
-- DataMover MM2S Status Interface Ports (AXI Stream)
sgcntl2mm2s_sts_tready => sig_sgcntl2mm2s_sts_tready ,
mm2s2sgcntl_sts_tvalid => sig_mm2s2sgcntl_sts_tvalid ,
mm2s2sgcntl_sts_tdata => sig_dm_mm2s_sts_tdata ,
mm2s2sgcntl_sts_tstrb => sig_dm_mm2s_sts_tkeep ,
-- DataMover MM2S error discrete
mm2s2sgcntl_err => sig_dm_mm2s_err ,
-- DataMover MM2S Halt
sgcntl2mm2s_halt => sig_sgcntl2mm2s_halt ,
mm2s2sgcntl_halt_cmplt => sig_dm_mm2s_halt_cmplt ,
-- DataMover S2MM Command Interface Ports (AXI Stream)
s2mm2sgcntl_cmd_tready => sig_s2mm2sgcntl_cmd_tready ,
sgcntl2s2mm_cmd_tvalid => sig_sgcntl2s2mm_cmd_tvalid ,
sgcntl2s2mm_cmd_tdata => sig_sgcntl2s2mm_cmd_tdata ,
-- DataMover S2MM Status Interface Ports (AXI Stream)
sgcntl2s2mm_sts_tready => sig_sgcntl2s2mm_sts_tready ,
s2mm2sgcntl_sts_tvalid => sig_s2mm2sgcntl_sts_tvalid ,
s2mm2sgcntl_sts_tdata => sig_s2mm2sgcntl_sts_tdata ,
s2mm2sgcntl_sts_tstrb => sig_s2mm2sgcntl_sts_tstrb ,
-- DataMover S2MM error discrete
s2mm2sgcntl_err => sig_dm_s2mm_err ,
-- DataMover MM2S Halt
sgcntl2s2mm_halt => sig_sgcntl2s2mm_halt ,
s2mm2sgcntl_halt_cmplt => sig_dm_s2mm_halt_cmplt
);
-------------------------------------------------------------------------------
-- Scatter Gather Engine
-------------------------------------------------------------------------------
I_SG_ENGINE : entity axi_sg_v4_1.axi_sg
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH ,
C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD ,
C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERROR ,
C_INCLUDE_CH1 => INCLUDE_CH1 ,
C_INCLUDE_CH2 => OMIT_CH2 ,
C_INCLUDE_DESC_UPDATE => INCLUDE_UPDATE_ENG ,
C_INCLUDE_INTRPT => INCLUDE_IRPT_CNTLR ,
C_INCLUDE_DLYTMR => INCLUDE_DLY_TIMER ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_AXIS_IS_ASYNC => 0 ,
C_ENABLE_MULTI_CHANNEL => 0 ,
C_ENABLE_CDMA => 1 ,
C_NUM_S2MM_CHANNELS => 1 ,
C_NUM_MM2S_CHANNELS => 1 ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => axi_aclk ,
m_axi_mm2s_aclk => axi_aclk ,
p_reset_n => '1' ,
m_axi_sg_aresetn => sig_rst2sg_resetn ,
dm_resetn => sig_rst2dm_resetn ,
sg_ctl => "00000000" ,
-- Scatter Gather Write Address Channel
m_axi_sg_awaddr => m_axi_sg_awaddr ,
m_axi_sg_awlen => m_axi_sg_awlen ,
m_axi_sg_awsize => m_axi_sg_awsize ,
m_axi_sg_awburst => m_axi_sg_awburst ,
m_axi_sg_awprot => m_axi_sg_awprot ,
m_axi_sg_awcache => m_axi_sg_awcache ,
m_axi_sg_awuser => open, --m_axi_sg_awcache ,
m_axi_sg_awvalid => m_axi_sg_awvalid ,
m_axi_sg_awready => m_axi_sg_awready ,
-- Scatter Gather Write Data Channel
m_axi_sg_wdata => m_axi_sg_wdata ,
m_axi_sg_wstrb => m_axi_sg_wstrb ,
m_axi_sg_wlast => m_axi_sg_wlast ,
m_axi_sg_wvalid => m_axi_sg_wvalid ,
m_axi_sg_wready => m_axi_sg_wready ,
-- Scatter Gather Write Response Channel
m_axi_sg_bresp => m_axi_sg_bresp ,
m_axi_sg_bvalid => m_axi_sg_bvalid ,
m_axi_sg_bready => m_axi_sg_bready ,
-- Scatter Gather Read Address Channel
m_axi_sg_araddr => m_axi_sg_araddr ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
m_axi_sg_aruser => open, --m_axi_sg_arcache ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_arready => m_axi_sg_arready ,
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rready => m_axi_sg_rready ,
-- Channel 1 Control and Status
ch1_run_stop => sig_sgcntlr2sg_run_stop ,
ch1_cyclic => dma_cyclic,
ch1_desc_flush => sig_sgcntlr2sg_desc_flush ,
ch1_cntrl_strm_stop => '0' ,
ch1_ftch_idle => sig_sg2sgcntlr_ftch_idle ,
ch1_ftch_interr_set => sig_sg2reg_ftch_interr_set ,
ch1_ftch_slverr_set => sig_sg2reg_ftch_slverr_set ,
ch1_ftch_decerr_set => sig_sg2reg_ftch_decerr_set ,
ch1_ftch_err_early => sig_sg2sgcntlr_ftch_err_early ,
ch1_ftch_stale_desc => sig_sg2sgcntlr_ftch_stale_desc ,
ch1_updt_idle => sig_sg2sgcntlr_updt_idle ,
ch1_updt_ioc_irq_set => sig_sg2sgcntlr_updt_ioc_irq_set ,
ch1_updt_interr_set => sig_sg2reg_updt_interr_set ,
ch1_updt_slverr_set => sig_sg2reg_updt_slverr_set ,
ch1_updt_decerr_set => sig_sg2reg_updt_decerr_set ,
ch1_dma_interr_set => sig_sg2sgcntlr_dma_interr_set ,
ch1_dma_slverr_set => sig_sg2sgcntlr_dma_slverr_set ,
ch1_dma_decerr_set => sig_sg2sgcntlr_dma_decerr_set ,
ch1_tailpntr_enabled => sig_reg2sg_dmacr(DMACR_TAILPEN_BIT) ,
ch1_taildesc_wren => sig_reg2sg_tailpntr_updated ,
ch1_taildesc => sig_reg2sg_taildesc ,
ch1_curdesc => sig_reg2sg_curdesc ,
-- Channel 1 Interrupt Coalescing Signals
ch1_irqthresh_rstdsbl => LOGIC_LOW ,
ch1_dlyirq_dsble => sig_reg2sg_dmasr(DMASR_DLYIRQ_BIT) ,
ch1_irqdelay_wren => sig_reg2sg_irqdelay_wren ,
ch1_irqdelay => sig_reg2sg_dmacr(DMACR_IRQDELAY_MSB_BIT downto
DMACR_IRQDELAY_LSB_BIT) ,
ch1_irqthresh_wren => sig_reg2sg_irqthresh_wren ,
ch1_irqthresh => sig_reg2sg_dmacr(DMACR_IRQTHRESH_MSB_BIT downto
DMACR_IRQTHRESH_LSB_BIT) ,
ch1_packet_sof => sig_sgcntl2sg_pkt_sof ,
ch1_packet_eof => sig_sgcntl2sg_pkt_eof ,
ch1_ioc_irq_set => sig_sg2sgcntl_ioc_irq_set ,
ch1_dly_irq_set => sig_sg2sgcntl_dly_irq_set ,
ch1_irqdelay_status => sig_sg2reg_irqdelay_status ,
ch1_irqthresh_status => sig_sg2reg_irqthresh_status ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => axi_aclk ,
m_axis_ch1_ftch_tdata => sig_sg2sgcntlr_ftch_tdata ,
m_axis_ch1_ftch_tdata_new => sig_sg2sgcntlr_ftch_tdata_new ,
m_axis_ch1_ftch_tvalid => sig_sg2sgcntlr_ftch_tvalid ,
m_axis_ch1_ftch_tvalid_new => sig_sg2sgcntlr_ftch_tvalid_new ,
m_axis_ch1_ftch_tready => sig_sgcntl2sg_ftch_tready ,
m_axis_ch1_ftch_tlast => sig_sg2sgcntlr_ftch_tlast ,
m_axis_ftch1_desc_available => sig_sg2sgcntlr_ftch_desc_available,
-- Channel 1 Pointer Update Stream In
s_axis_ch1_updt_aclk => axi_aclk ,
s_axis_ch1_updtptr_tdata => sig_sgcntl2sg_updptr_tdata ,
s_axis_ch1_updtptr_tvalid => sig_sgcntl2sg_updptr_tvalid ,
s_axis_ch1_updtptr_tready => sig_sg2sgcntlr_updptr_tready ,
s_axis_ch1_updtptr_tlast => sig_sgcntl2sg_updptr_tlast ,
-- Channel 1 Status Update Stream In
s_axis_ch1_updtsts_tdata => sig_sgcntl2sg_updsts_tdata ,
s_axis_ch1_updtsts_tvalid => sig_sgcntl2sg_updsts_tvalid ,
s_axis_ch1_updtsts_tready => sig_sg2sgcntlr_updsts_tready ,
s_axis_ch1_updtsts_tlast => sig_sgcntl2sg_updsts_tlast ,
-- Channel 2 Control and Status
ch2_run_stop => LOGIC_LOW ,
ch2_cyclic => '0',
ch2_desc_flush => LOGIC_LOW ,
ch2_ftch_idle => open ,
ch2_ftch_interr_set => open ,
ch2_ftch_slverr_set => open ,
ch2_ftch_decerr_set => open ,
ch2_ftch_err_early => open ,
ch2_ftch_stale_desc => open ,
ch2_updt_idle => open ,
ch2_updt_ioc_irq_set => open ,
ch2_updt_interr_set => open ,
ch2_updt_slverr_set => open ,
ch2_updt_decerr_set => open ,
ch2_dma_interr_set => open ,
ch2_dma_slverr_set => open ,
ch2_dma_decerr_set => open ,
ch2_tailpntr_enabled => LOGIC_LOW ,
ch2_taildesc_wren => LOGIC_LOW ,
ch2_taildesc => SG_ADDR_ZEROS ,
ch2_curdesc => SG_ADDR_ZEROS ,
-- Channel 2 Interrupt Coalescing Signals
ch2_irqthresh_rstdsbl => LOGIC_LOW ,
ch2_dlyirq_dsble => LOGIC_LOW ,
ch2_irqdelay_wren => LOGIC_LOW ,
ch2_irqdelay => IRQ_DLY_THRESH_ZEROS ,
ch2_irqthresh_wren => LOGIC_LOW ,
ch2_irqthresh => IRQ_DLY_THRESH_ZEROS ,
ch2_packet_sof => LOGIC_LOW ,
ch2_packet_eof => LOGIC_LOW ,
ch2_ioc_irq_set => open ,
ch2_dly_irq_set => open ,
ch2_irqdelay_status => open ,
ch2_irqthresh_status => open ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => axi_aclk ,
m_axis_ch2_ftch_tdata => open ,
m_axis_ch2_ftch_tvalid => open ,
m_axis_ch2_ftch_tready => LOGIC_LOW ,
m_axis_ch2_ftch_tlast => open ,
-- Channel 2 Pointer Update Stream In
s_axis_ch2_updt_aclk => axi_aclk ,
s_axis_ch2_updtptr_tdata => SG_UPDPTR_DATA_ZEROS ,
s_axis_ch2_updtptr_tvalid => LOGIC_LOW ,
s_axis_ch2_updtptr_tready => open ,
s_axis_ch2_updtptr_tlast => LOGIC_LOW ,
-- Channel 2 Status Update Stream In
s_axis_ch2_updtsts_tdata => SG_UPDSTS_DATA_ZEROS ,
s_axis_ch2_updtsts_tvalid => LOGIC_LOW ,
s_axis_ch2_updtsts_tready => open ,
s_axis_ch2_updtsts_tlast => LOGIC_LOW ,
-- Error addresses
ftch_error => sig_sg2sgcntlr_ftch_error ,
ftch_error_addr => sig_sg2reg_ftch_error_addr ,
updt_error => sig_sg2sgcntlr_updt_error ,
updt_error_addr => sig_sg2reg_updt_error_addr
);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DM_IF_MUX
--
-- Process Description:
-- THis process implements a multiplexer for the input controls
-- to the Main dataMover that are driven by the Simple Mode
-- Controller or the SG Mode Controller.
--
-------------------------------------------------------------
DM_IF_MUX : process (sig_reg2cntlr_sg_mode ,
sig_sgcntl2mm2s_cmd_tdata ,
sig_sgcntl2mm2s_cmd_tvalid ,
sig_sgcntl2mm2s_sts_tready ,
sig_sgcntl2s2mm_cmd_tdata ,
sig_sgcntl2s2mm_cmd_tvalid ,
sig_sgcntl2s2mm_sts_tready ,
sig_cntl2mm2s_cmd_tdata ,
sig_cntl2mm2s_cmd_tvalid ,
sig_cntl2mm2s_sts_tready ,
sig_cntl2s2mm_cmd_tdata ,
sig_cntl2s2mm_cmd_tvalid ,
sig_cntl2s2mm_sts_tready ,
sig_sgcntl2mm2s_halt ,
sig_sgcntl2s2mm_halt ,
sig_rst2mm2s_halt ,
sig_rst2s2mm_halt
)
begin
case sig_reg2cntlr_sg_mode is
when '1' => -- SG Mode Enabled
sig_dm_mm2s_cmd_tdata <= sig_sgcntl2mm2s_cmd_tdata ;
sig_dm_mm2s_cmd_tvalid <= sig_sgcntl2mm2s_cmd_tvalid ;
sig_dm_mm2s_sts_tready <= sig_sgcntl2mm2s_sts_tready ;
sig_dm_s2mm_cmd_tdata <= sig_sgcntl2s2mm_cmd_tdata ;
sig_dm_s2mm_cmd_tvalid <= sig_sgcntl2s2mm_cmd_tvalid ;
sig_dm_s2mm_sts_tready <= sig_sgcntl2s2mm_sts_tready ;
sig_dm_mm2s_halt <= sig_sgcntl2mm2s_halt ;
sig_dm_s2mm_halt <= sig_sgcntl2s2mm_halt ;
when others => -- Simple DMA Enabled
sig_dm_mm2s_cmd_tdata <= sig_cntl2mm2s_cmd_tdata ;
sig_dm_mm2s_cmd_tvalid <= sig_cntl2mm2s_cmd_tvalid ;
sig_dm_mm2s_sts_tready <= sig_cntl2mm2s_sts_tready ;
sig_dm_s2mm_cmd_tdata <= sig_cntl2s2mm_cmd_tdata ;
sig_dm_s2mm_cmd_tvalid <= sig_cntl2s2mm_cmd_tvalid ;
sig_dm_s2mm_sts_tready <= sig_cntl2s2mm_sts_tready ;
sig_dm_mm2s_halt <= sig_rst2mm2s_halt ;
sig_dm_s2mm_halt <= sig_rst2s2mm_halt ;
end case;
end process DM_IF_MUX;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DM_RDY_VLD_DEMUX
--
-- Process Description:
-- This process implements a demultiplexer for the DataMover
-- Ready/Valid signals driven back to the Simple Mode Controller
-- and the SG Mode Controller. Data and Strobes are not
-- Demux'd.
--
-------------------------------------------------------------
DM_RDY_VLD_DEMUX : process (sig_reg2cntlr_sg_mode ,
sig_dm_mm2s_cmd_tready ,
sig_dm_mm2s_sts_tvalid ,
sig_dm_s2mm_cmd_tready ,
sig_dm_s2mm_sts_tvalid
)
begin
case sig_reg2cntlr_sg_mode is
when '1' => -- SG Mode Enabled
sig_mm2s2cntl_cmd_tready <= '0';
sig_mm2s2sgcntl_cmd_tready <= sig_dm_mm2s_cmd_tready;
sig_mm2s2cntl_sts_tvalid <= '0';
sig_mm2s2sgcntl_sts_tvalid <= sig_dm_mm2s_sts_tvalid;
sig_s2mm2cntl_cmd_tready <= '0';
sig_s2mm2sgcntl_cmd_tready <= sig_dm_s2mm_cmd_tready;
sig_s2mm2cntl_sts_tvalid <= '0';
sig_s2mm2sgcntl_sts_tvalid <= sig_dm_s2mm_sts_tvalid;
when others => -- Simple DMA Mode Enabled
sig_mm2s2cntl_cmd_tready <= sig_dm_mm2s_cmd_tready;
sig_mm2s2sgcntl_cmd_tready <= '0';
sig_mm2s2cntl_sts_tvalid <= sig_dm_mm2s_sts_tvalid;
sig_mm2s2sgcntl_sts_tvalid <= '0';
sig_s2mm2cntl_cmd_tready <= sig_dm_s2mm_cmd_tready;
sig_s2mm2sgcntl_cmd_tready <= '0';
sig_s2mm2cntl_sts_tvalid <= sig_dm_s2mm_sts_tvalid;
sig_s2mm2sgcntl_sts_tvalid <= '0';
end case;
end process DM_RDY_VLD_DEMUX;
---------------------------------------------------------------------------------------
-- DataMover and support
-- Rip the basic status output from the DataMover S2MM status reply stream
sig_s2mm2sgcntl_sts_tdata <= sig_dm_s2mm_sts_tdata(BASE_STATUS_WIDTH-1 downto 0);
sig_s2mm2sgcntl_sts_tstrb <= sig_dm_s2mm_sts_tkeep((BASE_STATUS_WIDTH/8)-1 downto 0);
------------------------------------------------------------
-- Instance: I_DATAMOVER
--
-- Description:
--
-- Data Path DataMover
-- Reads data from the AXI MMAP Read Channel and Writes the data
-- to the AXI MMAP Write Channel via commands from the Controller
-- Module.
--
--
------------------------------------------------------------
I_DATAMOVER : entity axi_datamover_v5_1.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_FULL_MODE ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_M_AXIS_MM2S_TDATA_WIDTH => DM_STREAM_DWIDTH ,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => DM_SG_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => DM_USE_SYNC_CLOCKS ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_DRE ,
C_MM2S_BURST_SIZE => C_M_AXI_MAX_BURST_LEN ,
C_MM2S_BTT_USED => DM_BTT_WIDTH ,
C_MM2S_ADDR_PIPE_DEPTH => DM_READ_ADDR_PIPE_DEPTH ,
C_MM2S_INCLUDE_SF => 0 ,
C_ENABLE_CACHE_USER => 0 ,
C_ENABLE_SKID_BUF => "11000" ,
C_INCLUDE_S2MM => S2MM_FULL_MODE ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_S_AXIS_S2MM_TDATA_WIDTH => DM_STREAM_DWIDTH ,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => DM_SG_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => DM_USE_SYNC_CLOCKS ,
C_INCLUDE_S2MM_DRE => DM_S2MM_DRE_DISABLED ,
C_S2MM_BURST_SIZE => C_M_AXI_MAX_BURST_LEN ,
C_S2MM_BTT_USED => DM_BTT_WIDTH ,
C_S2MM_SUPPORT_INDET_BTT => STORE_FORWARD_CNTL ,
C_S2MM_ADDR_PIPE_DEPTH => DM_WRITE_ADDR_PIPE_DEPTH ,
C_S2MM_INCLUDE_SF => 0 ,
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => axi_aclk ,
m_axi_mm2s_aresetn => sig_rst2dm_resetn ,
-- MM2S Soft Shutdown
mm2s_halt => sig_dm_mm2s_halt ,
mm2s_halt_cmplt => sig_dm_mm2s_halt_cmplt ,
-- MM2S Error output discrete
mm2s_err => sig_dm_mm2s_err ,
-- Memory Map to Stream Command FIFO and Status FIFO Async CLK/RST --------------
m_axis_mm2s_cmdsts_aclk => LOGIC_LOW ,
m_axis_mm2s_cmdsts_aresetn => LOGIC_HIGH ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => sig_dm_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => sig_dm_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => sig_dm_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => sig_dm_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => sig_dm_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => sig_dm_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => sig_dm_mm2s_sts_tkeep ,
m_axis_mm2s_sts_tlast => open ,
-- Address Posting contols
mm2s_allow_addr_req => sig_mm2s_allow_addr_req ,
mm2s_addr_req_posted => sig_mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => sig_mm2s_rd_xfer_cmplt ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_araddr ,
m_axi_mm2s_arlen => m_axi_arlen ,
m_axi_mm2s_arsize => m_axi_arsize ,
m_axi_mm2s_arburst => m_axi_arburst ,
m_axi_mm2s_arprot => m_axi_arprot ,
m_axi_mm2s_arcache => m_axi_arcache ,
m_axi_mm2s_aruser => open, --m_axi_arcache ,
m_axi_mm2s_arvalid => m_axi_arvalid ,
m_axi_mm2s_arready => m_axi_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_rdata ,
m_axi_mm2s_rresp => m_axi_rresp ,
m_axi_mm2s_rlast => m_axi_rlast ,
m_axi_mm2s_rvalid => m_axi_rvalid ,
m_axi_mm2s_rready => m_axi_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => sig_mm2s_axis_tdata ,
m_axis_mm2s_tkeep => sig_mm2s_axis_tkeep ,
m_axis_mm2s_tlast => sig_mm2s_axis_tlast ,
m_axis_mm2s_tvalid => sig_mm2s_axis_tvalid ,
m_axis_mm2s_tready => sig_mm2s_axis_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => axi_aclk ,
m_axi_s2mm_aresetn => sig_rst2dm_resetn ,
-- S2MM Soft Shutdown
s2mm_halt => sig_dm_s2mm_halt ,
s2mm_halt_cmplt => sig_dm_s2mm_halt_cmplt ,
-- S2MM Error output discrete
s2mm_err => sig_dm_s2mm_err ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => LOGIC_LOW ,
m_axis_s2mm_cmdsts_aresetn => LOGIC_HIGH ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => sig_dm_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => sig_dm_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => sig_dm_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => sig_dm_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => sig_dm_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => sig_dm_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => sig_dm_s2mm_sts_tkeep ,
m_axis_s2mm_sts_tlast => open ,
-- Address posting controls
s2mm_allow_addr_req => sig_s2mm_allow_addr_req ,
s2mm_addr_req_posted => sig_s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len ,
s2mm_wr_len => sig_s2mm_wr_len ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_awaddr ,
m_axi_s2mm_awlen => m_axi_awlen ,
m_axi_s2mm_awsize => m_axi_awsize ,
m_axi_s2mm_awburst => m_axi_awburst ,
m_axi_s2mm_awprot => m_axi_awprot ,
m_axi_s2mm_awcache => m_axi_awcache ,
m_axi_s2mm_awuser => open, --m_axi_awcache ,
m_axi_s2mm_awvalid => m_axi_awvalid ,
m_axi_s2mm_awready => m_axi_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_wdata ,
m_axi_s2mm_wstrb => m_axi_wstrb ,
m_axi_s2mm_wlast => m_axi_wlast ,
m_axi_s2mm_wvalid => m_axi_wvalid ,
m_axi_s2mm_wready => m_axi_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_bresp ,
m_axi_s2mm_bvalid => m_axi_bvalid ,
m_axi_s2mm_bready => m_axi_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => sig_s2mm_axis_tdata ,
s_axis_s2mm_tkeep => sig_s2mm_axis_tkeep ,
s_axis_s2mm_tlast => sig_s2mm_axis_tlast ,
s_axis_s2mm_tvalid => sig_s2mm_axis_tvalid ,
s_axis_s2mm_tready => sig_s2mm_axis_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SF
--
-- If Generate Description:
-- This IfGen includes the Store and Forward module
--
--
------------------------------------------------------------
GEN_INCLUDE_SF : if (C_INCLUDE_SF = 1) generate
begin
------------------------------------------------------------
-- Instance: I_STORE_FORWARD
--
-- Description:
-- This is the instance for the AXI CDMA Store and Forward
-- Module.
--
------------------------------------------------------------
I_STORE_FORWARD : entity axi_cdma_v4_1.axi_cdma_sf
generic map (
C_WR_ADDR_PIPE_DEPTH => DM_WRITE_ADDR_PIPE_DEPTH,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MAX_BURST_LEN => C_M_AXI_MAX_BURST_LEN ,
C_DRE_IS_USED => C_INCLUDE_DRE ,
C_STREAM_DWIDTH => C_M_AXI_DATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input
aclk => axi_aclk ,
-- Reset input
reset => sig_sf_reset ,
-- DataMover Read Side Address Pipelining control Interface ----
ok_to_post_rd_addr => sig_mm2s_allow_addr_req ,
rd_addr_posted => sig_mm2s_addr_req_posted ,
rd_xfer_cmplt => sig_mm2s_rd_xfer_cmplt ,
-- Read Side Stream In from DataMover MM2S ---------------------
sf2sin_tready => sig_mm2s_axis_tready ,
sin2sf_tvalid => sig_mm2s_axis_tvalid ,
sin2sf_tdata => sig_mm2s_axis_tdata ,
sin2sf_tkeep => sig_mm2s_axis_tkeep ,
sin2sf_tlast => sig_mm2s_axis_tlast ,
-- DataMover Write Side Address Pipelining control Interface ---
ok_to_post_wr_addr => sig_s2mm_allow_addr_req ,
wr_addr_posted => sig_s2mm_addr_req_posted ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
wr_ld_nxt_len => sig_s2mm_ld_nxt_len ,
wr_len => sig_s2mm_wr_len ,
-- Write Side Stream Out to DataMover S2MM --------------------
sout2sf_tready => sig_s2mm_axis_tready ,
sf2sout_tvalid => sig_s2mm_axis_tvalid ,
sf2sout_tdata => sig_s2mm_axis_tdata ,
sf2sout_tkeep => sig_s2mm_axis_tkeep ,
sf2sout_tlast => sig_s2mm_axis_tlast
);
end generate GEN_INCLUDE_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SF
--
-- If Generate Description:
-- This IfGen includes the Store and Forward module
--
--
------------------------------------------------------------
GEN_OMIT_SF : if (C_INCLUDE_SF = 0) generate
begin
sig_mm2s_allow_addr_req <= LOGIC_HIGH;
sig_s2mm_allow_addr_req <= LOGIC_HIGH;
sig_mm2s_axis_tready <= sig_s2mm_axis_tready ;
sig_s2mm_axis_tvalid <= sig_mm2s_axis_tvalid ;
sig_s2mm_axis_tdata <= sig_mm2s_axis_tdata ;
sig_s2mm_axis_tkeep <= sig_mm2s_axis_tkeep ;
sig_s2mm_axis_tlast <= sig_mm2s_axis_tlast ;
end generate GEN_OMIT_SF;
end implementation;
| gpl-3.0 | 2df11976ecf23ecab7aa896e65412182 | 0.470503 | 3.826521 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep3c25-eek/altera_eek_clkgen.vhd | 1 | 4,171 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity altera_eek_clkgen is
generic (
clk0_mul : integer := 1;
clk0_div : integer := 1;
clk1_mul : integer := 1;
clk1_div : integer := 1;
clk_freq : integer := 25000);
port (
inclk0 : in std_ulogic;
clk0 : out std_ulogic;
clk0x3 : out std_ulogic;
clksel : in std_logic_vector(1 downto 0);
locked : out std_ulogic);
end;
architecture rtl of altera_eek_clkgen is
component altpll
generic (
intended_device_family : string := "CycloneIII" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "clock0";
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
clk3_multiply_by : positive := 1;
clk3_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (4 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK0_MUL3X : integer := clk0_mul * 3;
constant CLK1_MUL3X : integer := clk1_mul * 3;
constant VERSION : integer := 1;
attribute syn_keep : boolean;
attribute syn_keep of clkout : signal is true;
begin
clkena(5 downto 4) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1';
clkena(2) <= '1';
clkena(3) <= '1';
inclk <= '0' & inclk0;
clk_select: process (clkout, clksel)
begin -- process clk_select
case clksel is
when "00" => clk0 <= clkout(0); clk0x3 <= clkout(1);
when "01" => clk0 <= clkout(2); clk0x3 <= clkout(3);
when others => clk0 <= '0'; clk0x3 <= '0';
end case;
end process clk_select;
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "NO_COMPENSATION", inclk0_input_frequency => clk_period,
width_clock => 5, compensate_clock => "CLK1",
clk0_multiply_by => clk0_mul, clk0_divide_by => clk0_div,
clk1_multiply_by => CLK0_MUL3X, clk1_divide_by => clk0_div,
clk2_multiply_by => clk1_mul, clk2_divide_by => clk1_div,
clk3_multiply_by => CLK1_MUL3X, clk3_divide_by => clk1_div)
port map (clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_cycloneiii" & ": altpll lcd/vga clock generator, version " & tost(VERSION)
);
-- pragma translate_on
end;
| gpl-2.0 | 840d0de3b84a0a5d194ecd9e7378b626 | 0.60537 | 3.55584 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/uart/ahbuart.vhd | 1 | 2,654 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbuart
-- File: ahbuart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UART with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
use gaisler.uart.all;
use gaisler.libdcom.all;
entity ahbuart is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
uarti : in uart_in_type;
uarto : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type );
end;
architecture struct of ahbuart is
constant REVISION : integer := 0;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal duarti : dcom_uart_in_type;
signal duarto : dcom_uart_out_type;
begin
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER, devid => GAISLER_AHBUART)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
dcom_uart0 : dcom_uart generic map (pindex, paddr, pmask)
port map (rst, clk, uarti, uarto, apbi, apbo, duarti, duarto);
dcom0 : dcom port map (rst, clk, dmai, dmao, duarti, duarto, ahbi);
-- pragma translate_off
bootmsg : report_version
generic map ("ahbuart" & tost(pindex) &
": AHB Debug UART rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 | 4f09e123d707381cd28320165d7c6e10 | 0.613791 | 3.796853 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-de2-ep2c35/testbench.vhd | 1 | 8,561 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romdepth : integer := 22 -- rom address depth (flash 4 MB)
-- sramwidth : integer := 32; -- ram data width (8/16/32)
-- sramdepth : integer := 20; -- ram address depth
-- srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(21 downto 0);
signal data : std_logic_vector(31 downto 24);
signal romsn : std_logic;
signal oen : std_logic;
signal writen : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal error : std_logic;
signal gpio_0 : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal gpio_1 : std_logic_vector(CFG_GRGPIO2_WIDTH-1 downto 0);
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal dram_ldqm : std_logic;
signal dram_udqm : std_logic;
signal sdclk : std_logic;
signal sw : std_logic_vector(0 to 2);
signal ps2_clk : std_logic;
signal ps2_dat : std_logic;
signal vga_clk : std_ulogic;
signal vga_blank : std_ulogic;
signal vga_sync : std_ulogic;
signal vga_hs : std_ulogic;
signal vga_vs : std_ulogic;
signal vga_r : std_logic_vector(9 downto 0);
signal vga_g : std_logic_vector(9 downto 0);
signal vga_b : std_logic_vector(9 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(13 downto 0);
signal sd : std_logic_vector(15 downto 0);
begin
clk <= not clk after ct * 1 ns; --50 MHz clk
rst <= dsurst; --reset
dsuen <= '1';
dsubre <= '1'; -- inverted on the board
sw(0) <= '1';
gpio_0(CFG_GRGPIO_WIDTH-1 downto 0) <= (others => 'H');
gpio_1(CFG_GRGPIO2_WIDTH-1 downto 0) <= (others => 'H');
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, error, address(21 downto 0), data,
sa(11 downto 0), sa(12), sa(13), sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, dram_ldqm, dram_udqm, dsutx, dsurx, dsubre, dsuact,
oen, writen, open, romsn, open, open, open, open, open, open, gpio_0, gpio_1,
ps2_clk, ps2_dat, vga_clk, vga_blank, vga_sync, vga_hs, vga_vs, vga_r,
vga_g, vga_b, sw);
sd1 : if (CFG_SDCTRL = 1) generate
u1: entity work.mt48lc16m16a2 generic map (addr_bits => 12, col_bits => 8, index => 1024, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(11 downto 0),
Ba => sa(13 downto 12), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm(0) => dram_ldqm, Dqm(1) => dram_udqm );
end generate;
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data) after 5 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0'; --reset low
wait for 500 ns;
dsurst <= '1'; --reset high
wait; --evig w8
wait for 5000 ns;
txc(dsutx, 16#55#, txp);
-- txc(dsutx, 16#c0#, txp); --control byte
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); --adress
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp); --write data
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | d62fbde100df7a7162cbfd5c686554dd | 0.579372 | 3.078389 | false | false | false | false |
Yuriu5/MiniBlaze | src/peripherals/peripheral_uart.vhd | 1 | 17,818 | -- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : peripheral_uart
-- Date : 07/25/2016
--
-- Description :
--
-- --------------------------------------------------------------------------------
-- Modifications
-- --------------------------------------------------------------------------------
-- Date : Ver. : Author : Modification comments
-- --------------------------------------------------------------------------------
-- : : :
-- 07/25/2016 : 1.0 : B.Lemoine : First draft
-- : : :
-- **********************************************************************************
-- MIT License
--
-- Copyright (c) 2016, Benjamin Lemoine
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- **********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity peripheral_uart is
generic (
CLK_IN : integer := 10000000;
BAUDRATE : integer := 115200;
DATA_BITS : integer range 7 to 8 := 8;
STOP_BITS : integer range 1 to 2 := 1;
USE_PARITY : integer range 0 to 1 := 0;
ODD_PARITY : integer range 0 to 1 := 0;
USE_FIFO_TX : integer range 0 to 1 := 1;
USE_FIFO_RX : integer range 0 to 1 := 1;
SIZE_FIFO_TX : integer range 0 to 10 := 4; -- Log2 of fifo size
SIZE_FIFO_RX : integer range 0 to 10 := 4 -- Log2 of fifo size
);
port (
clk : in std_logic;
rst_n : in std_logic;
--
addr : in std_logic_vector(31 downto 0);
data_wr : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
data_rd : out std_logic_vector(31 downto 0);
--
RX : in std_logic;
TX : out std_logic
);
end peripheral_uart;
architecture rtl of peripheral_uart is
-- Component declaration
component generic_hdl_fifo is
generic (
G_DEPTH_LOG2 : integer := 4; -- Depth is equal to 2^(G_DEPTH_LOG2)
G_WIDTH : integer := 8
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- Data
data_wr : in std_logic_vector(G_WIDTH-1 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
data_rd : out std_logic_vector(G_WIDTH-1 downto 0);
rd_valid : out std_logic;
-- Status
nb_data : out std_logic_vector(G_DEPTH_LOG2 downto 0);
empty : out std_logic;
full : out std_logic
);
end component;
-- Signal declaration
signal r_read_rx_data : std_logic := '0';
signal r_clear_received_bit : std_logic := '0';
signal r_clear_rx_sts : std_logic := '0';
signal r_clear_tx_sts : std_logic := '0';
signal r_input_data : std_logic_vector(7 downto 0) := (others => '0');
signal r_input_data_en : std_logic := '0';
signal r_reset_tx_fifo : std_logic := '0';
signal r_reset_rx_fifo : std_logic := '0';
signal s_clk_in : std_logic_vector(31 downto 0) := (others => '0');
signal s_baudrate : std_logic_vector(31 downto 0) := (others => '0');
signal s_data_bits : std_logic_vector(3 downto 0) := (others => '0');
signal s_stop_bits : std_logic_vector(3 downto 0) := (others => '0');
signal s_use_parity : std_logic := '0';
signal s_odd_parity : std_logic := '0';
signal s_user_fifo_tx : std_logic := '0';
signal s_user_fifo_rx : std_logic := '0';
signal s_size_fifo_tx : std_logic_vector(15 downto 0) := (others => '0');
signal s_size_fifo_rx : std_logic_vector(15 downto 0) := (others => '0');
signal s2_nb_data_tx : std_logic_vector(15 downto 0) := (others => '0');
signal s2_nb_data_rx : std_logic_vector(15 downto 0) := (others => '0');
signal r_data_rd : std_logic_vector(7 downto 0) := (others => '0');
signal r_rd_fifo_tx : std_logic := '0';
signal s_data_rd_tx : std_logic_vector(7 downto 0) := (others => '0');
signal s_rd_valid_tx : std_logic := '0';
signal s_nb_data_tx : std_logic_vector(SIZE_FIFO_TX downto 0) := (others => '0');
signal s_empty_tx : std_logic := '0';
signal s_full_tx : std_logic := '0';
signal r_last_word_sent : std_logic := '1';
signal s_data_tx : std_logic_vector(7 downto 0) := (others => '0');
signal s_data_tx_en : std_logic := '0';
signal s_ack_tx : std_logic := '0';
signal s_data_rx : std_logic_vector(7 downto 0) := (others => '0');
signal s_data_rx_en : std_logic := '0';
signal s_data_rd_rx : std_logic_vector(7 downto 0) := (others => '0');
signal s_rd_valid_rx : std_logic := '0';
signal s_nb_data_rx : std_logic_vector(SIZE_FIFO_RX downto 0) := (others => '0');
signal s_empty_rx : std_logic := '0';
signal s_full_rx : std_logic := '0';
signal r_data_received : std_logic_vector(7 downto 0) := (others => '0');
signal r_data_received_bit : std_logic := '0';
signal r_rx_underflow : std_logic := '0';
signal r_rx_overflow : std_logic := '0';
signal r_tx_overflow : std_logic := '0';
signal r_tx_underflow : std_logic := '0';
begin
-- ====================================
-- Configuration registry
-- ====================================
process(clk)
begin
if rising_edge(clk) then
-- Default values
r_read_rx_data <= '0';
r_clear_received_bit <= '0';
r_clear_rx_sts <= '0';
r_clear_tx_sts <= '0';
r_input_data_en <= '0';
if wr_en = '1' then
case addr(7 downto 0) is
when x"00" =>
r_input_data <= data_wr(DATA_BITS-1 downto 0);
when x"01" =>
r_input_data_en <= data_wr(0);
when x"02" =>
r_reset_tx_fifo <= not data_wr(0);
r_reset_rx_fifo <= not data_wr(1);
when x"03" =>
r_read_rx_data <= data_wr(0);
r_clear_received_bit <= data_wr(1);
r_clear_rx_sts <= data_wr(2);
r_clear_tx_sts <= data_wr(3);
when x"11" =>
when others =>
null;
end case;
end if;
end if;
end process;
-- ====================================
-- Status registry
-- ====================================
s_clk_in <= std_logic_vector(to_unsigned(CLK_IN,32));
s_baudrate <= std_logic_vector(to_unsigned(BAUDRATE,32));
s_data_bits <= std_logic_vector(to_unsigned(DATA_BITS,4));
s_stop_bits <= std_logic_vector(to_unsigned(STOP_BITS,4));
s_use_parity <= '1' when USE_PARITY = 1 else '0';
s_odd_parity <= '1' when ODD_PARITY = 1 else '0';
s_user_fifo_tx <= '1' when USE_FIFO_TX = 1 else '0';
s_user_fifo_rx <= '1' when USE_FIFO_RX = 1 else '0';
s_size_fifo_tx <= std_logic_vector(to_unsigned(2**SIZE_FIFO_TX,16));
s_size_fifo_rx <= std_logic_vector(to_unsigned(2**SIZE_FIFO_RX,16));
s2_nb_data_tx <= std_logic_vector(resize(unsigned(s_nb_data_tx),16));
s2_nb_data_rx <= std_logic_vector(resize(unsigned(s_nb_data_rx),16));
process(clk)
begin
if rising_edge(clk) then
case addr(7 downto 0) is
when x"80" =>
r_data_rd <= "000000" & s_empty_rx & s_full_rx;
when x"81" =>
r_data_rd <= s2_nb_data_rx(7 downto 0);
when x"82" =>
r_data_rd <= s2_nb_data_rx(15 downto 8);
when x"83" =>
r_data_rd <= "00000" & r_rx_underflow & r_rx_overflow & r_data_received_bit;
when x"84" =>
r_data_rd <= r_data_received;
when x"90" =>
r_data_rd <= "000000" & s_empty_tx & s_full_tx;
when x"91" =>
r_data_rd <= s2_nb_data_tx(7 downto 0);
when x"92" =>
r_data_rd <= s2_nb_data_tx(15 downto 8);
when x"B0" =>
r_data_rd <= s_clk_in(7 downto 0);
when x"B1" =>
r_data_rd <= s_clk_in(15 downto 8);
when x"B2" =>
r_data_rd <= s_clk_in(23 downto 16);
when x"B3" =>
r_data_rd <= s_clk_in(31 downto 24);
when x"B4" =>
r_data_rd <= s_baudrate(7 downto 0);
when x"B5" =>
r_data_rd <= s_baudrate(15 downto 8);
when x"B6" => -- Reserved for baudrate if 16b not enough
r_data_rd <= (others => '0');
when x"B7" => -- Reserved for baudrate if 16b not enough
r_data_rd <= (others => '0');
when x"B8" =>
r_data_rd <= s_stop_bits & s_data_bits;
when x"B9" =>
r_data_rd <= "0000" & s_use_parity & s_odd_parity & s_user_fifo_tx & s_user_fifo_rx;
when x"BA" =>
r_data_rd <= s_size_fifo_tx(7 downto 0);
when x"BB" =>
r_data_rd <= s_size_fifo_tx(15 downto 8);
when x"BC" =>
r_data_rd <= s_size_fifo_rx(7 downto 0);
when x"BD" =>
r_data_rd <= s_size_fifo_rx(15 downto 8);
when others =>
r_data_rd <= (others => '0');
end case;
end if;
end process;
data_rd(7 downto 0) <= r_data_rd;
data_rd(31 downto 8) <= (others => '0');
-- ====================================
-- TX fifo
-- ====================================
g_fifo_tx : if USE_FIFO_TX = 1 generate
i_fifo_tx : generic_hdl_fifo
generic map (
G_DEPTH_LOG2 => SIZE_FIFO_TX,
G_WIDTH => DATA_BITS
)
port map (
clk => clk,
rst_n => rst_n,
data_wr => r_input_data,
wr_en => r_input_data_en,
rd_en => r_rd_fifo_tx,
data_rd => s_data_rd_tx,
rd_valid => s_rd_valid_tx,
nb_data => s_nb_data_tx,
empty => s_empty_tx,
full => s_full_tx
);
process(clk)
begin
if rising_edge(clk) then
-- Consume words if fifo is not empty
if rst_n = '0' then
r_last_word_sent <= '1';
r_rd_fifo_tx <= '0';
else
if s_empty_tx = '0' and r_last_word_sent = '1' then
r_rd_fifo_tx <= '1';
r_last_word_sent <= '0';
elsif s_ack_tx = '1' then
r_last_word_sent <= '1';
r_rd_fifo_tx <= '0';
else
r_rd_fifo_tx <= '0';
end if;
end if;
end if;
end process;
s_data_tx <= s_data_rd_tx;
s_data_tx_en <= s_rd_valid_tx;
end generate;
g_no_fifo_tx : if USE_FIFO_TX = 0 generate
process(clk)
begin
if rising_edge(clk) then
if rst_n = '0' then
s_empty_tx <= '1';
s_full_tx <= '0';
else
if r_input_data_en = '1' then
s_empty_tx <= '0';
s_full_tx <= '1';
elsif s_ack_tx = '1' then
s_empty_tx <= '1';
s_full_tx <= '0';
end if;
end if;
end if;
end process;
s_data_tx <= r_input_data;
s_data_tx_en <= r_input_data_en;
end generate;
process(clk)
begin
if rising_edge(clk) then
if r_clear_tx_sts = '1' then
r_tx_overflow <= '0';
r_tx_underflow <= '0';
end if;
if r_input_data_en = '1' and s_full_tx = '1' then
r_tx_overflow <= '1';
end if;
if r_rd_fifo_tx = '1' and s_empty_tx = '1' then
r_tx_underflow <= '1';
end if;
end if;
end process;
-- ====================================
-- UART module
-- ====================================
i_UART : entity work.UART
generic map(
CLK_IN => CLK_IN,
BAUDRATE => BAUDRATE,
DATA_BITS => DATA_BITS,
STOP_BITS => STOP_BITS,
USE_PARITY => USE_PARITY,
ODD_PARITY => ODD_PARITY
)
port map(
clk => clk,
rst_n => rst_n,
-- User intf
data_in => s_data_tx,
data_in_en => s_data_tx_en,
data_in_ack => s_ack_tx,
data_out => s_data_rx,
data_out_en => s_data_rx_en,
-- TX/RX
RX => RX,
TX => TX
);
-- ====================================
-- RX fifo
-- ====================================
g_fifo_rx : if USE_FIFO_RX = 1 generate
i_fifo_tx : generic_hdl_fifo
generic map (
G_DEPTH_LOG2 => SIZE_FIFO_RX,
G_WIDTH => DATA_BITS
)
port map (
clk => clk,
rst_n => rst_n,
data_wr => s_data_rx,
wr_en => s_data_rx_en,
rd_en => r_read_rx_data,
data_rd => s_data_rd_rx,
rd_valid => s_rd_valid_rx,
nb_data => s_nb_data_rx,
empty => s_empty_rx,
full => s_full_rx
);
end generate;
g_no_fifo_rx : if USE_FIFO_RX = 0 generate
s_data_rd_rx <= s_data_rx;
s_rd_valid_rx <= s_data_rx_en;
process(clk)
begin
if rising_edge(clk) then
if s_data_rx_en = '1' then
s_full_rx <= '1';
s_empty_rx <= '0';
elsif r_read_rx_data = '1' then
s_full_rx <= '0';
s_empty_rx <= '1';
end if;
end if;
end process;
end generate;
process(clk)
begin
if rising_edge(clk) then
if r_clear_received_bit = '1' then
r_data_received_bit <= '0';
end if;
if r_clear_rx_sts = '1' then
r_data_received_bit <= '0';
r_rx_underflow <= '0';
r_rx_overflow <= '0';
end if;
if s_rd_valid_rx = '1' then
r_data_received_bit <= '1';
r_data_received <= s_data_rd_rx;
end if;
if r_read_rx_data = '1' and s_empty_rx = '1' then
r_rx_underflow <= '1';
end if;
if s_data_rx_en = '1' and s_full_rx = '1' then
r_rx_overflow <= '1';
end if;
end if;
end process;
end rtl;
| mit | b0664ade576036448661cd86be034c8a | 0.40605 | 3.72372 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-terasic-de4/leon3mp.vhd | 1 | 45,815 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- clocks
OSC_50_BANK2 : in std_logic;
OSC_50_BANK3 : in std_logic;
OSC_50_BANK4 : in std_logic;
OSC_50_BANK5 : in std_logic;
OSC_50_BANK6 : in std_logic;
OSC_50_BANK7 : in std_logic;
PLL_CLKIN_p : in std_logic;
SMA_CLKIN_p : in std_logic;
-- SMA_GXBCLK_p : in std_logic;
GCLKIN : in std_logic;
GCLKOUT_FPGA : out std_logic;
SMA_CLKOUT_p : out std_logic;
-- cpu reset
CPU_RESET_n : in std_ulogic;
-- max i/o
MAX_CONF_D : inout std_logic_vector(3 downto 0);
MAX_I2C_SCLK : out std_logic;
MAX_I2C_SDAT : inout std_logic;
-- LEDs
LED : out std_logic_vector(7 downto 0);
-- buttons
BUTTON : in std_logic_vector(3 downto 0);
-- switches
SW : in std_logic_vector(3 downto 0);
-- slide switches
SLIDE_SW : in std_logic_vector(3 downto 0);
-- temperature
TEMP_SMCLK : out std_logic;
TEMP_SMDAT : inout std_logic;
TEMP_INT_n : in std_logic;
-- current
CSENSE_ADC_FO : out std_logic;
CSENSE_SCK : inout std_logic;
CSENSE_SDI : out std_logic;
CSENSE_SDO : in std_logic;
CSENSE_CS_n : out std_logic_vector(1 downto 0);
-- fan
FAN_CTRL : out std_logic;
-- eeprom
EEP_SCL : out std_logic;
EEP_SDA : inout std_logic;
-- sdcard
SD_CLK : out std_logic;
SD_CMD : inout std_logic;
SD_DAT : inout std_logic_vector(3 downto 0);
SD_WP_n : in std_logic;
-- Ethernet interfaces
ETH_INT_n : in std_logic_vector(3 downto 0);
ETH_MDC : out std_logic_vector(3 downto 0);
ETH_MDIO : inout std_logic_vector(3 downto 0);
ETH_RST_n : out std_ulogic;
ETH_RX_p : in std_logic_vector(3 downto 0);
ETH_TX_p : out std_logic_vector(3 downto 0);
-- PCIe interfaces
-- PCIE_PREST_n : in std_ulogic;
-- PCIE_REFCLK_p : in std_ulogic;
-- PCIE_RX_p : in std_logic_vector(7 downto 0);
-- PCIE_SMBCLK : in std_logic;
-- PCIE_SMBDAT : inout std_logic;
-- PCIE_TX_p : out std_logic_vector(7 downto 0);
-- PCIE_WAKE_n : out std_logic;
-- Flash and SRAM, shared signals
FSM_A : out std_logic_vector(25 downto 1);
FSM_D : inout std_logic_vector(15 downto 0);
-- Flash control
FLASH_ADV_n : out std_ulogic;
FLASH_CE_n : out std_ulogic;
FLASH_CLK : out std_ulogic;
FLASH_OE_n : out std_ulogic;
FLASH_RESET_n : out std_ulogic;
FLASH_RYBY_n : in std_ulogic;
FLASH_WE_n : out std_ulogic;
-- SSRAM control
SSRAM_ADV : out std_ulogic;
SSRAM_BWA_n : out std_ulogic;
SSRAM_BWB_n : out std_ulogic;
SSRAM_CE_n : out std_ulogic;
SSRAM_CKE_n : out std_ulogic;
SSRAM_CLK : out std_ulogic;
SSRAM_OE_n : out std_ulogic;
SSRAM_WE_n : out std_ulogic;
-- USB OTG
-- OTG_A : out std_logic_vector(17 downto 1);
-- OTG_CS_n : out std_ulogic;
-- OTG_D : inout std_logic_vector(31 downto 0);
-- OTG_DC_DACK : out std_ulogic;
-- OTG_DC_DREQ : in std_ulogic;
-- OTG_DC_IRQ : in std_ulogic;
-- OTG_HC_DACK : out std_ulogic;
-- OTG_HC_DREQ : in std_ulogic;
-- OTG_HC_IRQ : in std_ulogic;
-- OTG_OE_n : out std_ulogic;
-- OTG_RESET_n : out std_ulogic;
-- OTG_WE_n : out std_ulogic;
-- SATA
-- SATA_REFCLK_p : in std_logic;
-- SATA_HOST_RX_p : in std_logic_vector(1 downto 0);
-- SATA_HOST_TX_p : out std_logic_vector(1 downto 0);
-- SATA_DEVICE_RX_p : in std_logic_vector(1 downto 0);
-- SATA_DEVICE_TX_p : out std_logic_vector(1 downto 0);
-- DDR2 SODIMM
M1_DDR2_addr : out std_logic_vector(15 downto 0);
M1_DDR2_ba : out std_logic_vector(2 downto 0);
M1_DDR2_cas_n : out std_logic;
M1_DDR2_cke : out std_logic_vector(1 downto 0);
M1_DDR2_clk : out std_logic_vector(1 downto 0);
M1_DDR2_clk_n : out std_logic_vector(1 downto 0);
M1_DDR2_cs_n : out std_logic_vector(1 downto 0);
M1_DDR2_dm : out std_logic_vector(7 downto 0);
M1_DDR2_dq : inout std_logic_vector(63 downto 0);
M1_DDR2_dqs : inout std_logic_vector(7 downto 0);
M1_DDR2_dqsn : inout std_logic_vector(7 downto 0);
M1_DDR2_odt : out std_logic_vector(1 downto 0);
M1_DDR2_ras_n : out std_logic;
-- M1_DDR2_SA : out std_logic_vector(1 downto 0);
-- M1_DDR2_SCL : out std_logic;
-- M1_DDR2_SDA : inout std_logic;
M1_DDR2_we_n : out std_logic;
M1_DDR2_oct_rdn : in std_logic;
M1_DDR2_oct_rup : in std_logic;
-- DDR2 SODIMM
-- M2_DDR2_addr : out std_logic_vector(15 downto 0);
-- M2_DDR2_ba : out std_logic_vector(2 downto 0);
-- M2_DDR2_cas_n : out std_logic;
-- M2_DDR2_cke : out std_logic_vector(1 downto 0);
-- M2_DDR2_clk : out std_logic_vector(1 downto 0);
-- M2_DDR2_clk_n : out std_logic_vector(1 downto 0);
-- M2_DDR2_cs_n : out std_logic_vector(1 downto 0);
-- M2_DDR2_dm : out std_logic_vector(7 downto 0);
-- M2_DDR2_dq : inout std_logic_vector(63 downto 0);
-- M2_DDR2_dqs : inout std_logic_vector(7 downto 0);
-- M2_DDR2_dqsn : inout std_logic_vector(7 downto 0);
-- M2_DDR2_odt : out std_logic_vector(1 downto 0);
-- M2_DDR2_ras_n : out std_logic;
-- M2_DDR2_SA : out std_logic_vector(1 downto 0);
-- M2_DDR2_SCL : out std_logic;
-- M2_DDR2_SDA : inout std_logic;
-- M2_DDR2_we_n : out std_logic;
-- GPIO
GPIO0_D : inout std_logic_vector(35 downto 0);
GPIO1_D : inout std_logic_vector(35 downto 0);
-- Ext I/O
-- EXT_IO : inout std_logic;
-- HSMC A
-- HSMA_CLKIN_n1 : in std_logic;
-- HSMA_CLKIN_n2 : in std_logic;
-- HSMA_CLKIN_p1 : in std_logic;
-- HSMA_CLKIN_p2 : in std_logic;
-- HSMA_CLKIN0 : in std_logic;
-- HSMA_CLKOUT_n2 : out std_logic;
-- HSMA_CLKOUT_p2 : out std_logic;
-- HSMA_D : inout std_logic_vector(3 downto 0);
-- HSMA_GXB_RX_p : in std_logic_vector(3 downto 0);
-- HSMA_GXB_TX_p : out std_logic_vector(3 downto 0);
-- HSMA_OUT_n1 : inout std_logic;
-- HSMA_OUT_p1 : inout std_logic;
-- HSMA_OUT0 : inout std_logic;
-- HSMA_REFCLK_p : in std_logic;
-- HSMA_RX_n : inout std_logic_vector(16 downto 0);
-- HSMA_RX_p : inout std_logic_vector(16 downto 0);
-- HSMA_TX_n : inout std_logic_vector(16 downto 0);
-- HSMA_TX_p : inout std_logic_vector(16 downto 0);
-- HSMC_B
-- HSMB_CLKIN_n1 : in std_logic;
-- HSMB_CLKIN_n2 : in std_logic;
-- HSMB_CLKIN_p1 : in std_logic;
-- HSMB_CLKIN_p2 : in std_logic;
-- HSMB_CLKIN0 : in std_logic;
-- HSMB_CLKOUT_n2 : out std_logic;
-- HSMB_CLKOUT_p2 : out std_logic;
-- HSMB_D : inout std_logic_vector(3 downto 0);
-- HSMB_GXB_RX_p : in std_logic_vector(3 downto 0);
-- HSMB_GXB_TX_p : out std_logic_vector(3 downto 0);
-- HSMB_OUT_n1 : inout std_logic;
-- HSMB_OUT_p1 : inout std_logic;
-- HSMB_OUT0 : inout std_logic;
-- HSMB_REFCLK_p : in std_logic;
-- HSMB_RX_n : inout std_logic_vector(16 downto 0);
-- HSMB_RX_p : inout std_logic_vector(16 downto 0);
-- HSMB_TX_n : inout std_logic_vector(16 downto 0);
-- HSMB_TX_p : inout std_logic_vector(16 downto 0);
-- HSMC i2c
-- HSMC_SCL : out std_logic;
-- HSMC_SDA : inout std_logic;
-- Display
-- SEG0_D : out std_logic_vector(6 downto 0);
-- SEG1_D : out std_logic_vector(6 downto 0);
-- SEG0_DP : out std_ulogic;
-- SEG1_DP : out std_ulogic;
-- UART
UART_CTS : out std_ulogic;
UART_RTS : in std_ulogic;
UART_RXD : in std_ulogic;
UART_TXD : out std_ulogic
);
end;
architecture rtl of leon3mp is
component sgmii2gmii is
port (
ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
clk : in std_logic := '0'; -- control_port_clock_connection.clk
reset : in std_logic := '0'; -- reset_connection.reset
address : in std_logic_vector(4 downto 0) := (others => '0'); -- control_port.address
readdata : out std_logic_vector(15 downto 0); -- .readdata
read : in std_logic := '0'; -- .read
writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
waitrequest : out std_logic; -- .waitrequest
tx_clk : out std_logic; -- pcs_transmit_clock_connection.clk
rx_clk : out std_logic; -- pcs_receive_clock_connection.clk
reset_tx_clk : in std_logic := '0'; -- pcs_transmit_reset_connection.reset
reset_rx_clk : in std_logic := '0'; -- pcs_receive_reset_connection.reset
gmii_rx_dv : out std_logic; -- gmii_connection.gmii_rx_dv
gmii_rx_d : out std_logic_vector(7 downto 0); -- .gmii_rx_d
gmii_rx_err : out std_logic; -- .gmii_rx_err
gmii_tx_en : in std_logic := '0'; -- .gmii_tx_en
gmii_tx_d : in std_logic_vector(7 downto 0) := (others => '0'); -- .gmii_tx_d
gmii_tx_err : in std_logic := '0'; -- .gmii_tx_err
tx_clkena : out std_logic; -- clock_enable_connection.tx_clkena
rx_clkena : out std_logic; -- .rx_clkena
mii_rx_dv : out std_logic; -- mii_connection.mii_rx_dv
mii_rx_d : out std_logic_vector(3 downto 0); -- .mii_rx_d
mii_rx_err : out std_logic; -- .mii_rx_err
mii_tx_en : in std_logic := '0'; -- .mii_tx_en
mii_tx_d : in std_logic_vector(3 downto 0) := (others => '0'); -- .mii_tx_d
mii_tx_err : in std_logic := '0'; -- .mii_tx_err
mii_col : out std_logic; -- .mii_col
mii_crs : out std_logic; -- .mii_crs
set_10 : out std_logic; -- sgmii_status_connection.set_10
set_1000 : out std_logic; -- .set_1000
set_100 : out std_logic; -- .set_100
hd_ena : out std_logic; -- .hd_ena
led_crs : out std_logic; -- status_led_connection.crs
led_link : out std_logic; -- .link
led_col : out std_logic; -- .col
led_an : out std_logic; -- .an
led_char_err : out std_logic; -- .char_err
led_disp_err : out std_logic; -- .disp_err
rx_recovclkout : out std_logic; -- serdes_control_connection.export
txp : out std_logic; -- serial_connection.txp
rxp : in std_logic := '0' -- .rxp
);
end component sgmii2gmii;
component pll_125 is
port(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal del_addr : std_logic_vector(25 downto 1);
signal del_ce, del_we: std_logic;
signal del_bwa_n, del_bwb_n: std_logic_vector(1 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal spii, spislvi : spi_in_type;
signal spio, spislvo : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal stati : ahbstat_in_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal dsubren : std_logic;
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal gmiii1, gmiii2 : eth_in_type;
signal gmiio1, gmiio2 : eth_out_type;
signal sgmiii1, sgmiii2 : eth_sgmii_in_type;
signal sgmiio1, sgmiio2 : eth_sgmii_out_type;
signal eth_tx_pad, eth_rx_pad : std_logic_vector(3 downto 0) ;
signal reset1_tx_clk, reset1_rx_clk, reset2_tx_clk, reset2_rx_clk, ref_clk, ctrl_rst: std_logic;
signal led_crs1, led_link1, led_col1, led_an1, led_char_err1, led_disp_err1 : std_logic;
signal led_crs2, led_link2, led_col2, led_an2, led_char_err2, led_disp_err2 : std_logic;
constant BOARD_FREQ : integer := 100000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 0;
constant OEPOL : integer := padoen_polarity(padtech);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep : boolean;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_clk_fb : std_ulogic;
signal clkm125 : std_logic;
signal clklock, lock, clkml : std_logic;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1');
gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clklock <= cgo.clklock and lock;
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 0,
noclkfb => CFG_CLK_NOFB, freq => BOARD_FREQ)
port map (clkin => PLL_CLKIN_p, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo);
-- clk125_pad : clkpad generic map (tech => padtech) port map (clk125, lclk125);
-- clkm125 <= clk125;
rst0 : rstgen -- reset generator
port map (CPU_RESET_n, clkm, clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (LED(0), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (BUTTON(0), dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (LED(1), dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= uart_rxd when slide_sw(0) = '0' else '1';
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
data_pad : iopadvv generic map (tech => padtech, width => 16, oepol => OEPOL)
port map (FSM_D, memo.data(31 downto 16), memo.vbdrive(31 downto 16), memi.data(31 downto 16));
FSM_A <= memo.address(25 downto 1);
FLASH_CLK <= clkm;
FLASH_RESET_n <= rstn;
FLASH_CE_n <= memo.romsn(0);
FLASH_OE_n <= memo.oen;
FLASH_WE_n <= memo.writen;
FLASH_ADV_n <= '0';
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= (others => '1');
memi.bwidth <= "01";
memi.sd <= (others => '0');
memi.cb <= (others => '0');
memi.scb <= (others => '0');
memi.edac <= '0';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
romaddr => 16#000#, rommask => 16#fc0#,
ioaddr => 0, iomask => 0,
ramaddr => 0, rammask => 0,
ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open);
end generate;
nomctrl0: if CFG_MCTRL_LEON2 = 0 generate
ahbso(0) <= ahbs_none;
apbo(0) <= apb_none;
memo <= memory_out_none;
end generate;
ddr2if0: entity work.ddr2if
generic map(
hindex => 3,
haddr => 16#400#,
hmask => 16#C00#,
burstlen => 32
)
port map (
pll_ref_clk => OSC_50_BANK4,
global_reset_n => CPU_RESET_n,
mem_a => M1_DDR2_addr(13 downto 0),
mem_ba => M1_DDR2_ba,
mem_ck => M1_DDR2_clk,
mem_ck_n => M1_DDR2_clk_n,
mem_cke => M1_DDR2_cke(0),
mem_cs_n => M1_DDR2_cs_n(0),
mem_dm => M1_DDR2_dm,
mem_ras_n => M1_DDR2_ras_n,
mem_cas_n => M1_DDR2_cas_n,
mem_we_n => M1_DDR2_we_n,
mem_dq => M1_DDR2_dq,
mem_dqs => M1_DDR2_dqs,
mem_dqs_n => M1_DDR2_dqsn,
mem_odt => M1_DDR2_odt(0),
ahb_clk => clkm,
ahb_rst => rstn,
ahbsi => ahbsi,
ahbso => ahbso(3),
oct_rdn => M1_DDR2_oct_rdn,
oct_rup => M1_DDR2_oct_rup
);
lock <= '1';
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= '1' when slide_sw(0) = '0' else uart_rxd;
u1i.ctsn <= uart_rts; u1i.extclk <= '0';
end generate;
uart_txd <= u1o.txd when slide_sw(0) = '1' else duo.txd;
uart_cts <= u1o.rtsn;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (GPIO0_D(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (tech => padtech)
port map (CSENSE_SDO, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (CSENSE_SDI, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (CSENSE_SCK, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (CSENSE_CS_n(0), slvsel(0));
slvseladc_pad : outpad generic map (tech => padtech)
port map (CSENSE_ADC_FO, slvsel(1));
end generate spic;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat
generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
pll0: entity work.pll_125
port map (OSC_50_BANK3, ref_clk);
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (CPU_RESET_n, clkm, '1', ctrl_rst, open);
rst10 : rstgen -- reset generator
generic map (acthigh => 1)
port map (CPU_RESET_n, gmiii1.tx_clk, '1', reset1_tx_clk, open);
rst11 : rstgen -- reset generator
generic map (acthigh => 1)
port map (CPU_RESET_n, gmiii1.rx_clk, '1', reset1_rx_clk, open);
bridge1: sgmii2gmii
port map(
ref_clk => ref_clk, -- in pcs_ref_clk_clock_connection.clk
clk => clkm, -- in control_port_clock_connection.clk
reset => ctrl_rst, -- in reset_connection.reset
address => zero32(4 downto 0), -- in control_port.address
readdata => open, -- out .readdata
read => '0', -- in .read
writedata => zero32(15 downto 0), -- in .writedata
write => '0', -- in .write
waitrequest => open, -- out .waitrequest
tx_clk => gmiii1.tx_clk, -- out pcs_transmit_clock_connection.clk
rx_clk => gmiii1.rx_clk, -- out pcs_receive_clock_connection.clk
reset_tx_clk => reset1_tx_clk, -- in pcs_transmit_reset_connection.reset
reset_rx_clk => reset1_rx_clk, -- in pcs_receive_reset_connection.reset
gmii_rx_dv => gmiii1.rx_dv, -- out gmii_connection.gmii_rx_dv
gmii_rx_d => gmiii1.rxd, -- out .gmii_rx_d
gmii_rx_err => gmiii1.rx_er, -- out .gmii_rx_err
gmii_tx_en => gmiio1.tx_en, -- in .gmii_tx_en
gmii_tx_d => gmiio1.txd, -- in .gmii_tx_d
gmii_tx_err => gmiio1.tx_er, -- in .gmii_tx_err
tx_clkena => open, -- out clock_enable_connection.tx_clkena
rx_clkena => open, -- out .rx_clkena
mii_rx_dv => open, -- out mii_connection.mii_rx_dv
mii_rx_d => open, -- out .mii_rx_d
mii_rx_err => open, -- out .mii_rx_err
mii_tx_en => '0', -- in .mii_tx_en
mii_tx_d => zero32(3 downto 0), -- in .mii_tx_d
mii_tx_err => '0', -- in .mii_tx_err
mii_col => open, -- out .mii_col
mii_crs => open, -- out .mii_crs
set_10 => open, -- out sgmii_status_connection.set_10
set_1000 => open, -- out .set_1000
set_100 => open, -- out .set_100
hd_ena => open, -- out .hd_ena
led_crs => led_crs1, -- out status_led_connection.crs
led_link => led_link1, -- out .link
led_col => open, -- out .col
led_an => open, -- out .an
led_char_err => open, -- out .char_err
led_disp_err => open, -- out .disp_err
rx_recovclkout => open, -- out serdes_control_connection.export
txp => ETH_TX_p(0), -- out serial_connection.txp
rxp => ETH_RX_p(0) -- in .rxp
);
led2_pad : outpad generic map (tech => padtech) port map (LED(2), led_crs1);
led3_pad : outpad generic map (tech => padtech) port map (LED(3), led_link1);
--led4_pad : outpad generic map (tech => padtech) port map (LED(4), led_col);
--led5_pad : outpad generic map (tech => padtech) port map (LED(5), led_an);
--led6_pad : outpad generic map (tech => padtech) port map (LED(6), led_char_err);
--led7_pad : outpad generic map (tech => padtech) port map (LED(7), led_disp_err);
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 11,
paddr => 11,
pirq => 6,
memtech => stratix3,
mdcscaler => CPU_FREQ/1000,
enable_mdio => 1,
fifosize => CFG_ETH_FIFO,
nsync => 2,
edcl => CFG_DSU_ETH,
edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM,
macaddrl => CFG_ETH_ENL,
phyrstadr => 0,
ipaddrh => CFG_ETH_IPM,
ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G
)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi,
apbo => apbo(11),
ethi => gmiii1,
etho => gmiio1
);
-- MDIO interface setup
emdio_pad1 : iopad generic map (tech => padtech)
port map (ETH_MDIO(0), gmiio1.mdio_o, gmiio1.mdio_oe, gmiii1.mdio_i);
emdc_pad1 : outpad generic map (tech => padtech)
port map (ETH_MDC(0), gmiio1.mdc);
eint_pad1 : inpad generic map (tech => padtech)
port map (ETH_INT_n(0), gmiii1.mdint);
erst_pad1 : outpad generic map (tech => padtech)
port map (ETH_RST_n, gmiio1.reset);
gmiii1.edclsepahb <= '0';
gmiii1.edcldisable <= '0';
gmiii1.phyrstaddr <= (others => '0');
gmiii1.edcladdr <= (others => '0');
gmiii1.gtx_clk <= ref_clk;
gmiii1.rmii_clk <= '0';
gmiii1.rx_col <= '0';
gmiii1.rx_crs <= '0';
end generate;
noeth1 : if CFG_GRETH = 0 generate
gmiio1 <= eth_out_none;
end generate;
eth2: if CFG_GRETH2 = 1 generate -- Gaisler ethernet MAC
rst20 : rstgen -- reset generator
generic map (acthigh => 1)
port map (CPU_RESET_n, gmiii2.tx_clk, '1', reset2_tx_clk, open);
rst21 : rstgen -- reset generator
generic map (acthigh => 1)
port map (CPU_RESET_n, gmiii2.rx_clk, '1', reset2_rx_clk, open);
bridge2: sgmii2gmii
port map(
ref_clk => ref_clk, -- in pcs_ref_clk_clock_connection.clk
clk => clkm, -- in control_port_clock_connection.clk
reset => ctrl_rst, -- in reset_connection.reset
address => zero32(4 downto 0), -- in control_port.address
readdata => open, -- out .readdata
read => '0', -- in .read
writedata => zero32(15 downto 0), -- in .writedata
write => '0', -- in .write
waitrequest => open, -- out .waitrequest
tx_clk => gmiii2.tx_clk, -- out pcs_transmit_clock_connection.clk
rx_clk => gmiii2.rx_clk, -- out pcs_receive_clock_connection.clk
reset_tx_clk => reset2_tx_clk, -- in pcs_transmit_reset_connection.reset
reset_rx_clk => reset2_rx_clk, -- in pcs_receive_reset_connection.reset
gmii_rx_dv => gmiii2.rx_dv, -- out gmii_connection.gmii_rx_dv
gmii_rx_d => gmiii2.rxd, -- out .gmii_rx_d
gmii_rx_err => gmiii2.rx_er, -- out .gmii_rx_err
gmii_tx_en => gmiio2.tx_en, -- in .gmii_tx_en
gmii_tx_d => gmiio2.txd, -- in .gmii_tx_d
gmii_tx_err => gmiio2.tx_er, -- in .gmii_tx_err
tx_clkena => open, -- out clock_enable_connection.tx_clkena
rx_clkena => open, -- out .rx_clkena
mii_rx_dv => open, -- out mii_connection.mii_rx_dv
mii_rx_d => open, -- out .mii_rx_d
mii_rx_err => open, -- out .mii_rx_err
mii_tx_en => '0', -- in .mii_tx_en
mii_tx_d => zero32(3 downto 0), -- in .mii_tx_d
mii_tx_err => '0', -- in .mii_tx_err
mii_col => open, -- out .mii_col
mii_crs => open, -- out .mii_crs
set_10 => open, -- out sgmii_status_connection.set_10
set_1000 => open, -- out .set_1000
set_100 => open, -- out .set_100
hd_ena => open, -- out .hd_ena
led_crs => led_crs2, -- out status_led_connection.crs
led_link => led_link2, -- out .link
led_col => open, -- out .col
led_an => open, -- out .an
led_char_err => open, -- out .char_err
led_disp_err => open, -- out .disp_err
rx_recovclkout => open, -- out serdes_control_connection.export
txp => ETH_TX_p(1), -- out serial_connection.txp
rxp => ETH_RX_p(1) -- in .rxp
);
led4_pad : outpad generic map (tech => padtech) port map (LED(4), led_crs2);
led5_pad : outpad generic map (tech => padtech) port map (LED(5), led_link2);
e2 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
pindex => 12,
paddr => 12,
pirq => 7,
memtech => stratix3,
mdcscaler => CPU_FREQ/1000,
enable_mdio => 1,
fifosize => CFG_ETH2_FIFO,
nsync => 2,
edcl => CFG_DSU_ETH,
edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM,
macaddrl => CFG_ETH_ENL,
phyrstadr => 0,
ipaddrh => CFG_ETH_IPM,
ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH21G
)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH),
apbi => apbi,
apbo => apbo(12),
ethi => gmiii2,
etho => gmiio2
);
-- MDIO interface setup
emdio_pad2 : iopad generic map (tech => padtech)
port map (ETH_MDIO(1), gmiio2.mdio_o, gmiio2.mdio_oe, gmiii2.mdio_i);
emdc_pad2 : outpad generic map (tech => padtech)
port map (ETH_MDC(1), gmiio2.mdc);
eint_pad2 : inpad generic map (tech => padtech)
port map (ETH_INT_n(1), gmiii2.mdint);
--gmiio2.reset <= ; -- not connected, using gmiio1.reset
gmiii2.edclsepahb <= '0';
gmiii2.edcldisable <= '0';
gmiii2.phyrstaddr <= "00001";
gmiii2.edcladdr <= (others => '0');
gmiii2.gtx_clk <= ref_clk;
gmiii2.rmii_clk <= '0';
gmiii2.rx_col <= '0';
gmiii2.rx_crs <= '0';
end generate;
noeth2 : if CFG_GRETH2 = 0 generate
gmiio2 <= eth_out_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_GRETH2) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
--ahbmo(ahbmo'high downto nahbm) <= (others => ahbm_none);
ahbso(ahbso'high downto 5) <= (others => ahbs_none);
--apbo(napbs to apbo'high) <= (others => apb_none);
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 TerASIC DE4 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 0e1d9ccbb53eb87481071048d37df221 | 0.459304 | 3.785425 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_gray_rows_V.vhd | 2 | 4,556 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_gray_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_gray_rows_V_shiftReg;
architecture rtl of FIFO_image_filter_gray_rows_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_gray_rows_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_gray_rows_V is
component FIFO_image_filter_gray_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_gray_rows_V_shiftReg : FIFO_image_filter_gray_rows_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | a7be2ce227c7c5ae80a99f070a651bf4 | 0.535558 | 3.520866 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_Duplicate_1080_1920_32_32_s.vhd | 2 | 21,237 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Duplicate_1080_1920_32_32_s is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
src_data_stream_0_V_empty_n : IN STD_LOGIC;
src_data_stream_0_V_read : OUT STD_LOGIC;
src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
src_data_stream_1_V_empty_n : IN STD_LOGIC;
src_data_stream_1_V_read : OUT STD_LOGIC;
src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
src_data_stream_2_V_empty_n : IN STD_LOGIC;
src_data_stream_2_V_read : OUT STD_LOGIC;
dst1_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
dst1_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
dst1_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst1_data_stream_0_V_full_n : IN STD_LOGIC;
dst1_data_stream_0_V_write : OUT STD_LOGIC;
dst1_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst1_data_stream_1_V_full_n : IN STD_LOGIC;
dst1_data_stream_1_V_write : OUT STD_LOGIC;
dst1_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst1_data_stream_2_V_full_n : IN STD_LOGIC;
dst1_data_stream_2_V_write : OUT STD_LOGIC;
dst2_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
dst2_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
dst2_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst2_data_stream_0_V_full_n : IN STD_LOGIC;
dst2_data_stream_0_V_write : OUT STD_LOGIC;
dst2_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst2_data_stream_1_V_full_n : IN STD_LOGIC;
dst2_data_stream_1_V_write : OUT STD_LOGIC;
dst2_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
dst2_data_stream_2_V_full_n : IN STD_LOGIC;
dst2_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of image_filter_Duplicate_1080_1920_32_32_s is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_st5_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_22 : BOOLEAN;
signal p_3_reg_223 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond3_fu_239_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_85 : BOOLEAN;
signal i_V_fu_244_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_279 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond_fu_254_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_reg_284 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_96 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_sig_bdd_128 : BOOLEAN;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal j_V_fu_259_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal p_s_reg_212 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_st5_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_152 : BOOLEAN;
signal p_cast_fu_235_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_3_cast_fu_250_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond_fu_254_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_239_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond_fu_254_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_239_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond_fu_254_p2 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- p_3_reg_223 assign process. --
p_3_reg_223_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and (exitcond_fu_254_p2 = ap_const_lv1_0))) then
p_3_reg_223 <= j_V_fu_259_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond3_fu_239_p2 = ap_const_lv1_0))) then
p_3_reg_223 <= ap_const_lv11_0;
end if;
end if;
end process;
-- p_s_reg_212 assign process. --
p_s_reg_212_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
p_s_reg_212 <= ap_const_lv11_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_3)) then
p_s_reg_212 <= i_V_reg_279;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
exitcond_reg_284 <= exitcond_fu_254_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
i_V_reg_279 <= i_V_fu_244_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, exitcond3_fu_239_p2, exitcond_fu_254_p2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_128, ap_reg_ppiten_pp0_it1)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((exitcond3_fu_239_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_pp0_stg0_fsm_2 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond_fu_254_p2 = ap_const_lv1_0))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) and not((exitcond_fu_254_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st5_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2;
end if;
when ap_ST_st5_fsm_3 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, exitcond3_fu_239_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_239_p2 = ap_const_lv1_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(exitcond3_fu_239_p2, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond3_fu_239_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_128 assign process. --
ap_sig_bdd_128_assign_proc : process(src_data_stream_0_V_empty_n, src_data_stream_1_V_empty_n, src_data_stream_2_V_empty_n, dst1_data_stream_0_V_full_n, dst1_data_stream_1_V_full_n, dst1_data_stream_2_V_full_n, dst2_data_stream_0_V_full_n, dst2_data_stream_1_V_full_n, dst2_data_stream_2_V_full_n, exitcond_reg_284)
begin
ap_sig_bdd_128 <= (((src_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_reg_284 = ap_const_lv1_0)) or ((exitcond_reg_284 = ap_const_lv1_0) and (src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_reg_284 = ap_const_lv1_0) and (src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_reg_284 = ap_const_lv1_0) and (dst1_data_stream_0_V_full_n = ap_const_logic_0)) or ((exitcond_reg_284 = ap_const_lv1_0) and (dst1_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_reg_284 = ap_const_lv1_0) and (dst1_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_reg_284 = ap_const_lv1_0) and (dst2_data_stream_0_V_full_n = ap_const_logic_0)) or ((exitcond_reg_284 = ap_const_lv1_0) and (dst2_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_reg_284 = ap_const_lv1_0) and (dst2_data_stream_2_V_full_n = ap_const_logic_0)));
end process;
-- ap_sig_bdd_152 assign process. --
ap_sig_bdd_152_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_152 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_22 assign process. --
ap_sig_bdd_22_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_22 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_85 assign process. --
ap_sig_bdd_85_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_85 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_96 assign process. --
ap_sig_bdd_96_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_96 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_96)
begin
if (ap_sig_bdd_96) then
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_22)
begin
if (ap_sig_bdd_22) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_85)
begin
if (ap_sig_bdd_85) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_3 assign process. --
ap_sig_cseq_ST_st5_fsm_3_assign_proc : process(ap_sig_bdd_152)
begin
if (ap_sig_bdd_152) then
ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_3 <= ap_const_logic_0;
end if;
end process;
dst1_data_stream_0_V_din <= src_data_stream_0_V_dout;
-- dst1_data_stream_0_V_write assign process. --
dst1_data_stream_0_V_write_assign_proc : process(exitcond_reg_284, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_128, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_284 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
dst1_data_stream_0_V_write <= ap_const_logic_1;
else
dst1_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
dst1_data_stream_1_V_din <= src_data_stream_1_V_dout;
-- dst1_data_stream_1_V_write assign process. --
dst1_data_stream_1_V_write_assign_proc : process(exitcond_reg_284, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_128, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_284 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
dst1_data_stream_1_V_write <= ap_const_logic_1;
else
dst1_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
dst1_data_stream_2_V_din <= src_data_stream_2_V_dout;
-- dst1_data_stream_2_V_write assign process. --
dst1_data_stream_2_V_write_assign_proc : process(exitcond_reg_284, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_128, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_284 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
dst1_data_stream_2_V_write <= ap_const_logic_1;
else
dst1_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
dst2_data_stream_0_V_din <= src_data_stream_0_V_dout;
-- dst2_data_stream_0_V_write assign process. --
dst2_data_stream_0_V_write_assign_proc : process(exitcond_reg_284, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_128, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_284 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
dst2_data_stream_0_V_write <= ap_const_logic_1;
else
dst2_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
dst2_data_stream_1_V_din <= src_data_stream_1_V_dout;
-- dst2_data_stream_1_V_write assign process. --
dst2_data_stream_1_V_write_assign_proc : process(exitcond_reg_284, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_128, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_284 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
dst2_data_stream_1_V_write <= ap_const_logic_1;
else
dst2_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
dst2_data_stream_2_V_din <= src_data_stream_2_V_dout;
-- dst2_data_stream_2_V_write assign process. --
dst2_data_stream_2_V_write_assign_proc : process(exitcond_reg_284, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_128, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_284 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
dst2_data_stream_2_V_write <= ap_const_logic_1;
else
dst2_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
exitcond3_fu_239_p2 <= "1" when (p_cast_fu_235_p1 = dst2_rows_V_read) else "0";
exitcond_fu_254_p2 <= "1" when (p_3_cast_fu_250_p1 = dst2_cols_V_read) else "0";
i_V_fu_244_p2 <= std_logic_vector(unsigned(p_s_reg_212) + unsigned(ap_const_lv11_1));
j_V_fu_259_p2 <= std_logic_vector(unsigned(p_3_reg_223) + unsigned(ap_const_lv11_1));
p_3_cast_fu_250_p1 <= std_logic_vector(resize(unsigned(p_3_reg_223),12));
p_cast_fu_235_p1 <= std_logic_vector(resize(unsigned(p_s_reg_212),12));
-- src_data_stream_0_V_read assign process. --
src_data_stream_0_V_read_assign_proc : process(exitcond_reg_284, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_128, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_284 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
src_data_stream_0_V_read <= ap_const_logic_1;
else
src_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
-- src_data_stream_1_V_read assign process. --
src_data_stream_1_V_read_assign_proc : process(exitcond_reg_284, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_128, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_284 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
src_data_stream_1_V_read <= ap_const_logic_1;
else
src_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
-- src_data_stream_2_V_read assign process. --
src_data_stream_2_V_read_assign_proc : process(exitcond_reg_284, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_128, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_284 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not((ap_sig_bdd_128 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then
src_data_stream_2_V_read <= ap_const_logic_1;
else
src_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
end behav;
| gpl-3.0 | df57443961c22249e7934a3cf995d4e1 | 0.594293 | 2.672665 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_mask_data_stream_0_V.vhd | 2 | 4,621 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_mask_data_stream_0_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_mask_data_stream_0_V_shiftReg;
architecture rtl of FIFO_image_filter_mask_data_stream_0_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_mask_data_stream_0_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_mask_data_stream_0_V is
component FIFO_image_filter_mask_data_stream_0_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_mask_data_stream_0_V_shiftReg : FIFO_image_filter_mask_data_stream_0_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | 1d9d195f9a68c60c1fdf4d9c1ae8a79e | 0.538628 | 3.484917 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_Dilate_0_0_1080_1920_s.vhd | 2 | 92,940 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Dilate_0_0_1080_1920_s is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_V_empty_n : IN STD_LOGIC;
p_src_data_stream_V_read : OUT STD_LOGIC;
p_dst_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_V_full_n : IN STD_LOGIC;
p_dst_data_stream_V_write : OUT STD_LOGIC );
end;
architecture behav of image_filter_Dilate_0_0_1080_1920_s is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_pp0_stg0_fsm_3 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_st12_fsm_4 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv11_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000000101";
constant ap_const_lv11_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010";
constant ap_const_lv11_7FD : STD_LOGIC_VECTOR (10 downto 0) := "11111111101";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv11_7FF : STD_LOGIC_VECTOR (10 downto 0) := "11111111111";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv11_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100";
constant ap_const_lv12_FFC : STD_LOGIC_VECTOR (11 downto 0) := "111111111100";
constant ap_const_lv12_FFF : STD_LOGIC_VECTOR (11 downto 0) := "111111111111";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv12_FFB : STD_LOGIC_VECTOR (11 downto 0) := "111111111011";
constant ap_const_lv12_FFA : STD_LOGIC_VECTOR (11 downto 0) := "111111111010";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_24 : BOOLEAN;
signal p_025_0_i_i_reg_263 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_bdd_48 : BOOLEAN;
signal heightloop_fu_324_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal heightloop_reg_1240 : STD_LOGIC_VECTOR (10 downto 0);
signal widthloop_fu_330_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal widthloop_reg_1245 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_14_cast_fu_342_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_14_cast_reg_1250 : STD_LOGIC_VECTOR (11 downto 0);
signal p_neg226_i_i_cast_fu_350_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal p_neg226_i_i_cast_reg_1255 : STD_LOGIC_VECTOR (1 downto 0);
signal ref_fu_356_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ref_reg_1261 : STD_LOGIC_VECTOR (10 downto 0);
signal ref_cast_fu_362_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ref_cast_reg_1267 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_2_i_fu_366_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_2_i_reg_1272 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_2_i1_fu_376_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_2_i1_reg_1277 : STD_LOGIC_VECTOR (1 downto 0);
signal i_V_fu_391_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_1286 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_76 : BOOLEAN;
signal tmp_17_fu_397_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_reg_1291 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_fu_386_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_fu_409_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_23_reg_1296 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_fu_436_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_1301 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_104_reg_1306 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_105_fu_457_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_105_reg_1310 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_108_fu_473_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_108_reg_1316 : STD_LOGIC_VECTOR (1 downto 0);
signal or_cond_i1_fu_506_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_i1_reg_1322 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_110_reg_1327 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_111_fu_520_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_111_reg_1332 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_112_fu_524_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_112_reg_1337 : STD_LOGIC_VECTOR (1 downto 0);
signal or_cond_i2_fu_553_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_i2_reg_1344 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_114_reg_1349 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_115_fu_567_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_115_reg_1354 : STD_LOGIC_VECTOR (1 downto 0);
signal sel_tmp8_fu_575_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_reg_1359 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_116 : BOOLEAN;
signal sel_tmp3_fu_579_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp3_reg_1364 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_fu_602_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_reg_1369 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp7_fu_607_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp7_reg_1374 : STD_LOGIC_VECTOR (0 downto 0);
signal locy_2_t_fu_625_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal locy_2_t_reg_1379 : STD_LOGIC_VECTOR (1 downto 0);
signal brmerge_fu_630_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_reg_1383 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_fu_638_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_19_reg_1387 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_135 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_reg_1419 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_1419_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_154 : BOOLEAN;
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal or_cond219_i_i_reg_1396 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_172 : BOOLEAN;
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal j_V_fu_643_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal or_cond219_i_i_fu_665_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_117_fu_676_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_117_reg_1400 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_i_fu_698_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_reg_1405 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_i_reg_1405_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_i_reg_1405_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_i_fu_703_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_i_reg_1409 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_120_reg_1414 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_120_reg_1414_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_120_reg_1414_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_fu_723_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_or_cond2_reg_1419_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_729_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_reg_1423 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_tmp_29_reg_1423_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal col_assign_fu_734_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal col_assign_reg_1427 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_col_assign_reg_1427_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0);
signal k_buf_0_val_0_addr_reg_1433 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_1_addr_reg_1439 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_2_addr_reg_1445 : STD_LOGIC_VECTOR (10 downto 0);
signal col_assign_1_fu_762_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal col_assign_1_reg_1451 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 : STD_LOGIC_VECTOR (1 downto 0);
signal k_buf_0_val_0_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_2_0_reg_1457 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_0_reg_1464 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_2_0_reg_1471 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_0_1_reg_1477 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_0_1_6_reg_1483 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_1_6_reg_1490 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_2_lo_reg_1496 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_0_2_reg_1501 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_1_fu_1033_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_128_1_reg_1506 : STD_LOGIC_VECTOR (0 downto 0);
signal src_kernel_win_0_val_0_1_lo_reg_1511 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_1_lo_reg_1517 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_1_reg_1523 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_0_2_lo_reg_1529 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_2_reg_1534 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_2_fu_1080_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_128_2_reg_1539 : STD_LOGIC_VECTOR (0 downto 0);
signal temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal temp_0_i_i_i_057_i_i_1_2_1_reg_1544 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_0_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_0_ce0 : STD_LOGIC;
signal k_buf_0_val_0_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_0_ce1 : STD_LOGIC;
signal k_buf_0_val_0_we1 : STD_LOGIC;
signal k_buf_0_val_0_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_1_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_1_ce0 : STD_LOGIC;
signal k_buf_0_val_1_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_1_ce1 : STD_LOGIC;
signal k_buf_0_val_1_we1 : STD_LOGIC;
signal k_buf_0_val_1_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal k_buf_0_val_2_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_2_ce0 : STD_LOGIC;
signal k_buf_0_val_2_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal k_buf_0_val_2_ce1 : STD_LOGIC;
signal k_buf_0_val_2_we1 : STD_LOGIC;
signal k_buf_0_val_2_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_012_0_i_i_reg_252 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_sig_cseq_ST_st12_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_355 : BOOLEAN;
signal tmp_69_fu_755_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal src_kernel_win_0_val_0_1_fu_106 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_0_0_fu_934_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal col_buf_0_val_0_0_9_fu_989_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_0_2_fu_110 : STD_LOGIC_VECTOR (7 downto 0);
signal col_buf_0_val_0_0_3_fu_114 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_2_1_fu_118 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_1_fu_122 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_0_fu_946_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_11_fu_1006_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_1_2_fu_126 : STD_LOGIC_VECTOR (7 downto 0);
signal col_buf_0_val_0_0_5_fu_130 : STD_LOGIC_VECTOR (7 downto 0);
signal src_kernel_win_0_val_2_2_fu_134 : STD_LOGIC_VECTOR (7 downto 0);
signal col_buf_0_val_0_0_6_fu_138 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_1_fu_142 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_8_fu_877_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_2_fu_146 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_6_fu_868_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_7_fu_150 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_4_fu_851_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_0_0_fu_166 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_0_1_fu_170 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_0_2_fu_174 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_316_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_100_fu_320_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_14_fu_336_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_101_fu_346_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_102_fu_372_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_15_cast_cast_fu_382_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ImagLoc_y_fu_403_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_103_fu_415_p4 : STD_LOGIC_VECTOR (10 downto 0);
signal icmp_fu_425_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_431_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_i_i_fu_450_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_i5_fu_461_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_106_fu_466_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_107_fu_470_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal y_1_fu_481_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_109_fu_487_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i1_fu_501_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rev_fu_495_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal y_1_1_fu_528_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_113_fu_534_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i2_fu_548_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal rev1_fu_542_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal locy_fu_571_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_s_fu_585_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_80_fu_591_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal locy_1_t_fu_597_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_81_fu_613_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_82_fu_619_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_116_fu_649_p4 : STD_LOGIC_VECTOR (9 downto 0);
signal icmp2_fu_659_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_cast_fu_634_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ImagLoc_x_fu_670_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_119_fu_684_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rev2_fu_692_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_717_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_118_fu_680_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal p_assign_fu_739_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal p_assign_1_i_fu_745_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_121_fu_751_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal sel_tmp1_fu_833_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp5_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal right_border_buf_0_val_1_2_3_fu_838_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_5_fu_860_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_0_1_fu_904_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp9_fu_929_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal sel_tmp6_fu_941_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal sel_tmp_fu_971_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_fu_984_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal col_buf_0_val_0_0_2_fu_976_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal right_border_buf_0_val_1_2_fu_998_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_0_2_fu_1021_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal temp_0_i_i_i_057_i_i_1_1_fu_1050_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_1_1_fu_1055_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_128_1_2_fu_1070_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal temp_0_i_i_i_057_i_i_1_2_fu_1090_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_2_1_fu_1095_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_128_2_2_fu_1107_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
component image_filter_FAST_t_opr_k_buf_val_0_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (10 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (10 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
k_buf_0_val_0_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_0_val_0_address0,
ce0 => k_buf_0_val_0_ce0,
q0 => k_buf_0_val_0_q0,
address1 => k_buf_0_val_0_address1,
ce1 => k_buf_0_val_0_ce1,
we1 => k_buf_0_val_0_we1,
d1 => k_buf_0_val_0_d1);
k_buf_0_val_1_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_0_val_1_address0,
ce0 => k_buf_0_val_1_ce0,
q0 => k_buf_0_val_1_q0,
address1 => k_buf_0_val_1_address1,
ce1 => k_buf_0_val_1_ce1,
we1 => k_buf_0_val_1_we1,
d1 => k_buf_0_val_1_d1);
k_buf_0_val_2_U : component image_filter_FAST_t_opr_k_buf_val_0_V
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => k_buf_0_val_2_address0,
ce0 => k_buf_0_val_2_ce0,
q0 => k_buf_0_val_2_q0,
address1 => k_buf_0_val_2_address1,
ce1 => k_buf_0_val_2_ce1,
we1 => k_buf_0_val_2_we1,
d1 => k_buf_0_val_2_d1);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_19_fu_638_p2))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
if (not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2))) then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- p_012_0_i_i_reg_252 assign process. --
p_012_0_i_i_reg_252_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_4)) then
p_012_0_i_i_reg_252 <= i_V_reg_1286;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_48))) then
p_012_0_i_i_reg_252 <= ap_const_lv11_0;
end if;
end if;
end process;
-- p_025_0_i_i_reg_263 assign process. --
p_025_0_i_i_reg_263_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then
p_025_0_i_i_reg_263 <= j_V_fu_643_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
p_025_0_i_i_reg_263 <= ap_const_lv11_0;
end if;
end if;
end process;
-- src_kernel_win_0_val_0_1_fu_106 assign process. --
src_kernel_win_0_val_0_1_fu_106_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2))) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2))))) then
src_kernel_win_0_val_0_1_fu_106 <= right_border_buf_0_val_2_0_reg_1457;
elsif (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0))))) then
src_kernel_win_0_val_0_1_fu_106 <= col_buf_0_val_0_0_9_fu_989_p3;
elsif ((((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))))) then
src_kernel_win_0_val_0_1_fu_106 <= src_kernel_win_0_val_0_0_fu_934_p3;
end if;
end if;
end process;
-- src_kernel_win_0_val_1_1_fu_122 assign process. --
src_kernel_win_0_val_1_1_fu_122_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2))) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2))))) then
src_kernel_win_0_val_1_1_fu_122 <= right_border_buf_0_val_1_0_reg_1464;
elsif (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0))))) then
src_kernel_win_0_val_1_1_fu_122 <= right_border_buf_0_val_1_2_11_fu_1006_p3;
elsif ((((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))))) then
src_kernel_win_0_val_1_1_fu_122 <= src_kernel_win_0_val_1_0_fu_946_p3;
end if;
end if;
end process;
-- src_kernel_win_0_val_2_1_fu_118 assign process. --
src_kernel_win_0_val_2_1_fu_118_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and not((col_assign_1_reg_1451 = ap_const_lv2_1)) and not((col_assign_1_reg_1451 = ap_const_lv2_0)))) then
src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_2_fu_174;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and (col_assign_1_reg_1451 = ap_const_lv2_0))) then
src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_0_fu_166;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and (col_assign_1_reg_1451 = ap_const_lv2_1))) then
src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_1_fu_170;
elsif (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1))))) then
src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_2_q0;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0))) then
src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_0_q0;
elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1))) then
src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_1_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then
ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 <= col_assign_1_reg_1451;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5;
ap_reg_ppstg_or_cond2_reg_1419_pp0_it2 <= ap_reg_ppstg_or_cond2_reg_1419_pp0_it1;
ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4 <= src_kernel_win_0_val_0_1_6_reg_1483;
ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4;
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5 <= src_kernel_win_0_val_0_1_lo_reg_1511;
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5;
ap_reg_ppstg_tmp_120_reg_1414_pp0_it2 <= ap_reg_ppstg_tmp_120_reg_1414_pp0_it1;
ap_reg_ppstg_tmp_19_reg_1387_pp0_it2 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it1;
ap_reg_ppstg_tmp_19_reg_1387_pp0_it3 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it2;
ap_reg_ppstg_tmp_19_reg_1387_pp0_it4 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it3;
ap_reg_ppstg_tmp_i_reg_1405_pp0_it2 <= ap_reg_ppstg_tmp_i_reg_1405_pp0_it1;
src_kernel_win_0_val_0_1_6_reg_1483 <= src_kernel_win_0_val_0_1_fu_106;
src_kernel_win_0_val_1_1_6_reg_1490 <= src_kernel_win_0_val_1_1_fu_122;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
ap_reg_ppstg_col_assign_reg_1427_pp0_it1 <= col_assign_reg_1427;
ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1 <= or_cond219_i_i_reg_1396;
ap_reg_ppstg_or_cond2_reg_1419_pp0_it1 <= or_cond2_reg_1419;
ap_reg_ppstg_tmp_120_reg_1414_pp0_it1 <= tmp_120_reg_1414;
ap_reg_ppstg_tmp_19_reg_1387_pp0_it1 <= tmp_19_reg_1387;
ap_reg_ppstg_tmp_29_reg_1423_pp0_it1 <= tmp_29_reg_1423;
ap_reg_ppstg_tmp_i_reg_1405_pp0_it1 <= tmp_i_reg_1405;
tmp_19_reg_1387 <= tmp_19_fu_638_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
brmerge_reg_1383 <= brmerge_fu_630_p2;
locy_2_t_reg_1379 <= locy_2_t_fu_625_p2;
sel_tmp3_reg_1364 <= sel_tmp3_fu_579_p2;
sel_tmp4_reg_1369 <= sel_tmp4_fu_602_p2;
sel_tmp7_reg_1374 <= sel_tmp7_fu_607_p2;
sel_tmp8_reg_1359 <= sel_tmp8_fu_575_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_reg_1387)) and (ap_const_lv1_0 = or_cond2_reg_1419) and (ap_const_lv1_0 = tmp_120_reg_1414) and (ap_const_lv1_0 = tmp_i_reg_1405))) then
col_assign_1_reg_1451 <= col_assign_1_fu_762_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)) and not((ap_const_lv1_0 = or_cond2_fu_723_p2)) and (ap_const_lv1_0 = tmp_29_fu_729_p2))) then
col_assign_reg_1427 <= col_assign_fu_734_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0)))) then
col_buf_0_val_0_0_3_fu_114 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_2_fu_174 <= k_buf_0_val_2_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1))) then
col_buf_0_val_0_0_5_fu_130 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_1_fu_170 <= k_buf_0_val_2_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0))) then
col_buf_0_val_0_0_6_fu_138 <= k_buf_0_val_0_q0;
right_border_buf_0_val_0_0_fu_166 <= k_buf_0_val_2_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_48))) then
heightloop_reg_1240 <= heightloop_fu_324_p2;
p_neg226_i_i_cast_reg_1255 <= p_neg226_i_i_cast_fu_350_p2;
ref_cast_reg_1267(0) <= ref_cast_fu_362_p1(0);
ref_cast_reg_1267(1) <= ref_cast_fu_362_p1(1);
ref_cast_reg_1267(2) <= ref_cast_fu_362_p1(2);
ref_cast_reg_1267(3) <= ref_cast_fu_362_p1(3);
ref_cast_reg_1267(4) <= ref_cast_fu_362_p1(4);
ref_cast_reg_1267(5) <= ref_cast_fu_362_p1(5);
ref_cast_reg_1267(6) <= ref_cast_fu_362_p1(6);
ref_cast_reg_1267(7) <= ref_cast_fu_362_p1(7);
ref_cast_reg_1267(8) <= ref_cast_fu_362_p1(8);
ref_cast_reg_1267(9) <= ref_cast_fu_362_p1(9);
ref_cast_reg_1267(10) <= ref_cast_fu_362_p1(10);
ref_reg_1261 <= ref_fu_356_p2;
tmp_14_cast_reg_1250(0) <= tmp_14_cast_fu_342_p1(0);
tmp_14_cast_reg_1250(1) <= tmp_14_cast_fu_342_p1(1);
tmp_14_cast_reg_1250(2) <= tmp_14_cast_fu_342_p1(2);
tmp_14_cast_reg_1250(3) <= tmp_14_cast_fu_342_p1(3);
tmp_14_cast_reg_1250(4) <= tmp_14_cast_fu_342_p1(4);
tmp_14_cast_reg_1250(5) <= tmp_14_cast_fu_342_p1(5);
tmp_14_cast_reg_1250(6) <= tmp_14_cast_fu_342_p1(6);
tmp_14_cast_reg_1250(7) <= tmp_14_cast_fu_342_p1(7);
tmp_14_cast_reg_1250(8) <= tmp_14_cast_fu_342_p1(8);
tmp_14_cast_reg_1250(9) <= tmp_14_cast_fu_342_p1(9);
tmp_14_cast_reg_1250(10) <= tmp_14_cast_fu_342_p1(10);
tmp_2_i1_reg_1277 <= tmp_2_i1_fu_376_p2;
tmp_2_i_reg_1272 <= tmp_2_i_fu_366_p2;
widthloop_reg_1245 <= widthloop_fu_330_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
i_V_reg_1286 <= i_V_fu_391_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_reg_1387)))) then
k_buf_0_val_0_addr_reg_1433 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_1_addr_reg_1439 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_2_addr_reg_1445 <= tmp_69_fu_755_p1(11 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then
or_cond219_i_i_reg_1396 <= or_cond219_i_i_fu_665_p2;
or_cond_i_reg_1409 <= or_cond_i_fu_703_p2;
tmp_117_reg_1400 <= tmp_117_fu_676_p1;
tmp_120_reg_1414 <= ImagLoc_x_fu_670_p2(11 downto 11);
tmp_i_reg_1405 <= tmp_i_fu_698_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then
or_cond2_reg_1419 <= or_cond2_fu_723_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((tmp_16_fu_386_p2 = ap_const_lv1_0)))) then
or_cond_i1_reg_1322 <= or_cond_i1_fu_506_p2;
or_cond_i2_reg_1344 <= or_cond_i2_fu_553_p2;
or_cond_reg_1301 <= or_cond_fu_436_p2;
tmp_104_reg_1306 <= ImagLoc_y_fu_403_p2(11 downto 11);
tmp_105_reg_1310 <= tmp_105_fu_457_p1;
tmp_108_reg_1316 <= tmp_108_fu_473_p3;
tmp_110_reg_1327 <= y_1_fu_481_p2(11 downto 11);
tmp_111_reg_1332 <= tmp_111_fu_520_p1;
tmp_112_reg_1337 <= tmp_112_fu_524_p1;
tmp_114_reg_1349 <= y_1_1_fu_528_p2(11 downto 11);
tmp_115_reg_1354 <= tmp_115_fu_567_p1;
tmp_17_reg_1291 <= tmp_17_fu_397_p2;
tmp_23_reg_1296 <= tmp_23_fu_409_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
right_border_buf_0_val_1_0_reg_1464 <= k_buf_0_val_1_q0;
right_border_buf_0_val_2_0_reg_1457 <= k_buf_0_val_0_q0;
src_kernel_win_0_val_2_0_reg_1471 <= k_buf_0_val_2_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0)))) then
right_border_buf_0_val_1_2_1_fu_142 <= right_border_buf_0_val_1_2_8_fu_877_p3;
right_border_buf_0_val_1_2_2_fu_146 <= right_border_buf_0_val_1_2_6_fu_868_p3;
right_border_buf_0_val_1_2_7_fu_150 <= right_border_buf_0_val_1_2_4_fu_851_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3)))) then
src_kernel_win_0_val_0_1_lo_reg_1511 <= src_kernel_win_0_val_0_1_fu_106;
src_kernel_win_0_val_1_1_lo_reg_1517 <= src_kernel_win_0_val_1_1_fu_122;
temp_0_i_i_i_057_i_i_1_1_1_reg_1523 <= temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it4)))) then
src_kernel_win_0_val_0_2_fu_110 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4)))) then
src_kernel_win_0_val_0_2_lo_reg_1529 <= src_kernel_win_0_val_0_2_fu_110;
temp_0_i_i_i_057_i_i_1_1_2_reg_1534 <= temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3;
tmp_128_2_reg_1539 <= tmp_128_2_fu_1080_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)))) then
src_kernel_win_0_val_1_2_fu_126 <= src_kernel_win_0_val_1_1_fu_122;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2)))) then
src_kernel_win_0_val_1_2_lo_reg_1496 <= src_kernel_win_0_val_1_2_fu_126;
temp_0_i_i_i_057_i_i_1_0_2_reg_1501 <= temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3;
tmp_128_1_reg_1506 <= tmp_128_1_fu_1033_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
src_kernel_win_0_val_2_2_fu_134 <= src_kernel_win_0_val_2_1_fu_118;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1)))) then
temp_0_i_i_i_057_i_i_1_0_1_reg_1477 <= temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5)))) then
temp_0_i_i_i_057_i_i_1_2_1_reg_1544 <= temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)) and not((ap_const_lv1_0 = or_cond2_fu_723_p2)))) then
tmp_29_reg_1423 <= tmp_29_fu_729_p2;
end if;
end if;
end process;
tmp_14_cast_reg_1250(11) <= '0';
ref_cast_reg_1267(11) <= '0';
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_48, tmp_16_fu_386_p2, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it6, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_48)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((tmp_16_fu_386_p2 = ap_const_lv1_0)) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3;
when ap_ST_pp0_stg0_fsm_3 =>
if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it6)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it4)))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3;
elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it6))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it4))))) then
ap_NS_fsm <= ap_ST_st12_fsm_4;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3;
end if;
when ap_ST_st12_fsm_4 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ImagLoc_x_fu_670_p2 <= std_logic_vector(unsigned(tmp_18_cast_fu_634_p1) + unsigned(ap_const_lv12_FFF));
ImagLoc_y_fu_403_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFC));
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st2_fsm_1, tmp_16_fu_386_p2)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_16_fu_386_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_116 assign process. --
ap_sig_bdd_116_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_116 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_135 assign process. --
ap_sig_bdd_135_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_135 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_154 assign process. --
ap_sig_bdd_154_assign_proc : process(p_src_data_stream_V_empty_n, brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)
begin
ap_sig_bdd_154 <= ((p_src_data_stream_V_empty_n = ap_const_logic_0) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)));
end process;
-- ap_sig_bdd_172 assign process. --
ap_sig_bdd_172_assign_proc : process(p_dst_data_stream_V_full_n, ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6)
begin
ap_sig_bdd_172 <= ((p_dst_data_stream_V_full_n = ap_const_logic_0) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6)));
end process;
-- ap_sig_bdd_24 assign process. --
ap_sig_bdd_24_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_24 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_355 assign process. --
ap_sig_bdd_355_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_355 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_48 assign process. --
ap_sig_bdd_48_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_48 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_76 assign process. --
ap_sig_bdd_76_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_76 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_3 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_3_assign_proc : process(ap_sig_bdd_135)
begin
if (ap_sig_bdd_135) then
ap_sig_cseq_ST_pp0_stg0_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_4 assign process. --
ap_sig_cseq_ST_st12_fsm_4_assign_proc : process(ap_sig_bdd_355)
begin
if (ap_sig_bdd_355) then
ap_sig_cseq_ST_st12_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_24)
begin
if (ap_sig_bdd_24) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_76)
begin
if (ap_sig_bdd_76) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_116)
begin
if (ap_sig_bdd_116) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
brmerge_fu_630_p2 <= (tmp_23_reg_1296 or or_cond_reg_1301);
col_assign_1_fu_762_p2 <= std_logic_vector(unsigned(tmp_121_fu_751_p1) + unsigned(p_neg226_i_i_cast_reg_1255));
col_assign_fu_734_p2 <= std_logic_vector(unsigned(tmp_118_fu_680_p1) + unsigned(p_neg226_i_i_cast_reg_1255));
col_buf_0_val_0_0_2_fu_976_p3 <=
col_buf_0_val_0_0_5_fu_130 when (sel_tmp_fu_971_p2(0) = '1') else
col_buf_0_val_0_0_3_fu_114;
col_buf_0_val_0_0_9_fu_989_p3 <=
col_buf_0_val_0_0_6_fu_138 when (sel_tmp2_fu_984_p2(0) = '1') else
col_buf_0_val_0_0_2_fu_976_p3;
heightloop_fu_324_p2 <= std_logic_vector(unsigned(tmp_fu_316_p1) + unsigned(ap_const_lv11_5));
i_V_fu_391_p2 <= std_logic_vector(unsigned(p_012_0_i_i_reg_252) + unsigned(ap_const_lv11_1));
icmp2_fu_659_p2 <= "0" when (tmp_116_fu_649_p4 = ap_const_lv10_0) else "1";
icmp_fu_425_p2 <= "1" when (signed(tmp_103_fu_415_p4) > signed(ap_const_lv11_0)) else "0";
j_V_fu_643_p2 <= std_logic_vector(unsigned(p_025_0_i_i_reg_263) + unsigned(ap_const_lv11_1));
k_buf_0_val_0_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_0_address1 <= k_buf_0_val_0_addr_reg_1433;
-- k_buf_0_val_0_ce0 assign process. --
k_buf_0_val_0_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
k_buf_0_val_0_ce0 <= ap_const_logic_1;
else
k_buf_0_val_0_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_0_val_0_ce1 assign process. --
k_buf_0_val_0_ce1_assign_proc : process(ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
k_buf_0_val_0_ce1 <= ap_const_logic_1;
else
k_buf_0_val_0_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_0_d1 <= p_src_data_stream_V_dout;
-- k_buf_0_val_0_we1 assign process. --
k_buf_0_val_0_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))))) then
k_buf_0_val_0_we1 <= ap_const_logic_1;
else
k_buf_0_val_0_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_1_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_1_address1 <= k_buf_0_val_1_addr_reg_1439;
-- k_buf_0_val_1_ce0 assign process. --
k_buf_0_val_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
k_buf_0_val_1_ce0 <= ap_const_logic_1;
else
k_buf_0_val_1_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_0_val_1_ce1 assign process. --
k_buf_0_val_1_ce1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then
k_buf_0_val_1_ce1 <= ap_const_logic_1;
else
k_buf_0_val_1_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_1_d1 <= k_buf_0_val_0_q0;
-- k_buf_0_val_1_we1 assign process. --
k_buf_0_val_1_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then
k_buf_0_val_1_we1 <= ap_const_logic_1;
else
k_buf_0_val_1_we1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_2_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0);
k_buf_0_val_2_address1 <= k_buf_0_val_2_addr_reg_1445;
-- k_buf_0_val_2_ce0 assign process. --
k_buf_0_val_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
k_buf_0_val_2_ce0 <= ap_const_logic_1;
else
k_buf_0_val_2_ce0 <= ap_const_logic_0;
end if;
end process;
-- k_buf_0_val_2_ce1 assign process. --
k_buf_0_val_2_ce1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then
k_buf_0_val_2_ce1 <= ap_const_logic_1;
else
k_buf_0_val_2_ce1 <= ap_const_logic_0;
end if;
end process;
k_buf_0_val_2_d1 <= k_buf_0_val_1_q0;
-- k_buf_0_val_2_we1 assign process. --
k_buf_0_val_2_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)
begin
if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then
k_buf_0_val_2_we1 <= ap_const_logic_1;
else
k_buf_0_val_2_we1 <= ap_const_logic_0;
end if;
end process;
locy_1_t_fu_597_p2 <= std_logic_vector(unsigned(tmp_112_reg_1337) - unsigned(tmp_80_fu_591_p3));
locy_2_t_fu_625_p2 <= std_logic_vector(unsigned(tmp_112_reg_1337) - unsigned(tmp_82_fu_619_p3));
locy_fu_571_p2 <= std_logic_vector(unsigned(tmp_105_reg_1310) - unsigned(tmp_108_reg_1316));
or_cond219_i_i_fu_665_p2 <= (tmp_17_reg_1291 and icmp2_fu_659_p2);
or_cond2_fu_723_p2 <= (tmp_26_fu_717_p2 and tmp_i_fu_698_p2);
or_cond_fu_436_p2 <= (icmp_fu_425_p2 and tmp_25_fu_431_p2);
or_cond_i1_fu_506_p2 <= (tmp_i1_fu_501_p2 and rev_fu_495_p2);
or_cond_i2_fu_553_p2 <= (tmp_i2_fu_548_p2 and rev1_fu_542_p2);
or_cond_i_fu_703_p2 <= (tmp_i_fu_698_p2 and rev2_fu_692_p2);
p_assign_1_i_fu_745_p3 <=
tmp_117_reg_1400 when (or_cond_i_reg_1409(0) = '1') else
p_assign_fu_739_p3;
p_assign_fu_739_p3 <=
ap_const_lv11_0 when (tmp_120_reg_1414(0) = '1') else
tmp_2_i_reg_1272;
p_dst_data_stream_V_din <=
ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 when (tmp_128_2_2_fu_1107_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_2_1_reg_1544;
-- p_dst_data_stream_V_write assign process. --
p_dst_data_stream_V_write_assign_proc : process(ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if ((not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
p_dst_data_stream_V_write <= ap_const_logic_1;
else
p_dst_data_stream_V_write <= ap_const_logic_0;
end if;
end process;
p_i_i_fu_450_p3 <=
ap_const_lv11_2 when (tmp_25_fu_431_p2(0) = '1') else
ref_reg_1261;
p_neg226_i_i_cast_fu_350_p2 <= (tmp_101_fu_346_p1 xor ap_const_lv2_3);
-- p_src_data_stream_V_read assign process. --
p_src_data_stream_V_read_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7)
begin
if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then
p_src_data_stream_V_read <= ap_const_logic_1;
else
p_src_data_stream_V_read <= ap_const_logic_0;
end if;
end process;
ref_cast_fu_362_p1 <= std_logic_vector(resize(unsigned(ref_fu_356_p2),12));
ref_fu_356_p2 <= std_logic_vector(unsigned(tmp_fu_316_p1) + unsigned(ap_const_lv11_7FF));
rev1_fu_542_p2 <= (tmp_113_fu_534_p3 xor ap_const_lv1_1);
rev2_fu_692_p2 <= (tmp_119_fu_684_p3 xor ap_const_lv1_1);
rev_fu_495_p2 <= (tmp_109_fu_487_p3 xor ap_const_lv1_1);
right_border_buf_0_val_1_2_11_fu_1006_p3 <=
right_border_buf_0_val_1_2_1_fu_142 when (sel_tmp2_fu_984_p2(0) = '1') else
right_border_buf_0_val_1_2_fu_998_p3;
right_border_buf_0_val_1_2_3_fu_838_p3 <=
right_border_buf_0_val_1_2_7_fu_150 when (sel_tmp1_fu_833_p2(0) = '1') else
k_buf_0_val_1_q0;
right_border_buf_0_val_1_2_4_fu_851_p3 <=
right_border_buf_0_val_1_2_7_fu_150 when (sel_tmp5_fu_846_p2(0) = '1') else
right_border_buf_0_val_1_2_3_fu_838_p3;
right_border_buf_0_val_1_2_5_fu_860_p3 <=
k_buf_0_val_1_q0 when (sel_tmp1_fu_833_p2(0) = '1') else
right_border_buf_0_val_1_2_2_fu_146;
right_border_buf_0_val_1_2_6_fu_868_p3 <=
right_border_buf_0_val_1_2_2_fu_146 when (sel_tmp5_fu_846_p2(0) = '1') else
right_border_buf_0_val_1_2_5_fu_860_p3;
right_border_buf_0_val_1_2_8_fu_877_p3 <=
k_buf_0_val_1_q0 when (sel_tmp5_fu_846_p2(0) = '1') else
right_border_buf_0_val_1_2_1_fu_142;
right_border_buf_0_val_1_2_fu_998_p3 <=
right_border_buf_0_val_1_2_2_fu_146 when (sel_tmp_fu_971_p2(0) = '1') else
right_border_buf_0_val_1_2_7_fu_150;
sel_tmp1_fu_833_p2 <= "1" when (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1) else "0";
sel_tmp2_fu_984_p2 <= "1" when (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0) else "0";
sel_tmp3_fu_579_p2 <= "1" when (locy_fu_571_p2 = ap_const_lv2_1) else "0";
sel_tmp4_fu_602_p2 <= "1" when (tmp_112_reg_1337 = tmp_80_fu_591_p3) else "0";
sel_tmp5_fu_846_p2 <= "1" when (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0) else "0";
sel_tmp6_fu_941_p3 <=
right_border_buf_0_val_2_0_reg_1457 when (sel_tmp4_reg_1369(0) = '1') else
src_kernel_win_0_val_2_0_reg_1471;
sel_tmp7_fu_607_p2 <= "1" when (locy_1_t_fu_597_p2 = ap_const_lv2_1) else "0";
sel_tmp8_fu_575_p2 <= "1" when (tmp_105_reg_1310 = tmp_108_reg_1316) else "0";
sel_tmp9_fu_929_p3 <=
right_border_buf_0_val_2_0_reg_1457 when (sel_tmp8_reg_1359(0) = '1') else
src_kernel_win_0_val_2_0_reg_1471;
sel_tmp_fu_971_p2 <= "1" when (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1) else "0";
src_kernel_win_0_val_0_0_fu_934_p3 <=
right_border_buf_0_val_1_0_reg_1464 when (sel_tmp3_reg_1364(0) = '1') else
sel_tmp9_fu_929_p3;
src_kernel_win_0_val_1_0_fu_946_p3 <=
right_border_buf_0_val_1_0_reg_1464 when (sel_tmp7_reg_1374(0) = '1') else
sel_tmp6_fu_941_p3;
temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3 <=
src_kernel_win_0_val_2_1_fu_118 when (tmp_128_0_1_fu_904_p2(0) = '1') else
src_kernel_win_0_val_2_2_fu_134;
temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3 <=
src_kernel_win_0_val_2_1_fu_118 when (tmp_128_0_2_fu_1021_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_0_1_reg_1477;
temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3 <=
src_kernel_win_0_val_1_1_6_reg_1490 when (tmp_128_1_1_fu_1055_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_1_fu_1050_p3;
temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3 <=
src_kernel_win_0_val_1_1_lo_reg_1517 when (tmp_128_1_2_fu_1070_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_1_1_reg_1523;
temp_0_i_i_i_057_i_i_1_1_fu_1050_p3 <=
src_kernel_win_0_val_1_2_lo_reg_1496 when (tmp_128_1_reg_1506(0) = '1') else
temp_0_i_i_i_057_i_i_1_0_2_reg_1501;
temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3 <=
ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 when (tmp_128_2_1_fu_1095_p2(0) = '1') else
temp_0_i_i_i_057_i_i_1_2_fu_1090_p3;
temp_0_i_i_i_057_i_i_1_2_fu_1090_p3 <=
src_kernel_win_0_val_0_2_lo_reg_1529 when (tmp_128_2_reg_1539(0) = '1') else
temp_0_i_i_i_057_i_i_1_1_2_reg_1534;
tmp_100_fu_320_p1 <= p_src_cols_V_read(11 - 1 downto 0);
tmp_101_fu_346_p1 <= p_src_cols_V_read(2 - 1 downto 0);
tmp_102_fu_372_p1 <= p_src_rows_V_read(2 - 1 downto 0);
tmp_103_fu_415_p4 <= ImagLoc_y_fu_403_p2(11 downto 1);
tmp_105_fu_457_p1 <= p_i_i_fu_450_p3(2 - 1 downto 0);
tmp_106_fu_466_p1 <= ImagLoc_y_fu_403_p2(2 - 1 downto 0);
tmp_107_fu_470_p1 <= ref_reg_1261(2 - 1 downto 0);
tmp_108_fu_473_p3 <=
tmp_106_fu_466_p1 when (tmp_i5_fu_461_p2(0) = '1') else
tmp_107_fu_470_p1;
tmp_109_fu_487_p3 <= y_1_fu_481_p2(11 downto 11);
tmp_111_fu_520_p1 <= y_1_fu_481_p2(2 - 1 downto 0);
tmp_112_fu_524_p1 <= p_i_i_fu_450_p3(2 - 1 downto 0);
tmp_113_fu_534_p3 <= y_1_1_fu_528_p2(11 downto 11);
tmp_115_fu_567_p1 <= y_1_1_fu_528_p2(2 - 1 downto 0);
tmp_116_fu_649_p4 <= p_025_0_i_i_reg_263(10 downto 1);
tmp_117_fu_676_p1 <= ImagLoc_x_fu_670_p2(11 - 1 downto 0);
tmp_118_fu_680_p1 <= ImagLoc_x_fu_670_p2(2 - 1 downto 0);
tmp_119_fu_684_p3 <= ImagLoc_x_fu_670_p2(11 downto 11);
tmp_121_fu_751_p1 <= p_assign_1_i_fu_745_p3(2 - 1 downto 0);
tmp_128_0_1_fu_904_p2 <= "1" when (unsigned(src_kernel_win_0_val_2_1_fu_118) > unsigned(src_kernel_win_0_val_2_2_fu_134)) else "0";
tmp_128_0_2_fu_1021_p2 <= "1" when (unsigned(src_kernel_win_0_val_2_1_fu_118) > unsigned(temp_0_i_i_i_057_i_i_1_0_1_reg_1477)) else "0";
tmp_128_1_1_fu_1055_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_1_6_reg_1490) > unsigned(temp_0_i_i_i_057_i_i_1_1_fu_1050_p3)) else "0";
tmp_128_1_2_fu_1070_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_1_lo_reg_1517) > unsigned(temp_0_i_i_i_057_i_i_1_1_1_reg_1523)) else "0";
tmp_128_1_fu_1033_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_2_fu_126) > unsigned(temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3)) else "0";
tmp_128_2_1_fu_1095_p2 <= "1" when (unsigned(ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5) > unsigned(temp_0_i_i_i_057_i_i_1_2_fu_1090_p3)) else "0";
tmp_128_2_2_fu_1107_p2 <= "1" when (unsigned(ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6) > unsigned(temp_0_i_i_i_057_i_i_1_2_1_reg_1544)) else "0";
tmp_128_2_fu_1080_p2 <= "1" when (unsigned(src_kernel_win_0_val_0_2_fu_110) > unsigned(temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3)) else "0";
tmp_14_cast_fu_342_p1 <= std_logic_vector(resize(unsigned(tmp_14_fu_336_p2),12));
tmp_14_fu_336_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_7FD));
tmp_15_cast_cast_fu_382_p1 <= std_logic_vector(resize(unsigned(p_012_0_i_i_reg_252),12));
tmp_16_fu_386_p2 <= "1" when (unsigned(p_012_0_i_i_reg_252) < unsigned(heightloop_reg_1240)) else "0";
tmp_17_fu_397_p2 <= "1" when (unsigned(p_012_0_i_i_reg_252) > unsigned(ap_const_lv11_4)) else "0";
tmp_18_cast_fu_634_p1 <= std_logic_vector(resize(unsigned(p_025_0_i_i_reg_263),12));
tmp_19_fu_638_p2 <= "1" when (unsigned(p_025_0_i_i_reg_263) < unsigned(widthloop_reg_1245)) else "0";
tmp_23_fu_409_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(ap_const_lv12_FFF)) else "0";
tmp_25_fu_431_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(ref_cast_reg_1267)) else "0";
tmp_26_fu_717_p2 <= "0" when (p_025_0_i_i_reg_263 = ap_const_lv11_0) else "1";
tmp_29_fu_729_p2 <= "1" when (signed(ImagLoc_x_fu_670_p2) < signed(tmp_14_cast_reg_1250)) else "0";
tmp_2_i1_fu_376_p2 <= std_logic_vector(unsigned(tmp_102_fu_372_p1) + unsigned(ap_const_lv2_3));
tmp_2_i_fu_366_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_7FF));
tmp_69_fu_755_p1 <= std_logic_vector(resize(unsigned(p_assign_1_i_fu_745_p3),64));
tmp_80_fu_591_p3 <=
tmp_111_reg_1332 when (or_cond_i1_reg_1322(0) = '1') else
tmp_s_fu_585_p3;
tmp_81_fu_613_p3 <=
ap_const_lv2_0 when (tmp_114_reg_1349(0) = '1') else
tmp_2_i1_reg_1277;
tmp_82_fu_619_p3 <=
tmp_115_reg_1354 when (or_cond_i2_reg_1344(0) = '1') else
tmp_81_fu_613_p3;
tmp_fu_316_p1 <= p_src_rows_V_read(11 - 1 downto 0);
tmp_i1_fu_501_p2 <= "1" when (signed(y_1_fu_481_p2) < signed(p_src_rows_V_read)) else "0";
tmp_i2_fu_548_p2 <= "1" when (signed(y_1_1_fu_528_p2) < signed(p_src_rows_V_read)) else "0";
tmp_i5_fu_461_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(p_src_rows_V_read)) else "0";
tmp_i_fu_698_p2 <= "1" when (signed(ImagLoc_x_fu_670_p2) < signed(p_src_cols_V_read)) else "0";
tmp_s_fu_585_p3 <=
ap_const_lv2_0 when (tmp_110_reg_1327(0) = '1') else
tmp_2_i1_reg_1277;
widthloop_fu_330_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_2));
y_1_1_fu_528_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFA));
y_1_fu_481_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFB));
end behav;
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`protect end_protected
| lgpl-3.0 | 274cc85c3657719eec64fb1536d150d4 | 0.951498 | 1.815706 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/road/simulation/road_tb.vhd | 1 | 4,331 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: road_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY road_tb IS
END ENTITY;
ARCHITECTURE road_tb_ARCH OF road_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
road_synth_inst:ENTITY work.road_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | bb9526839672fabd1b3bf0e983a32c15 | 0.618333 | 4.632086 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_cmd_status.vhd | 5 | 19,764 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1;
Use axi_sg_v4_1.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_sg_cmd_status;
architecture implementation of axi_sg_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
-- coverage off
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
-- coverage on
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_sg_v4_1.axi_sg_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
I_CACHE_FIFO : entity axi_sg_v4_1.axi_sg_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_sg_v4_1.axi_sg_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
| gpl-3.0 | 76313314662960f4e1d4e2cb33764b42 | 0.42289 | 4.918865 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter.vhd | 2 | 183,530 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter is
port (
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
OUTPUT_STREAM_TVALID : OUT STD_LOGIC;
OUTPUT_STREAM_TREADY : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC );
end;
architecture behav of image_filter is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"image_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=6.666670,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=6.112860,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=59,HLS_SYN_DSP=3,HLS_SYN_FF=7667,HLS_SYN_LUT=13162}";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_true : BOOLEAN := true;
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_logic_1 : STD_LOGIC := '1';
signal ap_rst_n_inv : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_start : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_done : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_continue : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_idle : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_ready : STD_LOGIC;
signal image_filter_Block_proc_U0_rows : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Block_proc_U0_cols : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Block_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_2 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_3 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_4 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_5 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_6 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_7 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_8 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_9 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_10 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_11 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel : STD_LOGIC;
signal p_dst_cols_V_channel_full_n : STD_LOGIC;
signal ap_reg_ready_p_dst_cols_V_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_p_dst_cols_V_channel_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1 : STD_LOGIC;
signal p_src_cols_V_2_loc_channel1_full_n : STD_LOGIC;
signal ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n : STD_LOGIC := '0';
signal ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel : STD_LOGIC;
signal p_src_cols_V_2_loc_channel_full_n : STD_LOGIC;
signal ap_reg_ready_p_src_cols_V_2_loc_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_p_src_cols_V_2_loc_channel_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1 : STD_LOGIC;
signal p_src_rows_V_2_loc_channel1_full_n : STD_LOGIC;
signal ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n : STD_LOGIC := '0';
signal ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel : STD_LOGIC;
signal p_src_rows_V_2_loc_channel_full_n : STD_LOGIC;
signal ap_reg_ready_p_src_rows_V_2_loc_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_p_src_rows_V_2_loc_channel_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel : STD_LOGIC;
signal p_src_cols_V_channel_full_n : STD_LOGIC;
signal ap_reg_ready_p_src_cols_V_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_p_src_cols_V_channel_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V : STD_LOGIC;
signal p_dst_cols_V_full_n : STD_LOGIC;
signal ap_reg_ready_p_dst_cols_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_p_dst_cols_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel : STD_LOGIC;
signal p_dst_rows_V_channel_full_n : STD_LOGIC;
signal ap_reg_ready_p_dst_rows_V_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_p_dst_rows_V_channel_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V : STD_LOGIC;
signal p_dst_rows_V_full_n : STD_LOGIC;
signal ap_reg_ready_p_dst_rows_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_p_dst_rows_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel : STD_LOGIC;
signal p_src_rows_V_channel_full_n : STD_LOGIC;
signal ap_reg_ready_p_src_rows_V_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_p_src_rows_V_channel_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1 : STD_LOGIC;
signal p_src_rows_V_channel1_full_n : STD_LOGIC;
signal ap_reg_ready_p_src_rows_V_channel1_full_n : STD_LOGIC := '0';
signal ap_sig_ready_p_src_rows_V_channel1_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1 : STD_LOGIC;
signal p_src_cols_V_channel1_full_n : STD_LOGIC;
signal ap_reg_ready_p_src_cols_V_channel1_full_n : STD_LOGIC := '0';
signal ap_sig_ready_p_src_cols_V_channel1_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_start : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_done : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_continue : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_idle : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_ready : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_start : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_done : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_continue : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_idle : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_ready : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_p_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_p_read2 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_p_read16 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_p_read17 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_empty_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_read : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_empty_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_read : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_empty_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_read : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_write : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_full_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_write : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_full_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_write : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_write : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_full_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_write : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_full_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_write : STD_LOGIC;
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_2 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_3 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_4 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_5 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_6 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_7 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V : STD_LOGIC;
signal src0_rows_V_full_n : STD_LOGIC;
signal ap_reg_ready_src0_rows_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_src0_rows_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V : STD_LOGIC;
signal src0_cols_V_full_n : STD_LOGIC;
signal ap_reg_ready_src0_cols_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_src0_cols_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V : STD_LOGIC;
signal src1_rows_V_full_n : STD_LOGIC;
signal ap_reg_ready_src1_rows_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_src1_rows_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V : STD_LOGIC;
signal src1_cols_V_full_n : STD_LOGIC;
signal ap_reg_ready_src1_cols_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_src1_cols_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V : STD_LOGIC;
signal mask_rows_V_full_n : STD_LOGIC;
signal ap_reg_ready_mask_rows_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_mask_rows_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V : STD_LOGIC;
signal mask_cols_V_full_n : STD_LOGIC;
signal ap_reg_ready_mask_cols_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_mask_cols_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V : STD_LOGIC;
signal dmask_rows_V_full_n : STD_LOGIC;
signal ap_reg_ready_dmask_rows_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_dmask_rows_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V : STD_LOGIC;
signal dmask_cols_V_full_n : STD_LOGIC;
signal ap_reg_ready_dmask_cols_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_dmask_cols_V_full_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_ap_start : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_ap_done : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_ap_continue : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_ap_idle : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_ap_ready : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_p_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1222_proc1_U0_p_read2 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1222_proc1_U0_p_read6 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1222_proc1_U0_p_read7 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_empty_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_read : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_empty_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_read : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_empty_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_read : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_write : STD_LOGIC;
signal image_filter_Block_Mat_exit1222_proc1_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_Mat_exit1222_proc1_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V : STD_LOGIC;
signal gray_rows_V_full_n : STD_LOGIC;
signal ap_reg_ready_gray_rows_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_gray_rows_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V : STD_LOGIC;
signal gray_cols_V_full_n : STD_LOGIC;
signal ap_reg_ready_gray_cols_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_gray_cols_V_full_n : STD_LOGIC;
signal image_filter_FAST_t_opr_U0_ap_start : STD_LOGIC;
signal image_filter_FAST_t_opr_U0_ap_done : STD_LOGIC;
signal image_filter_FAST_t_opr_U0_ap_continue : STD_LOGIC;
signal image_filter_FAST_t_opr_U0_ap_idle : STD_LOGIC;
signal image_filter_FAST_t_opr_U0_ap_ready : STD_LOGIC;
signal image_filter_FAST_t_opr_U0_p_src_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_FAST_t_opr_U0_p_src_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_FAST_t_opr_U0_p_src_data_stream_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_FAST_t_opr_U0_p_src_data_stream_V_empty_n : STD_LOGIC;
signal image_filter_FAST_t_opr_U0_p_src_data_stream_V_read : STD_LOGIC;
signal image_filter_FAST_t_opr_U0_p_mask_data_stream_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_FAST_t_opr_U0_p_mask_data_stream_V_full_n : STD_LOGIC;
signal image_filter_FAST_t_opr_U0_p_mask_data_stream_V_write : STD_LOGIC;
signal image_filter_Dilate_0_0_1080_1920_U0_ap_start : STD_LOGIC;
signal image_filter_Dilate_0_0_1080_1920_U0_ap_done : STD_LOGIC;
signal image_filter_Dilate_0_0_1080_1920_U0_ap_continue : STD_LOGIC;
signal image_filter_Dilate_0_0_1080_1920_U0_ap_idle : STD_LOGIC;
signal image_filter_Dilate_0_0_1080_1920_U0_ap_ready : STD_LOGIC;
signal image_filter_Dilate_0_0_1080_1920_U0_p_src_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Dilate_0_0_1080_1920_U0_p_src_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_empty_n : STD_LOGIC;
signal image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_read : STD_LOGIC;
signal image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_full_n : STD_LOGIC;
signal image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_write : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_ap_start : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_ap_done : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_ap_continue : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_ap_idle : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_ap_ready : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_empty_n : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_read : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_empty_n : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_read : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_empty_n : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_read : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_empty_n : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_read : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_write : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_full_n : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_write : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_full_n : STD_LOGIC;
signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_write : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_start : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_done : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_continue : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_idle : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_ready : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_hs_continue : STD_LOGIC;
signal p_src_cols_V_2_loc_channel1_U_ap_dummy_ce : STD_LOGIC;
signal p_src_cols_V_2_loc_channel1_din : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_cols_V_2_loc_channel1_write : STD_LOGIC;
signal p_src_cols_V_2_loc_channel1_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_cols_V_2_loc_channel1_empty_n : STD_LOGIC;
signal p_src_cols_V_2_loc_channel1_read : STD_LOGIC;
signal p_src_cols_V_2_loc_channel_U_ap_dummy_ce : STD_LOGIC;
signal p_src_cols_V_2_loc_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_cols_V_2_loc_channel_write : STD_LOGIC;
signal p_src_cols_V_2_loc_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_cols_V_2_loc_channel_empty_n : STD_LOGIC;
signal p_src_cols_V_2_loc_channel_read : STD_LOGIC;
signal p_src_rows_V_2_loc_channel1_U_ap_dummy_ce : STD_LOGIC;
signal p_src_rows_V_2_loc_channel1_din : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_rows_V_2_loc_channel1_write : STD_LOGIC;
signal p_src_rows_V_2_loc_channel1_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_rows_V_2_loc_channel1_empty_n : STD_LOGIC;
signal p_src_rows_V_2_loc_channel1_read : STD_LOGIC;
signal p_src_rows_V_2_loc_channel_U_ap_dummy_ce : STD_LOGIC;
signal p_src_rows_V_2_loc_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_rows_V_2_loc_channel_write : STD_LOGIC;
signal p_src_rows_V_2_loc_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_rows_V_2_loc_channel_empty_n : STD_LOGIC;
signal p_src_rows_V_2_loc_channel_read : STD_LOGIC;
signal p_dst_cols_V_channel_U_ap_dummy_ce : STD_LOGIC;
signal p_dst_cols_V_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal p_dst_cols_V_channel_write : STD_LOGIC;
signal p_dst_cols_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_dst_cols_V_channel_empty_n : STD_LOGIC;
signal p_dst_cols_V_channel_read : STD_LOGIC;
signal p_dst_cols_V_U_ap_dummy_ce : STD_LOGIC;
signal p_dst_cols_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal p_dst_cols_V_write : STD_LOGIC;
signal p_dst_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_dst_cols_V_empty_n : STD_LOGIC;
signal p_dst_cols_V_read : STD_LOGIC;
signal p_dst_rows_V_channel_U_ap_dummy_ce : STD_LOGIC;
signal p_dst_rows_V_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal p_dst_rows_V_channel_write : STD_LOGIC;
signal p_dst_rows_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_dst_rows_V_channel_empty_n : STD_LOGIC;
signal p_dst_rows_V_channel_read : STD_LOGIC;
signal p_dst_rows_V_U_ap_dummy_ce : STD_LOGIC;
signal p_dst_rows_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal p_dst_rows_V_write : STD_LOGIC;
signal p_dst_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_dst_rows_V_empty_n : STD_LOGIC;
signal p_dst_rows_V_read : STD_LOGIC;
signal p_src_cols_V_channel_U_ap_dummy_ce : STD_LOGIC;
signal p_src_cols_V_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_cols_V_channel_write : STD_LOGIC;
signal p_src_cols_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_cols_V_channel_empty_n : STD_LOGIC;
signal p_src_cols_V_channel_read : STD_LOGIC;
signal p_src_rows_V_channel_U_ap_dummy_ce : STD_LOGIC;
signal p_src_rows_V_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_rows_V_channel_write : STD_LOGIC;
signal p_src_rows_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_rows_V_channel_empty_n : STD_LOGIC;
signal p_src_rows_V_channel_read : STD_LOGIC;
signal p_src_rows_V_channel1_U_ap_dummy_ce : STD_LOGIC;
signal p_src_rows_V_channel1_din : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_rows_V_channel1_write : STD_LOGIC;
signal p_src_rows_V_channel1_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_rows_V_channel1_empty_n : STD_LOGIC;
signal p_src_rows_V_channel1_read : STD_LOGIC;
signal p_src_cols_V_channel1_U_ap_dummy_ce : STD_LOGIC;
signal p_src_cols_V_channel1_din : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_cols_V_channel1_write : STD_LOGIC;
signal p_src_cols_V_channel1_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_cols_V_channel1_empty_n : STD_LOGIC;
signal p_src_cols_V_channel1_read : STD_LOGIC;
signal p_src_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal p_src_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal p_src_data_stream_0_V_full_n : STD_LOGIC;
signal p_src_data_stream_0_V_write : STD_LOGIC;
signal p_src_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal p_src_data_stream_0_V_empty_n : STD_LOGIC;
signal p_src_data_stream_0_V_read : STD_LOGIC;
signal p_src_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC;
signal p_src_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal p_src_data_stream_1_V_full_n : STD_LOGIC;
signal p_src_data_stream_1_V_write : STD_LOGIC;
signal p_src_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal p_src_data_stream_1_V_empty_n : STD_LOGIC;
signal p_src_data_stream_1_V_read : STD_LOGIC;
signal p_src_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC;
signal p_src_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal p_src_data_stream_2_V_full_n : STD_LOGIC;
signal p_src_data_stream_2_V_write : STD_LOGIC;
signal p_src_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal p_src_data_stream_2_V_empty_n : STD_LOGIC;
signal p_src_data_stream_2_V_read : STD_LOGIC;
signal src0_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal src0_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal src0_data_stream_0_V_full_n : STD_LOGIC;
signal src0_data_stream_0_V_write : STD_LOGIC;
signal src0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal src0_data_stream_0_V_empty_n : STD_LOGIC;
signal src0_data_stream_0_V_read : STD_LOGIC;
signal src0_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC;
signal src0_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal src0_data_stream_1_V_full_n : STD_LOGIC;
signal src0_data_stream_1_V_write : STD_LOGIC;
signal src0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal src0_data_stream_1_V_empty_n : STD_LOGIC;
signal src0_data_stream_1_V_read : STD_LOGIC;
signal src0_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC;
signal src0_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal src0_data_stream_2_V_full_n : STD_LOGIC;
signal src0_data_stream_2_V_write : STD_LOGIC;
signal src0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal src0_data_stream_2_V_empty_n : STD_LOGIC;
signal src0_data_stream_2_V_read : STD_LOGIC;
signal src1_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal src1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal src1_data_stream_0_V_full_n : STD_LOGIC;
signal src1_data_stream_0_V_write : STD_LOGIC;
signal src1_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal src1_data_stream_0_V_empty_n : STD_LOGIC;
signal src1_data_stream_0_V_read : STD_LOGIC;
signal src1_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC;
signal src1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal src1_data_stream_1_V_full_n : STD_LOGIC;
signal src1_data_stream_1_V_write : STD_LOGIC;
signal src1_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal src1_data_stream_1_V_empty_n : STD_LOGIC;
signal src1_data_stream_1_V_read : STD_LOGIC;
signal src1_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC;
signal src1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal src1_data_stream_2_V_full_n : STD_LOGIC;
signal src1_data_stream_2_V_write : STD_LOGIC;
signal src1_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal src1_data_stream_2_V_empty_n : STD_LOGIC;
signal src1_data_stream_2_V_read : STD_LOGIC;
signal src0_rows_V_U_ap_dummy_ce : STD_LOGIC;
signal src0_rows_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal src0_rows_V_write : STD_LOGIC;
signal src0_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal src0_rows_V_empty_n : STD_LOGIC;
signal src0_rows_V_read : STD_LOGIC;
signal src0_cols_V_U_ap_dummy_ce : STD_LOGIC;
signal src0_cols_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal src0_cols_V_write : STD_LOGIC;
signal src0_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal src0_cols_V_empty_n : STD_LOGIC;
signal src0_cols_V_read : STD_LOGIC;
signal src1_rows_V_U_ap_dummy_ce : STD_LOGIC;
signal src1_rows_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal src1_rows_V_write : STD_LOGIC;
signal src1_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal src1_rows_V_empty_n : STD_LOGIC;
signal src1_rows_V_read : STD_LOGIC;
signal src1_cols_V_U_ap_dummy_ce : STD_LOGIC;
signal src1_cols_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal src1_cols_V_write : STD_LOGIC;
signal src1_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal src1_cols_V_empty_n : STD_LOGIC;
signal src1_cols_V_read : STD_LOGIC;
signal mask_rows_V_U_ap_dummy_ce : STD_LOGIC;
signal mask_rows_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal mask_rows_V_write : STD_LOGIC;
signal mask_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal mask_rows_V_empty_n : STD_LOGIC;
signal mask_rows_V_read : STD_LOGIC;
signal mask_cols_V_U_ap_dummy_ce : STD_LOGIC;
signal mask_cols_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal mask_cols_V_write : STD_LOGIC;
signal mask_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal mask_cols_V_empty_n : STD_LOGIC;
signal mask_cols_V_read : STD_LOGIC;
signal dmask_rows_V_U_ap_dummy_ce : STD_LOGIC;
signal dmask_rows_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal dmask_rows_V_write : STD_LOGIC;
signal dmask_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal dmask_rows_V_empty_n : STD_LOGIC;
signal dmask_rows_V_read : STD_LOGIC;
signal dmask_cols_V_U_ap_dummy_ce : STD_LOGIC;
signal dmask_cols_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal dmask_cols_V_write : STD_LOGIC;
signal dmask_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal dmask_cols_V_empty_n : STD_LOGIC;
signal dmask_cols_V_read : STD_LOGIC;
signal gray_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal gray_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal gray_data_stream_0_V_full_n : STD_LOGIC;
signal gray_data_stream_0_V_write : STD_LOGIC;
signal gray_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal gray_data_stream_0_V_empty_n : STD_LOGIC;
signal gray_data_stream_0_V_read : STD_LOGIC;
signal gray_rows_V_U_ap_dummy_ce : STD_LOGIC;
signal gray_rows_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal gray_rows_V_write : STD_LOGIC;
signal gray_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal gray_rows_V_empty_n : STD_LOGIC;
signal gray_rows_V_read : STD_LOGIC;
signal gray_cols_V_U_ap_dummy_ce : STD_LOGIC;
signal gray_cols_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal gray_cols_V_write : STD_LOGIC;
signal gray_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal gray_cols_V_empty_n : STD_LOGIC;
signal gray_cols_V_read : STD_LOGIC;
signal mask_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal mask_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal mask_data_stream_0_V_full_n : STD_LOGIC;
signal mask_data_stream_0_V_write : STD_LOGIC;
signal mask_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal mask_data_stream_0_V_empty_n : STD_LOGIC;
signal mask_data_stream_0_V_read : STD_LOGIC;
signal dmask_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal dmask_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal dmask_data_stream_0_V_full_n : STD_LOGIC;
signal dmask_data_stream_0_V_write : STD_LOGIC;
signal dmask_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal dmask_data_stream_0_V_empty_n : STD_LOGIC;
signal dmask_data_stream_0_V_read : STD_LOGIC;
signal p_dst_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal p_dst_data_stream_0_V_full_n : STD_LOGIC;
signal p_dst_data_stream_0_V_write : STD_LOGIC;
signal p_dst_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal p_dst_data_stream_0_V_empty_n : STD_LOGIC;
signal p_dst_data_stream_0_V_read : STD_LOGIC;
signal p_dst_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC;
signal p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal p_dst_data_stream_1_V_full_n : STD_LOGIC;
signal p_dst_data_stream_1_V_write : STD_LOGIC;
signal p_dst_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal p_dst_data_stream_1_V_empty_n : STD_LOGIC;
signal p_dst_data_stream_1_V_read : STD_LOGIC;
signal p_dst_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC;
signal p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal p_dst_data_stream_2_V_full_n : STD_LOGIC;
signal p_dst_data_stream_2_V_write : STD_LOGIC;
signal p_dst_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal p_dst_data_stream_2_V_empty_n : STD_LOGIC;
signal p_dst_data_stream_2_V_read : STD_LOGIC;
signal ap_reg_procdone_image_filter_Block_proc_U0 : STD_LOGIC := '0';
signal ap_sig_hs_done : STD_LOGIC;
signal ap_reg_procdone_image_filter_AXIvideo2Mat_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_FAST_t_opr_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_Mat2AXIvideo_U0 : STD_LOGIC := '0';
signal ap_CS : STD_LOGIC;
signal ap_sig_top_allready : STD_LOGIC;
component image_filter_Block_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_4 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_5 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_6 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_7 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_8 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_9 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_10 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_11 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end component;
component image_filter_AXIvideo2Mat IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component image_filter_Block_Mat_exit1220_proc1 IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_read2 : IN STD_LOGIC_VECTOR (11 downto 0);
p_read16 : IN STD_LOGIC_VECTOR (11 downto 0);
p_read17 : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
src0_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
src0_data_stream_0_V_full_n : IN STD_LOGIC;
src0_data_stream_0_V_write : OUT STD_LOGIC;
src0_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
src0_data_stream_1_V_full_n : IN STD_LOGIC;
src0_data_stream_1_V_write : OUT STD_LOGIC;
src0_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
src0_data_stream_2_V_full_n : IN STD_LOGIC;
src0_data_stream_2_V_write : OUT STD_LOGIC;
src1_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
src1_data_stream_0_V_full_n : IN STD_LOGIC;
src1_data_stream_0_V_write : OUT STD_LOGIC;
src1_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
src1_data_stream_1_V_full_n : IN STD_LOGIC;
src1_data_stream_1_V_write : OUT STD_LOGIC;
src1_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
src1_data_stream_2_V_full_n : IN STD_LOGIC;
src1_data_stream_2_V_write : OUT STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_4 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_5 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_6 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_7 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end component;
component image_filter_Block_Mat_exit1222_proc1 IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_read2 : IN STD_LOGIC_VECTOR (11 downto 0);
p_read6 : IN STD_LOGIC_VECTOR (11 downto 0);
p_read7 : IN STD_LOGIC_VECTOR (11 downto 0);
src0_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
src0_data_stream_0_V_empty_n : IN STD_LOGIC;
src0_data_stream_0_V_read : OUT STD_LOGIC;
src0_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
src0_data_stream_1_V_empty_n : IN STD_LOGIC;
src0_data_stream_1_V_read : OUT STD_LOGIC;
src0_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
src0_data_stream_2_V_empty_n : IN STD_LOGIC;
src0_data_stream_2_V_read : OUT STD_LOGIC;
gray_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
gray_data_stream_0_V_full_n : IN STD_LOGIC;
gray_data_stream_0_V_write : OUT STD_LOGIC;
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end component;
component image_filter_FAST_t_opr IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_V_empty_n : IN STD_LOGIC;
p_src_data_stream_V_read : OUT STD_LOGIC;
p_mask_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_mask_data_stream_V_full_n : IN STD_LOGIC;
p_mask_data_stream_V_write : OUT STD_LOGIC );
end component;
component image_filter_Dilate_0_0_1080_1920_s IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_V_empty_n : IN STD_LOGIC;
p_src_data_stream_V_read : OUT STD_LOGIC;
p_dst_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_V_full_n : IN STD_LOGIC;
p_dst_data_stream_V_write : OUT STD_LOGIC );
end component;
component image_filter_PaintMask_32_0_1080_1920_s IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_mask_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_mask_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_mask_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_mask_data_stream_V_empty_n : IN STD_LOGIC;
p_mask_data_stream_V_read : OUT STD_LOGIC;
p_dst_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_dst_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component image_filter_Mat2AXIvideo IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
OUTPUT_STREAM_TVALID : OUT STD_LOGIC;
OUTPUT_STREAM_TREADY : IN STD_LOGIC;
OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component FIFO_image_filter_p_src_cols_V_2_loc_channel1 IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_src_cols_V_2_loc_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_src_rows_V_2_loc_channel1 IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_src_rows_V_2_loc_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_dst_cols_V_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_dst_cols_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_dst_rows_V_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_dst_rows_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_src_cols_V_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_src_rows_V_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_src_rows_V_channel1 IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_src_cols_V_channel1 IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_src_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_src_data_stream_1_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_src_data_stream_2_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_src0_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_src0_data_stream_1_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_src0_data_stream_2_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_src1_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_src1_data_stream_1_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_src1_data_stream_2_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_src0_rows_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_src0_cols_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_src1_rows_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_src1_cols_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_mask_rows_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_mask_cols_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_dmask_rows_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_dmask_cols_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_gray_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_gray_rows_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_gray_cols_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_mask_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_dmask_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_dst_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_dst_data_stream_1_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_p_dst_data_stream_2_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
begin
image_filter_Block_proc_U0 : component image_filter_Block_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Block_proc_U0_ap_start,
ap_done => image_filter_Block_proc_U0_ap_done,
ap_continue => image_filter_Block_proc_U0_ap_continue,
ap_idle => image_filter_Block_proc_U0_ap_idle,
ap_ready => image_filter_Block_proc_U0_ap_ready,
rows => image_filter_Block_proc_U0_rows,
cols => image_filter_Block_proc_U0_cols,
ap_return_0 => image_filter_Block_proc_U0_ap_return_0,
ap_return_1 => image_filter_Block_proc_U0_ap_return_1,
ap_return_2 => image_filter_Block_proc_U0_ap_return_2,
ap_return_3 => image_filter_Block_proc_U0_ap_return_3,
ap_return_4 => image_filter_Block_proc_U0_ap_return_4,
ap_return_5 => image_filter_Block_proc_U0_ap_return_5,
ap_return_6 => image_filter_Block_proc_U0_ap_return_6,
ap_return_7 => image_filter_Block_proc_U0_ap_return_7,
ap_return_8 => image_filter_Block_proc_U0_ap_return_8,
ap_return_9 => image_filter_Block_proc_U0_ap_return_9,
ap_return_10 => image_filter_Block_proc_U0_ap_return_10,
ap_return_11 => image_filter_Block_proc_U0_ap_return_11);
image_filter_AXIvideo2Mat_U0 : component image_filter_AXIvideo2Mat
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_AXIvideo2Mat_U0_ap_start,
ap_done => image_filter_AXIvideo2Mat_U0_ap_done,
ap_continue => image_filter_AXIvideo2Mat_U0_ap_continue,
ap_idle => image_filter_AXIvideo2Mat_U0_ap_idle,
ap_ready => image_filter_AXIvideo2Mat_U0_ap_ready,
INPUT_STREAM_TDATA => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA,
INPUT_STREAM_TVALID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY,
INPUT_STREAM_TKEEP => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST,
INPUT_STREAM_TID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID,
INPUT_STREAM_TDEST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST,
img_rows_V_read => image_filter_AXIvideo2Mat_U0_img_rows_V_read,
img_cols_V_read => image_filter_AXIvideo2Mat_U0_img_cols_V_read,
img_data_stream_0_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din,
img_data_stream_0_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n,
img_data_stream_0_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write,
img_data_stream_1_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din,
img_data_stream_1_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n,
img_data_stream_1_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write,
img_data_stream_2_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din,
img_data_stream_2_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n,
img_data_stream_2_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write);
image_filter_Block_Mat_exit1220_proc1_U0 : component image_filter_Block_Mat_exit1220_proc1
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Block_Mat_exit1220_proc1_U0_ap_start,
ap_done => image_filter_Block_Mat_exit1220_proc1_U0_ap_done,
ap_continue => image_filter_Block_Mat_exit1220_proc1_U0_ap_continue,
ap_idle => image_filter_Block_Mat_exit1220_proc1_U0_ap_idle,
ap_ready => image_filter_Block_Mat_exit1220_proc1_U0_ap_ready,
p_read => image_filter_Block_Mat_exit1220_proc1_U0_p_read,
p_read2 => image_filter_Block_Mat_exit1220_proc1_U0_p_read2,
p_read16 => image_filter_Block_Mat_exit1220_proc1_U0_p_read16,
p_read17 => image_filter_Block_Mat_exit1220_proc1_U0_p_read17,
p_src_data_stream_0_V_dout => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_dout,
p_src_data_stream_0_V_empty_n => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_empty_n,
p_src_data_stream_0_V_read => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_dout,
p_src_data_stream_1_V_empty_n => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_empty_n,
p_src_data_stream_1_V_read => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_dout,
p_src_data_stream_2_V_empty_n => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_empty_n,
p_src_data_stream_2_V_read => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_read,
src0_data_stream_0_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_din,
src0_data_stream_0_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_full_n,
src0_data_stream_0_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_write,
src0_data_stream_1_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_din,
src0_data_stream_1_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_full_n,
src0_data_stream_1_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_write,
src0_data_stream_2_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_din,
src0_data_stream_2_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_full_n,
src0_data_stream_2_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_write,
src1_data_stream_0_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_din,
src1_data_stream_0_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_full_n,
src1_data_stream_0_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_write,
src1_data_stream_1_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_din,
src1_data_stream_1_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_full_n,
src1_data_stream_1_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_write,
src1_data_stream_2_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_din,
src1_data_stream_2_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_full_n,
src1_data_stream_2_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_write,
ap_return_0 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_0,
ap_return_1 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_1,
ap_return_2 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_2,
ap_return_3 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_3,
ap_return_4 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_4,
ap_return_5 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_5,
ap_return_6 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_6,
ap_return_7 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_7);
image_filter_Block_Mat_exit1222_proc1_U0 : component image_filter_Block_Mat_exit1222_proc1
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Block_Mat_exit1222_proc1_U0_ap_start,
ap_done => image_filter_Block_Mat_exit1222_proc1_U0_ap_done,
ap_continue => image_filter_Block_Mat_exit1222_proc1_U0_ap_continue,
ap_idle => image_filter_Block_Mat_exit1222_proc1_U0_ap_idle,
ap_ready => image_filter_Block_Mat_exit1222_proc1_U0_ap_ready,
p_read => image_filter_Block_Mat_exit1222_proc1_U0_p_read,
p_read2 => image_filter_Block_Mat_exit1222_proc1_U0_p_read2,
p_read6 => image_filter_Block_Mat_exit1222_proc1_U0_p_read6,
p_read7 => image_filter_Block_Mat_exit1222_proc1_U0_p_read7,
src0_data_stream_0_V_dout => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_dout,
src0_data_stream_0_V_empty_n => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_empty_n,
src0_data_stream_0_V_read => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_read,
src0_data_stream_1_V_dout => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_dout,
src0_data_stream_1_V_empty_n => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_empty_n,
src0_data_stream_1_V_read => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_read,
src0_data_stream_2_V_dout => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_dout,
src0_data_stream_2_V_empty_n => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_empty_n,
src0_data_stream_2_V_read => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_read,
gray_data_stream_0_V_din => image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_din,
gray_data_stream_0_V_full_n => image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_full_n,
gray_data_stream_0_V_write => image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_write,
ap_return_0 => image_filter_Block_Mat_exit1222_proc1_U0_ap_return_0,
ap_return_1 => image_filter_Block_Mat_exit1222_proc1_U0_ap_return_1);
image_filter_FAST_t_opr_U0 : component image_filter_FAST_t_opr
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_FAST_t_opr_U0_ap_start,
ap_done => image_filter_FAST_t_opr_U0_ap_done,
ap_continue => image_filter_FAST_t_opr_U0_ap_continue,
ap_idle => image_filter_FAST_t_opr_U0_ap_idle,
ap_ready => image_filter_FAST_t_opr_U0_ap_ready,
p_src_rows_V_read => image_filter_FAST_t_opr_U0_p_src_rows_V_read,
p_src_cols_V_read => image_filter_FAST_t_opr_U0_p_src_cols_V_read,
p_src_data_stream_V_dout => image_filter_FAST_t_opr_U0_p_src_data_stream_V_dout,
p_src_data_stream_V_empty_n => image_filter_FAST_t_opr_U0_p_src_data_stream_V_empty_n,
p_src_data_stream_V_read => image_filter_FAST_t_opr_U0_p_src_data_stream_V_read,
p_mask_data_stream_V_din => image_filter_FAST_t_opr_U0_p_mask_data_stream_V_din,
p_mask_data_stream_V_full_n => image_filter_FAST_t_opr_U0_p_mask_data_stream_V_full_n,
p_mask_data_stream_V_write => image_filter_FAST_t_opr_U0_p_mask_data_stream_V_write);
image_filter_Dilate_0_0_1080_1920_U0 : component image_filter_Dilate_0_0_1080_1920_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Dilate_0_0_1080_1920_U0_ap_start,
ap_done => image_filter_Dilate_0_0_1080_1920_U0_ap_done,
ap_continue => image_filter_Dilate_0_0_1080_1920_U0_ap_continue,
ap_idle => image_filter_Dilate_0_0_1080_1920_U0_ap_idle,
ap_ready => image_filter_Dilate_0_0_1080_1920_U0_ap_ready,
p_src_rows_V_read => image_filter_Dilate_0_0_1080_1920_U0_p_src_rows_V_read,
p_src_cols_V_read => image_filter_Dilate_0_0_1080_1920_U0_p_src_cols_V_read,
p_src_data_stream_V_dout => image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_dout,
p_src_data_stream_V_empty_n => image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_empty_n,
p_src_data_stream_V_read => image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_read,
p_dst_data_stream_V_din => image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_din,
p_dst_data_stream_V_full_n => image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_full_n,
p_dst_data_stream_V_write => image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_write);
image_filter_PaintMask_32_0_1080_1920_U0 : component image_filter_PaintMask_32_0_1080_1920_s
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_PaintMask_32_0_1080_1920_U0_ap_start,
ap_done => image_filter_PaintMask_32_0_1080_1920_U0_ap_done,
ap_continue => image_filter_PaintMask_32_0_1080_1920_U0_ap_continue,
ap_idle => image_filter_PaintMask_32_0_1080_1920_U0_ap_idle,
ap_ready => image_filter_PaintMask_32_0_1080_1920_U0_ap_ready,
p_src_rows_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_rows_V_read,
p_src_cols_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_cols_V_read,
p_src_data_stream_0_V_dout => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_dout,
p_src_data_stream_0_V_empty_n => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_empty_n,
p_src_data_stream_0_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_dout,
p_src_data_stream_1_V_empty_n => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_empty_n,
p_src_data_stream_1_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_dout,
p_src_data_stream_2_V_empty_n => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_empty_n,
p_src_data_stream_2_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_read,
p_mask_rows_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_rows_V_read,
p_mask_cols_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_cols_V_read,
p_mask_data_stream_V_dout => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_dout,
p_mask_data_stream_V_empty_n => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_empty_n,
p_mask_data_stream_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_read,
p_dst_rows_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_rows_V_read,
p_dst_cols_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_cols_V_read,
p_dst_data_stream_0_V_din => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_full_n,
p_dst_data_stream_0_V_write => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_full_n,
p_dst_data_stream_1_V_write => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_full_n,
p_dst_data_stream_2_V_write => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_write);
image_filter_Mat2AXIvideo_U0 : component image_filter_Mat2AXIvideo
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Mat2AXIvideo_U0_ap_start,
ap_done => image_filter_Mat2AXIvideo_U0_ap_done,
ap_continue => image_filter_Mat2AXIvideo_U0_ap_continue,
ap_idle => image_filter_Mat2AXIvideo_U0_ap_idle,
ap_ready => image_filter_Mat2AXIvideo_U0_ap_ready,
img_rows_V_read => image_filter_Mat2AXIvideo_U0_img_rows_V_read,
img_cols_V_read => image_filter_Mat2AXIvideo_U0_img_cols_V_read,
img_data_stream_0_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout,
img_data_stream_0_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n,
img_data_stream_0_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read,
img_data_stream_1_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout,
img_data_stream_1_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n,
img_data_stream_1_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read,
img_data_stream_2_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout,
img_data_stream_2_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n,
img_data_stream_2_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read,
OUTPUT_STREAM_TDATA => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TVALID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TKEEP => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST);
p_src_cols_V_2_loc_channel1_U : component FIFO_image_filter_p_src_cols_V_2_loc_channel1
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_src_cols_V_2_loc_channel1_U_ap_dummy_ce,
if_write_ce => p_src_cols_V_2_loc_channel1_U_ap_dummy_ce,
if_din => p_src_cols_V_2_loc_channel1_din,
if_full_n => p_src_cols_V_2_loc_channel1_full_n,
if_write => p_src_cols_V_2_loc_channel1_write,
if_dout => p_src_cols_V_2_loc_channel1_dout,
if_empty_n => p_src_cols_V_2_loc_channel1_empty_n,
if_read => p_src_cols_V_2_loc_channel1_read);
p_src_cols_V_2_loc_channel_U : component FIFO_image_filter_p_src_cols_V_2_loc_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_src_cols_V_2_loc_channel_U_ap_dummy_ce,
if_write_ce => p_src_cols_V_2_loc_channel_U_ap_dummy_ce,
if_din => p_src_cols_V_2_loc_channel_din,
if_full_n => p_src_cols_V_2_loc_channel_full_n,
if_write => p_src_cols_V_2_loc_channel_write,
if_dout => p_src_cols_V_2_loc_channel_dout,
if_empty_n => p_src_cols_V_2_loc_channel_empty_n,
if_read => p_src_cols_V_2_loc_channel_read);
p_src_rows_V_2_loc_channel1_U : component FIFO_image_filter_p_src_rows_V_2_loc_channel1
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_src_rows_V_2_loc_channel1_U_ap_dummy_ce,
if_write_ce => p_src_rows_V_2_loc_channel1_U_ap_dummy_ce,
if_din => p_src_rows_V_2_loc_channel1_din,
if_full_n => p_src_rows_V_2_loc_channel1_full_n,
if_write => p_src_rows_V_2_loc_channel1_write,
if_dout => p_src_rows_V_2_loc_channel1_dout,
if_empty_n => p_src_rows_V_2_loc_channel1_empty_n,
if_read => p_src_rows_V_2_loc_channel1_read);
p_src_rows_V_2_loc_channel_U : component FIFO_image_filter_p_src_rows_V_2_loc_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_src_rows_V_2_loc_channel_U_ap_dummy_ce,
if_write_ce => p_src_rows_V_2_loc_channel_U_ap_dummy_ce,
if_din => p_src_rows_V_2_loc_channel_din,
if_full_n => p_src_rows_V_2_loc_channel_full_n,
if_write => p_src_rows_V_2_loc_channel_write,
if_dout => p_src_rows_V_2_loc_channel_dout,
if_empty_n => p_src_rows_V_2_loc_channel_empty_n,
if_read => p_src_rows_V_2_loc_channel_read);
p_dst_cols_V_channel_U : component FIFO_image_filter_p_dst_cols_V_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_dst_cols_V_channel_U_ap_dummy_ce,
if_write_ce => p_dst_cols_V_channel_U_ap_dummy_ce,
if_din => p_dst_cols_V_channel_din,
if_full_n => p_dst_cols_V_channel_full_n,
if_write => p_dst_cols_V_channel_write,
if_dout => p_dst_cols_V_channel_dout,
if_empty_n => p_dst_cols_V_channel_empty_n,
if_read => p_dst_cols_V_channel_read);
p_dst_cols_V_U : component FIFO_image_filter_p_dst_cols_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_dst_cols_V_U_ap_dummy_ce,
if_write_ce => p_dst_cols_V_U_ap_dummy_ce,
if_din => p_dst_cols_V_din,
if_full_n => p_dst_cols_V_full_n,
if_write => p_dst_cols_V_write,
if_dout => p_dst_cols_V_dout,
if_empty_n => p_dst_cols_V_empty_n,
if_read => p_dst_cols_V_read);
p_dst_rows_V_channel_U : component FIFO_image_filter_p_dst_rows_V_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_dst_rows_V_channel_U_ap_dummy_ce,
if_write_ce => p_dst_rows_V_channel_U_ap_dummy_ce,
if_din => p_dst_rows_V_channel_din,
if_full_n => p_dst_rows_V_channel_full_n,
if_write => p_dst_rows_V_channel_write,
if_dout => p_dst_rows_V_channel_dout,
if_empty_n => p_dst_rows_V_channel_empty_n,
if_read => p_dst_rows_V_channel_read);
p_dst_rows_V_U : component FIFO_image_filter_p_dst_rows_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_dst_rows_V_U_ap_dummy_ce,
if_write_ce => p_dst_rows_V_U_ap_dummy_ce,
if_din => p_dst_rows_V_din,
if_full_n => p_dst_rows_V_full_n,
if_write => p_dst_rows_V_write,
if_dout => p_dst_rows_V_dout,
if_empty_n => p_dst_rows_V_empty_n,
if_read => p_dst_rows_V_read);
p_src_cols_V_channel_U : component FIFO_image_filter_p_src_cols_V_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_src_cols_V_channel_U_ap_dummy_ce,
if_write_ce => p_src_cols_V_channel_U_ap_dummy_ce,
if_din => p_src_cols_V_channel_din,
if_full_n => p_src_cols_V_channel_full_n,
if_write => p_src_cols_V_channel_write,
if_dout => p_src_cols_V_channel_dout,
if_empty_n => p_src_cols_V_channel_empty_n,
if_read => p_src_cols_V_channel_read);
p_src_rows_V_channel_U : component FIFO_image_filter_p_src_rows_V_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_src_rows_V_channel_U_ap_dummy_ce,
if_write_ce => p_src_rows_V_channel_U_ap_dummy_ce,
if_din => p_src_rows_V_channel_din,
if_full_n => p_src_rows_V_channel_full_n,
if_write => p_src_rows_V_channel_write,
if_dout => p_src_rows_V_channel_dout,
if_empty_n => p_src_rows_V_channel_empty_n,
if_read => p_src_rows_V_channel_read);
p_src_rows_V_channel1_U : component FIFO_image_filter_p_src_rows_V_channel1
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_src_rows_V_channel1_U_ap_dummy_ce,
if_write_ce => p_src_rows_V_channel1_U_ap_dummy_ce,
if_din => p_src_rows_V_channel1_din,
if_full_n => p_src_rows_V_channel1_full_n,
if_write => p_src_rows_V_channel1_write,
if_dout => p_src_rows_V_channel1_dout,
if_empty_n => p_src_rows_V_channel1_empty_n,
if_read => p_src_rows_V_channel1_read);
p_src_cols_V_channel1_U : component FIFO_image_filter_p_src_cols_V_channel1
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_src_cols_V_channel1_U_ap_dummy_ce,
if_write_ce => p_src_cols_V_channel1_U_ap_dummy_ce,
if_din => p_src_cols_V_channel1_din,
if_full_n => p_src_cols_V_channel1_full_n,
if_write => p_src_cols_V_channel1_write,
if_dout => p_src_cols_V_channel1_dout,
if_empty_n => p_src_cols_V_channel1_empty_n,
if_read => p_src_cols_V_channel1_read);
p_src_data_stream_0_V_U : component FIFO_image_filter_p_src_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_src_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => p_src_data_stream_0_V_U_ap_dummy_ce,
if_din => p_src_data_stream_0_V_din,
if_full_n => p_src_data_stream_0_V_full_n,
if_write => p_src_data_stream_0_V_write,
if_dout => p_src_data_stream_0_V_dout,
if_empty_n => p_src_data_stream_0_V_empty_n,
if_read => p_src_data_stream_0_V_read);
p_src_data_stream_1_V_U : component FIFO_image_filter_p_src_data_stream_1_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_src_data_stream_1_V_U_ap_dummy_ce,
if_write_ce => p_src_data_stream_1_V_U_ap_dummy_ce,
if_din => p_src_data_stream_1_V_din,
if_full_n => p_src_data_stream_1_V_full_n,
if_write => p_src_data_stream_1_V_write,
if_dout => p_src_data_stream_1_V_dout,
if_empty_n => p_src_data_stream_1_V_empty_n,
if_read => p_src_data_stream_1_V_read);
p_src_data_stream_2_V_U : component FIFO_image_filter_p_src_data_stream_2_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_src_data_stream_2_V_U_ap_dummy_ce,
if_write_ce => p_src_data_stream_2_V_U_ap_dummy_ce,
if_din => p_src_data_stream_2_V_din,
if_full_n => p_src_data_stream_2_V_full_n,
if_write => p_src_data_stream_2_V_write,
if_dout => p_src_data_stream_2_V_dout,
if_empty_n => p_src_data_stream_2_V_empty_n,
if_read => p_src_data_stream_2_V_read);
src0_data_stream_0_V_U : component FIFO_image_filter_src0_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => src0_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => src0_data_stream_0_V_U_ap_dummy_ce,
if_din => src0_data_stream_0_V_din,
if_full_n => src0_data_stream_0_V_full_n,
if_write => src0_data_stream_0_V_write,
if_dout => src0_data_stream_0_V_dout,
if_empty_n => src0_data_stream_0_V_empty_n,
if_read => src0_data_stream_0_V_read);
src0_data_stream_1_V_U : component FIFO_image_filter_src0_data_stream_1_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => src0_data_stream_1_V_U_ap_dummy_ce,
if_write_ce => src0_data_stream_1_V_U_ap_dummy_ce,
if_din => src0_data_stream_1_V_din,
if_full_n => src0_data_stream_1_V_full_n,
if_write => src0_data_stream_1_V_write,
if_dout => src0_data_stream_1_V_dout,
if_empty_n => src0_data_stream_1_V_empty_n,
if_read => src0_data_stream_1_V_read);
src0_data_stream_2_V_U : component FIFO_image_filter_src0_data_stream_2_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => src0_data_stream_2_V_U_ap_dummy_ce,
if_write_ce => src0_data_stream_2_V_U_ap_dummy_ce,
if_din => src0_data_stream_2_V_din,
if_full_n => src0_data_stream_2_V_full_n,
if_write => src0_data_stream_2_V_write,
if_dout => src0_data_stream_2_V_dout,
if_empty_n => src0_data_stream_2_V_empty_n,
if_read => src0_data_stream_2_V_read);
src1_data_stream_0_V_U : component FIFO_image_filter_src1_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => src1_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => src1_data_stream_0_V_U_ap_dummy_ce,
if_din => src1_data_stream_0_V_din,
if_full_n => src1_data_stream_0_V_full_n,
if_write => src1_data_stream_0_V_write,
if_dout => src1_data_stream_0_V_dout,
if_empty_n => src1_data_stream_0_V_empty_n,
if_read => src1_data_stream_0_V_read);
src1_data_stream_1_V_U : component FIFO_image_filter_src1_data_stream_1_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => src1_data_stream_1_V_U_ap_dummy_ce,
if_write_ce => src1_data_stream_1_V_U_ap_dummy_ce,
if_din => src1_data_stream_1_V_din,
if_full_n => src1_data_stream_1_V_full_n,
if_write => src1_data_stream_1_V_write,
if_dout => src1_data_stream_1_V_dout,
if_empty_n => src1_data_stream_1_V_empty_n,
if_read => src1_data_stream_1_V_read);
src1_data_stream_2_V_U : component FIFO_image_filter_src1_data_stream_2_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => src1_data_stream_2_V_U_ap_dummy_ce,
if_write_ce => src1_data_stream_2_V_U_ap_dummy_ce,
if_din => src1_data_stream_2_V_din,
if_full_n => src1_data_stream_2_V_full_n,
if_write => src1_data_stream_2_V_write,
if_dout => src1_data_stream_2_V_dout,
if_empty_n => src1_data_stream_2_V_empty_n,
if_read => src1_data_stream_2_V_read);
src0_rows_V_U : component FIFO_image_filter_src0_rows_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => src0_rows_V_U_ap_dummy_ce,
if_write_ce => src0_rows_V_U_ap_dummy_ce,
if_din => src0_rows_V_din,
if_full_n => src0_rows_V_full_n,
if_write => src0_rows_V_write,
if_dout => src0_rows_V_dout,
if_empty_n => src0_rows_V_empty_n,
if_read => src0_rows_V_read);
src0_cols_V_U : component FIFO_image_filter_src0_cols_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => src0_cols_V_U_ap_dummy_ce,
if_write_ce => src0_cols_V_U_ap_dummy_ce,
if_din => src0_cols_V_din,
if_full_n => src0_cols_V_full_n,
if_write => src0_cols_V_write,
if_dout => src0_cols_V_dout,
if_empty_n => src0_cols_V_empty_n,
if_read => src0_cols_V_read);
src1_rows_V_U : component FIFO_image_filter_src1_rows_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => src1_rows_V_U_ap_dummy_ce,
if_write_ce => src1_rows_V_U_ap_dummy_ce,
if_din => src1_rows_V_din,
if_full_n => src1_rows_V_full_n,
if_write => src1_rows_V_write,
if_dout => src1_rows_V_dout,
if_empty_n => src1_rows_V_empty_n,
if_read => src1_rows_V_read);
src1_cols_V_U : component FIFO_image_filter_src1_cols_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => src1_cols_V_U_ap_dummy_ce,
if_write_ce => src1_cols_V_U_ap_dummy_ce,
if_din => src1_cols_V_din,
if_full_n => src1_cols_V_full_n,
if_write => src1_cols_V_write,
if_dout => src1_cols_V_dout,
if_empty_n => src1_cols_V_empty_n,
if_read => src1_cols_V_read);
mask_rows_V_U : component FIFO_image_filter_mask_rows_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => mask_rows_V_U_ap_dummy_ce,
if_write_ce => mask_rows_V_U_ap_dummy_ce,
if_din => mask_rows_V_din,
if_full_n => mask_rows_V_full_n,
if_write => mask_rows_V_write,
if_dout => mask_rows_V_dout,
if_empty_n => mask_rows_V_empty_n,
if_read => mask_rows_V_read);
mask_cols_V_U : component FIFO_image_filter_mask_cols_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => mask_cols_V_U_ap_dummy_ce,
if_write_ce => mask_cols_V_U_ap_dummy_ce,
if_din => mask_cols_V_din,
if_full_n => mask_cols_V_full_n,
if_write => mask_cols_V_write,
if_dout => mask_cols_V_dout,
if_empty_n => mask_cols_V_empty_n,
if_read => mask_cols_V_read);
dmask_rows_V_U : component FIFO_image_filter_dmask_rows_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => dmask_rows_V_U_ap_dummy_ce,
if_write_ce => dmask_rows_V_U_ap_dummy_ce,
if_din => dmask_rows_V_din,
if_full_n => dmask_rows_V_full_n,
if_write => dmask_rows_V_write,
if_dout => dmask_rows_V_dout,
if_empty_n => dmask_rows_V_empty_n,
if_read => dmask_rows_V_read);
dmask_cols_V_U : component FIFO_image_filter_dmask_cols_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => dmask_cols_V_U_ap_dummy_ce,
if_write_ce => dmask_cols_V_U_ap_dummy_ce,
if_din => dmask_cols_V_din,
if_full_n => dmask_cols_V_full_n,
if_write => dmask_cols_V_write,
if_dout => dmask_cols_V_dout,
if_empty_n => dmask_cols_V_empty_n,
if_read => dmask_cols_V_read);
gray_data_stream_0_V_U : component FIFO_image_filter_gray_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => gray_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => gray_data_stream_0_V_U_ap_dummy_ce,
if_din => gray_data_stream_0_V_din,
if_full_n => gray_data_stream_0_V_full_n,
if_write => gray_data_stream_0_V_write,
if_dout => gray_data_stream_0_V_dout,
if_empty_n => gray_data_stream_0_V_empty_n,
if_read => gray_data_stream_0_V_read);
gray_rows_V_U : component FIFO_image_filter_gray_rows_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => gray_rows_V_U_ap_dummy_ce,
if_write_ce => gray_rows_V_U_ap_dummy_ce,
if_din => gray_rows_V_din,
if_full_n => gray_rows_V_full_n,
if_write => gray_rows_V_write,
if_dout => gray_rows_V_dout,
if_empty_n => gray_rows_V_empty_n,
if_read => gray_rows_V_read);
gray_cols_V_U : component FIFO_image_filter_gray_cols_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => gray_cols_V_U_ap_dummy_ce,
if_write_ce => gray_cols_V_U_ap_dummy_ce,
if_din => gray_cols_V_din,
if_full_n => gray_cols_V_full_n,
if_write => gray_cols_V_write,
if_dout => gray_cols_V_dout,
if_empty_n => gray_cols_V_empty_n,
if_read => gray_cols_V_read);
mask_data_stream_0_V_U : component FIFO_image_filter_mask_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => mask_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => mask_data_stream_0_V_U_ap_dummy_ce,
if_din => mask_data_stream_0_V_din,
if_full_n => mask_data_stream_0_V_full_n,
if_write => mask_data_stream_0_V_write,
if_dout => mask_data_stream_0_V_dout,
if_empty_n => mask_data_stream_0_V_empty_n,
if_read => mask_data_stream_0_V_read);
dmask_data_stream_0_V_U : component FIFO_image_filter_dmask_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => dmask_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => dmask_data_stream_0_V_U_ap_dummy_ce,
if_din => dmask_data_stream_0_V_din,
if_full_n => dmask_data_stream_0_V_full_n,
if_write => dmask_data_stream_0_V_write,
if_dout => dmask_data_stream_0_V_dout,
if_empty_n => dmask_data_stream_0_V_empty_n,
if_read => dmask_data_stream_0_V_read);
p_dst_data_stream_0_V_U : component FIFO_image_filter_p_dst_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_dst_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => p_dst_data_stream_0_V_U_ap_dummy_ce,
if_din => p_dst_data_stream_0_V_din,
if_full_n => p_dst_data_stream_0_V_full_n,
if_write => p_dst_data_stream_0_V_write,
if_dout => p_dst_data_stream_0_V_dout,
if_empty_n => p_dst_data_stream_0_V_empty_n,
if_read => p_dst_data_stream_0_V_read);
p_dst_data_stream_1_V_U : component FIFO_image_filter_p_dst_data_stream_1_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_dst_data_stream_1_V_U_ap_dummy_ce,
if_write_ce => p_dst_data_stream_1_V_U_ap_dummy_ce,
if_din => p_dst_data_stream_1_V_din,
if_full_n => p_dst_data_stream_1_V_full_n,
if_write => p_dst_data_stream_1_V_write,
if_dout => p_dst_data_stream_1_V_dout,
if_empty_n => p_dst_data_stream_1_V_empty_n,
if_read => p_dst_data_stream_1_V_read);
p_dst_data_stream_2_V_U : component FIFO_image_filter_p_dst_data_stream_2_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => p_dst_data_stream_2_V_U_ap_dummy_ce,
if_write_ce => p_dst_data_stream_2_V_U_ap_dummy_ce,
if_din => p_dst_data_stream_2_V_din,
if_full_n => p_dst_data_stream_2_V_full_n,
if_write => p_dst_data_stream_2_V_write,
if_dout => p_dst_data_stream_2_V_dout,
if_empty_n => p_dst_data_stream_2_V_empty_n,
if_read => p_dst_data_stream_2_V_read);
-- ap_reg_procdone_image_filter_AXIvideo2Mat_U0 assign process. --
ap_reg_procdone_image_filter_AXIvideo2Mat_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_done)) then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 assign process. --
ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done)) then
ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 assign process. --
ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done)) then
ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Block_proc_U0 assign process. --
ap_reg_procdone_image_filter_Block_proc_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
elsif ((image_filter_Block_proc_U0_ap_done = ap_const_logic_1)) then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 assign process. --
ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_Dilate_0_0_1080_1920_U0_ap_done)) then
ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_FAST_t_opr_U0 assign process. --
ap_reg_procdone_image_filter_FAST_t_opr_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_FAST_t_opr_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_FAST_t_opr_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_FAST_t_opr_U0_ap_done)) then
ap_reg_procdone_image_filter_FAST_t_opr_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Mat2AXIvideo_U0 assign process. --
ap_reg_procdone_image_filter_Mat2AXIvideo_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 assign process. --
ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_PaintMask_32_0_1080_1920_U0_ap_done)) then
ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_dmask_cols_V_full_n assign process. --
ap_reg_ready_dmask_cols_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_dmask_cols_V_full_n <= ap_const_logic_0;
else
if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then
ap_reg_ready_dmask_cols_V_full_n <= ap_const_logic_0;
elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = dmask_cols_V_full_n))) then
ap_reg_ready_dmask_cols_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_dmask_rows_V_full_n assign process. --
ap_reg_ready_dmask_rows_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_dmask_rows_V_full_n <= ap_const_logic_0;
else
if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then
ap_reg_ready_dmask_rows_V_full_n <= ap_const_logic_0;
elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = dmask_rows_V_full_n))) then
ap_reg_ready_dmask_rows_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_gray_cols_V_full_n assign process. --
ap_reg_ready_gray_cols_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_gray_cols_V_full_n <= ap_const_logic_0;
else
if (((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_continue))) then
ap_reg_ready_gray_cols_V_full_n <= ap_const_logic_0;
elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done) and (ap_const_logic_1 = gray_cols_V_full_n))) then
ap_reg_ready_gray_cols_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_gray_rows_V_full_n assign process. --
ap_reg_ready_gray_rows_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_gray_rows_V_full_n <= ap_const_logic_0;
else
if (((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_continue))) then
ap_reg_ready_gray_rows_V_full_n <= ap_const_logic_0;
elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done) and (ap_const_logic_1 = gray_rows_V_full_n))) then
ap_reg_ready_gray_rows_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_mask_cols_V_full_n assign process. --
ap_reg_ready_mask_cols_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_mask_cols_V_full_n <= ap_const_logic_0;
else
if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then
ap_reg_ready_mask_cols_V_full_n <= ap_const_logic_0;
elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = mask_cols_V_full_n))) then
ap_reg_ready_mask_cols_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_mask_rows_V_full_n assign process. --
ap_reg_ready_mask_rows_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_mask_rows_V_full_n <= ap_const_logic_0;
else
if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then
ap_reg_ready_mask_rows_V_full_n <= ap_const_logic_0;
elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = mask_rows_V_full_n))) then
ap_reg_ready_mask_rows_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_p_dst_cols_V_channel_full_n assign process. --
ap_reg_ready_p_dst_cols_V_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_p_dst_cols_V_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_p_dst_cols_V_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (p_dst_cols_V_channel_full_n = ap_const_logic_1))) then
ap_reg_ready_p_dst_cols_V_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_p_dst_cols_V_full_n assign process. --
ap_reg_ready_p_dst_cols_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_p_dst_cols_V_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_p_dst_cols_V_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_dst_cols_V_full_n))) then
ap_reg_ready_p_dst_cols_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_p_dst_rows_V_channel_full_n assign process. --
ap_reg_ready_p_dst_rows_V_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_p_dst_rows_V_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_p_dst_rows_V_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_dst_rows_V_channel_full_n))) then
ap_reg_ready_p_dst_rows_V_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_p_dst_rows_V_full_n assign process. --
ap_reg_ready_p_dst_rows_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_p_dst_rows_V_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_p_dst_rows_V_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_dst_rows_V_full_n))) then
ap_reg_ready_p_dst_rows_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n assign process. --
ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_cols_V_2_loc_channel1_full_n))) then
ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_p_src_cols_V_2_loc_channel_full_n assign process. --
ap_reg_ready_p_src_cols_V_2_loc_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_p_src_cols_V_2_loc_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_p_src_cols_V_2_loc_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_cols_V_2_loc_channel_full_n))) then
ap_reg_ready_p_src_cols_V_2_loc_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_p_src_cols_V_channel1_full_n assign process. --
ap_reg_ready_p_src_cols_V_channel1_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_p_src_cols_V_channel1_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_p_src_cols_V_channel1_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_cols_V_channel1_full_n))) then
ap_reg_ready_p_src_cols_V_channel1_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_p_src_cols_V_channel_full_n assign process. --
ap_reg_ready_p_src_cols_V_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_p_src_cols_V_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_p_src_cols_V_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_cols_V_channel_full_n))) then
ap_reg_ready_p_src_cols_V_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n assign process. --
ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_rows_V_2_loc_channel1_full_n))) then
ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_p_src_rows_V_2_loc_channel_full_n assign process. --
ap_reg_ready_p_src_rows_V_2_loc_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_p_src_rows_V_2_loc_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_p_src_rows_V_2_loc_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_rows_V_2_loc_channel_full_n))) then
ap_reg_ready_p_src_rows_V_2_loc_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_p_src_rows_V_channel1_full_n assign process. --
ap_reg_ready_p_src_rows_V_channel1_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_p_src_rows_V_channel1_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_p_src_rows_V_channel1_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_rows_V_channel1_full_n))) then
ap_reg_ready_p_src_rows_V_channel1_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_p_src_rows_V_channel_full_n assign process. --
ap_reg_ready_p_src_rows_V_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_p_src_rows_V_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_p_src_rows_V_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_rows_V_channel_full_n))) then
ap_reg_ready_p_src_rows_V_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_src0_cols_V_full_n assign process. --
ap_reg_ready_src0_cols_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_src0_cols_V_full_n <= ap_const_logic_0;
else
if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then
ap_reg_ready_src0_cols_V_full_n <= ap_const_logic_0;
elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = src0_cols_V_full_n))) then
ap_reg_ready_src0_cols_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_src0_rows_V_full_n assign process. --
ap_reg_ready_src0_rows_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_src0_rows_V_full_n <= ap_const_logic_0;
else
if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then
ap_reg_ready_src0_rows_V_full_n <= ap_const_logic_0;
elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = src0_rows_V_full_n))) then
ap_reg_ready_src0_rows_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_src1_cols_V_full_n assign process. --
ap_reg_ready_src1_cols_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_src1_cols_V_full_n <= ap_const_logic_0;
else
if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then
ap_reg_ready_src1_cols_V_full_n <= ap_const_logic_0;
elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = src1_cols_V_full_n))) then
ap_reg_ready_src1_cols_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_src1_rows_V_full_n assign process. --
ap_reg_ready_src1_rows_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_src1_rows_V_full_n <= ap_const_logic_0;
else
if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then
ap_reg_ready_src1_rows_V_full_n <= ap_const_logic_0;
elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = src1_rows_V_full_n))) then
ap_reg_ready_src1_rows_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_CS assign process. --
ap_CS_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
ap_CS <= ap_const_logic_0;
end if;
end process;
INPUT_STREAM_TREADY <= image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY;
OUTPUT_STREAM_TDATA <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA;
OUTPUT_STREAM_TDEST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST;
OUTPUT_STREAM_TID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID;
OUTPUT_STREAM_TKEEP <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP;
OUTPUT_STREAM_TLAST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST;
OUTPUT_STREAM_TSTRB <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB;
OUTPUT_STREAM_TUSER <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER;
OUTPUT_STREAM_TVALID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID;
-- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V assign process. --
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_dmask_cols_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_dmask_cols_V_full_n)) then
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V assign process. --
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_dmask_rows_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_dmask_rows_V_full_n)) then
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V assign process. --
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_mask_cols_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_mask_cols_V_full_n)) then
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V assign process. --
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_mask_rows_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_mask_rows_V_full_n)) then
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V assign process. --
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_src0_cols_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_src0_cols_V_full_n)) then
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V assign process. --
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_src0_rows_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_src0_rows_V_full_n)) then
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V assign process. --
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_src1_cols_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_src1_cols_V_full_n)) then
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V assign process. --
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_src1_rows_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_src1_rows_V_full_n)) then
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V assign process. --
ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V_assign_proc : process(image_filter_Block_Mat_exit1222_proc1_U0_ap_done, ap_reg_ready_gray_cols_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_gray_cols_V_full_n)) then
ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V <= image_filter_Block_Mat_exit1222_proc1_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V assign process. --
ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V_assign_proc : process(image_filter_Block_Mat_exit1222_proc1_U0_ap_done, ap_reg_ready_gray_rows_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_gray_rows_V_full_n)) then
ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V <= image_filter_Block_Mat_exit1222_proc1_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V assign process. --
ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_dst_cols_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_p_dst_cols_V_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_dst_cols_V_channel_full_n)
begin
if ((ap_reg_ready_p_dst_cols_V_channel_full_n = ap_const_logic_1)) then
ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V assign process. --
ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_dst_rows_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_p_dst_rows_V_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_dst_rows_V_channel_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_p_dst_rows_V_channel_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_cols_V_2_loc_channel_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_p_src_cols_V_2_loc_channel_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1 assign process. --
ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1 <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1 <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_cols_V_channel_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_p_src_cols_V_channel_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1 assign process. --
ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_cols_V_channel1_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_p_src_cols_V_channel1_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1 <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1 <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_rows_V_2_loc_channel_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_p_src_rows_V_2_loc_channel_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1 assign process. --
ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1 <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1 <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_rows_V_channel_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_p_src_rows_V_channel_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1 assign process. --
ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_rows_V_channel1_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_p_src_rows_V_channel1_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1 <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1 <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
ap_done <= ap_sig_hs_done;
-- ap_idle assign process. --
ap_idle_assign_proc : process(image_filter_Block_proc_U0_ap_idle, image_filter_AXIvideo2Mat_U0_ap_idle, image_filter_Block_Mat_exit1220_proc1_U0_ap_idle, image_filter_Block_Mat_exit1222_proc1_U0_ap_idle, image_filter_FAST_t_opr_U0_ap_idle, image_filter_Dilate_0_0_1080_1920_U0_ap_idle, image_filter_PaintMask_32_0_1080_1920_U0_ap_idle, image_filter_Mat2AXIvideo_U0_ap_idle, p_src_cols_V_2_loc_channel1_empty_n, p_src_cols_V_2_loc_channel_empty_n, p_src_rows_V_2_loc_channel1_empty_n, p_src_rows_V_2_loc_channel_empty_n, p_dst_cols_V_channel_empty_n, p_dst_cols_V_empty_n, p_dst_rows_V_channel_empty_n, p_dst_rows_V_empty_n, p_src_cols_V_channel_empty_n, p_src_rows_V_channel_empty_n, p_src_rows_V_channel1_empty_n, p_src_cols_V_channel1_empty_n, src0_rows_V_empty_n, src0_cols_V_empty_n, src1_rows_V_empty_n, src1_cols_V_empty_n, mask_rows_V_empty_n, mask_cols_V_empty_n, dmask_rows_V_empty_n, dmask_cols_V_empty_n, gray_rows_V_empty_n, gray_cols_V_empty_n)
begin
if (((image_filter_Block_proc_U0_ap_idle = ap_const_logic_1) and (ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_idle) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_idle) and (ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_idle) and (ap_const_logic_1 = image_filter_FAST_t_opr_U0_ap_idle) and (ap_const_logic_1 = image_filter_Dilate_0_0_1080_1920_U0_ap_idle) and (ap_const_logic_1 = image_filter_PaintMask_32_0_1080_1920_U0_ap_idle) and (ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_idle) and (ap_const_logic_0 = p_src_cols_V_2_loc_channel1_empty_n) and (ap_const_logic_0 = p_src_cols_V_2_loc_channel_empty_n) and (ap_const_logic_0 = p_src_rows_V_2_loc_channel1_empty_n) and (ap_const_logic_0 = p_src_rows_V_2_loc_channel_empty_n) and (ap_const_logic_0 = p_dst_cols_V_channel_empty_n) and (ap_const_logic_0 = p_dst_cols_V_empty_n) and (ap_const_logic_0 = p_dst_rows_V_channel_empty_n) and (ap_const_logic_0 = p_dst_rows_V_empty_n) and (ap_const_logic_0 = p_src_cols_V_channel_empty_n) and (ap_const_logic_0 = p_src_rows_V_channel_empty_n) and (ap_const_logic_0 = p_src_rows_V_channel1_empty_n) and (ap_const_logic_0 = p_src_cols_V_channel1_empty_n) and (ap_const_logic_0 = src0_rows_V_empty_n) and (ap_const_logic_0 = src0_cols_V_empty_n) and (ap_const_logic_0 = src1_rows_V_empty_n) and (ap_const_logic_0 = src1_cols_V_empty_n) and (ap_const_logic_0 = mask_rows_V_empty_n) and (ap_const_logic_0 = mask_cols_V_empty_n) and (ap_const_logic_0 = dmask_rows_V_empty_n) and (ap_const_logic_0 = dmask_cols_V_empty_n) and (ap_const_logic_0 = gray_rows_V_empty_n) and (ap_const_logic_0 = gray_cols_V_empty_n))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= ap_sig_top_allready;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_hs_continue <= ap_const_logic_1;
-- ap_sig_hs_done assign process. --
ap_sig_hs_done_assign_proc : process(image_filter_Mat2AXIvideo_U0_ap_done)
begin
if ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then
ap_sig_hs_done <= ap_const_logic_1;
else
ap_sig_hs_done <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ready_dmask_cols_V_full_n assign process. --
ap_sig_ready_dmask_cols_V_full_n_assign_proc : process(dmask_cols_V_full_n, ap_reg_ready_dmask_cols_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_dmask_cols_V_full_n)) then
ap_sig_ready_dmask_cols_V_full_n <= dmask_cols_V_full_n;
else
ap_sig_ready_dmask_cols_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_dmask_rows_V_full_n assign process. --
ap_sig_ready_dmask_rows_V_full_n_assign_proc : process(dmask_rows_V_full_n, ap_reg_ready_dmask_rows_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_dmask_rows_V_full_n)) then
ap_sig_ready_dmask_rows_V_full_n <= dmask_rows_V_full_n;
else
ap_sig_ready_dmask_rows_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_gray_cols_V_full_n assign process. --
ap_sig_ready_gray_cols_V_full_n_assign_proc : process(gray_cols_V_full_n, ap_reg_ready_gray_cols_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_gray_cols_V_full_n)) then
ap_sig_ready_gray_cols_V_full_n <= gray_cols_V_full_n;
else
ap_sig_ready_gray_cols_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_gray_rows_V_full_n assign process. --
ap_sig_ready_gray_rows_V_full_n_assign_proc : process(gray_rows_V_full_n, ap_reg_ready_gray_rows_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_gray_rows_V_full_n)) then
ap_sig_ready_gray_rows_V_full_n <= gray_rows_V_full_n;
else
ap_sig_ready_gray_rows_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_mask_cols_V_full_n assign process. --
ap_sig_ready_mask_cols_V_full_n_assign_proc : process(mask_cols_V_full_n, ap_reg_ready_mask_cols_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_mask_cols_V_full_n)) then
ap_sig_ready_mask_cols_V_full_n <= mask_cols_V_full_n;
else
ap_sig_ready_mask_cols_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_mask_rows_V_full_n assign process. --
ap_sig_ready_mask_rows_V_full_n_assign_proc : process(mask_rows_V_full_n, ap_reg_ready_mask_rows_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_mask_rows_V_full_n)) then
ap_sig_ready_mask_rows_V_full_n <= mask_rows_V_full_n;
else
ap_sig_ready_mask_rows_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_p_dst_cols_V_channel_full_n assign process. --
ap_sig_ready_p_dst_cols_V_channel_full_n_assign_proc : process(p_dst_cols_V_channel_full_n, ap_reg_ready_p_dst_cols_V_channel_full_n)
begin
if ((ap_reg_ready_p_dst_cols_V_channel_full_n = ap_const_logic_0)) then
ap_sig_ready_p_dst_cols_V_channel_full_n <= p_dst_cols_V_channel_full_n;
else
ap_sig_ready_p_dst_cols_V_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_p_dst_cols_V_full_n assign process. --
ap_sig_ready_p_dst_cols_V_full_n_assign_proc : process(p_dst_cols_V_full_n, ap_reg_ready_p_dst_cols_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_p_dst_cols_V_full_n)) then
ap_sig_ready_p_dst_cols_V_full_n <= p_dst_cols_V_full_n;
else
ap_sig_ready_p_dst_cols_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_p_dst_rows_V_channel_full_n assign process. --
ap_sig_ready_p_dst_rows_V_channel_full_n_assign_proc : process(p_dst_rows_V_channel_full_n, ap_reg_ready_p_dst_rows_V_channel_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_p_dst_rows_V_channel_full_n)) then
ap_sig_ready_p_dst_rows_V_channel_full_n <= p_dst_rows_V_channel_full_n;
else
ap_sig_ready_p_dst_rows_V_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_p_dst_rows_V_full_n assign process. --
ap_sig_ready_p_dst_rows_V_full_n_assign_proc : process(p_dst_rows_V_full_n, ap_reg_ready_p_dst_rows_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_p_dst_rows_V_full_n)) then
ap_sig_ready_p_dst_rows_V_full_n <= p_dst_rows_V_full_n;
else
ap_sig_ready_p_dst_rows_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n assign process. --
ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n_assign_proc : process(p_src_cols_V_2_loc_channel1_full_n, ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n)) then
ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n <= p_src_cols_V_2_loc_channel1_full_n;
else
ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_p_src_cols_V_2_loc_channel_full_n assign process. --
ap_sig_ready_p_src_cols_V_2_loc_channel_full_n_assign_proc : process(p_src_cols_V_2_loc_channel_full_n, ap_reg_ready_p_src_cols_V_2_loc_channel_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_p_src_cols_V_2_loc_channel_full_n)) then
ap_sig_ready_p_src_cols_V_2_loc_channel_full_n <= p_src_cols_V_2_loc_channel_full_n;
else
ap_sig_ready_p_src_cols_V_2_loc_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_p_src_cols_V_channel1_full_n assign process. --
ap_sig_ready_p_src_cols_V_channel1_full_n_assign_proc : process(p_src_cols_V_channel1_full_n, ap_reg_ready_p_src_cols_V_channel1_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_p_src_cols_V_channel1_full_n)) then
ap_sig_ready_p_src_cols_V_channel1_full_n <= p_src_cols_V_channel1_full_n;
else
ap_sig_ready_p_src_cols_V_channel1_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_p_src_cols_V_channel_full_n assign process. --
ap_sig_ready_p_src_cols_V_channel_full_n_assign_proc : process(p_src_cols_V_channel_full_n, ap_reg_ready_p_src_cols_V_channel_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_p_src_cols_V_channel_full_n)) then
ap_sig_ready_p_src_cols_V_channel_full_n <= p_src_cols_V_channel_full_n;
else
ap_sig_ready_p_src_cols_V_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n assign process. --
ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n_assign_proc : process(p_src_rows_V_2_loc_channel1_full_n, ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n)) then
ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n <= p_src_rows_V_2_loc_channel1_full_n;
else
ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_p_src_rows_V_2_loc_channel_full_n assign process. --
ap_sig_ready_p_src_rows_V_2_loc_channel_full_n_assign_proc : process(p_src_rows_V_2_loc_channel_full_n, ap_reg_ready_p_src_rows_V_2_loc_channel_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_p_src_rows_V_2_loc_channel_full_n)) then
ap_sig_ready_p_src_rows_V_2_loc_channel_full_n <= p_src_rows_V_2_loc_channel_full_n;
else
ap_sig_ready_p_src_rows_V_2_loc_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_p_src_rows_V_channel1_full_n assign process. --
ap_sig_ready_p_src_rows_V_channel1_full_n_assign_proc : process(p_src_rows_V_channel1_full_n, ap_reg_ready_p_src_rows_V_channel1_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_p_src_rows_V_channel1_full_n)) then
ap_sig_ready_p_src_rows_V_channel1_full_n <= p_src_rows_V_channel1_full_n;
else
ap_sig_ready_p_src_rows_V_channel1_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_p_src_rows_V_channel_full_n assign process. --
ap_sig_ready_p_src_rows_V_channel_full_n_assign_proc : process(p_src_rows_V_channel_full_n, ap_reg_ready_p_src_rows_V_channel_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_p_src_rows_V_channel_full_n)) then
ap_sig_ready_p_src_rows_V_channel_full_n <= p_src_rows_V_channel_full_n;
else
ap_sig_ready_p_src_rows_V_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_src0_cols_V_full_n assign process. --
ap_sig_ready_src0_cols_V_full_n_assign_proc : process(src0_cols_V_full_n, ap_reg_ready_src0_cols_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_src0_cols_V_full_n)) then
ap_sig_ready_src0_cols_V_full_n <= src0_cols_V_full_n;
else
ap_sig_ready_src0_cols_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_src0_rows_V_full_n assign process. --
ap_sig_ready_src0_rows_V_full_n_assign_proc : process(src0_rows_V_full_n, ap_reg_ready_src0_rows_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_src0_rows_V_full_n)) then
ap_sig_ready_src0_rows_V_full_n <= src0_rows_V_full_n;
else
ap_sig_ready_src0_rows_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_src1_cols_V_full_n assign process. --
ap_sig_ready_src1_cols_V_full_n_assign_proc : process(src1_cols_V_full_n, ap_reg_ready_src1_cols_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_src1_cols_V_full_n)) then
ap_sig_ready_src1_cols_V_full_n <= src1_cols_V_full_n;
else
ap_sig_ready_src1_cols_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_src1_rows_V_full_n assign process. --
ap_sig_ready_src1_rows_V_full_n_assign_proc : process(src1_rows_V_full_n, ap_reg_ready_src1_rows_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_src1_rows_V_full_n)) then
ap_sig_ready_src1_rows_V_full_n <= src1_rows_V_full_n;
else
ap_sig_ready_src1_rows_V_full_n <= ap_const_logic_1;
end if;
end process;
ap_sig_top_allready <= image_filter_AXIvideo2Mat_U0_ap_ready;
dmask_cols_V_U_ap_dummy_ce <= ap_const_logic_1;
dmask_cols_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_7;
dmask_cols_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready;
dmask_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V;
dmask_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
dmask_data_stream_0_V_din <= image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_din;
dmask_data_stream_0_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_read;
dmask_data_stream_0_V_write <= image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_write;
dmask_rows_V_U_ap_dummy_ce <= ap_const_logic_1;
dmask_rows_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_6;
dmask_rows_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready;
dmask_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V;
gray_cols_V_U_ap_dummy_ce <= ap_const_logic_1;
gray_cols_V_din <= image_filter_Block_Mat_exit1222_proc1_U0_ap_return_1;
gray_cols_V_read <= image_filter_FAST_t_opr_U0_ap_ready;
gray_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V;
gray_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
gray_data_stream_0_V_din <= image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_din;
gray_data_stream_0_V_read <= image_filter_FAST_t_opr_U0_p_src_data_stream_V_read;
gray_data_stream_0_V_write <= image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_write;
gray_rows_V_U_ap_dummy_ce <= ap_const_logic_1;
gray_rows_V_din <= image_filter_Block_Mat_exit1222_proc1_U0_ap_return_0;
gray_rows_V_read <= image_filter_FAST_t_opr_U0_ap_ready;
gray_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA <= INPUT_STREAM_TDATA;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST <= INPUT_STREAM_TDEST;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID <= INPUT_STREAM_TID;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP <= INPUT_STREAM_TKEEP;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST <= INPUT_STREAM_TLAST;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB <= INPUT_STREAM_TSTRB;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER <= INPUT_STREAM_TUSER;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID <= INPUT_STREAM_TVALID;
image_filter_AXIvideo2Mat_U0_ap_continue <= ap_const_logic_1;
image_filter_AXIvideo2Mat_U0_ap_start <= (ap_start and p_src_cols_V_channel_empty_n and p_src_rows_V_channel_empty_n);
image_filter_AXIvideo2Mat_U0_img_cols_V_read <= p_src_cols_V_channel_dout;
image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n <= p_src_data_stream_0_V_full_n;
image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n <= p_src_data_stream_1_V_full_n;
image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n <= p_src_data_stream_2_V_full_n;
image_filter_AXIvideo2Mat_U0_img_rows_V_read <= p_src_rows_V_channel_dout;
-- image_filter_Block_Mat_exit1220_proc1_U0_ap_continue assign process. --
image_filter_Block_Mat_exit1220_proc1_U0_ap_continue_assign_proc : process(ap_sig_ready_src0_rows_V_full_n, ap_sig_ready_src0_cols_V_full_n, ap_sig_ready_src1_rows_V_full_n, ap_sig_ready_src1_cols_V_full_n, ap_sig_ready_mask_rows_V_full_n, ap_sig_ready_mask_cols_V_full_n, ap_sig_ready_dmask_rows_V_full_n, ap_sig_ready_dmask_cols_V_full_n)
begin
if (((ap_const_logic_1 = ap_sig_ready_src0_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_src0_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_src1_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_src1_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_mask_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_mask_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_dmask_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_dmask_cols_V_full_n))) then
image_filter_Block_Mat_exit1220_proc1_U0_ap_continue <= ap_const_logic_1;
else
image_filter_Block_Mat_exit1220_proc1_U0_ap_continue <= ap_const_logic_0;
end if;
end process;
image_filter_Block_Mat_exit1220_proc1_U0_ap_start <= (p_src_cols_V_2_loc_channel_empty_n and p_src_rows_V_2_loc_channel_empty_n and p_src_rows_V_channel1_empty_n and p_src_cols_V_channel1_empty_n);
image_filter_Block_Mat_exit1220_proc1_U0_p_read <= p_src_rows_V_2_loc_channel_dout;
image_filter_Block_Mat_exit1220_proc1_U0_p_read16 <= p_src_rows_V_channel1_dout;
image_filter_Block_Mat_exit1220_proc1_U0_p_read17 <= p_src_cols_V_channel1_dout;
image_filter_Block_Mat_exit1220_proc1_U0_p_read2 <= p_src_cols_V_2_loc_channel_dout;
image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_dout <= p_src_data_stream_0_V_dout;
image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_empty_n <= p_src_data_stream_0_V_empty_n;
image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_dout <= p_src_data_stream_1_V_dout;
image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_empty_n <= p_src_data_stream_1_V_empty_n;
image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_dout <= p_src_data_stream_2_V_dout;
image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_empty_n <= p_src_data_stream_2_V_empty_n;
image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_full_n <= src0_data_stream_0_V_full_n;
image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_full_n <= src0_data_stream_1_V_full_n;
image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_full_n <= src0_data_stream_2_V_full_n;
image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_full_n <= src1_data_stream_0_V_full_n;
image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_full_n <= src1_data_stream_1_V_full_n;
image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_full_n <= src1_data_stream_2_V_full_n;
-- image_filter_Block_Mat_exit1222_proc1_U0_ap_continue assign process. --
image_filter_Block_Mat_exit1222_proc1_U0_ap_continue_assign_proc : process(ap_sig_ready_gray_rows_V_full_n, ap_sig_ready_gray_cols_V_full_n)
begin
if (((ap_const_logic_1 = ap_sig_ready_gray_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_gray_cols_V_full_n))) then
image_filter_Block_Mat_exit1222_proc1_U0_ap_continue <= ap_const_logic_1;
else
image_filter_Block_Mat_exit1222_proc1_U0_ap_continue <= ap_const_logic_0;
end if;
end process;
image_filter_Block_Mat_exit1222_proc1_U0_ap_start <= (p_src_cols_V_2_loc_channel1_empty_n and p_src_rows_V_2_loc_channel1_empty_n and src0_rows_V_empty_n and src0_cols_V_empty_n);
image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_full_n <= gray_data_stream_0_V_full_n;
image_filter_Block_Mat_exit1222_proc1_U0_p_read <= p_src_rows_V_2_loc_channel1_dout;
image_filter_Block_Mat_exit1222_proc1_U0_p_read2 <= p_src_cols_V_2_loc_channel1_dout;
image_filter_Block_Mat_exit1222_proc1_U0_p_read6 <= src0_rows_V_dout;
image_filter_Block_Mat_exit1222_proc1_U0_p_read7 <= src0_cols_V_dout;
image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_dout <= src0_data_stream_0_V_dout;
image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_empty_n <= src0_data_stream_0_V_empty_n;
image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_dout <= src0_data_stream_1_V_dout;
image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_empty_n <= src0_data_stream_1_V_empty_n;
image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_dout <= src0_data_stream_2_V_dout;
image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_empty_n <= src0_data_stream_2_V_empty_n;
-- image_filter_Block_proc_U0_ap_continue assign process. --
image_filter_Block_proc_U0_ap_continue_assign_proc : process(ap_sig_ready_p_dst_cols_V_channel_full_n, ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n, ap_sig_ready_p_src_cols_V_2_loc_channel_full_n, ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n, ap_sig_ready_p_src_rows_V_2_loc_channel_full_n, ap_sig_ready_p_src_cols_V_channel_full_n, ap_sig_ready_p_dst_cols_V_full_n, ap_sig_ready_p_dst_rows_V_channel_full_n, ap_sig_ready_p_dst_rows_V_full_n, ap_sig_ready_p_src_rows_V_channel_full_n, ap_sig_ready_p_src_rows_V_channel1_full_n, ap_sig_ready_p_src_cols_V_channel1_full_n)
begin
if (((ap_sig_ready_p_dst_cols_V_channel_full_n = ap_const_logic_1) and (ap_const_logic_1 = ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_cols_V_2_loc_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_rows_V_2_loc_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_cols_V_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_dst_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_p_dst_rows_V_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_dst_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_rows_V_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_rows_V_channel1_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_cols_V_channel1_full_n))) then
image_filter_Block_proc_U0_ap_continue <= ap_const_logic_1;
else
image_filter_Block_proc_U0_ap_continue <= ap_const_logic_0;
end if;
end process;
image_filter_Block_proc_U0_ap_start <= ap_start;
image_filter_Block_proc_U0_cols <= cols;
image_filter_Block_proc_U0_rows <= rows;
image_filter_Dilate_0_0_1080_1920_U0_ap_continue <= ap_const_logic_1;
image_filter_Dilate_0_0_1080_1920_U0_ap_start <= (mask_rows_V_empty_n and mask_cols_V_empty_n);
image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_full_n <= dmask_data_stream_0_V_full_n;
image_filter_Dilate_0_0_1080_1920_U0_p_src_cols_V_read <= mask_cols_V_dout;
image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_dout <= mask_data_stream_0_V_dout;
image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_empty_n <= mask_data_stream_0_V_empty_n;
image_filter_Dilate_0_0_1080_1920_U0_p_src_rows_V_read <= mask_rows_V_dout;
image_filter_FAST_t_opr_U0_ap_continue <= ap_const_logic_1;
image_filter_FAST_t_opr_U0_ap_start <= (gray_rows_V_empty_n and gray_cols_V_empty_n);
image_filter_FAST_t_opr_U0_p_mask_data_stream_V_full_n <= mask_data_stream_0_V_full_n;
image_filter_FAST_t_opr_U0_p_src_cols_V_read <= gray_cols_V_dout;
image_filter_FAST_t_opr_U0_p_src_data_stream_V_dout <= gray_data_stream_0_V_dout;
image_filter_FAST_t_opr_U0_p_src_data_stream_V_empty_n <= gray_data_stream_0_V_empty_n;
image_filter_FAST_t_opr_U0_p_src_rows_V_read <= gray_rows_V_dout;
image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY;
image_filter_Mat2AXIvideo_U0_ap_continue <= ap_sig_hs_continue;
image_filter_Mat2AXIvideo_U0_ap_start <= (p_dst_cols_V_channel_empty_n and p_dst_rows_V_channel_empty_n);
image_filter_Mat2AXIvideo_U0_img_cols_V_read <= p_dst_cols_V_channel_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout <= p_dst_data_stream_0_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n <= p_dst_data_stream_0_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout <= p_dst_data_stream_1_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n <= p_dst_data_stream_1_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout <= p_dst_data_stream_2_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n <= p_dst_data_stream_2_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_rows_V_read <= p_dst_rows_V_channel_dout;
image_filter_PaintMask_32_0_1080_1920_U0_ap_continue <= ap_const_logic_1;
image_filter_PaintMask_32_0_1080_1920_U0_ap_start <= (p_dst_cols_V_empty_n and p_dst_rows_V_empty_n and src1_rows_V_empty_n and src1_cols_V_empty_n and dmask_rows_V_empty_n and dmask_cols_V_empty_n);
image_filter_PaintMask_32_0_1080_1920_U0_p_dst_cols_V_read <= p_dst_cols_V_dout;
image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_full_n <= p_dst_data_stream_0_V_full_n;
image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_full_n <= p_dst_data_stream_1_V_full_n;
image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_full_n <= p_dst_data_stream_2_V_full_n;
image_filter_PaintMask_32_0_1080_1920_U0_p_dst_rows_V_read <= p_dst_rows_V_dout;
image_filter_PaintMask_32_0_1080_1920_U0_p_mask_cols_V_read <= dmask_cols_V_dout;
image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_dout <= dmask_data_stream_0_V_dout;
image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_empty_n <= dmask_data_stream_0_V_empty_n;
image_filter_PaintMask_32_0_1080_1920_U0_p_mask_rows_V_read <= dmask_rows_V_dout;
image_filter_PaintMask_32_0_1080_1920_U0_p_src_cols_V_read <= src1_cols_V_dout;
image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_dout <= src1_data_stream_0_V_dout;
image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_empty_n <= src1_data_stream_0_V_empty_n;
image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_dout <= src1_data_stream_1_V_dout;
image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_empty_n <= src1_data_stream_1_V_empty_n;
image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_dout <= src1_data_stream_2_V_dout;
image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_empty_n <= src1_data_stream_2_V_empty_n;
image_filter_PaintMask_32_0_1080_1920_U0_p_src_rows_V_read <= src1_rows_V_dout;
mask_cols_V_U_ap_dummy_ce <= ap_const_logic_1;
mask_cols_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_5;
mask_cols_V_read <= image_filter_Dilate_0_0_1080_1920_U0_ap_ready;
mask_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V;
mask_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
mask_data_stream_0_V_din <= image_filter_FAST_t_opr_U0_p_mask_data_stream_V_din;
mask_data_stream_0_V_read <= image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_read;
mask_data_stream_0_V_write <= image_filter_FAST_t_opr_U0_p_mask_data_stream_V_write;
mask_rows_V_U_ap_dummy_ce <= ap_const_logic_1;
mask_rows_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_4;
mask_rows_V_read <= image_filter_Dilate_0_0_1080_1920_U0_ap_ready;
mask_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V;
p_dst_cols_V_U_ap_dummy_ce <= ap_const_logic_1;
p_dst_cols_V_channel_U_ap_dummy_ce <= ap_const_logic_1;
p_dst_cols_V_channel_din <= image_filter_Block_proc_U0_ap_return_5;
p_dst_cols_V_channel_read <= image_filter_Mat2AXIvideo_U0_ap_ready;
p_dst_cols_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel;
p_dst_cols_V_din <= image_filter_Block_proc_U0_ap_return_4;
p_dst_cols_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready;
p_dst_cols_V_write <= ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V;
p_dst_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
p_dst_data_stream_0_V_din <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_din;
p_dst_data_stream_0_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read;
p_dst_data_stream_0_V_write <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_write;
p_dst_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1;
p_dst_data_stream_1_V_din <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_din;
p_dst_data_stream_1_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read;
p_dst_data_stream_1_V_write <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_write;
p_dst_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1;
p_dst_data_stream_2_V_din <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_din;
p_dst_data_stream_2_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read;
p_dst_data_stream_2_V_write <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_write;
p_dst_rows_V_U_ap_dummy_ce <= ap_const_logic_1;
p_dst_rows_V_channel_U_ap_dummy_ce <= ap_const_logic_1;
p_dst_rows_V_channel_din <= image_filter_Block_proc_U0_ap_return_3;
p_dst_rows_V_channel_read <= image_filter_Mat2AXIvideo_U0_ap_ready;
p_dst_rows_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel;
p_dst_rows_V_din <= image_filter_Block_proc_U0_ap_return_2;
p_dst_rows_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready;
p_dst_rows_V_write <= ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V;
p_src_cols_V_2_loc_channel1_U_ap_dummy_ce <= ap_const_logic_1;
p_src_cols_V_2_loc_channel1_din <= image_filter_Block_proc_U0_ap_return_9;
p_src_cols_V_2_loc_channel1_read <= image_filter_Block_Mat_exit1222_proc1_U0_ap_ready;
p_src_cols_V_2_loc_channel1_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1;
p_src_cols_V_2_loc_channel_U_ap_dummy_ce <= ap_const_logic_1;
p_src_cols_V_2_loc_channel_din <= image_filter_Block_proc_U0_ap_return_8;
p_src_cols_V_2_loc_channel_read <= image_filter_Block_Mat_exit1220_proc1_U0_ap_ready;
p_src_cols_V_2_loc_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel;
p_src_cols_V_channel1_U_ap_dummy_ce <= ap_const_logic_1;
p_src_cols_V_channel1_din <= image_filter_Block_proc_U0_ap_return_11;
p_src_cols_V_channel1_read <= image_filter_Block_Mat_exit1220_proc1_U0_ap_ready;
p_src_cols_V_channel1_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1;
p_src_cols_V_channel_U_ap_dummy_ce <= ap_const_logic_1;
p_src_cols_V_channel_din <= image_filter_Block_proc_U0_ap_return_1;
p_src_cols_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready;
p_src_cols_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel;
p_src_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
p_src_data_stream_0_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din;
p_src_data_stream_0_V_read <= image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_read;
p_src_data_stream_0_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write;
p_src_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1;
p_src_data_stream_1_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din;
p_src_data_stream_1_V_read <= image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_read;
p_src_data_stream_1_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write;
p_src_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1;
p_src_data_stream_2_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din;
p_src_data_stream_2_V_read <= image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_read;
p_src_data_stream_2_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write;
p_src_rows_V_2_loc_channel1_U_ap_dummy_ce <= ap_const_logic_1;
p_src_rows_V_2_loc_channel1_din <= image_filter_Block_proc_U0_ap_return_7;
p_src_rows_V_2_loc_channel1_read <= image_filter_Block_Mat_exit1222_proc1_U0_ap_ready;
p_src_rows_V_2_loc_channel1_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1;
p_src_rows_V_2_loc_channel_U_ap_dummy_ce <= ap_const_logic_1;
p_src_rows_V_2_loc_channel_din <= image_filter_Block_proc_U0_ap_return_6;
p_src_rows_V_2_loc_channel_read <= image_filter_Block_Mat_exit1220_proc1_U0_ap_ready;
p_src_rows_V_2_loc_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel;
p_src_rows_V_channel1_U_ap_dummy_ce <= ap_const_logic_1;
p_src_rows_V_channel1_din <= image_filter_Block_proc_U0_ap_return_10;
p_src_rows_V_channel1_read <= image_filter_Block_Mat_exit1220_proc1_U0_ap_ready;
p_src_rows_V_channel1_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1;
p_src_rows_V_channel_U_ap_dummy_ce <= ap_const_logic_1;
p_src_rows_V_channel_din <= image_filter_Block_proc_U0_ap_return_0;
p_src_rows_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready;
p_src_rows_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel;
src0_cols_V_U_ap_dummy_ce <= ap_const_logic_1;
src0_cols_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_1;
src0_cols_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_ap_ready;
src0_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V;
src0_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
src0_data_stream_0_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_din;
src0_data_stream_0_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_read;
src0_data_stream_0_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_write;
src0_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1;
src0_data_stream_1_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_din;
src0_data_stream_1_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_read;
src0_data_stream_1_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_write;
src0_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1;
src0_data_stream_2_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_din;
src0_data_stream_2_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_read;
src0_data_stream_2_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_write;
src0_rows_V_U_ap_dummy_ce <= ap_const_logic_1;
src0_rows_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_0;
src0_rows_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_ap_ready;
src0_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V;
src1_cols_V_U_ap_dummy_ce <= ap_const_logic_1;
src1_cols_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_3;
src1_cols_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready;
src1_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V;
src1_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
src1_data_stream_0_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_din;
src1_data_stream_0_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_read;
src1_data_stream_0_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_write;
src1_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1;
src1_data_stream_1_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_din;
src1_data_stream_1_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_read;
src1_data_stream_1_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_write;
src1_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1;
src1_data_stream_2_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_din;
src1_data_stream_2_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_read;
src1_data_stream_2_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_write;
src1_rows_V_U_ap_dummy_ce <= ap_const_logic_1;
src1_rows_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_2;
src1_rows_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready;
src1_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V;
end behav;
| gpl-3.0 | 4d7a2c9f52d8b444a5d3bd8a4ea41a05 | 0.636179 | 2.662131 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-terasic-de4/testbench.vhd | 1 | 18,563 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romdepth : integer := 25; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
-- clocks
signal OSC_50_BANK2 : std_logic := '0';
signal OSC_50_BANK3 : std_logic := '0';
signal OSC_50_BANK4 : std_logic := '0';
signal OSC_50_BANK5 : std_logic := '0';
signal OSC_50_BANK6 : std_logic := '0';
signal OSC_50_BANK7 : std_logic := '0';
signal PLL_CLKIN_p : std_logic := '0';
signal SMA_CLKIN_p : std_logic := '0';
--signal SMA_GXBCLK_p : std_logic;
signal GCLKIN : std_logic := '0';
signal GCLKOUT_FPGA : std_logic := '0';
signal SMA_CLKOUT_p : std_logic := '0';
-- cpu reset
signal CPU_RESET_n : std_ulogic := '0';
-- max i/o
signal MAX_CONF_D : std_logic_vector(3 downto 0);
signal MAX_I2C_SCLK : std_logic;
signal MAX_I2C_SDAT : std_logic;
-- LEDs
signal LED : std_logic_vector(7 downto 0);
-- buttons
signal BUTTON : std_logic_vector(3 downto 0);
-- switches
signal SW : std_logic_vector(3 downto 0);
-- slide switches
signal SLIDE_SW : std_logic_vector(3 downto 0);
-- temperature
signal TEMP_SMCLK : std_logic;
signal TEMP_SMDAT : std_logic;
signal TEMP_INT_n : std_logic;
-- current
signal CSENSE_ADC_FO : std_logic;
signal CSENSE_SCK : std_logic;
signal CSENSE_SDI : std_logic;
signal CSENSE_SDO : std_logic;
signal CSENSE_CS_n : std_logic_vector(1 downto 0);
-- fan
signal FAN_CTRL : std_logic;
-- eeprom
signal EEP_SCL : std_logic;
signal EEP_SDA : std_logic;
-- sdcard
signal SD_CLK : std_logic;
signal SD_CMD : std_logic;
signal SD_DAT : std_logic_vector(3 downto 0);
signal SD_WP_n : std_logic;
-- Ethernet interfaces
signal ETH_INT_n : std_logic_vector(3 downto 0);
signal ETH_MDC : std_logic_vector(3 downto 0);
signal ETH_MDIO : std_logic_vector(3 downto 0);
signal ETH_RST_n : std_ulogic;
signal ETH_RX_p : std_logic_vector(3 downto 0);
signal ETH_TX_p : std_logic_vector(3 downto 0);
-- PCIe interfaces
--signal PCIE_PREST_n : std_ulogic;
--signal PCIE_REFCLK_p : std_ulogic;
--signal PCIE_RX_p : std_logic_vector(7 downto 0);
--signal PCIE_SMBCLK : std_logic;
--signal PCIE_SMBDAT : std_logic;
--signal PCIE_TX_p : std_logic_vector(7 downto 0);
--signal PCIE_WAKE_n : std_logic;
-- Flash and SRAM, shared signals
signal FSM_A : std_logic_vector(25 downto 1);
signal FSM_D : std_logic_vector(15 downto 0);
-- Flash control
signal FLASH_ADV_n : std_ulogic;
signal FLASH_CE_n : std_ulogic;
signal FLASH_CLK : std_ulogic;
signal FLASH_OE_n : std_ulogic;
signal FLASH_RESET_n : std_ulogic;
signal FLASH_RYBY_n : std_ulogic;
signal FLASH_WE_n : std_ulogic;
-- SSRAM control
signal SSRAM_ADV : std_ulogic;
signal SSRAM_BWA_n : std_ulogic;
signal SSRAM_BWB_n : std_ulogic;
signal SSRAM_CE_n : std_ulogic;
signal SSRAM_CKE_n : std_ulogic;
signal SSRAM_CLK : std_ulogic;
signal SSRAM_OE_n : std_ulogic;
signal SSRAM_WE_n : std_ulogic;
-- USB OTG
--signal OTG_A : std_logic_vector(17 downto 1);
--signal OTG_CS_n : std_ulogic;
--signal OTG_D : std_logic_vector(31 downto 0);
--signal OTG_DC_DACK : std_ulogic;
--signal OTG_DC_DREQ : std_ulogic;
--signal OTG_DC_IRQ : std_ulogic;
--signal OTG_HC_DACK : std_ulogic;
--signal OTG_HC_DREQ : std_ulogic;
--signal OTG_HC_IRQ : std_ulogic;
--signal OTG_OE_n : std_ulogic;
--signal OTG_RESET_n : std_ulogic;
--signal OTG_WE_n : std_ulogic;
-- SATA
--signal SATA_REFCLK_p : std_logic;
--signal SATA_HOST_RX_p : std_logic_vector(1 downto 0);
--signal SATA_HOST_TX_p : std_logic_vector(1 downto 0);
--signal SATA_DEVICE_RX_p : std_logic_vector(1 downto 0);
--signal SATA_DEVICE_TX_p : std_logic_vector(1 downto 0);
-- DDR2 SODIMM
signal M1_DDR2_addr : std_logic_vector(15 downto 0);
signal M1_DDR2_ba : std_logic_vector(2 downto 0);
signal M1_DDR2_cas_n : std_logic;
signal M1_DDR2_cke : std_logic_vector(1 downto 0);
signal M1_DDR2_clk : std_logic_vector(1 downto 0);
signal M1_DDR2_clk_n : std_logic_vector(1 downto 0);
signal M1_DDR2_cs_n : std_logic_vector(1 downto 0);
signal M1_DDR2_dm : std_logic_vector(7 downto 0);
signal M1_DDR2_dq : std_logic_vector(63 downto 0);
signal M1_DDR2_dqs : std_logic_vector(7 downto 0);
signal M1_DDR2_dqsn : std_logic_vector(7 downto 0);
signal M1_DDR2_odt : std_logic_vector(1 downto 0);
signal M1_DDR2_ras_n : std_logic;
-- signal M1_DDR2_SA : std_logic_vector(1 downto 0);
-- signal M1_DDR2_SCL : std_logic;
-- signal M1_DDR2_SDA : std_logic;
signal M1_DDR2_we_n : std_logic;
signal M1_DDR2_oct_rdn : std_logic;
signal M1_DDR2_oct_rup : std_logic;
-- DDR2 SODIMM
--signal M2_DDR2_addr : std_logic_vector(15 downto 0);
--signal M2_DDR2_ba : std_logic_vector(2 downto 0);
--signal M2_DDR2_cas_n : std_logic;
--signal M2_DDR2_cke : std_logic_vector(1 downto 0);
--signal M2_DDR2_clk : std_logic_vector(1 downto 0);
--signal M2_DDR2_clk_n : std_logic_vector(1 downto 0);
--signal M2_DDR2_cs_n : std_logic_vector(1 downto 0);
--signal M2_DDR2_dm : std_logic_vector(7 downto 0);
--signal M2_DDR2_dq : std_logic_vector(63 downto 0);
--signal M2_DDR2_dqs : std_logic_vector(7 downto 0);
--signal M2_DDR2_dqsn : std_logic_vector(7 downto 0);
--signal M2_DDR2_odt : std_logic_vector(1 downto 0);
--signal M2_DDR2_ras_n : std_logic;
--signal M2_DDR2_SA : std_logic_vector(1 downto 0);
--signal M2_DDR2_SCL : std_logic;
--signal M2_DDR2_SDA : std_logic;
--signal M2_DDR2_we_n : std_logic;
-- GPIO
signal GPIO0_D : std_logic_vector(35 downto 0);
signal GPIO1_D : std_logic_vector(35 downto 0);
-- Ext I/O
signal EXT_IO : std_logic;
-- HSMC A
-- signal HSMA_CLKIN_n1 : std_logic;
-- signal HSMA_CLKIN_n2 : std_logic;
-- signal HSMA_CLKIN_p1 : std_logic;
-- signal HSMA_CLKIN_p2 : std_logic;
-- signal HSMA_CLKIN0 : std_logic;
-- signal HSMA_CLKOUT_n2 : std_logic;
-- signal HSMA_CLKOUT_p2 : std_logic;
-- signal HSMA_D : std_logic_vector(3 downto 0);
-- HSMA_GXB_RX_p : std_logic_vector(3 downto 0);
-- HSMA_GXB_TX_p : std_logic_vector(3 downto 0);
-- signal HSMA_OUT_n1 : std_logic;
-- signal HSMA_OUT_p1 : std_logic;
-- signal HSMA_OUT0 : std_logic;
-- HSMA_REFCLK_p : in std_logic;
-- signal HSMA_RX_n : std_logic_vector(16 downto 0);
-- signal HSMA_RX_p : std_logic_vector(16 downto 0);
-- signal HSMA_TX_n : std_logic_vector(16 downto 0);
-- signal HSMA_TX_p : std_logic_vector(16 downto 0);
-- HSMC_B
-- signal HSMB_CLKIN_n1 : std_logic;
-- signal HSMB_CLKIN_n2 : std_logic;
-- signal HSMB_CLKIN_p1 : std_logic;
-- signal HSMB_CLKIN_p2 : std_logic;
-- signal HSMB_CLKIN0 : std_logic;
-- signal HSMB_CLKOUT_n2 : std_logic;
-- signal HSMB_CLKOUT_p2 : std_logic;
-- signal HSMB_D : std_logic_vector(3 downto 0);
-- signal HSMB_GXB_RX_p : in std_logic_vector(3 downto 0);
-- signal HSMB_GXB_TX_p : out std_logic_vector(3 downto 0);
-- signal HSMB_OUT_n1 : std_logic;
-- signal HSMB_OUT_p1 : std_logic;
-- signal HSMB_OUT0 : std_logic;
-- signal HSMB_REFCLK_p : in std_logic;
-- signal HSMB_RX_n : std_logic_vector(16 downto 0);
-- signal HSMB_RX_p : std_logic_vector(16 downto 0);
-- signal HSMB_TX_n : std_logic_vector(16 downto 0);
-- signal HSMB_TX_p : std_logic_vector(16 downto 0);
-- HSMC i2c
-- signal HSMC_SCL : std_logic;
-- signal HSMC_SDA : std_logic;
-- Display
-- signal SEG0_D : std_logic_vector(6 downto 0);
-- signal SEG1_D : std_logic_vector(6 downto 0);
-- signal SEG0_DP : std_ulogic;
-- signal SEG1_DP : std_ulogic;
-- UART
signal UART_CTS : std_ulogic;
signal UART_RTS : std_ulogic;
signal UART_RXD : std_logic;
signal UART_TXD : std_logic;
signal dsuen, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
constant lresp : boolean := false;
begin
-- clock and reset
-- 50 MHz clocks
OSC_50_BANK2 <= not OSC_50_BANK2 after 10 ns;
OSC_50_BANK3 <= not OSC_50_BANK3 after 10 ns;
OSC_50_BANK4 <= not OSC_50_BANK4 after 10 ns;
OSC_50_BANK5 <= not OSC_50_BANK5 after 10 ns;
OSC_50_BANK6 <= not OSC_50_BANK6 after 10 ns;
OSC_50_BANK7 <= not OSC_50_BANK7 after 10 ns;
-- 100 MHz
PLL_CLKIN_p <= not PLL_CLKIN_p after 5 ns;
SMA_CLKIN_p <= not SMA_CLKIN_p after 10 ns;
GCLKIN <= not GCLKIN after 10 ns;
CPU_RESET_n <= '0', '1' after 200 ns;
-- various interfaces
MAX_CONF_D <= (others => 'H');
MAX_I2C_SDAT <= 'H';
BUTTON <= "HHHH";
SW <= (others => 'H');
SLIDE_SW <= (others => 'L');
TEMP_SMDAT <= 'H';
TEMP_INT_n <= 'H';
CSENSE_SCK <= 'H';
CSENSE_SDO <= 'H';
EEP_SDA <= 'H';
SD_CMD <= 'H';
SD_DAT <= (others => 'H');
SD_WP_n <= 'H';
GPIO0_D <= (others => 'H');
GPIO1_D <= (others => 'H');
EXT_IO <= 'H';
LED(0) <= 'H';
-- HSMC_SDA <= 'H';
UART_RTS <= '1';
UART_RXD <= 'H';
-- LEON3 SoC
d3 : entity work.leon3mp
generic map (
fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
OSC_50_BANK2, OSC_50_BANK3, OSC_50_BANK4, OSC_50_BANK5, OSC_50_BANK6,
OSC_50_BANK7, PLL_CLKIN_p, SMA_CLKIN_p,
-- SMA_GXBCLK_p
GCLKIN, GCLKOUT_FPGA, SMA_CLKOUT_p,
-- cpu reset
CPU_RESET_n,
-- max i/o
MAX_CONF_D, MAX_I2C_SCLK, MAX_I2C_SDAT,
-- LEDs
LED,
-- buttons
BUTTON,
-- switches
SW,
-- slide switches
SLIDE_SW,
-- temperature
TEMP_SMCLK, TEMP_SMDAT, TEMP_INT_n,
-- current
CSENSE_ADC_FO, CSENSE_SCK, CSENSE_SDI, CSENSE_SDO, CSENSE_CS_n,
-- fan
FAN_CTRL,
-- eeprom
EEP_SCL, EEP_SDA,
-- sdcard
SD_CLK, SD_CMD, SD_DAT, SD_WP_n,
-- Ethernet interfaces
ETH_INT_n, ETH_MDC, ETH_MDIO, ETH_RST_n, ETH_RX_p, ETH_TX_p,
-- PCIe interfaces
-- PCIE_PREST_n, PCIE_REFCLK_p, PCIE_RX_p, PCIE_SMBCLK,
-- PCIE_SMBDAT, PCIE_TX_p PCIE_WAKE_n
-- Flash and SRAM, shared signals
FSM_A, FSM_D,
-- Flash control
FLASH_ADV_n, FLASH_CE_n, FLASH_CLK, FLASH_OE_n,
FLASH_RESET_n, FLASH_RYBY_n, FLASH_WE_n,
-- SSRAM control
SSRAM_ADV, SSRAM_BWA_n, SSRAM_BWB_n, SSRAM_CE_n,
SSRAM_CKE_n, SSRAM_CLK, SSRAM_OE_n, SSRAM_WE_n,
-- USB OTG
-- OTG_A, OTG_CS_n, OTG_D, OTG_DC_DACK, OTG_DC_DRE, OTG_DC_IRQ,
-- OTG_HC_DACK, OTG_HC_DREQ, OTG_HC_IRQ, OTG_OE_n, OTG_RESET_n,
-- OTG_WE_n,
-- SATA
-- SATA_REFCLK_p, SATA_HOST_RX_p, SATA_HOST_TX_p, SATA_DEVICE_RX_p, SATA_DEVICE_TX_p,
-- DDR2 SODIMM
M1_DDR2_addr, M1_DDR2_ba, M1_DDR2_cas_n, M1_DDR2_cke, M1_DDR2_clk, M1_DDR2_clk_n,
M1_DDR2_cs_n, M1_DDR2_dm, M1_DDR2_dq, M1_DDR2_dqs, M1_DDR2_dqsn, M1_DDR2_odt,
M1_DDR2_ras_n,
-- M1_DDR2_SA, M1_DDR2_SCL, M1_DDR2_SDA,
M1_DDR2_we_n,
M1_DDR2_oct_rdn, M1_DDR2_oct_rup,
-- DDR2 SODIMM
-- M2_DDR2_addr, M2_DDR2_ba, M2_DDR2_cas_n, M2_DDR2_cke, M2_DDR2_clk, M2_DDR2_clk_n
-- M2_DDR2_cs_n, M2_DDR2_dm, M2_DDR2_dq, M2_DDR2_dqs, M2_DDR2_dqsn, M2_DDR2_odt,
-- M2_DDR2_ras_n, M2_DDR2_SA, M2_DDR2_SCL, M2_DDR2_SDA M2_DDR2_we_n
-- GPIO
GPIO0_D, GPIO1_D,
-- Ext I/O
-- EXT_IO,
-- HSMC A
-- HSMA_CLKIN_n1, HSMA_CLKIN_n2, HSMA_CLKIN_p1, HSMA_CLKIN_p2, HSMA_CLKIN0,
-- HSMA_CLKOUT_n2, HSMA_CLKOUT_p2, HSMA_D,
-- HSMA_GXB_RX_p, HSMA_GXB_TX_p,
-- HSMA_OUT_n1, HSMA_OUT_p1, HSMA_OUT0,
-- HSMA_REFCLK_p,
-- HSMA_RX_n, HSMA_RX_p, HSMA_TX_n, HSMA_TX_p,
-- HSMC_B
-- HSMB_CLKIN_n1, HSMB_CLKIN_n2, HSMB_CLKIN_p1, HSMB_CLKIN_p2, HSMB_CLKIN0,
-- HSMB_CLKOUT_n2, HSMB_CLKOUT_p2, HSMB_D,
-- HSMB_GXB_RX_p, HSMB_GXB_TX_p,
-- HSMB_OUT_n1, HSMB_OUT_p1, HSMB_OUT0,
-- HSMB_REFCLK_p,
-- HSMB_RX_n, HSMB_RX_p, HSMB_TX_n, HSMB_TX_p,
-- HSMC i2c
-- HSMC_SCL, HSMC_SDA,
-- Display
-- SEG0_D, SEG1_D, SEG0_DP, SEG1_DP,
-- UART
UART_CTS, UART_RTS, UART_RXD, UART_TXD
);
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (FSM_A(romdepth downto 1), FSM_D, FLASH_CE_n, FLASH_CE_n, FLASH_CE_n,
FLASH_WE_n, FLASH_OE_n);
FLASH_RYBY_n <= 'H';
test0 : grtestmod
generic map ( width => 16 )
port map ( CPU_RESET_n, OSC_50_BANK3, LED(0), FSM_A(20 downto 1), FSM_D,
'0', FLASH_OE_n, FLASH_WE_n);
iuerr : process
begin
wait for 2500 ns;
if to_x01(LED(0)) = '1' then wait on LED(0); end if;
assert (to_x01(LED(0)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
FSM_D <= buskeep(FSM_D) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);--
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);--
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);--
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);--
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);--
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);--
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);--
end;--
begin--
dsucfg(UART_TXD, UART_RXD);--
wait;
end process;
end ;
| gpl-2.0 | 98b4e8e2a2dbd50f620a34498622a521 | 0.582126 | 2.758247 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/unisim/memory_unisim.vhd | 1 | 26,997 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_xilinx_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Xilinx rams
------------------------------------------------------------------------------
-- parametrisable sync ram generator using UNISIM RAMB16 block rams
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S36;
use unisim.RAMB16_S18;
use unisim.RAMB16_S9;
use unisim.RAMB16_S4;
use unisim.RAMB16_S2;
use unisim.RAMB16_S1;
--pragma translate_on
entity unisim_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of unisim_syncram is
component RAMB16_S36_S36
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S1
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+72 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(dbits+72 downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(19 downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a8 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 8)) generate
x : for i in 0 to ((dbits-1)/72) generate
r0 : RAMB16_S36_S36 port map (
do(i*72+36+31 downto i*72+36), do(i*72+31 downto i*72),
do(i*72+36+32+3 downto i*72+36+32), do(i*72+32+3 downto i*72+32),
xa(8 downto 0), ya(8 downto 0), clk, clk,
di(i*72+36+31 downto i*72+36), di(i*72+31 downto i*72),
di(i*72+36+32+3 downto i*72+36+32), di(i*72+32+3 downto i*72+32),
enable, enable, gnd, gnd, write, write);
end generate;
do(dbits+72 downto 72*(((dbits-1)/72)+1)) <= (others => '0');
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/36) generate
r : RAMB16_S36 port map ( do(((i+1)*36)-5 downto i*36),
do(((i+1)*36)-1 downto i*36+32), xa(8 downto 0), clk,
di(((i+1)*36)-5 downto i*36), di(((i+1)*36)-1 downto i*36+32),
enable, gnd, write);
end generate;
do(dbits+72 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/18) generate
r : RAMB16_S18 port map ( do(((i+1)*18)-3 downto i*18),
do(((i+1)*18)-1 downto i*18+16), xa(9 downto 0), clk,
di(((i+1)*18)-3 downto i*18), di(((i+1)*18)-1 downto i*18+16),
enable, gnd, write);
end generate;
do(dbits+72 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r : RAMB16_S9 port map ( do(((i+1)*9)-2 downto i*9),
do(((i+1)*9)-1 downto i*9+8), xa(10 downto 0), clk,
di(((i+1)*9)-2 downto i*9), di(((i+1)*9)-1 downto i*9+8),
enable, gnd, write);
end generate;
do(dbits+72 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB16_S4 port map ( do(((i+1)*4)-1 downto i*4), xa(11 downto 0),
clk, di(((i+1)*4)-1 downto i*4), enable, gnd, write);
end generate;
do(dbits+72 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB16_S2 port map ( do(((i+1)*2)-1 downto i*2), xa(12 downto 0),
clk, di(((i+1)*2)-1 downto i*2), enable, gnd, write);
end generate;
do(dbits+72 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to (dbits-1) generate
r : RAMB16_S1 port map ( do((i+1)-1 downto i), xa(13 downto 0),
clk, di((i+1)-1 downto i), enable, gnd, write);
end generate;
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a15 : if abits > 14 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
-- a_to_high : if abits > 14 generate
-- x : process
-- begin
-- assert false
-- report "Address depth larger than 14 not supported for unisim_syncram"
-- severity failure;
-- wait;
-- end process;
-- end generate;
-- pragma translate_on
end;
LIBRARY ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S18_S18;
use unisim.RAMB16_S9_S9;
use unisim.RAMB16_S4_S4;
use unisim.RAMB16_S2_S2;
use unisim.RAMB16_S1_S1;
--pragma translate_on
entity unisim_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of unisim_syncram_dp is
component RAMB16_S4_S4
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+36 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+36 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+36 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/36) generate
r0 : RAMB16_S36_S36 port map (
do1(((i+1)*36)-5 downto i*36), do2(((i+1)*36)-5 downto i*36),
do1(((i+1)*36)-1 downto i*36+32), do2(((i+1)*36)-1 downto i*36+32),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*36)-5 downto i*36), di2(((i+1)*36)-5 downto i*36),
di1(((i+1)*36)-1 downto i*36+32), di2(((i+1)*36)-1 downto i*36+32),
enable1, enable2, gnd, gnd, write1, write2);
-- vcc, vcc, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
do2(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : RAMB16_S18_S18 port map (
do1(((i+1)*18)-3 downto i*18), do2(((i+1)*18)-3 downto i*18),
do1(((i+1)*18)-1 downto i*18+16), do2(((i+1)*18)-1 downto i*18+16),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*18)-3 downto i*18), di2(((i+1)*18)-3 downto i*18),
di1(((i+1)*18)-1 downto i*18+16), di2(((i+1)*18)-1 downto i*18+16),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
do2(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : RAMB16_S9_S9 port map (
do1(((i+1)*9)-2 downto i*9), do2(((i+1)*9)-2 downto i*9),
do1(((i+1)*9)-1 downto i*9+8), do2(((i+1)*9)-1 downto i*9+8),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*9)-2 downto i*9), di2(((i+1)*9)-2 downto i*9),
di1(((i+1)*9)-1 downto i*9+8), di2(((i+1)*9)-1 downto i*9+8),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
do2(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB16_S4_S4 port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
do2(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB16_S2_S2 port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
do2(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB16_S1_S1 port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(13 downto 0), addr2(13 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto dbits) <= (others => '0');
do2(dbits+36 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
a_to_high : if abits > 14 generate
x : process
begin
assert false
report "Address depth larger than 14 not supported for unisim_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
entity unisim_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture behav of unisim_syncram_2p is
component unisim_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component generic_syncram_2p
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
signal write2, renable2 : std_ulogic;
signal datain2 : std_logic_vector((dbits-1) downto 0);
begin
-- nowf: if wrfst = 0 generate
write2 <= '0'; renable2 <= renable; datain2 <= (others => '0');
-- end generate;
-- wf : if wrfst = 1 generate
-- write2 <= '0' when (waddress /= raddress) else write;
-- renable2 <= renable or write2; datain2 <= datain;
-- end generate;
a0 : if abits <= 5 and GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
a6 : if abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0 generate
x0 : unisim_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, datain2, dataout, renable2, write2);
end generate;
end;
-- parametrisable sync ram generator using unisim block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end;
architecture behav of unisim_syncram64 is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S36_S36
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a8 : if abits <= 8 generate
r0 : RAMB16_S36_S36 port map (
dataout(63 downto 32), dataout(31 downto 0), open, open,
xa(8 downto 0), ya(8 downto 0), clk, clk,
datain(63 downto 32), datain(31 downto 0), gnd, gnd,
enable(1), enable(0), gnd(0), gnd(0), write(1), write(0));
end generate;
a9 : if abits > 8 generate
x1 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(63 downto 32), dataout(63 downto 32),
enable(1), write(1));
x2 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(31 downto 0), dataout(31 downto 0),
enable(0), write(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity unisim_syncram128 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0)
);
end;
architecture behav of unisim_syncram128 is
component unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
begin
x0 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(127 downto 64), dataout(127 downto 64),
enable(3 downto 2), write(3 downto 2));
x1 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(63 downto 0), dataout(63 downto 0),
enable(1 downto 0), write(1 downto 0));
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram128bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end;
architecture behav of unisim_syncram128bw is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S9_S9
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a11 : if abits <= 10 generate
x0 : for i in 0 to 7 generate
r0 : RAMB16_S9_S9 port map (
dataout(i*8+7+64 downto i*8+64), dataout(i*8+7 downto i*8), open, open,
xa(10 downto 0), ya(10 downto 0), clk, clk,
datain(i*8+7+64 downto i*8+64), datain(i*8+7 downto i*8), gnd(0 downto 0), gnd(0 downto 0),
enable(i+8), enable(i), gnd(0), gnd(0), write(i+8), write(i));
end generate;
end generate;
a12 : if abits > 10 generate
x0 : for i in 0 to 15 generate
x2 : unisim_syncram generic map ( abits, 8)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i));
end generate;
end generate;
end;
| gpl-2.0 | 82f84cea3dfe79ac250ae2ab8115e827 | 0.614809 | 3.020474 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/grpci1/pciahbmst.vhd | 1 | 5,709 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pciahbmst
-- File: pciahbmst.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Generic AHB master interface
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
entity pciahbmst is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in pci_ahb_dma_in_type;
dmao : out pci_ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture rtl of pciahbmst is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
start : std_ulogic;
retry : std_ulogic;
grant : std_ulogic;
active : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(ahbi, dmai, rst, r)
variable v : reg_type;
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(3 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(31 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(10 downto 0); -- next sequential address
variable hbusreq : std_ulogic; -- bus request
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable kblimit : std_logic; -- 1 kB limit indicator
begin
v := r; ready := '0'; mexc := '0'; retry := '0'; inc := (others => '0');
hprot := conv_std_logic_vector(chprot, 4); -- non-cached supervisor data
xhirq := (others => '0'); xhirq(hirq) := dmai.irq; kblimit := '0';
haddr := dmai.address; hbusreq := dmai.start; hwdata := dmai.wdata;
newaddr := dmai.address(10 downto 0);
if INCADDR > 0 then
inc(conv_integer(dmai.size)) := '1';
newaddr := haddr(10 downto 0) + inc;
if (newaddr(10) xor haddr(10)) = '1' then kblimit := '1'; end if;
end if;
-- hburst := HBURST_SINGLE;
if dmai.burst = '0' then hburst := HBURST_SINGLE;
else hburst := HBURST_INCR; end if;
if dmai.start = '1' then
-- hburst := HBURST_INCR;
if (r.active and dmai.burst and not r.retry) = '1' then
haddr(9 downto 0) := newaddr(9 downto 0);
if dmai.busy = '1' then htrans := HTRANS_BUSY;
elsif kblimit = '1' then htrans := HTRANS_IDLE;
else htrans := HTRANS_SEQ; end if;
else htrans := HTRANS_NONSEQ; end if;
else htrans := HTRANS_IDLE; end if;
if r.active = '1' then
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => ready := '1';
when HRESP_RETRY | HRESP_SPLIT=> retry := '1';
when others => ready := '1'; mexc := '1';
end case;
end if;
if ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT)) then
v.retry := not ahbi.hready;
else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
v.start := '0';
if ahbi.hready = '1' then
v.grant := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) or (htrans = HTRANS_BUSY) then
v.active := r.grant; v.start := r.grant;
else
v.active := '0';
end if;
end if;
if rst = '0' then v.retry := '0'; v.active := '0'; end if;
rin <= v;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= ahbdrivedata(dmai.wdata);
ahbo.hconfig <= hconfig;
ahbo.hlock <= '0';
ahbo.hwrite <= dmai.write;
ahbo.hsize <= '0' & dmai.size;
ahbo.hburst <= hburst;
ahbo.hprot <= hprot;
ahbo.hirq <= xhirq;
ahbo.hindex <= hindex;
dmao.start <= r.start;
dmao.active <= r.active;
dmao.ready <= ready;
dmao.mexc <= mexc;
dmao.retry <= retry;
dmao.haddr <= newaddr(9 downto 0);
dmao.rdata <= ahbreadword(ahbi.hrdata);
end process;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
| gpl-2.0 | fff8e0f0462cc5ff37c7b01f135e1eaa | 0.589771 | 3.574828 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/libfpu.vhd | 1 | 4,618 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libfpu
-- File: libfpu.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 FPU interface types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
package libfpu is
type fp_rf_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type fp_rf_out_type is record
data1 : std_logic_vector(31 downto 0); -- read data 1
data2 : std_logic_vector(31 downto 0); -- read data 2
end record;
type fpc_pipeline_control_type is record
pc : std_logic_vector(31 downto 0);
inst : std_logic_vector(31 downto 0);
cnt : std_logic_vector(1 downto 0);
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
end record;
type fpc_debug_in_type is record
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic; -- FSR access
addr : std_logic_vector(4 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type fpc_debug_out_type is record
data : std_logic_vector(31 downto 0);
end record;
constant fpc_debug_none : fpc_debug_out_type := (data => X"00000000"
);
type fpc_in_type is record
flush : std_ulogic; -- pipeline flush
exack : std_ulogic; -- FP exception acknowledge
a_rs1 : std_logic_vector(4 downto 0);
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector(31 downto 0); -- load data
dbg : fpc_debug_in_type; -- debug signals
end record;
type fpc_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- FP exception
cc : std_logic_vector(1 downto 0); -- FP condition codes
ccv : std_ulogic; -- FP condition codes valid
ldlock : std_logic; -- FP pipeline hold
holdn : std_ulogic;
dbg : fpc_debug_out_type; -- FP debug signals
end record;
constant fpc_out_none : fpc_out_type := (X"00000000", '0', "00", '1', '0', '1',
fpc_debug_none);
component grfpwxsh
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
end;
| gpl-2.0 | fb983d6518b8fb2c65686eac0c412faf | 0.542443 | 3.970765 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/tech/unisim/ise/unisim_VCOMP.vhd | 2 | 174,848 |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: vcomponents
-- File: vcomponents.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declartions of some XILINX primitives
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package vcomponents is
-- synopsys translate_off
-----------------------------------------
----------- FPGA Globals --------------
-----------------------------------------
signal GSR : std_logic := '0';
signal GTS : std_logic := '0';
signal GWE : std_logic := '0';
signal PLL_LOCKG : std_logic := 'H';
signal PROGB_GLBL : std_logic := '0';
signal CCLKO_GLBL : std_logic := 'H';
-----------------------------------------
----------- CPLD Globals --------------
-----------------------------------------
signal PRLD : std_logic := '0';
-----------------------------------------
----------- JTAG Globals --------------
-----------------------------------------
signal JTAG_TDO_GLBL : std_logic;
signal JTAG_TDI_GLBL : std_logic := '0';
signal JTAG_TMS_GLBL : std_logic := '0';
signal JTAG_TCK_GLBL : std_logic := '0';
signal JTAG_TRST_GLBL : std_logic := '0';
signal JTAG_CAPTURE_GLBL : std_logic := '0';
signal JTAG_RESET_GLBL : std_logic := '1';
signal JTAG_SHIFT_GLBL : std_logic := '1';
signal JTAG_UPDATE_GLBL : std_logic := '0';
signal JTAG_RUNTEST_GLBL : std_logic := '0';
signal JTAG_SEL1_GLBL : std_logic := '0';
signal JTAG_SEL2_GLBL : std_logic := '0';
signal JTAG_SEL3_GLBL : std_logic := '0';
signal JTAG_SEL4_GLBL : std_logic := '0';
signal JTAG_USER_TDO1_GLBL : std_logic := 'Z';
signal JTAG_USER_TDO2_GLBL : std_logic := 'Z';
signal JTAG_USER_TDO3_GLBL : std_logic := 'Z';
signal JTAG_USER_TDO4_GLBL : std_logic := 'Z';
-- synopsys translate_on
component ramb4_s16 port (
do : out std_logic_vector (15 downto 0);
addr : in std_logic_vector (7 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (15 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S8
port (do : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (8 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (7 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S4
port (do : out std_logic_vector (3 downto 0);
addr : in std_logic_vector (9 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (3 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S2
port (do : out std_logic_vector (1 downto 0);
addr : in std_logic_vector (10 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (1 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1
port (do : out std_logic_vector (0 downto 0);
addr : in std_logic_vector (11 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (0 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1_S1
port (
doa : out std_logic_vector (0 downto 0);
dob : out std_logic_vector (0 downto 0);
addra : in std_logic_vector (11 downto 0);
addrb : in std_logic_vector (11 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (0 downto 0);
dib : in std_logic_vector (0 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S2_S2
port (
doa : out std_logic_vector (1 downto 0);
dob : out std_logic_vector (1 downto 0);
addra : in std_logic_vector (10 downto 0);
addrb : in std_logic_vector (10 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (1 downto 0);
dib : in std_logic_vector (1 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S4_S4
port (
doa : out std_logic_vector (3 downto 0);
dob : out std_logic_vector (3 downto 0);
addra : in std_logic_vector (9 downto 0);
addrb : in std_logic_vector (9 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (3 downto 0);
dib : in std_logic_vector (3 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S8_S8
port (
doa : out std_logic_vector (7 downto 0);
dob : out std_logic_vector (7 downto 0);
addra : in std_logic_vector (8 downto 0);
addrb : in std_logic_vector (8 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (7 downto 0);
dib : in std_logic_vector (7 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S16_S16
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB16_S1
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
-- pragma translate_off
generic
(
INIT : bit_vector := X"000";
SRVAL : bit_vector := X"000";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
-- pragma translate_off
generic
(
INIT : bit_vector := X"00000";
SRVAL : bit_vector := X"00000";
write_mode : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
-- pragma translate_off
generic
(
INIT : bit_vector := X"000000000";
SRVAL : bit_vector := X"000000000";
WRITE_MODE : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4_S4
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000";
INIT_B : bit_vector := X"000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000";
SRVAL_B : bit_vector := X"000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"00000";
INIT_B : bit_vector := X"00000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"00000";
SRVAL_B : bit_vector := X"00000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component DCM_SP
generic (
TimingChecksOn : boolean := true;
InstancePath : string := "*";
Xon : boolean := true;
MsgOn : boolean := false;
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0; --non-simulatable
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE"; --non-simulatable
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080"; --non-simulatable
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false --non-simulatable
);
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK2X180 : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
CLKFX : out std_ulogic := '0';
CLKFX180 : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
STATUS : out std_logic_vector(7 downto 0) := "00000000";
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
DSSEN : in std_ulogic := '0';
PSCLK : in std_ulogic := '0';
PSEN : in std_ulogic := '0';
PSINCDEC : in std_ulogic := '0';
RST : in std_ulogic := '0'
);
end component;
----- component PLLE2_ADV -----
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component PLL_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_DESKEW_ADJUST : string := "NONE";
CLKFBOUT_MULT : integer := 1;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DESKEW_ADJUST : string := "NONE";
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DESKEW_ADJUST : string := "NONE";
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DESKEW_ADJUST : string := "NONE";
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DESKEW_ADJUST : string := "NONE";
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DESKEW_ADJUST : string := "NONE";
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DESKEW_ADJUST : string := "NONE";
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
CLK_FEEDBACK : string := "CLKFBOUT";
COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
DIVCLK_DIVIDE : integer := 1;
EN_REL : boolean := FALSE;
PLL_PMCD_MODE : boolean := FALSE;
REF_JITTER : real := 0.100;
RESET_ON_LOSS_OF_LOCK : boolean := FALSE;
RST_DEASSERT_CLK : string := "CLKIN1";
SIM_DEVICE : string := "VIRTEX5"
);
port (
CLKFBDCM : out std_ulogic := '0';
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
CLKOUTDCM0 : out std_ulogic := '0';
CLKOUTDCM1 : out std_ulogic := '0';
CLKOUTDCM2 : out std_ulogic := '0';
CLKOUTDCM3 : out std_ulogic := '0';
CLKOUTDCM4 : out std_ulogic := '0';
CLKOUTDCM5 : out std_ulogic := '0';
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(4 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
REL : in std_ulogic;
RST : in std_ulogic
);
end component;
component PLL_BASE
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 1;
CLKFBOUT_PHASE : real := 0.0;
CLKIN_PERIOD : real := 0.000;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
CLK_FEEDBACK : string := "CLKFBOUT";
COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER : real := 0.100;
RESET_ON_LOSS_OF_LOCK : boolean := FALSE
);
port (
CLKFBOUT : out std_ulogic;
CLKOUT0 : out std_ulogic;
CLKOUT1 : out std_ulogic;
CLKOUT2 : out std_ulogic;
CLKOUT3 : out std_ulogic;
CLKOUT4 : out std_ulogic;
CLKOUT5 : out std_ulogic;
LOCKED : out std_ulogic;
CLKFBIN : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic
);
end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGP port (O : out std_logic; I : in std_logic); end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
component IBUFG generic(
CAPACITANCE : string := "DONT_CARE";
IBUF_LOW_PWR : boolean := TRUE;
IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end component;
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
component IOBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IBUF_DELAY_VALUE : string := "0"; IBUF_LOW_PWR : boolean := TRUE;
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
component OBUFT generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I, T : in std_ulogic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component CLKDLLHF
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
RST : in std_ulogic := '0');
end component;
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
component IBUFDS
generic (
CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE;
IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT");
port (
O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IBUFDS_LVDS_25
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_25
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IOBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT");
port (
O : out std_ulogic;
IO : inout std_ulogic;
IOB : inout std_ulogic;
I : in std_ulogic;
T : in std_ulogic
);
end component;
component OBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT";
SLEW : string := "SLOW"
);
port(
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
component OBUFDS_LVDS_25
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic);
end component;
component OBUFTDS_LVDS_25
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic;
T : in std_ulogic);
end component;
component IBUFGDS is
generic( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IBUF_LOW_PWR : boolean := TRUE;
IOSTANDARD : string := "DEFAULT");
port (O : out std_logic; I, IB : in std_logic);
end component;
component IBUFDS_LVDS_33
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_33
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component OBUFDS_LVDS_33
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic);
end component;
component OBUFTDS_LVDS_33
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic;
T : in std_ulogic);
end component;
component FDCPE
generic ( INIT : bit := '0');
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic);
end component;
component IDDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ODDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC");
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component OFDDRRSE
port (
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDDRRSE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFIO
port ( O : out std_ulogic;
I : in std_ulogic);
end component;
component BUFR
generic ( BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "VIRTEX4");
port ( O : out std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
I : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component SYSMON
generic
(
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt"
);
port
(
ALM : out std_logic_vector(2 downto 0);
BUSY : out std_ulogic;
CHANNEL : out std_logic_vector(4 downto 0);
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic;
EOC : out std_ulogic;
EOS : out std_ulogic;
JTAGBUSY : out std_ulogic;
JTAGLOCKED : out std_ulogic;
JTAGMODIFIED : out std_ulogic;
OT : out std_ulogic;
CONVST : in std_ulogic;
CONVSTCLK : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
RESET : in std_ulogic;
VAUXN : in std_logic_vector(15 downto 0);
VAUXP : in std_logic_vector(15 downto 0);
VN : in std_ulogic;
VP : in std_ulogic
);
end component;
component FDRSE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDR
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic);
end component;
component FDRE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component FDRS
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic);
end component;
component MUXF5
port ( O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic);
end component;
component VCC
port ( P : out std_ulogic := '1');
end component;
component GND
port ( G : out std_ulogic := '0');
end component;
component INV
port
(
O : out std_ulogic;
I : in std_ulogic
);
end component;
component LUT2_L
generic
(
INIT : bit_vector := X"0"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component LUT4
generic
(
INIT : bit_vector := X"0000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end component;
component LUT3
generic
(
INIT : bit_vector := X"00"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
component LUT2
generic
(
INIT : bit_vector := X"0"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component FDC
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component LUT3_L
generic
(
INIT : bit_vector := X"00"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
component LUT1
generic
(
INIT : bit_vector := X"0"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic
);
end component;
component LUT4_L
generic
(
INIT : bit_vector := X"0000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end component;
component FDCE
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component FDC_1
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component FDP
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end component;
component FDS
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component LUT1_L
generic
(
INIT : bit_vector := X"0"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic
);
end component;
component MUXF6
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF5_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component MUXCY_L
port
(
LO : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component FDSE
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
component MULT_AND
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component SRL16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component ROM256X1
generic
(
INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
A7 : in std_ulogic
);
end component;
component FDPE
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end component;
component MULT18X18
port
(
P : out std_logic_vector (35 downto 0);
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0)
);
end component;
component MULT18X18S
port
(
P : out std_logic_vector (35 downto 0);
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0);
C : in std_ulogic;
CE : in std_ulogic;
R : in std_ulogic
);
end component;
component MUXF7
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component IODELAY
generic
(
DELAY_SRC : string := "I";
HIGH_PERFORMANCE_MODE : boolean := true;
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
REFCLK_FREQUENCY : real := 200.0;
SIGNAL_PATTERN : string := "DATA"
);
port
(
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component IODELAY2
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75
);
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component ISERDES
generic
(
BITSLIP_ENABLE : boolean := false;
DATA_RATE : string := "DDR";
DATA_WIDTH : integer := 4;
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
INIT_Q3 : bit := '0';
INIT_Q4 : bit := '0';
INTERFACE_TYPE : string := "MEMORY";
IOBDELAY : string := "NONE";
IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0;
NUM_CE : integer := 2;
SERDES_MODE : string := "MASTER";
SRVAL_Q1 : bit := '0';
SRVAL_Q2 : bit := '0';
SRVAL_Q3 : bit := '0';
SRVAL_Q4 : bit := '0'
);
port
(
O : out std_ulogic;
Q1 : out std_ulogic;
Q2 : out std_ulogic;
Q3 : out std_ulogic;
Q4 : out std_ulogic;
Q5 : out std_ulogic;
Q6 : out std_ulogic;
SHIFTOUT1 : out std_ulogic;
SHIFTOUT2 : out std_ulogic;
BITSLIP : in std_ulogic;
CE1 : in std_ulogic;
CE2 : in std_ulogic;
CLK : in std_ulogic;
CLKDIV : in std_ulogic;
D : in std_ulogic;
DLYCE : in std_ulogic;
DLYINC : in std_ulogic;
DLYRST : in std_ulogic;
OCLK : in std_ulogic;
REV : in std_ulogic;
SHIFTIN1 : in std_ulogic;
SHIFTIN2 : in std_ulogic;
SR : in std_ulogic
);
end component;
component RAM16X1S
generic
(
INIT : bit_vector(15 downto 0) := X"0000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAM16X1D
generic
(
INIT : bit_vector(15 downto 0) := X"0000"
);
port
(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component ROM32X1
generic
(
INIT : bit_vector := X"00000000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic
);
end component;
component DSP48
generic
(
AREG : integer := 1;
B_INPUT : string := "DIRECT";
BREG : integer := 1;
CARRYINREG : integer := 1;
CARRYINSELREG : integer := 1;
CREG : integer := 1;
LEGACY_MODE : string := "MULT18X18S";
MREG : integer := 1;
OPMODEREG : integer := 1;
PREG : integer := 1;
SUBTRACTREG : integer := 1
);
port
(
BCOUT : out std_logic_vector(17 downto 0);
P : out std_logic_vector(47 downto 0);
PCOUT : out std_logic_vector(47 downto 0);
A : in std_logic_vector(17 downto 0);
B : in std_logic_vector(17 downto 0);
BCIN : in std_logic_vector(17 downto 0);
C : in std_logic_vector(47 downto 0);
CARRYIN : in std_ulogic;
CARRYINSEL : in std_logic_vector(1 downto 0);
CEA : in std_ulogic;
CEB : in std_ulogic;
CEC : in std_ulogic;
CECARRYIN : in std_ulogic;
CECINSUB : in std_ulogic;
CECTRL : in std_ulogic;
CEM : in std_ulogic;
CEP : in std_ulogic;
CLK : in std_ulogic;
OPMODE : in std_logic_vector(6 downto 0);
PCIN : in std_logic_vector(47 downto 0);
RSTA : in std_ulogic;
RSTB : in std_ulogic;
RSTC : in std_ulogic;
RSTCARRYIN : in std_ulogic;
RSTCTRL : in std_ulogic;
RSTM : in std_ulogic;
RSTP : in std_ulogic;
SUBTRACT : in std_ulogic
);
end component;
component RAMB16
generic
(
DOA_REG : integer := 0;
DOB_REG : integer := 0;
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INVERT_CLK_DOA_REG : boolean := false;
INVERT_CLK_DOB_REG : boolean := false;
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port
(
CASCADEOUTA : out std_ulogic;
CASCADEOUTB : out std_ulogic;
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (14 downto 0);
ADDRB : in std_logic_vector (14 downto 0);
CASCADEINA : in std_ulogic;
CASCADEINB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector (3 downto 0);
WEB : in std_logic_vector (3 downto 0)
);
end component;
component MUXF8
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component RAM64X1D
generic ( INIT : bit_vector(63 downto 0) := X"0000000000000000");
port
(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
DPRA4 : in std_ulogic;
DPRA5 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component BUF
port
(
O : out std_ulogic;
I : in std_ulogic
);
end component;
component LUT5
generic
(
INIT : bit_vector := X"00000000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic
);
end component;
component LUT5_L
generic
(
INIT : bit_vector := X"00000000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic
);
end component;
component LUT6
generic
(
INIT : bit_vector := X"0000000000000000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end component;
component LUT6_L
generic
(
INIT : bit_vector := X"0000000000000000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end component;
component RAM128X1S
generic (
INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component SRLC16E
generic (
INIT : bit_vector := X"0000"
);
port (
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component LD_1
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic := '0';
D : in std_ulogic;
G : in std_ulogic
);
end component;
component RAM32X1D
generic (
INIT : bit_vector(31 downto 0) := X"00000000"
);
port (
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
DPRA4 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component FD_1
generic(
INIT : bit := '0'
);
port(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic
);
end component;
component XORCY_L
port(
LO : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component RAM32M
generic (
INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
);
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
DOC : out std_logic_vector (1 downto 0);
DOD : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector(4 downto 0);
ADDRB : in std_logic_vector(4 downto 0);
ADDRC : in std_logic_vector(4 downto 0);
ADDRD : in std_logic_vector(4 downto 0);
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
DIC : in std_logic_vector (1 downto 0);
DID : in std_logic_vector (1 downto 0);
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAM128X1D
generic
(
INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
);
port
(
DPO : out std_ulogic;
SPO : out std_ulogic;
A : in std_logic_vector(6 downto 0);
D : in std_ulogic;
DPRA : in std_logic_vector(6 downto 0);
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAM64M
generic (
INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
);
port (
DOA : out std_ulogic;
DOB : out std_ulogic;
DOC : out std_ulogic;
DOD : out std_ulogic;
ADDRA : in std_logic_vector(5 downto 0);
ADDRB : in std_logic_vector(5 downto 0);
ADDRC : in std_logic_vector(5 downto 0);
ADDRD : in std_logic_vector(5 downto 0);
DIA : in std_ulogic;
DIB : in std_ulogic;
DIC : in std_ulogic;
DID : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component XOR2
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
component BSCAN_SPARTAN6
generic (
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
component BSCAN_VIRTEX6
generic (
DISABLE_JTAG : boolean := FALSE;
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
component SRL16
generic ( INIT : bit_vector := X"0000");
port (
Q : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC);
end component;
component LUT6_2
generic(
INIT : bit_vector := X"0000000000000000"
);
port(
O5 : out std_ulogic;
O6 : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end component;
component DSP48E
generic(
SIM_MODE : string := "SAFE";
ACASCREG : integer := 1;
ALUMODEREG : integer := 1;
AREG : integer := 1;
AUTORESET_PATTERN_DETECT : boolean := FALSE;
AUTORESET_PATTERN_DETECT_OPTINV : string := "MATCH";
A_INPUT : string := "DIRECT";
BCASCREG : integer := 1;
BREG : integer := 1;
B_INPUT : string := "DIRECT";
CARRYINREG : integer := 1;
CARRYINSELREG : integer := 1;
CREG : integer := 1;
MASK : bit_vector := X"3FFFFFFFFFFF";
MREG : integer := 1;
MULTCARRYINREG : integer := 1;
OPMODEREG : integer := 1;
PATTERN : bit_vector := X"000000000000";
PREG : integer := 1;
SEL_MASK : string := "MASK";
SEL_PATTERN : string := "PATTERN";
SEL_ROUNDING_MASK : string := "SEL_MASK";
USE_MULT : string := "MULT_S";
USE_PATTERN_DETECT : string := "NO_PATDET";
USE_SIMD : string := "ONE48"
);
port(
ACOUT : out std_logic_vector(29 downto 0);
BCOUT : out std_logic_vector(17 downto 0);
CARRYCASCOUT : out std_ulogic;
CARRYOUT : out std_logic_vector(3 downto 0);
MULTSIGNOUT : out std_ulogic;
OVERFLOW : out std_ulogic;
P : out std_logic_vector(47 downto 0);
PATTERNBDETECT : out std_ulogic;
PATTERNDETECT : out std_ulogic;
PCOUT : out std_logic_vector(47 downto 0);
UNDERFLOW : out std_ulogic;
A : in std_logic_vector(29 downto 0);
ACIN : in std_logic_vector(29 downto 0);
ALUMODE : in std_logic_vector(3 downto 0);
B : in std_logic_vector(17 downto 0);
BCIN : in std_logic_vector(17 downto 0);
C : in std_logic_vector(47 downto 0);
CARRYCASCIN : in std_ulogic;
CARRYIN : in std_ulogic;
CARRYINSEL : in std_logic_vector(2 downto 0);
CEA1 : in std_ulogic;
CEA2 : in std_ulogic;
CEALUMODE : in std_ulogic;
CEB1 : in std_ulogic;
CEB2 : in std_ulogic;
CEC : in std_ulogic;
CECARRYIN : in std_ulogic;
CECTRL : in std_ulogic;
CEM : in std_ulogic;
CEMULTCARRYIN : in std_ulogic;
CEP : in std_ulogic;
CLK : in std_ulogic;
MULTSIGNIN : in std_ulogic;
OPMODE : in std_logic_vector(6 downto 0);
PCIN : in std_logic_vector(47 downto 0);
RSTA : in std_ulogic;
RSTALLCARRYIN : in std_ulogic;
RSTALUMODE : in std_ulogic;
RSTB : in std_ulogic;
RSTC : in std_ulogic;
RSTCTRL : in std_ulogic;
RSTM : in std_ulogic;
RSTP : in std_ulogic
);
end component;
component RAMB18
generic (
DOA_REG : integer := 0;
DOB_REG : integer := 0;
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"00000";
INIT_B : bit_vector := X"00000";
INIT_FILE : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SIM_MODE : string := "SAFE";
SRVAL_A : bit_vector := X"00000";
SRVAL_B : bit_vector := X"00000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port (
DOA : out std_logic_vector(15 downto 0);
DOB : out std_logic_vector(15 downto 0);
DOPA : out std_logic_vector(1 downto 0);
DOPB : out std_logic_vector(1 downto 0);
ADDRA : in std_logic_vector(13 downto 0);
ADDRB : in std_logic_vector(13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(15 downto 0);
DIB : in std_logic_vector(15 downto 0);
DIPA : in std_logic_vector(1 downto 0);
DIPB : in std_logic_vector(1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector(1 downto 0);
WEB : in std_logic_vector(1 downto 0)
);
end component;
component RAMB36
generic (
DOA_REG : integer := 0;
DOB_REG : integer := 0;
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
INIT_FILE : string := "NONE";
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SIM_MODE : string := "SAFE";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port (
CASCADEOUTLATA : out std_ulogic;
CASCADEOUTLATB : out std_ulogic;
CASCADEOUTREGA : out std_ulogic;
CASCADEOUTREGB : out std_ulogic;
DOA : out std_logic_vector(31 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ADDRA : in std_logic_vector(15 downto 0);
ADDRB : in std_logic_vector(15 downto 0);
CASCADEINLATA : in std_ulogic;
CASCADEINLATB : in std_ulogic;
CASCADEINREGA : in std_ulogic;
CASCADEINREGB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(31 downto 0);
DIB : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DIPB : in std_logic_vector(3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector(3 downto 0);
WEB : in std_logic_vector(3 downto 0)
);
end component;
component BUFGCE
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC
);
end component;
component RAM64X1S
generic (
INIT : bit_vector(63 downto 0) := X"0000000000000000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component IBUFDS_GTXE1
generic (
CLKCM_CFG : boolean := TRUE;
CLKRCV_TRST : boolean := TRUE;
REFCLKOUT_DLY : bit_vector := b"0000000000"
);
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
----- component MMCM_ADV -----
component MMCM_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT_F : real := 5.000;
CLKFBOUT_PHASE : real := 0.000;
CLKFBOUT_USE_FINE_PS : boolean := FALSE;
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DIVIDE_F : real := 1.000;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
CLKOUT0_USE_FINE_PS : boolean := FALSE;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
CLKOUT1_USE_FINE_PS : boolean := FALSE;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
CLKOUT2_USE_FINE_PS : boolean := FALSE;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
CLKOUT3_USE_FINE_PS : boolean := FALSE;
CLKOUT4_CASCADE : boolean := FALSE;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
CLKOUT4_USE_FINE_PS : boolean := FALSE;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
CLKOUT5_USE_FINE_PS : boolean := FALSE;
CLKOUT6_DIVIDE : integer := 1;
CLKOUT6_DUTY_CYCLE : real := 0.500;
CLKOUT6_PHASE : real := 0.000;
CLKOUT6_USE_FINE_PS : boolean := FALSE;
CLOCK_HOLD : boolean := FALSE;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : boolean := FALSE
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKFBOUTB : out std_ulogic := '0';
CLKFBSTOPPED : out std_ulogic := '0';
CLKINSTOPPED : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT0B : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT1B : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT2B : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT3B : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
CLKOUT6 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component OSERDESE1
generic (
DATA_RATE_OQ : string := "DDR";
DATA_RATE_TQ : string := "DDR";
DATA_WIDTH : integer := 4;
DDR3_DATA : integer := 1;
INIT_OQ : bit := '0';
INIT_TQ : bit := '0';
INTERFACE_TYPE : string := "DEFAULT";
ODELAY_USED : integer := 0;
SERDES_MODE : string := "MASTER";
SRVAL_OQ : bit := '0';
SRVAL_TQ : bit := '0';
TRISTATE_WIDTH : integer := 4
);
port (
OCBEXTEND : out std_ulogic;
OFB : out std_ulogic;
OQ : out std_ulogic;
SHIFTOUT1 : out std_ulogic;
SHIFTOUT2 : out std_ulogic;
TFB : out std_ulogic;
TQ : out std_ulogic;
CLK : in std_ulogic;
CLKDIV : in std_ulogic;
CLKPERF : in std_ulogic;
CLKPERFDELAY : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
D3 : in std_ulogic;
D4 : in std_ulogic;
D5 : in std_ulogic;
D6 : in std_ulogic;
OCE : in std_ulogic;
ODV : in std_ulogic;
RST : in std_ulogic;
SHIFTIN1 : in std_ulogic;
SHIFTIN2 : in std_ulogic;
T1 : in std_ulogic;
T2 : in std_ulogic;
T3 : in std_ulogic;
T4 : in std_ulogic;
TCE : in std_ulogic;
WC : in std_ulogic
);
end component;
component IODELAYE1
generic (
CINVCTRL_SEL : boolean := FALSE;
DELAY_SRC : string := "I";
HIGH_PERFORMANCE_MODE : boolean := FALSE;
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_TYPE : string := "FIXED";
ODELAY_VALUE : integer := 0;
REFCLK_FREQUENCY : real := 200.0;
SIGNAL_PATTERN : string := "DATA"
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CLKIN : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component ISERDESE1
generic (
DATA_RATE : string := "DDR";
DATA_WIDTH : integer := 4;
DYN_CLKDIV_INV_EN : boolean := FALSE;
DYN_CLK_INV_EN : boolean := FALSE;
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
INIT_Q3 : bit := '0';
INIT_Q4 : bit := '0';
INTERFACE_TYPE : string := "MEMORY";
IOBDELAY : string := "NONE";
NUM_CE : integer := 2;
OFB_USED : boolean := FALSE;
SERDES_MODE : string := "MASTER";
SRVAL_Q1 : bit := '0';
SRVAL_Q2 : bit := '0';
SRVAL_Q3 : bit := '0';
SRVAL_Q4 : bit := '0'
);
port (
O : out std_ulogic;
Q1 : out std_ulogic;
Q2 : out std_ulogic;
Q3 : out std_ulogic;
Q4 : out std_ulogic;
Q5 : out std_ulogic;
Q6 : out std_ulogic;
SHIFTOUT1 : out std_ulogic;
SHIFTOUT2 : out std_ulogic;
BITSLIP : in std_ulogic;
CE1 : in std_ulogic;
CE2 : in std_ulogic;
CLK : in std_ulogic;
CLKB : in std_ulogic;
CLKDIV : in std_ulogic;
D : in std_ulogic;
DDLY : in std_ulogic;
DYNCLKDIVSEL : in std_ulogic;
DYNCLKSEL : in std_ulogic;
OCLK : in std_ulogic;
OFB : in std_ulogic;
RST : in std_ulogic;
SHIFTIN1 : in std_ulogic;
SHIFTIN2 : in std_ulogic
);
end component;
component IOBUFDS_DIFF_OUT
generic (
DIFF_TERM : boolean := FALSE;
IBUF_LOW_PWR : boolean := TRUE;
IOSTANDARD : string := "DEFAULT"
);
port (
O : out std_ulogic;
OB : out std_ulogic;
IO : inout std_ulogic;
IOB : inout std_ulogic;
I : in std_ulogic;
TM : in std_ulogic;
TS : in std_ulogic
);
end component;
component SRLC32E
generic (
INIT : bit_vector := X"00000000"
);
port (
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
end;
| gpl-2.0 | 33c98201780d6fbaaaee997c854aa652 | 0.733431 | 4.592682 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-sp605/ahb2mig_sp605.vhd | 1 | 16,873 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_sp605
-- File: ahb2mig_sp605.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus, while
-- a second read-only port can be enabled for a VGA frame buffer.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_sp605 is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
vgamst : integer := 0;
vgaburst : integer := 0
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbmi : out ahb_mst_in_type;
ahbmo : in ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
clk_mem_p : in std_logic;
clk_mem_n : in std_logic;
clk_125 : out std_logic;
clk_50 : out std_logic
);
end ;
architecture rtl of ahb2mig_sp605 is
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
type reg2_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
end record;
type p2_if_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_bl : std_logic_vector(5 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
rd_en : std_logic;
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
end record;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
signal i : mcb_type;
signal p2 : p2_if_type;
begin
comb: process( rst_n_syn, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r <= rin;
end if;
end process;
port2 : if vgamst /= 0 generate
comb2: process( rst_n_syn, r2, ahbmo, p2 )
variable v2 : reg2_type;
variable cmd_en : std_logic;
variable rd_en : std_logic;
begin
v2 := r2; cmd_en := '0'; rd_en := '0';
case r2.bstate is
when idle =>
if ahbmo.htrans(1) = '1' then
v2.bstate := start;
v2.hready := '0';
v2.haddr := ahbmo.haddr;
else v2.hready := '1'; end if;
v2.cmd_bl := (others => '0');
when start =>
if p2.cmd_full = '0' then
cmd_en := '1';
v2.cmd_bl := conv_std_logic_vector(vgaburst-1, 6);
v2.bstate := read1;
end if;
when read1 =>
v2.hready := '0';
if (r2.rd_cnt = "000000") then -- flush data from previous line
if (p2.rd_empty = '0') or ((r2.hready = '1') and (ahbmo.htrans /= "11")) then
v2.hrdata(31 downto 0) := p2.rd_data(15 downto 0) & p2.rd_data(31 downto 16);
v2.hready := '1';
if (p2.rd_empty = '0') then v2.cmd_bl := r2.cmd_bl - 1; rd_en := '1'; end if;
if (r2.cmd_bl = "000000") or (ahbmo.htrans /= "11") then
if (ahbmo.htrans = "10") and (r2.hready = '1') then
v2.bstate := start; v2.hready := '0';
v2.cmd_bl := (others => '0');
else
v2.bstate := idle;
end if;
if (p2.rd_empty = '1') then v2.rd_cnt := r2.cmd_bl + 1;
else v2.rd_cnt := r2.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
if (r2.rd_cnt /= "000000") and (p2.rd_empty = '0') then
rd_en := '1'; v2.rd_cnt := r2.rd_cnt - 1;
end if;
v2.haddr(1 downto 0) := "00";
if rst_n_syn = '0' then
v2.rd_cnt := "000000"; v2.bstate := idle; v2.hready := '1';
end if;
r2in <= v2;
p2.rd_en <= rd_en;
p2.cmd_bl <= v2.cmd_bl;
p2.cmd_en <= cmd_en;
p2.cmd_instr <= "001";
end process;
ahbmi.hrdata <= r2.hrdata;
ahbmi.hresp <= "00";
ahbmi.hgrant <= (others => '1');
ahbmi.hready <= r2.hready;
ahbmi.hirq <= (others => '0');
ahbmi.testen <= '0';
ahbmi.testrst <= '0';
ahbmi.scanen <= '0';
ahbmi.testoen <= '0';
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
r2 <= r2in;
end if;
end process;
end generate;
noport2 : if vgamst = 0 generate
p2.cmd_en <= '0';
p2.rd_en <= '0';
end generate;
MCB_inst : entity work.mig_38 generic map(
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
-- C3_MEMCLK_PERIOD => 5000,
C3_RST_ACT_LOW => 1,
C3_INPUT_CLK_TYPE => "DIFFERENTIAL",
C3_CALIB_SOFT_IP => "TRUE",
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_NUM_DQ_PINS => 16,
C3_MEM_ADDR_WIDTH => 13,
C3_MEM_BANKADDR_WIDTH => 3
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
c3_sys_clk_p => clk_mem_p,
c3_sys_clk_n => clk_mem_n,
c3_sys_rst_i => rst_n_async,
c3_calib_done => calib_done,
c3_clk0 => open,
c3_rst0 => open,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_p0_cmd_clk => clk_amba,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error,
c3_p2_cmd_clk => clk_amba,
c3_p2_cmd_en => p2.cmd_en,
c3_p2_cmd_instr => p2.cmd_instr,
c3_p2_cmd_bl => p2.cmd_bl,
c3_p2_cmd_byte_addr => r2.haddr(29 downto 0),
c3_p2_cmd_empty => p2.cmd_empty,
c3_p2_cmd_full => p2.cmd_full,
c3_p2_rd_clk => clk_amba,
c3_p2_rd_en => p2.rd_en,
c3_p2_rd_data => p2.rd_data,
c3_p2_rd_full => p2.rd_full,
c3_p2_rd_empty => p2.rd_empty,
c3_p2_rd_count => p2.rd_count,
c3_p2_rd_overflow => p2.rd_overflow,
c3_p2_rd_error => p2.rd_error,
clk_125 => clk_125,
clk_50 => clk_50
);
end;
| gpl-2.0 | 75efb8c949abe0f2e8379a1bdffc932e | 0.518699 | 2.903631 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/background/simulation/bmg_stim_gen.vhd | 1 | 12,588 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (11 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0):= hex_to_std_logic_vector("0",12);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (76799 downto 0) of std_logic_vector(11 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"background.mif",
DEFAULT_DATA,
12,
76800);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>76800 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(16 DOWNTO 0) <= READ_ADDR(16 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 76800 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit | 7bba72c1c5e9b669fee2df6cf298ba23 | 0.548062 | 3.688251 | false | false | false | false |
lynnieana/autosub_new_task_timingDemo | timingDemo/static/timingDemo_example.vhdl | 1 | 443 | ENTITY top IS END top;
ARCHITECTURE example OF top IS
SIGNAL w,x,y,z : integer := 0; -- initialised to 0 (zero)
BEGIN
p1 : PROCESS(z)
VARIABLE a : integer := 0; -- initialised to 0 (zero)
BEGIN
a := a + 100;
w <= w + 80;
x <= a + w AFTER 40 ns;
y <= a - w AFTER 60 ns;
END PROCESS;
p2: PROCESS
BEGIN
z <= (x + y) AFTER 70 ns;
--z <= x AFTER 70 ns;
WAIT ON x,y;
END PROCESS;
END example;
| gpl-2.0 | c3598324ecbcac753aa5e083e0554823 | 0.546275 | 3.055172 | false | false | false | false |
IamVNIE/Hardware-Security | DES CryptoCore/src/pc2.vhd | 2 | 969 | library ieee;
use ieee.std_logic_1164.all;
entity pc2 is port
(
c,d : in std_logic_vector(1 TO 28);
k : out std_logic_vector(1 TO 48)
);
end pc2;
architecture behavior of pc2 is
signal YY : std_logic_vector(1 to 56);
begin
YY(1 to 28)<=c; YY(29 to 56)<=d;
k(1)<=YY(14); k(2)<=YY(17); k(3)<=YY(11); k(4)<=YY(24); k(5)<=YY(1); k(6)<=YY(5);
k(7)<=YY(3); k(8)<=YY(28);k(9)<=YY(15);k(10)<=YY(6);k(11)<=YY(21); k(12)<=YY(10);
k(13)<=YY(23); k(14)<=YY(19); k(15)<=YY(12); k(16)<=YY(4); k(17)<=YY(26); k(18)<=YY(8);
k(19)<=YY(16); k(20)<=YY(7);k(21)<=YY(27); k(22)<=YY(20); k(23)<=YY(13); k(24)<=YY(2);
k(25)<=YY(41); k(26)<=YY(52); k(27)<=YY(31); k(28)<=YY(37); k(29)<=YY(47); k(30)<=YY(55);
k(31)<=YY(30); k(32)<=YY(40); k(33)<=YY(51); k(34)<=YY(45); k(35)<=YY(33); k(36)<=YY(48);
k(37)<=YY(44); k(38)<=YY(49); k(39)<=YY(39); k(40)<=YY(56); k(41)<=YY(34); k(42)<=YY(53);
k(43)<=YY(46); k(44)<=YY(42); k(45)<=YY(50); k(46)<=YY(36); k(47)<=YY(29); k(48)<=YY(32);
end behavior;
| mit | 587117f06c2de497bbcaeb872b6e4d3b | 0.522188 | 1.934132 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_dmask_cols_V.vhd | 2 | 4,564 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_dmask_cols_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_dmask_cols_V_shiftReg;
architecture rtl of FIFO_image_filter_dmask_cols_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_dmask_cols_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_dmask_cols_V is
component FIFO_image_filter_dmask_cols_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_dmask_cols_V_shiftReg : FIFO_image_filter_dmask_cols_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | 2658cf519d56851241bc6b5853d06075 | 0.536372 | 3.505376 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-xc3s-1500/leon3mp.vhd | 1 | 38,591 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.grusb.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
clk3 : in std_ulogic; -- 25 MHz ethernet clock
pllref : in std_ulogic;
errorn : out std_ulogic;
wdogn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
bexcn : in std_ulogic; -- DSU rx data
brdyn : in std_ulogic; -- DSU rx data
romsn : out std_logic_vector (1 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 rx data
rtsn1 : out std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART1 rx data
rtsn2 : out std_ulogic; -- UART1 rx data
pio : inout std_logic_vector(17 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_ulogic;
usb_d : inout std_logic_vector(15 downto 0);
usb_linestate : in std_logic_vector(1 downto 0);
usb_opmode : out std_logic_vector(1 downto 0);
usb_reset : out std_ulogic;
usb_rxactive : in std_ulogic;
usb_rxerror : in std_ulogic;
usb_rxvalid : in std_ulogic;
usb_suspend : out std_ulogic;
usb_termsel : out std_ulogic;
usb_txready : in std_ulogic;
usb_txvalid : out std_ulogic;
usb_validh : inout std_ulogic;
usb_xcvrsel : out std_ulogic;
usb_vbus : in std_ulogic
);
end;
architecture rtl of leon3mp is
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
CFG_GRUSBDC;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, rst, ndsuact, wdogl : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_GRUSBDC;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_clkl : std_ulogic;
signal spw_clkln : std_ulogic;
signal stati : ahbstat_in_type;
signal uclk : std_ulogic;
signal usbi : grusb_in_type;
signal usbo : grusb_out_type;
constant SPW_LOOP_BACK : integer := 0;
signal dac_clk, video_clk, clk50 : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk50 : signal is true;
attribute syn_preserve of clk50 : signal is true;
attribute keep of clk50 : signal is true;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
ethclk_pad : inpad generic map (tech => padtech) port map(clk3, ethclk);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
rxd2_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
txd2_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
cts2_pad : inpad generic map (tech => padtech) port map (ctsn2, u2i.ctsn);
rts2_pad : outpad generic map (tech => padtech) port map (rtsn2, u2o.rtsn);
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate
apbo(9) <= apb_none; rtsn2 <= '0';
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
wden : if CFG_GPT_WDOGEN /= 0 generate
wdogl <= gpto.wdogn or not rstn;
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
end generate;
wddis : if CFG_GPT_WDOGEN = 0 generate
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc(0));
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, video_clk);
video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 20000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
vgaclk0 : entity work.vga_clkgen
port map (rstn, clk_sel, ethclk, clkm, clk50, video_clk);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
video_clk <= not clkm;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, video_clk);
end generate;
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
pio_pads : for i in 1 to 2 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
p1 : if (CFG_CAN = 0) generate
pio_pads : for i in 4 to 5 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
pio_pad0 : iopad generic map (tech => padtech)
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
pio_pad1 : iopad generic map (tech => padtech)
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
pio_pads : for i in 6 to 17 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 13, paddr => 13, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Multi-core CAN ---------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
can_tx_pad1 : iopad generic map (tech => padtech)
port map (pio(5), can_ltx(0), gnd(0), gpioi.din(5));
can_rx_pad1 : iopad generic map (tech => padtech)
port map (pio(4), gnd(0), vcc(0), can_lrx(0));
canpas : if CFG_CAN_NUM = 2 generate
can_tx_pad2 : iopad generic map (tech => padtech)
port map (pio(2), can_ltx(1), gnd(0), gpioi.din(2));
can_rx_pad2 : iopad generic map (tech => padtech)
port map (pio(1), gnd(0), vcc(0), can_lrx(1));
end generate;
end generate;
-- standby controlled by pio(3) and pio(0)
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
core0: if CFG_SPW_GRSPW = 1 generate
spw_clkl <= clkm;
spw_rxclkn <= not spw_rxtxclk;
end generate;
core1 : if CFG_SPW_GRSPW = 2 generate
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen_spw_rx : clkgen -- clock generator
generic map (clktech, 12, 2, 0,
1, 0, 0, 0, 25000)
port map (ethclk, ethclk, spw_clkl, spw_clkln, open, open, open, cgi2, cgo2, open, open);
spw_rxclkn <= spw_clkln;
end generate;
spw_rxtxclk <= spw_clkl;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j*2+1 downto j*2),
dov => spwi(i).dv(j*2+1 downto j*2),
dconnect => spwi(i).dconnect(j*2+1 downto j*2),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dv(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j),
ndo => spwi(i).nd(j*5+4 downto j*5),
dconnect => spwi(i).dconnect(j*2+1 downto j*2));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(1) <= '0'; -- For second port
spwi(i).d(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
end generate spw1_input;
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+i,
sysfreq => CPU_FREQ, usegen => 1,
pindex => 10+i, paddr => 10+i, pirq => 10+i,
nsync => 1, rmap => CFG_SPW_RMAP, rxunaligned => CFG_SPW_RXUNAL,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 2, dmachan => CFG_SPW_DMACHAN,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, ports => CFG_SPW_PORTS,
spwcore => CFG_SPW_GRSPW, netlist => CFG_SPW_NETLIST,
rxtx_sameclk => CFG_SPW_RTSAME, input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT)
port map(rstn, clkm, spw_rxclk(i*CFG_SPW_PORTS), spw_rxclk(i*CFG_SPW_PORTS+1),
spw_rxtxclk, spw_rxtxclk, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8) when CFG_SPW_GRSPW = 1
else conv_std_logic_vector((25*12/20)-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
swportloop1: for j in 0 to CFG_SPW_PORTS-1 generate
spwlb0 : if SPW_LOOP_BACK = 1 generate
dtmp(CFG_SPW_PORTS*i+j) <= spwo(i).d(j);
stmp(CFG_SPW_PORTS*i+j) <= spwo(i).s(j);
end generate;
nospwlb0 : if SPW_LOOP_BACK = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(CFG_SPW_PORTS*i+j), spw_rxdn(CFG_SPW_PORTS*i+j),
dtmp(CFG_SPW_PORTS*i+j));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(CFG_SPW_PORTS*i+j), spw_rxsn(CFG_SPW_PORTS*i+j),
stmp(CFG_SPW_PORTS*i+j));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(CFG_SPW_PORTS*i+j), spw_txdn(CFG_SPW_PORTS*i+j),
spwo(i).d(j), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(CFG_SPW_PORTS*i+j), spw_txsn(CFG_SPW_PORTS*i+j),
spwo(i).s(j), gnd(0));
end generate;
end generate;
end generate;
end generate;
-------------------------------------------------------------------------------
--- USB -----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that the GRUSBDC and GRUSB_DCL can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
usbo.oen <= '1'; usbo.reset <= '1';
end generate;
usb_clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (usb_clkout, uclk);
usb_d_pad: iopadv generic map(tech => padtech, width => 16, slew => 1)
port map (usb_d, usbo.dataout, usbo.oen, usbi.datain);
usb_txready_pad : inpad generic map (tech => padtech)
port map (usb_txready,usbi.txready);
usb_rxvalid_pad : inpad generic map (tech => padtech)
port map (usb_rxvalid,usbi.rxvalid);
usb_rxerror_pad : inpad generic map (tech => padtech)
port map (usb_rxerror,usbi.rxerror);
usb_rxactive_pad : inpad generic map (tech => padtech)
port map (usb_rxactive,usbi.rxactive);
usb_linestate_pad : inpadv generic map (tech => padtech, width => 2)
port map (usb_linestate,usbi.linestate);
usb_vbus_pad : inpad generic map (tech => padtech)
port map (usb_vbus, usbi.vbusvalid);
usb_reset_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_reset,usbo.reset);
usb_suspend_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_suspend,usbo.suspendm);
usb_termsel_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_termsel,usbo.termselect);
usb_xcvrsel_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_xcvrsel,usbo.xcvrselect(0));
usb_txvalid_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_txvalid,usbo.txvalid);
usb_opmode_pad : outpadv generic map (tech =>padtech ,width =>2, slew =>1)
port map (usb_opmode,usbo.opmode);
usb_validh_pad:iopad generic map(tech => padtech, slew => 1)
port map (usb_validh, usbo.txvalidh, usbo.oen, usbi.rxvalidh);
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 5, hirq => 7, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
aiface => CFG_GRUSBDC_AIFACE, uiface => 0, dwidth => CFG_GRUSBDC_DW,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech)
port map(
uclk => uclk,
usbi => usbi,
usbo => usbo,
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN),
ahbsi => ahbsi,
ahbso => ahbso(5)
);
end generate usbdc0;
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
memtech => memtech, uiface => 0, dwidth => CFG_GRUSB_DCL_DW)
port map (
uclk, usbi, usbo, clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+
CFG_SPW_NUM*CFG_SPW_EN));
end generate usb_dcl0;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-XC3S-1500 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | e1069e7b191c6e4bac1ad4fff66538f8 | 0.556995 | 3.493347 | false | false | false | false |
Luisda199824/ProcesadorMonociclo | Tb_Procesador2.vhd | 1 | 1,066 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Tb_Procesador2 IS
END Tb_Procesador2;
ARCHITECTURE behavior OF Tb_Procesador2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT unionModulos
PORT(
clk : IN std_logic;
rst : IN std_logic;
salida : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal salida : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: unionModulos PORT MAP (
clk => clk,
rst => rst,
salida => salida
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 10 ns;
rst <= '0';
wait;
end process;
END;
| mit | ada6b5408e89af1fa4c97ead102f5ea4 | 0.585366 | 3.601351 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/chips/rtl_lcd1602.vhd | 1 | 6,446 | -------------------------------------------------------------------------------
--
-- Title : rtl_lcd1602
-- Author : Alexander Kapitanov
-- Company : Instrumental Systems
-- E-mail : [email protected]
--
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : Controller for LCD Display LCD1602
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rtl_lcd1602 is
generic (
TD : in time; --! simulation time;
DIV_SCL : in integer --! clock division for SCL: clk50m/DIV_SCL
);
port(
-- global ports
clk50m : in std_logic; --! system frequency (50 MHz)
rstn : in std_logic; --! '0' - negative reset
-- main interface
start : in std_logic; --! start
data_ena : in std_logic; --! data enable (S)
data_int : in std_logic_vector(7 downto 0); --! data Tx
data_sel : in std_logic; --! select: '0' - data, '1' - command
data_rw : in std_logic; --! data write: write - '0', read - '1'
lcd_ready : out std_logic; --! ready for data
lcd_init : out std_logic; --! lcd initialization complete
-- lcd1602 interface
lcd_dt : out std_logic_vector(7 downto 0); --! lcd data
lcd_en : out std_logic; --! lcd clock enable
lcd_rw : out std_logic; --! lcd r/w: write - '0', read - '1'
lcd_rs : out std_logic --! lcd set: command - '0', data - '1'
);
end rtl_lcd1602;
architecture rtl_lcd1602 of rtl_lcd1602 is
signal clk_r : std_logic;
--signal clk_f : std_logic;
signal clk_z : std_logic;
signal clk_low : std_logic;
signal cnt_div : integer range 0 to DIV_SCL:=0;
type fsm_stage is (RDY_START, INIT, WAITING, DATA, DATA_WAIT, COM, COM_WAIT);
signal STM_OP : fsm_stage;
signal busy : std_logic;
signal en : std_logic;
signal rw : std_logic;
signal rs : std_logic;
signal dt : std_logic_vector(7 downto 0);
signal lcd_cnt : std_logic_vector(2 downto 0);
signal lcd_initr : std_logic;
--signal clk_rise : std_logic;
signal clk_en : std_logic;
begin
-- clk_div generator:
pr_cnt_div: process(clk50m, rstn) is
begin
if (rstn = '0') then
cnt_div <= 0;
clk_low <= '0';
elsif (rising_edge(clk50m)) then
if (cnt_div = DIV_SCL) then
cnt_div <= 0 after td;
clk_low <= not clk_low after td;
else
cnt_div <= cnt_div + 1 after td;
end if;
end if;
end process;
-- clk rising/falling
clk_z <= clk_low after td when rising_edge(clk50m);
clk_r <= (not clk_z) and clk_low after td when rising_edge(clk50m);
--clk_f <= (not clk_low) and clk_z after td when rising_edge(clk50m);
-- lcd_output data
--lcd_initr <= '0' when (rstn = '0') else lcd_cnt(2);
lcd_init <= lcd_initr after td when rising_edge(clk50m);
lcd_ready <= busy after td when rising_edge(clk50m);
lcd_dt <= dt after td when rising_edge(clk50m);
lcd_en <= en after td when rising_edge(clk50m);
lcd_rw <= rw after td when rising_edge(clk50m);
lcd_rs <= rs after td when rising_edge(clk50m);
pr_en_clk: process(clk50m, rstn) is
begin
if (rstn = '0') then
en <= '0';
elsif (rising_edge(clk50m)) then
if (clk_en = '1') then
if (clk_r = '1') then
en <= not en after td;
end if;
else
en <= '0' after td;
end if;
end if;
end process;
--clk_rise <= (clk_f and (not en)) after td when rising_edge(clk50m);
pr_fsm_operation: process(clk50m, rstn) is
variable cnt1: std_logic_vector(4 downto 0):="00000";
begin
if (rstn = '0') then
busy <= '0';
rs <= '0';
rw <= '0';
dt <= x"00";
clk_en <= '0';
lcd_initr <= '0';
lcd_cnt <= "000";
STM_OP <= RDY_START;
elsif (rising_edge(clk50m)) then
case STM_OP is
when RDY_START =>
cnt1 := "11111";
lcd_initr <= '0' after td;
rs <= '0' after td;
rw <= '0' after td;
lcd_cnt <= "001" after td;
if ((start = '1') and (clk_r = '1')) then
STM_OP <= INIT after td;
clk_en <= '1' after td;
end if;
when INIT =>
if (clk_r = '1') then
rs <= '0' after td;
rw <= '0' after td;
STM_OP <= WAITING after td;
if lcd_cnt = "001" then
if (lcd_initr = '0') then
dt <= x"01" after td;
else
dt <= x"00" after td;
end if;
elsif lcd_cnt = "010" then
dt <= x"38" after td;
elsif lcd_cnt = "011" then
dt <= x"0C" after td;
elsif lcd_cnt = "100" then
dt <= x"06" after td;
else
null;
end if;
end if;
when WAITING =>
if (clk_r = '1') then
if lcd_cnt(2) = '1' then
STM_OP <= DATA after td;
busy <= '1' after td;
lcd_initr <= '1' after td;
else
lcd_cnt <= lcd_cnt + '1' after td;
STM_OP <= INIT after td;
end if;
end if;
when DATA_WAIT =>
if (clk_r = '1') then
busy <= '0' after td;
STM_OP <= COM after td;
end if;
when DATA =>
if (clk_r = '1') then
if (data_ena = '1') then
busy <= '0' after td;
rs <= '1' after td;
rw <= data_rw after td;
dt <= data_int after td;
STM_OP <= DATA_WAIT after td;
end if;
end if;
when COM_WAIT =>
if (clk_r = '1') then
STM_OP <= INIT after td;
end if;
when COM =>
if (clk_r = '1') then
if (cnt1 < "11111") then
cnt1 := cnt1 + 1;
else
cnt1 := "00000";
end if;
if (cnt1(4) = '0') then
dt <= "10000000" + cnt1 after td;
else
dt <= "10110000" + cnt1 after td;--80H
end if;
rs <= '0' after td;
rw <= '0' after td;
lcd_cnt <= "001" after td;
STM_OP <= COM_WAIT after td;
end if;
end case;
end if;
end process;
end rtl_lcd1602; | mit | 0839d35a849a95f80794ec71ee156a5e | 0.477816 | 3.016378 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/jtag/bscanregs.vhd | 1 | 2,767 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: bscanregs
-- File: bscanregs.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: JTAG boundary scan registers, single-ended IO
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity bscanregs is
generic (
tech: integer := 0;
nsigs: integer range 1 to 30 := 8;
dirmask: integer := 2#00000000#;
enable: integer range 0 to 1 := 1
);
port (
sigi: in std_logic_vector(nsigs-1 downto 0);
sigo: out std_logic_vector(nsigs-1 downto 0);
tck: in std_ulogic;
tckn:in std_ulogic;
tdi: in std_ulogic;
tdo: out std_ulogic;
bsshft: in std_ulogic;
bscapt: in std_ulogic;
bsupdi: in std_ulogic;
bsupdo: in std_ulogic;
bsdrive: in std_ulogic;
bshighz: in std_ulogic
);
end;
architecture hier of bscanregs is
signal itdi: std_logic_vector(nsigs downto 0);
begin
disgen: if enable=0 generate
sigo <= sigi;
itdi <= (others => '0');
tdo <= '0';
end generate;
engen: if enable /= 0 generate
g0: for x in 0 to nsigs-1 generate
irgen: if ((dirmask / (2**x)) mod 2)=0 generate
ireg: scanregi
generic map (tech)
port map (sigi(x),sigo(x),tck,tckn,itdi(x),itdi(x+1),bsshft,bscapt,bsupdi,bsdrive,bshighz);
end generate;
orgen: if ((dirmask / (2**x)) mod 2)/=0 generate
oreg: scanrego
generic map (tech)
port map (sigo(x),sigi(x),sigi(x),tck,tckn,itdi(x),itdi(x+1),bsshft,bscapt,bsupdo,bsdrive);
end generate;
end generate;
itdi(0) <= tdi;
tdo <= itdi(nsigs);
end generate;
end;
| gpl-2.0 | 3682ea7dbc55827261a8d439d9a78388 | 0.594868 | 3.75441 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-kc705/leon3mp.vhd | 1 | 35,534 | -----------------------------------------------------------------------------
-- LEON3 Xilinx KC705 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_gtxclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
phy_int : in std_ulogic
);
end;
architecture rtl of leon3mp is
component ahb2mig_series7
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
component ddr_dummy
port (
ddr_dq : inout std_logic_vector(63 downto 0);
ddr_dqs : inout std_logic_vector(7 downto 0);
ddr_dqs_n : inout std_logic_vector(7 downto 0);
ddr_addr : out std_logic_vector(13 downto 0);
ddr_ba : out std_logic_vector(2 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_cke : out std_logic_vector(0 downto 0);
ddr_cs_n : out std_logic_vector(0 downto 0);
ddr_dm : out std_logic_vector(7 downto 0);
ddr_odt : out std_logic_vector(0 downto 0)
);
end component ;
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IDELAYCTRL
port (
RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic
);
end component;
component IODELAYE1
generic (
DELAY_SRC : string := "I";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CLKIN : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
--constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbm : integer := 16;
--constant maxahbs : integer := 1+CFG_DSU+CFG_MCTRL_LEON2+CFG_AHBROMEN+CFG_AHBRAMEN+2;
constant maxahbs : integer := 16;
constant maxapbs : integer := CFG_IRQ3_ENABLE+CFG_GPT_ENABLE+CFG_GRGPIO_ENABLE+CFG_AHBSTAT+CFG_AHBSTAT;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal ui_clk : std_ulogic;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii : eth_in_type;
signal gmiio : eth_out_type;
signal rgmiii,rgmiii_buf : eth_in_type;
signal rgmiio : eth_out_type;
signal sgmiii : eth_sgmii_in_type;
signal sgmiio : eth_sgmii_out_type;
signal sgmiirst : std_logic;
signal ethernet_phy_int : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gtx_clk,gtx_clk_nobuf,gtx_clk90 : std_ulogic;
signal rstgtxn : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ : integer := 200000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal dsurx_int : std_logic;
signal dsutx_int : std_logic;
signal dsuctsn_int : std_logic;
signal dsurtsn_int : std_logic;
signal dsu_sel : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal io_ref : std_logic;
signal clkref : std_logic;
signal migrstn : std_logic;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_gen0 : if (CFG_MIG_SERIES7 = 0) generate
clk_pad_ds : clkpad_ds generic map (tech => padtech, level => sstl, voltage => x15v) port map (clk200p, clk200n, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, open, open);
end generate;
reset_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1, syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_SERIES7 = 1 else cgo.clklock;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, '1', migrstn, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(1), dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui_break_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (button(0), dsui.break);
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.extclk <= '0';
end generate;
nouah : if CFG_AHB_UART = 0 generate
apbo(7) <= apb_none;
duo.txd <= '0';
duo.rtsn <= '0';
dui.extclk <= '0';
end generate;
sw4_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(3), '0', '1', dsu_sel);
dsutx_int <= duo.txd when dsu_sel = '1' else u1o.txd;
dui.rxd <= dsurx_int when dsu_sel = '1' else '1';
u1i.rxd <= dsurx_int when dsu_sel = '0' else '1';
dsurtsn_int <= duo.rtsn when dsu_sel = '1' else u1o.rtsn;
dui.ctsn <= dsuctsn_int when dsu_sel = '1' else '1';
u1i.ctsn <= dsuctsn_int when dsu_sel = '0' else '1';
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dsurx_int);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, dsutx_int);
dsuctsn_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsuctsn, dsuctsn_int);
dsurtsn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurtsn, dsurtsn_int);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+1)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+1),
open, open, open, open, open, open, open, gnd);
end generate;
nojtag : if CFG_AHB_JTAG = 0 generate apbo(CFG_NCPU+1) <= apb_none; end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl_gen : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 26, tech => padtech, level => cmos, voltage => x25v)
port map (address(25 downto 0), memo.address(26 downto 1));
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (oen, memo.oen);
adv_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (adv, '0');
wri_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (writen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 16, level => cmos, voltage => x25v)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (romsn, vcc); --ahbso(0) <= ahbso_none;
end generate;
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_SERIES7 = 1) generate
ddrc : ahb2mig_series7 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#C00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => rstraw,
clk_amba => clkm,
sys_clk_p => clk200p,
sys_clk_n => clk200n,
clk_ref_i => clkref,
ui_clk => clkm,
ui_clk_sync_rst => open
);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
end generate;
no_mig_gen : if (CFG_MIG_SERIES7 = 0) generate
ahbram0 : ahbram
generic map (hindex => 4, haddr => 16#400#, tech => CFG_MEMTECH, kbytes => 32)
port map ( rstn, clkm, ahbsi, ahbso(4));
ddrdummy0 : ddr_dummy
port map (
ddr_dq => ddr3_dq,
ddr_dqs => ddr3_dqs_p,
ddr_dqs_n => ddr3_dqs_n,
ddr_addr => ddr3_addr,
ddr_ba => ddr3_ba,
ddr_ras_n => ddr3_ras_n,
ddr_cas_n => ddr3_cas_n,
ddr_we_n => ddr3_we_n,
ddr_reset_n => ddr3_reset_n,
ddr_ck_p => ddr3_ck_p,
ddr_ck_n => ddr3_ck_n,
ddr_cke => ddr3_cke,
ddr_cs_n => ddr3_cs_n,
ddr_dm => ddr3_dm,
ddr_odt => ddr3_odt
);
calib_done <= '1';
end generate;
led2_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(2), calib_done);
led3_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(3), lock);
led4_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (led(4), ahbso(4).hready);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 16#C00#, pmask => 16#C00#, pirq => 14, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G, ramdebug => 2)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
-----------------------------------------------------------------------------
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
-- All IDELAYs in Fixed Tap Delay mode and the IDELAYCTRL primitives have
-- to be LOC'ed in the UCF file.
-----------------------------------------------------------------------------
dlyctrl0 : IDELAYCTRL port map (
RDY => OPEN,
REFCLK => io_ref,
RST => idelayctrl_reset
);
delay_rgmii_rx_ctl0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
ODATAIN => '0',
DATAOUT => rgmiii.rx_dv,
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
ODATAIN => '0',
DATAOUT => rgmiii.rxd(i),
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
end generate;
-- Generate a synchron delayed reset for Xilinx IO delay
rst1 : rstgen
generic map (acthigh => 1)
port map (rst, io_ref, lock, rstgtxn, OPEN);
process (io_ref,rstgtxn)
begin
if (rstgtxn = '0') then
idelay_reset_cnt <= (others => '0');
idelayctrl_reset <= '1';
elsif rising_edge(io_ref) then
if (idelay_reset_cnt > "1110") then
idelay_reset_cnt <= (others => '1');
idelayctrl_reset <= '0';
else
idelay_reset_cnt <= idelay_reset_cnt + 1;
idelayctrl_reset <= '1';
end if;
end if;
end process;
-- RGMII Interface
rgmii0 : rgmii generic map (11, 16#010# , 16#ff0#, fabtech, CFG_GRETH1G, 1, 1, 1)
port map (rstn, gtx_clk90, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11));
egtxc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_gtxclk, rgmiio.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v, arch => 4)
port map (phy_rxclk, rgmiii.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 4)
port map (phy_rxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_rxctl_rxdv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1, width => 4)
port map (phy_txd, rgmiio.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txctl_txen, rgmiio.tx_en);
emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdc, rgmiio.mdc);
eint_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_int, rgmiii.mdint);
erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_reset, rgmiio.reset);
-- GTX Clock
rgmiii.gtx_clk <= gtx_clk;
-- 125MHz input clock
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => gtrefclk_p,
IB => gtrefclk_n,
CEB => '0',
O => gtx_clk_nobuf,
ODIV2 => open
);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen_gtrefclk : clkgen
generic map (clktech, 8, 8, 0, 0, 0, 0, 0, 125000)
port map (gtx_clk_nobuf, gtx_clk_nobuf, gtx_clk, gtx_clk90, io_ref, open, open, cgi2, cgo2, open, open, open);
end generate;
noeth0 : if CFG_GRETH = 0 generate
-- TODO:
end generate;
----------------------------------------------------------------------
--- I2C Controller --------------------------------------------------
----------------------------------------------------------------------
--i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 11, filter => 9)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
--end generate i2cm;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16, debug => 2)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 2 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 3 to 5 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (button(i-2), gpioi.din(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
serrx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (led(5), rxd1);
sertx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (led(6), txd1);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 3, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
-- pragma translate_on
test1_gen : if (testahb = false) generate
ahbram0 : ahbram generic map (hindex => 3, haddr => 16#200#,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(3));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx KC705 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 4dfc9165852ef42139f5bd7128589a78 | 0.537795 | 3.520309 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-ztex-ufm-111/testbench.vhd | 1 | 7,702 | -------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library hynix;
use hynix.components.all;
use work.debug.all;
use work.config.all;
library micron;
use micron.components.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
signal reset : std_ulogic := '1';
signal clk48 : std_ulogic := '0';
signal errorn : std_logic;
signal mcb3_dram_dq : std_logic_vector(15 downto 0);
signal mcb3_rzq : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_a : std_logic_vector(12 downto 0);
signal mcb3_dram_ba : std_logic_vector(1 downto 0);
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_udm : std_logic;
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal dsubre : std_ulogic; -- Debug Unit break (connect to button)
signal dsuact : std_ulogic; -- Debug Unit break (connect to button)
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
signal rxd1 : std_ulogic;
signal txd1 : std_ulogic;
signal sd_dat : std_logic;
signal sd_cmd : std_logic;
signal sd_sck : std_logic;
signal sd_dat3 : std_logic;
signal csb : std_logic := '0'; -- dummy
begin
-- clock and reset
clk48 <= not clk48 after 10.05 ns;
reset <= '1', '0' after 300 ns;
dsubre <= '0';
sd_dat <= 'H';
sd_cmd <= 'H';
sd_sck <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => reset,
clk48 => clk48,
-- Processor error output
errorn => errorn,
-- DDR SDRAM
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
-- Debug support unit
dsubre => dsubre,
dsuact => dsuact,
-- AHB UART (debug link)
dsurx => dsurx,
dsutx => dsutx,
-- UART
rxd1 => rxd1,
txd1 => txd1,
-- SD card
sd_dat => sd_dat,
sd_cmd => sd_cmd,
sd_sck => sd_sck,
sd_dat3 => sd_dat3
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr0 : mt46v16m16
generic map (
tCK => 5.000 ns,
tCH => 2.250 ns, -- 0.45*tCK
tCL => 2.250 ns, -- 0.45*tCK
tDH => 0.500 ns,
tDS => 0.500 ns,
tIH => 0.900 ns,
tIS => 0.900 ns,
tMRD => 10.000 ns,
tRAS => 40.000 ns,
tRAP => 15.000 ns,
tRC => 55.000 ns,
tRFC => 70.000 ns,
tRCD => 15.000 ns,
tRP => 15.000 ns,
tRRD => 10.000 ns,
tWR => 15.000 ns,
index => -1, fname => sdramfile, cols_bits => 10, fdelay => 15,
chktiming => false)
port map(
Dq => mcb3_dram_dq, Dqs(1) => mcb3_dram_udqs, Dqs(0) => mcb3_dram_dqs,
Addr => mcb3_dram_a, Ba => mcb3_dram_ba, Clk => mcb3_dram_ck,
Clk_n => mcb3_dram_ck_n, Cke => mcb3_dram_cke, Cs_n => csb,
Ras_n => mcb3_dram_ras_n, Cas_n => mcb3_dram_cas_n, We_n => mcb3_dram_we_n,
Dm(1) => mcb3_dram_udm, Dm(0) => mcb3_dram_dm);
end generate;
--spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
--end generate spimem0;
iuerr : process
begin
wait for 5 us;
assert (to_X01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 | db791c053ff7e15ce46ca8be78b96eb4 | 0.543106 | 3.278842 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-clock-gate/leon3mp.vhd | 1 | 32,044 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic;
can_rxd : in std_logic;
can_stb : out std_logic;
spw_clk : in std_logic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_logic;
tdo : out std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant maxahbmsp : integer := NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkx, clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal gclk : std_logic_vector(NCPU-1 downto 0);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
constant BOARD_FREQ : integer := 40000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := CFG_SDCTRL + CFG_CAN;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_lclk, clkx, open, open, sdclkl, pciclk, cgi, cgo);
clkpwd : entity work.clkgate generic map (fabtech, NCPU, CFG_DSU)
port map (rstn, clkx, dsuo.pwd(NCPU-1 downto 0), clkm, gclk);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3cg -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), gclk(i));
nodsu : if CFG_DSU = 0 generate
dsuo.pwd(i) <= dbgo(i).pwd and not dbgo(i).ipend;
end generate;
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
dbgi <= (others => dbgi_none);
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data, sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm);
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) and (CFG_SDCTRL = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(5) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdis_pad : outpad generic map (tech => padtech)
port map (emddis, vcc(0));
eepwrdwn_pad : outpad generic map (tech => padtech)
port map (epwrdwn, gnd(0));
esleep_pad : outpad generic map (tech => padtech)
port map (esleep, gnd(0));
epause_pad : outpad generic map (tech => padtech)
port map (epause, gnd(0));
ereset_pad : outpad generic map (tech => padtech)
port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FFF#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_lclk);
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0'; -- For second port
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, ports => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC,rmapbufs => CFG_SPW_RMAPBUF,
dmachan => CFG_SPW_DMACHAN,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT, rxtx_sameclk => CFG_SPW_RTSAME)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 8d970ba685d83ed1605c0a1edf6c7088 | 0.560854 | 3.453762 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-xc3s-1500/config.vhd | 1 | 8,833 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 4;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000008#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := 1;
constant CFG_GRUSBDC_NEPO : integer := 1;
constant CFG_GRUSBDC_I0 : integer := 1024;
constant CFG_GRUSBDC_I1 : integer := 1024;
constant CFG_GRUSBDC_I2 : integer := 1024;
constant CFG_GRUSBDC_I3 : integer := 1024;
constant CFG_GRUSBDC_I4 : integer := 1024;
constant CFG_GRUSBDC_I5 : integer := 1024;
constant CFG_GRUSBDC_I6 : integer := 1024;
constant CFG_GRUSBDC_I7 : integer := 1024;
constant CFG_GRUSBDC_I8 : integer := 1024;
constant CFG_GRUSBDC_I9 : integer := 1024;
constant CFG_GRUSBDC_I10 : integer := 1024;
constant CFG_GRUSBDC_I11 : integer := 1024;
constant CFG_GRUSBDC_I12 : integer := 1024;
constant CFG_GRUSBDC_I13 : integer := 1024;
constant CFG_GRUSBDC_I14 : integer := 1024;
constant CFG_GRUSBDC_I15 : integer := 1024;
constant CFG_GRUSBDC_O0 : integer := 1024;
constant CFG_GRUSBDC_O1 : integer := 1024;
constant CFG_GRUSBDC_O2 : integer := 1024;
constant CFG_GRUSBDC_O3 : integer := 1024;
constant CFG_GRUSBDC_O4 : integer := 1024;
constant CFG_GRUSBDC_O5 : integer := 1024;
constant CFG_GRUSBDC_O6 : integer := 1024;
constant CFG_GRUSBDC_O7 : integer := 1024;
constant CFG_GRUSBDC_O8 : integer := 1024;
constant CFG_GRUSBDC_O9 : integer := 1024;
constant CFG_GRUSBDC_O10 : integer := 1024;
constant CFG_GRUSBDC_O11 : integer := 1024;
constant CFG_GRUSBDC_O12 : integer := 1024;
constant CFG_GRUSBDC_O13 : integer := 1024;
constant CFG_GRUSBDC_O14 : integer := 1024;
constant CFG_GRUSBDC_O15 : integer := 1024;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 0e4db364a03159a6db768bb65127119d | 0.65527 | 3.581914 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/greth/greth_gbit.vhd | 1 | 11,907 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gbit
-- File: greth_gbit.vhd
-- Author: Marko Isomaki
-- Description: Gigabit Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth_gbit is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth_gbit is
--host constants
constant fifosize : integer := 512;
constant fabits : integer := log2(fifosize);
constant fsize : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(fifosize, fabits+1);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufsize : integer := ebuf(log2(edclbufsz));
signal irq : std_ulogic;
signal gnd : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(8 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(8 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(8 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(8 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
begin
gnd <= '0';
gtxc0: greth_gbitc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => 0,
ramdebug => ramdebug,
mdiohold => mdiohold)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi.hgrant(hindex),
ehready => ahbmi.hready,
ehresp => ahbmi.hresp,
ehrdata => hrdata,
--edcl ahb mst out
ehbusreq => open,
ehlock => open,
ehtrans => open,
ehaddr => open,
ehwrite => open,
ehsize => open,
ehburst => open,
ehprot => open,
ehwdata => open,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
gtx_clk => ethi.gtx_clk,
tx_clk => ethi.tx_clk,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd,
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd,
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => etho.mdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
gbit => etho.gbit,
speed => etho.speed,
--cfg
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable);
etho.tx_clk <= '0'; -- driven in rgmii component
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, testen => scanen)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata, ahbmi.testin);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, testen => scanen)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata, ahbmi.testin);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, scanen) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16), ahbmi.testin);
r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, scanen) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0), ahbmi.testin);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100/1000 Mbit Ethernet MAC rev " &
tost(REVISION) & tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz*edcl) & " kbyte " & tost(fifosize) & " txfifo, " &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
| gpl-2.0 | f0d31b493193dd3ee19381c0b3ebbf7e | 0.51877 | 4.208908 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/srmmu/mmu.vhd | 1 | 20,753 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: MMU
-- File: mmu.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: Leon3 MMU top level entity
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu is
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type;
ramcclk : in std_ulogic := '0';
ramcin : in std_logic_vector(2*ramcbits-1 downto 0) := (others => '0');
ramcout : out std_logic_vector(2*ramcbits-1 downto 0)
);
end mmu;
architecture rtl of mmu is
constant MMUCTX_BITS : integer := M_CTX_SZ;
constant M_TLB_TYPE : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2)); -- eather split or combined
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
type mmu_op is record
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
end record;
constant mmu_op_none : mmu_op := ('0', '0', '0');
type mmu_cmbpctrl is record
tlbowner : mmu_idcache;
tlbactive : std_logic;
op : mmu_op;
end record;
constant mmu_cmbpctrl_none : mmu_cmbpctrl := (id_icache, '0', mmu_op_none);
type mmu_rtype is record
cmb_s1 : mmu_cmbpctrl;
cmb_s2 : mmu_cmbpctrl;
splt_is1 : mmu_cmbpctrl;
splt_is2 : mmu_cmbpctrl;
splt_ds1 : mmu_cmbpctrl;
splt_ds2 : mmu_cmbpctrl;
twactive : std_logic; -- split tlb
twowner : mmu_idcache; -- split tlb
flush : std_logic;
mmctrl2 : mmctrl_type2;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : mmu_rtype := (
cmb_s1 => mmu_cmbpctrl_none,
cmb_s2 => mmu_cmbpctrl_none,
splt_is1 => mmu_cmbpctrl_none,
splt_is2 => mmu_cmbpctrl_none,
splt_ds1 => mmu_cmbpctrl_none,
splt_ds2 => mmu_cmbpctrl_none,
twactive => '0',
twowner => id_icache,
flush => '0',
mmctrl2 => mmctrl2_zero);
signal r, c : mmu_rtype;
-- tlb
component mmutlb
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type;
ramcclk: in std_ulogic;
ramcin : in std_logic_vector(ramcbits-1 downto 0);
ramcout: out std_logic_vector(ramcbits-1 downto 0)
);
end component;
signal tlbi_a0 : mmutlb_in_type;
signal tlbi_a1 : mmutlb_in_type;
signal tlbo_a0 : mmutlb_out_type;
signal tlbo_a1 : mmutlb_out_type;
signal twi_a : mmutwi_a(1 downto 0);
signal two_a : mmutwo_a(1 downto 0);
-- table walk
component mmutw
generic (
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end component;
signal twi : mmutw_in_type;
signal two : mmutw_out_type;
signal mmctrl1 : mmctrl_type1;
begin
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
p0: process (rst, r, mmudci, mmuici, mcmmo, tlbo_a0, tlbo_a1, tlbi_a0, tlbi_a1, two_a, twi_a, two)
variable cmbtlbin : mmuidc_data_in_type;
variable cmbtlbout : mmutlb_out_type;
variable spltitlbin : mmuidc_data_in_type;
variable spltdtlbin : mmuidc_data_in_type;
variable spltitlbout : mmutlb_out_type;
variable spltdtlbout : mmutlb_out_type;
variable mmuico_transdata : mmuidc_data_out_type;
variable mmudco_transdata : mmuidc_data_out_type;
variable mmuico_grant : std_logic;
variable mmudco_grant : std_logic;
variable v : mmu_rtype;
variable twiv : mmutw_in_type;
variable twod, twoi : mmutw_out_type;
variable fault : mmutlbfault_out_type;
variable wbtransdata : mmuidc_data_out_type;
variable fs : mmctrl_fs_type;
variable fa : std_logic_vector(VA_I_SZ-1 downto 0);
begin
v := r;
wbtransdata.finish := '0';
wbtransdata.data := (others => '0');
wbtransdata.cache := '0';
wbtransdata.accexc := '0';
if (M_TLB_TYPE = 0) and (M_TLB_FASTWRITE /= 0) then
wbtransdata := tlbo_a1.wbtransdata;
end if;
cmbtlbin.data := (others => '0');
cmbtlbin.su := '0';
cmbtlbin.read := '0';
cmbtlbin.isid := id_dcache;
cmbtlbout.transdata.finish := '0';
cmbtlbout.transdata.data := (others => '0');
cmbtlbout.transdata.cache := '0';
cmbtlbout.transdata.accexc := '0';
cmbtlbout.fault.fault_pro := '0';
cmbtlbout.fault.fault_pri := '0';
cmbtlbout.fault.fault_access := '0';
cmbtlbout.fault.fault_mexc := '0';
cmbtlbout.fault.fault_trans := '0';
cmbtlbout.fault.fault_inv := '0';
cmbtlbout.fault.fault_lvl := (others => '0');
cmbtlbout.fault.fault_su := '0';
cmbtlbout.fault.fault_read := '0';
cmbtlbout.fault.fault_isid := id_dcache;
cmbtlbout.fault.fault_addr := (others => '0');
cmbtlbout.nexttrans := '0';
cmbtlbout.s1finished := '0';
mmuico_transdata.finish := '0';
mmuico_transdata.data := (others => '0');
mmuico_transdata.cache := '0';
mmuico_transdata.accexc := '0';
mmudco_transdata.finish := '0';
mmudco_transdata.data := (others => '0');
mmudco_transdata.cache := '0';
mmudco_transdata.accexc := '0';
mmuico_grant := '0';
mmudco_grant := '0';
twiv.walk_op_ur := '0';
twiv.areq_ur := '0';
twiv.data := (others => '0');
twiv.adata := (others => '0');
twiv.aaddr := (others => '0');
twod.finish := '0';
twod.data := (others => '0');
twod.addr := (others => '0');
twod.lvl := (others => '0');
twod.fault_mexc := '0';
twod.fault_trans := '0';
twod.fault_inv := '0';
twod.fault_lvl := (others => '0');
twoi.finish := '0';
twoi.data := (others => '0');
twoi.addr := (others => '0');
twoi.lvl := (others => '0');
twoi.fault_mexc := '0';
twoi.fault_trans := '0';
twoi.fault_inv := '0';
twoi.fault_lvl := (others => '0');
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
fs.ow := '0';
fs.fav := '0';
fs.ft := (others => '0');
fs.at_ls := '0';
fs.at_id := '0';
fs.at_su := '0';
fs.l := (others => '0');
fs.ebe := (others => '0');
fa := (others => '0');
if M_TLB_TYPE = 0 then
spltitlbout := tlbo_a0;
spltdtlbout := tlbo_a1;
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
spltdtlbin := mmudci.transdata;
spltitlbin := mmuici.transdata;
mmudco_transdata := spltdtlbout.transdata;
mmuico_transdata := spltitlbout.transdata;
-- d-tlb
if ((not r.splt_ds1.tlbactive) or spltdtlbout.s1finished) = '1' then
v.splt_ds1.tlbactive := '0';
v.splt_ds1.op.trans_op := '0';
v.splt_ds1.op.flush_op := '0';
if mmudci.trans_op = '1' then
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
v.flush := '1';
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.flush_op := '1';
end if;
end if;
-- i-tlb
if ((not r.splt_is1.tlbactive) or spltitlbout.s1finished) = '1' then
v.splt_is1.tlbactive := '0';
v.splt_is1.op.trans_op := '0';
v.splt_is1.op.flush_op := '0';
if v.flush = '1' then
v.flush := '0';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.flush_op := '1';
elsif mmuici.trans_op = '1' then
mmuico_grant := '1';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.trans_op := '1';
end if;
end if;
if spltitlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
fault := spltitlbout.fault;
end if;
if spltdtlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
if (spltdtlbout.fault.fault_mexc or
spltdtlbout.fault.fault_trans or
spltdtlbout.fault.fault_inv or
spltdtlbout.fault.fault_pro or
spltdtlbout.fault.fault_pri or
spltdtlbout.fault.fault_access) = '1' then
fault := spltdtlbout.fault; -- overwrite icache fault
end if;
end if;
if spltitlbout.s1finished = '1' then
v.splt_is2 := r.splt_is1;
end if;
if spltdtlbout.s1finished = '1' then
v.splt_ds2 := r.splt_ds1;
end if;
if ( r.splt_is2.op.flush_op ) = '1' then
mmuico_transdata.finish := '0';
end if;
-- share tw
if two.finish = '1' then
v.twactive := '0';
end if;
if r.twowner = id_icache then
twiv := twi_a(0);
twoi.finish := two.finish;
else
twiv := twi_a(1);
twod.finish := two.finish;
end if;
if (v.twactive) = '0' then
if (twi_a(1).areq_ur or twi_a(1).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_dcache;
elsif (twi_a(0).areq_ur or twi_a(0).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_icache;
end if;
end if;
else
--# combined i/d cache: 1 tlb, 1 tw
-- share one tlb among i and d cache
cmbtlbout := tlbo_a0;
mmuico_grant := '0'; mmudco_grant := '0';
mmuico_transdata.finish := '0'; mmudco_transdata.finish := '0';
twiv := twi_a(0);
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
-- twod.finish := two.finish;
twoi.finish := two.finish;
if ((not v.cmb_s1.tlbactive) or cmbtlbout.s1finished) = '1' then
v.cmb_s1.tlbactive := '0';
v.cmb_s1.op.trans_op := '0';
v.cmb_s1.op.flush_op := '0';
if (mmudci.trans_op or mmudci.flush_op or mmuici.trans_op) = '1' then
v.cmb_s1.tlbactive := '1';
end if;
if mmuici.trans_op = '1' then
mmuico_grant := '1';
v.cmb_s1.tlbowner := id_icache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.trans_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.flush_op := '1';
end if;
end if;
if (r.cmb_s1.tlbactive and not r.cmb_s2.tlbactive) = '1' then
end if;
if cmbtlbout.s1finished = '1' then
v.cmb_s2 := r.cmb_s1;
end if;
if r.cmb_s1.tlbowner = id_dcache then
cmbtlbin := mmudci.transdata;
else
cmbtlbin := mmuici.transdata;
end if;
if r.cmb_s2.tlbowner = id_dcache then
mmudco_transdata := cmbtlbout.transdata;
else
mmuico_transdata := cmbtlbout.transdata;
end if;
if cmbtlbout.transdata.finish = '1' and (r.cmb_s2.op.flush_op = '0') then
fault := cmbtlbout.fault;
end if;
end if;
-- # fault status register
if (mmudci.fsread) = '1' then
v.mmctrl2.valid := '0'; v.mmctrl2.fs.fav := '0';
end if;
if (fault.fault_mexc) = '1' then
fs.ft := FS_FT_TRANS;
elsif (fault.fault_trans) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_inv) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_pri) = '1' then
fs.ft := FS_FT_PRI;
elsif (fault.fault_pro) = '1' then
fs.ft := FS_FT_PRO;
elsif (fault.fault_access) = '1' then
fs.ft := FS_FT_BUS;
else
fs.ft := FS_FT_NONE;
end if;
fs.ow := '0';
fs.l := fault.fault_lvl;
if fault.fault_isid = id_dcache then
fs.at_id := '0';
else
fs.at_id := '1';
end if;
fs.at_su := fault.fault_su;
fs.at_ls := not fault.fault_read;
fs.fav := '1';
fs.ebe := (others => '0');
fa := fault.fault_addr(VA_I_U downto VA_I_D);
if (fault.fault_mexc or
fault.fault_trans or
fault.fault_inv or
fault.fault_pro or
fault.fault_pri or
fault.fault_access) = '1' then
--# priority
if v.mmctrl2.valid = '1'then
if (fault.fault_mexc) = '1' then
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
if (r.mmctrl2.fs.ft /= FS_FT_INV) then
if fault.fault_isid = id_dcache then
-- dcache
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
-- icache
if (not r.mmctrl2.fs.at_id) = '0' then
fs.ow := '1';
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
end if;
end if;
end if;
end if;
else
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
v.mmctrl2.valid := '1';
end if;
if (fault.fault_isid) = id_dcache then
mmudco_transdata.accexc := '1';
else
mmuico_transdata.accexc := '1';
end if;
end if;
-- # reset
if ( not RESET_ALL ) and ( rst = '0' ) then
if M_TLB_TYPE = 0 then
v.splt_is1.tlbactive := RRES.splt_is1.tlbactive;
v.splt_is2.tlbactive := RRES.splt_is2.tlbactive;
v.splt_ds1.tlbactive := RRES.splt_ds1.tlbactive;
v.splt_ds2.tlbactive := RRES.splt_ds2.tlbactive;
v.splt_is1.op.trans_op := RRES.splt_is1.op.trans_op;
v.splt_is2.op.trans_op := RRES.splt_is2.op.trans_op;
v.splt_ds1.op.trans_op := RRES.splt_ds1.op.trans_op;
v.splt_ds2.op.trans_op := RRES.splt_ds2.op.trans_op;
v.splt_is1.op.flush_op := RRES.splt_is1.op.flush_op;
v.splt_is2.op.flush_op := RRES.splt_is2.op.flush_op;
v.splt_ds1.op.flush_op := RRES.splt_ds1.op.flush_op;
v.splt_ds2.op.flush_op := RRES.splt_ds2.op.flush_op;
else
v.cmb_s1.tlbactive := RRES.cmb_s1.tlbactive;
v.cmb_s2.tlbactive := RRES.cmb_s2.tlbactive;
v.cmb_s1.op.trans_op := RRES.cmb_s1.op.trans_op;
v.cmb_s2.op.trans_op := RRES.cmb_s2.op.trans_op;
v.cmb_s1.op.flush_op := RRES.cmb_s1.op.flush_op;
v.cmb_s2.op.flush_op := RRES.cmb_s2.op.flush_op;
end if;
v.flush := RRES.flush;
v.mmctrl2.valid := RRES.mmctrl2.valid;
v.twactive := RRES.twactive;
v.twowner := RRES.twowner;
end if;
-- drive signals
if M_TLB_TYPE = 0 then
tlbi_a0.trans_op <= r.splt_is1.op.trans_op;
tlbi_a0.flush_op <= r.splt_is1.op.flush_op;
tlbi_a0.transdata <= spltitlbin;
tlbi_a0.s2valid <= r.splt_is2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
tlbi_a1.trans_op <= r.splt_ds1.op.trans_op;
tlbi_a1.flush_op <= r.splt_ds1.op.flush_op;
tlbi_a1.transdata <= spltdtlbin;
tlbi_a1.s2valid <= r.splt_ds2.tlbactive;
tlbi_a1.mmctrl1 <= mmudci.mmctrl1;
tlbi_a1.wb_op <= mmudci.wb_op;
else
tlbi_a0.trans_op <= r.cmb_s1.op.trans_op;
tlbi_a0.flush_op <= r.cmb_s1.op.flush_op;
tlbi_a0.transdata <= cmbtlbin;
tlbi_a0.s2valid <= r.cmb_s2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
end if;
tlbi_a0.testin <= mmudci.testin;
tlbi_a1.testin <= mmudci.testin;
mmudco.transdata <= mmudco_transdata;
mmuico.transdata <= mmuico_transdata;
mmudco.grant <= mmudco_grant;
mmuico.grant <= mmuico_grant;
mmuico.tlbmiss <= twi_a(0).tlbmiss;
mmudco.mmctrl2 <= r.mmctrl2;
mmudco.wbtransdata <= wbtransdata;
twi <= twiv;
two_a(0) <= twoi;
two_a(1) <= twod;
mmctrl1 <= mmudci.mmctrl1;
c <= v;
end process p0;
tlbcomb0: if M_TLB_TYPE = 1 generate
-- i/d tlb
ctlb0 : mmutlb
generic map ( tech, M_ENT_C, 0, tlb_rep, mmupgsz, ramcbits )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0),
ramcclk, ramcin(ramcbits-1 downto 0), ramcout(ramcbits-1 downto 0));
mmudco.tlbmiss <= twi_a(0).tlbmiss;
ramcout(2*ramcbits-1 downto ramcbits) <= (others => '0');
end generate tlbcomb0;
tlbsplit0: if M_TLB_TYPE = 0 generate
-- i tlb
itlb0 : mmutlb
generic map ( tech, M_ENT_I, 0, tlb_rep, mmupgsz, ramcbits )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0),
ramcclk, ramcin(ramcbits-1 downto 0), ramcout(ramcbits-1 downto 0));
-- d tlb
dtlb0 : mmutlb
generic map ( tech, M_ENT_D, tlb_type, tlb_rep, mmupgsz, ramcbits )
port map (rst, clk, tlbi_a1, tlbo_a1, two_a(1), twi_a(1),
ramcclk, ramcin(2*ramcbits-1 downto ramcbits), ramcout(2*ramcbits-1 downto ramcbits));
mmudco.tlbmiss <= twi_a(1).tlbmiss;
end generate tlbsplit0;
-- table walk component
tw0 : mmutw
generic map ( mmupgsz )
port map (rst, clk, mmctrl1, twi, two, mcmmo, mcmmi);
-- pragma translate_off
chk : process
begin
assert not ((M_TLB_TYPE = 1) and (M_TLB_FASTWRITE /= 0)) report
"Fast writebuffer only supported for combined cache"
severity failure;
wait;
end process;
-- pragma translate_on
end rtl;
| gpl-2.0 | 684589091b00c59ec7076ef00a52dada | 0.550475 | 3.174212 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_datamover.vhd | 4 | 51,606 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_mm2s_basic_wrap;
use axi_sg_v4_1.axi_sg_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_sg_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0) ;
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_MM2S_ADDR_WIDTH+40)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+40)-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_sg_datamover;
architecture implementation of axi_sg_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
-- coverage off
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
-- coverage on
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
-- coverage off
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
-- coverage on
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
-- coverage off
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
-- coverage on
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
-- coverage off
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
-- coverage on
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
-- coverage off
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
-- coverage on
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
-- coverage off
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
-- coverage on
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_sg_v4_1.axi_sg_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
sg_ctl => sg_ctl ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_sg_v4_1.axi_sg_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
sg_ctl => sg_ctl ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
end implementation;
| gpl-3.0 | 692b97879c1e2f8cba744fe0b30f6dcf | 0.407627 | 4.608913 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/ringosc.vhd | 1 | 1,991 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ringosc
-- File: ringosc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Ring-oscillator with tech mapping
------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ringosc is
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end ;
architecture rtl of ringosc is
component ringosc_rhumc
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
begin
dr : if tech = rhumc generate
drx : ringosc_rhumc port map (roen, roout);
end generate;
-- pragma translate_off
gen : if tech /= rhumc generate
signal tmp : std_ulogic := '0';
begin
tmp <= not tmp after 1 ns when roen = '1' else '0';
roout <= tmp;
end generate;
-- pragma translate_on
end architecture rtl; | gpl-2.0 | 236f1ab64c61584a08d76623a5761f76 | 0.599196 | 4.28172 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/mmu_cache.vhd | 1 | 6,174 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_cache
-- File: mmu_cache.vhd
-- Author: Jiri Gaisler
-- Description: Cache controllers and AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libleon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu_cache is
generic (
hindex : integer := 0;
memtech : integer range 0 to NTECH := 0;
dsu : integer range 0 to 1 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_ulogic;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_cache is
signal icol : icache_out_type;
signal dcol : dcache_out_type;
signal mcii : memory_ic_in_type;
signal mcio : memory_ic_out_type;
signal mcdi : memory_dc_in_type;
signal mcdo : memory_dc_out_type;
signal mcmmi : memory_mm_in_type;
signal mcmmo : memory_mm_out_type;
signal mmudci : mmudc_in_type;
signal mmudco : mmudc_out_type;
signal mmuici : mmuic_in_type;
signal mmuico : mmuic_out_type;
signal ahbsi2 : ahb_slv_in_type;
signal ahbi2 : ahb_mst_in_type;
signal ahbo2 : ahb_mst_out_type;
signal gndv: std_logic_vector(1 downto 0);
begin
gndv <= (others => '0');
icache0 : mmu_icache
generic map (icen, irepl, isets, ilinesize, isetsize, isetlock, ilram,
ilramsize, ilramstart,
mmuen)
port map (rst, clk, ici, icol, dci, dcol, mcii, mcio,
crami.icramin, cramo.icramo, fpuholdn, mmudci, mmuici, mmuico);
dcache0 : mmu_dcache
generic map (dsu, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop,
dlram, dlramsize, dlramstart, ilram, ilramstart,
itlbnum, dtlbnum, tlb_type,
memtech, cached, mmupgsz, smp, mmuen)
port map (rst, clk, dci, dcol, icol, mcdi, mcdo, ahbsi2,
crami.dcramin, cramo.dcramo, fpuholdn, mmudci, mmudco, sclk, ahbso);
-- AMBA AHB interface
a0 : mmu_acache
generic map (hindex, ilinesize, cached, clk2x, scantest
)
port map (rst, sclk, mcii, mcio, mcdi, mcdo, mcmmi, mcmmo, ahbi2, ahbo2, ahbso, hclken);
-- MMU
mmugen : if mmuen = 1 generate
m0 : mmu
generic map (memtech, itlbnum, dtlbnum, tlb_type, tlb_rep, mmupgsz, 1)
port map (rst, clk, mmudci, mmudco, mmuici, mmuico, mcmmo, mcmmi,
gndv(0), gndv(1 downto 0), open);
end generate;
nommu : if mmuen = 0 generate
mcmmi <= mci_zero; mmudco <= mmudco_zero; mmuico <= mmuico_zero;
end generate;
ico <= icol;
dco <= dcol;
clk2xgen: if clk2x /= 0 generate
sync0 : clk2xsync generic map (hindex, clk2x)
port map (rst, hclk, clk, ahbi, ahbi2, ahbo2, ahbo, ahbsi, ahbsi2,
mcii, mcdi, mcdo, mcmmi.req, mcmmo.grant, hclken);
end generate;
noclk2x : if clk2x = 0 generate
ahbsi2 <= ahbsi;
ahbi2 <= ahbi;
ahbo <= ahbo2;
end generate;
end;
| gpl-2.0 | 8eaaeba14e4f9c9f8f2f7ad03929abf0 | 0.560091 | 3.730514 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_mul_8ns_22ns_30_3.vhd | 2 | 2,706 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_mul_8ns_22ns_30_3_MAC3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(22 - 1 downto 0);
p: out std_logic_vector(30 - 1 downto 0));
end entity;
architecture behav of image_filter_mul_8ns_22ns_30_3_MAC3S_0 is
signal tmp_product : std_logic_vector(30 - 1 downto 0);
signal a_i : std_logic_vector(8 - 1 downto 0);
signal b_i : std_logic_vector(22 - 1 downto 0);
signal p_tmp : std_logic_vector(30 - 1 downto 0);
signal a_reg0 : std_logic_vector(8 - 1 downto 0);
signal b_reg0 : std_logic_vector(22 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(30 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 30));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity image_filter_mul_8ns_22ns_30_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of image_filter_mul_8ns_22ns_30_3 is
component image_filter_mul_8ns_22ns_30_3_MAC3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
image_filter_mul_8ns_22ns_30_3_MAC3S_0_U : component image_filter_mul_8ns_22ns_30_3_MAC3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| gpl-3.0 | 1752682b429e7607ddafe504f2e6edad | 0.551367 | 3.209964 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/proc3.vhd | 1 | 6,585 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: proc3
-- File: proc3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 processor core with pipeline, mul/div & cache control
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.arith.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity proc3 is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 0;
svt : integer range 0 to 1 := 0;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of proc3 is
constant IRFWT : integer := 1; --regfile_3p_write_through(memtech);
signal ici : icache_in_type;
signal ico : icache_out_type;
signal dci : dcache_in_type;
signal dco : dcache_out_type;
signal holdnx, pholdn : std_logic;
signal muli : mul32_in_type;
signal mulo : mul32_out_type;
signal divi : div32_in_type;
signal divo : div32_out_type;
begin
holdnx <= ico.hold and dco.hold and fpo.holdn; holdn <= holdnx;
pholdn <= fpo.holdn;
-- integer unit
iu : iu3
generic map (nwindows, isets, dsets, fpu, v8, cp, mac, dsu, nwp, pclow,
notag, hindex, lddel, IRFWT, disas, tbuf, pwd, svt, rstaddr, smp, fabtech,
clk2x, bp)
port map (clk, rstn, holdnx, ici, ico, dci, dco, rfi, rfo, irqi, irqo,
dbgi, dbgo, muli, mulo, divi, divo, fpo, fpi, cpo, cpi, tbo, tbi, sclk);
-- multiply and divide units
mgen : if v8 /= 0 generate
mul0 : mul32 generic map (fabtech, v8/16, (v8 mod 4)/2, mac, (v8 mod 16)/4)
port map (rstn, clk, holdnx, muli, mulo);
div0 : div32 port map (rstn, clk, holdnx, divi, divo);
end generate;
nomgen : if v8 = 0 generate
divo <= ('0', '0', "0000", zero32);
mulo <= ('0', '0', "0000", zero32&zero32);
end generate;
-- cache controller
c0mmu : mmu_cache
generic map (
hindex, memtech, dsu, icen, irepl, isets, ilinesize, isetsize,
isetlock, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, ilram, ilramsize, ilramstart, dlram, dlramsize, dlramstart,
itlbnum, dtlbnum, tlb_type, tlb_rep, cached,
clk2x, scantest, mmupgsz, smp, mmuen)
port map (rstn, clk, ici, ico, dci, dco, ahbi, ahbo, ahbsi, ahbso,
crami, cramo, pholdn, hclk, sclk, hclken);
end;
| gpl-2.0 | afe6503e02b2e2172ab7c4b27d316b8b | 0.548823 | 3.598361 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_p_src_cols_V_channel.vhd | 2 | 4,628 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_cols_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_p_src_cols_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_cols_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_cols_V_channel is
component FIFO_image_filter_p_src_cols_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_cols_V_channel_shiftReg : FIFO_image_filter_p_src_cols_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | aa89a874c5838da1e304fb2c767998d2 | 0.539326 | 3.490196 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/misc/misc.vhd | 1 | 45,597 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: misc
-- File: misc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Misc models
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package misc is
-- reset generator with filter
component rstgen
generic (acthigh : integer := 0; syncrst : integer := 0;
scanen : integer := 0; syncin : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0');
end component;
type gptimer_in_type is record
dhalt : std_ulogic;
extclk : std_ulogic;
wdogen : std_ulogic;
end record;
type gptimer_in_vector is array (natural range <>) of gptimer_in_type;
type gptimer_out_type is record
tick : std_logic_vector(0 to 7);
timer1 : std_logic_vector(31 downto 0);
wdogn : std_ulogic;
wdog : std_ulogic;
end record;
type gptimer_out_vector is array (natural range <>) of gptimer_out_type;
constant gptimer_in_none : gptimer_in_type := ('0', '0', '0');
constant gptimer_out_none : gptimer_out_type :=
((others => '0'), (others => '0'), '1', '0');
component gptimer
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0;
ewdogen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end component;
-- 32-bit ram with AHB interface
component ahbram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
end component;
type ahbram_out_type is record
ce : std_ulogic;
end record;
component ftahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer := 1;
autoscrub : integer := 0;
errcnten : integer := 0;
cntbits : integer range 1 to 8 := 1;
ahbpipe : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ftahbram2 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
testen : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ahbdpram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 2;
abits : integer range 8 to 19 := 8;
bytewrite : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
clkdp : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
enable : in std_ulogic; -- active high chip select
write : in std_logic_vector(0 to 3) -- active high byte write enable
); -- big-endian write: bwrite(0) => data(31:24)
end component;
component ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
ahbfilt : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
ahbfilt : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type
);
end component;
component ahbtrace_mmb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
ahbfilt : integer := 0;
ntrace : integer range 1 to 8 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmiv : in ahb_mst_in_vector_type(0 to ntrace-1); -- Trace
tahbsiv : in ahb_slv_in_vector_type(0 to ntrace-1)
);
end component;
type ahbmst2_request is record
req: std_logic; -- Request enable bit
wr: std_logic;
hsize: std_logic_vector(2 downto 0);
hburst: std_logic_vector(2 downto 0);
hprot: std_logic_vector(3 downto 0);
addr: std_logic_vector(32-1 downto 0);
burst_cont: std_logic; -- Set for all except the first request in a burst
burst_wrap: std_logic; -- High for the request where wrap occurs
end record;
constant ahbmst2_request_none: ahbmst2_request := (
req => '0', wr => '0', hsize => "010", hburst => "000", burst_cont => '0',
burst_wrap => '0', addr => (others => '0'), hprot => "0011");
type ahbmst2_in_type is record
request: ahbmst2_request;
wrdata: std_logic_vector(AHBDW-1 downto 0);
-- For back-to-back transfers or bursts, this must be set when done is high
-- and then copied over to request after the rising edge of clk.
next_request: ahbmst2_request;
-- Insert busy cycle, must only be asserted when request and next_request
-- are both part of the same burst.
busy: std_logic;
hlock: std_logic; -- Lock signal, passed through directly to AMBA.
keepreq: std_logic; -- Keep bus request high even when no request needs it.
end record;
type ahbmst2_out_type is record
done: std_logic;
flip: std_logic;
fail: std_logic;
rddata: std_logic_vector(AHBDW-1 downto 0);
end record;
component ahbmst2 is
generic (
hindex: integer := 0;
venid: integer;
devid: integer;
version: integer;
dmastyle: integer range 1 to 3 := 3;
syncrst: integer range 0 to 1 := 1
);
port (
clk: in std_logic;
rst: in std_logic;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
m2i: in ahbmst2_in_type;
m2o: out ahbmst2_out_type
);
end component;
type gpio_in_type is record
din : std_logic_vector(31 downto 0);
sig_in : std_logic_vector(31 downto 0);
sig_en : std_logic_vector(31 downto 0);
end record;
type gpio_in_vector is array (natural range <>) of gpio_in_type;
type gpio_out_type is record
dout : std_logic_vector(31 downto 0);
oen : std_logic_vector(31 downto 0);
val : std_logic_vector(31 downto 0);
sig_out : std_logic_vector(31 downto 0);
end record;
type gpio_out_vector is array (natural range <>) of gpio_out_type;
component grgpio
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0;
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#;
pirq : integer := 0;
irqgen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end component;
type ahb2ahb_ctrl_type is record
slck : std_ulogic;
blck : std_ulogic;
mlck : std_ulogic;
end record;
constant ahb2ahb_ctrl_none : ahb2ahb_ctrl_type := ('0', '0', '0');
type ahb2ahb_ifctrl_type is record
mstifen : std_ulogic;
slvifen : std_ulogic;
end record;
constant ahb2ahb_ifctrl_none : ahb2ahb_ifctrl_type := ('1', '1');
component ahb2ahb
generic(
memtech : integer := 0;
hsindex : integer := 0;
hmindex : integer := 0;
slv : integer range 0 to 1 := 0;
dir : integer range 0 to 1 := 0; -- 0 - down, 1 - up
ffact : integer range 0 to 15:= 2;
pfen : integer range 0 to 1 := 0;
wburst : integer range 2 to 32 := 8;
iburst : integer range 4 to 8 := 8;
rburst : integer range 2 to 32 := 8;
irqsync : integer range 0 to 2 := 0;
bar0 : integer range 0 to 1073741823 := 0;
bar1 : integer range 0 to 1073741823 := 0;
bar2 : integer range 0 to 1073741823 := 0;
bar3 : integer range 0 to 1073741823 := 0;
sbus : integer := 0;
mbus : integer := 0;
ioarea : integer := 0;
ibrsten : integer := 0;
lckdac : integer range 0 to 2 := 0;
slvmaccsz : integer range 32 to 256 := 32;
mstmaccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
ifctrlen : integer range 0 to 1 := 0;
fcfs : integer range 0 to NAHBMST := 0;
fcfsmtech : integer range 0 to NTECH := inferred;
scantest : integer range 0 to 1 := 0;
split : integer range 0 to 1 := 1;
pipe : integer range 0 to 128 := 0);
port (
rstn : in std_ulogic;
hclkm : in std_ulogic;
hclks : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbso2 : in ahb_slv_out_vector;
lcki : in ahb2ahb_ctrl_type;
lcko : out ahb2ahb_ctrl_type;
ifctrl : in ahb2ahb_ifctrl_type := ahb2ahb_ifctrl_none
);
end component;
component ahbbridge
generic(
memtech : integer := 0;
ffact : integer range 0 to 15 := 2;
-- high-speed bus
hsb_hsindex : integer := 0;
hsb_hmindex : integer := 0;
hsb_iclsize : integer range 4 to 8 := 8;
hsb_bank0 : integer range 0 to 1073741823 := 0;
hsb_bank1 : integer range 0 to 1073741823 := 0;
hsb_bank2 : integer range 0 to 1073741823 := 0;
hsb_bank3 : integer range 0 to 1073741823 := 0;
hsb_ioarea : integer := 0;
-- low-speed bus
lsb_hsindex : integer := 0;
lsb_hmindex : integer := 0;
lsb_rburst : integer range 16 to 32 := 16;
lsb_wburst : integer range 2 to 32 := 8;
lsb_bank0 : integer range 0 to 1073741823 := 0;
lsb_bank1 : integer range 0 to 1073741823 := 0;
lsb_bank2 : integer range 0 to 1073741823 := 0;
lsb_bank3 : integer range 0 to 1073741823 := 0;
lsb_ioarea : integer := 0;
--
lckdac : integer range 0 to 2 := 2;
maccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
fcfs : integer range 0 to NAHBMST := 0;
scantest : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
hsb_clk : in std_ulogic;
lsb_clk : in std_ulogic;
hsb_ahbsi : in ahb_slv_in_type;
hsb_ahbso : out ahb_slv_out_type;
hsb_ahbsov : in ahb_slv_out_vector;
hsb_ahbmi : in ahb_mst_in_type;
hsb_ahbmo : out ahb_mst_out_type;
lsb_ahbsi : in ahb_slv_in_type;
lsb_ahbso : out ahb_slv_out_type;
lsb_ahbsov : in ahb_slv_out_vector;
lsb_ahbmi : in ahb_mst_in_type;
lsb_ahbmo : out ahb_mst_out_type);
end component;
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer;
type ahbstat_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
end record;
component ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
type nuhosp3_in_type is record
flash_d : std_logic_vector(15 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_ardy : std_ulogic;
smsc_intr : std_ulogic;
smsc_nldev : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
end record;
type nuhosp3_out_type is record
flash_a : std_logic_vector(20 downto 0);
flash_d : std_logic_vector(15 downto 0);
flash_oen : std_ulogic;
flash_wen : std_ulogic;
flash_cen : std_ulogic;
smsc_addr : std_logic_vector(14 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_nbe : std_logic_vector(3 downto 0);
smsc_resetn : std_ulogic;
smsc_nrd : std_ulogic;
smsc_nwr : std_ulogic;
smsc_ncs : std_ulogic;
smsc_aen : std_ulogic;
smsc_lclk : std_ulogic;
smsc_wnr : std_ulogic;
smsc_rdyrtn : std_ulogic;
smsc_cycle : std_ulogic;
smsc_nads : std_ulogic;
smsc_ben : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
lcd_rs : std_ulogic;
lcd_rw : std_ulogic;
lcd_en : std_ulogic;
lcd_backl : std_ulogic;
lcd_ben : std_ulogic;
end record;
component nuhosp3
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
ioaddr : integer := 16#200#;
iomask : integer := 16#fff#);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
nui : in nuhosp3_in_type;
nuo : out nuhosp3_out_type
);
end component;
-- On-chip Logic Analyzer
component logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0;
usediv : integer range 0 to 1 := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic;
clk : in std_logic;
tclk : in std_logic;
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end component;
type ps2_in_type is record
ps2_clk_i : std_ulogic;
ps2_data_i : std_ulogic;
end record;
type ps2_out_type is record
ps2_clk_o : std_ulogic;
ps2_clk_oe : std_ulogic;
ps2_data_o : std_ulogic;
ps2_data_oe : std_ulogic;
end record;
component apbps2
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 0;
oepol : integer range 0 to 1 := 0);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end component;
type apbvga_out_type is record
hsync : std_ulogic; -- horizontal sync
vsync : std_ulogic; -- vertical sync
comp_sync : std_ulogic; -- composite sync
blank : std_ulogic; -- blank signal
video_out_r : std_logic_vector(7 downto 0); -- red channel
video_out_g : std_logic_vector(7 downto 0); -- green channel
video_out_b : std_logic_vector(7 downto 0); -- blue channel
bitdepth : std_logic_vector(1 downto 0); -- Bith depth
end record;
component apbvga
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end component;
component svgactrl
generic(
length : integer := 384; -- Fifo-length
part : integer := 128; -- Fifo-part lenght
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8;
ahbaccsz : integer := 32;
asyncrst : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0);
arst : in std_ulogic := '1'
);
end component;
constant vgao_none : apbvga_out_type :=
('0', '0', '0', '0', "00000000", "00000000", "00000000", "00");
constant ps2o_none : ps2_out_type := ('1', '1', '1', '1');
-- component ahbrom
-- generic (
-- hindex : integer := 0;
-- haddr : integer := 0;
-- hmask : integer := 16#fff#;
-- pipe : integer := 0;
-- tech : integer := 0;
-- kbytes : integer := 1);
-- port (
-- rst : in std_ulogic;
-- clk : in std_ulogic;
-- ahbsi : in ahb_slv_in_type;
-- ahbso : out ahb_slv_out_type
-- );
-- end component;
component ahbdma
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
dbuf : integer := 0);
port (
rst : in std_logic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for FIFO controller
-----------------------------------------------------------------------------
type FIFO_In_Type is record
Din: Std_Logic_Vector(31 downto 0); -- data input
Pin: Std_Logic_Vector( 3 downto 0); -- parity input
EFn: Std_ULogic; -- empty flag
FFn: Std_ULogic; -- full flag
HFn: Std_ULogic; -- half flag
end record;
type FIFO_Out_Type is record
Dout: Std_Logic_Vector(31 downto 0); -- data output
Den: Std_Logic_Vector(31 downto 0); -- data enable
Pout: Std_Logic_Vector( 3 downto 0); -- parity output
Pen: Std_Logic_Vector( 3 downto 0); -- parity enable
WEn: Std_ULogic; -- write enable
REn: Std_ULogic; -- read enable
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR FIFO Interface
-----------------------------------------------------------------------------
component grfifo is
generic (
hindex: Integer := 0;
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
dwidth: Integer := 16; -- data width
ptrwidth: Integer range 16 to 16 := 16; -- 16 to 64k bytes
-- 128 to 512k bits
singleirq: Integer range 0 to 1 := 0; -- single irq output
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
ahbi: in AHB_Mst_In_Type;
ahbo: out AHB_Mst_Out_Type;
fifoi: in FIFO_In_Type;
fifoo: out FIFO_Out_Type);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for CAN controllers
-----------------------------------------------------------------------------
type Analog_In_Type is record
Ain: Std_Logic_Vector(31 downto 0); -- address input
Din: Std_Logic_Vector(31 downto 0); -- data input
Rdy: Std_ULogic; -- adc ready input
Trig: Std_Logic_Vector( 2 downto 0); -- adc trigger inputs
end record;
type Analog_Out_Type is record
Aout: Std_Logic_Vector(31 downto 0); -- address output
Aen: Std_Logic_Vector(31 downto 0); -- address enable
Dout: Std_Logic_Vector(31 downto 0); -- dac data output
Den: Std_Logic_Vector(31 downto 0); -- dac data enable
Wr: Std_ULogic; -- dac write strobe
CS: Std_ULogic; -- adc chip select
RC: Std_ULogic; -- adc read/convert
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR ADC/DAC Interface
-----------------------------------------------------------------------------
component gradcdac is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
awidth: Integer := 8; -- address width
dwidth: Integer := 16; -- data width
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
adi: in Analog_In_Type;
ado: out Analog_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AMBA wrapper for System Monitor
-----------------------------------------------------------------------------
type grsysmon_in_type is record
convst : std_ulogic;
convstclk : std_ulogic;
vauxn : std_logic_vector(15 downto 0);
vauxp : std_logic_vector(15 downto 0);
vn : std_ulogic;
vp : std_ulogic;
end record;
type grsysmon_out_type is record
alm : std_logic_vector(2 downto 0);
ot : std_ulogic;
eoc : std_ulogic;
eos : std_ulogic;
channel : std_logic_vector(4 downto 0);
end record;
constant grsysmon_in_gnd : grsysmon_in_type :=
('0', '0', (others => '0'), (others => '0'), '0', '0');
component grsysmon
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
caddr : integer := 16#000#; -- Base address for configuration area
cmask : integer := 16#fff#; -- Area mask
saddr : integer := 16#001#; -- Base address for sysmon register area
smask : integer := 16#fff#; -- Area mask
split : integer := 0; -- Enable AMBA SPLIT support
extconvst : integer := 0; -- Use external CONVST signal
wrdalign : integer := 0; -- Word align System Monitor registers
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "sysmon.txt");
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sysmoni : in grsysmon_in_type;
sysmono : out grsysmon_out_type
);
end component;
-----------------------------------------------------------------------------
-- AMBA System ACE Interface Controller
-----------------------------------------------------------------------------
type gracectrl_in_type is record
di : std_logic_vector(15 downto 0);
-- brdy : std_ulogic;
irq : std_ulogic;
end record;
type gracectrl_out_type is record
addr : std_logic_vector(6 downto 0);
do : std_logic_vector(15 downto 0);
cen : std_ulogic;
wen : std_ulogic;
oen : std_ulogic;
doen : std_ulogic; -- Data output enable to pad
end record;
constant gracectrl_none : gracectrl_out_type :=
((others => '1'), (others => '1'), '1', '1', '1', '1');
component gracectrl
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
haddr : integer := 16#000#; -- Base address
hmask : integer := 16#fff#; -- Area mask
split : integer range 0 to 1 := 0; -- Enable AMBA SPLIT support
swap : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0; -- Output enable polarity
mode : integer range 0 to 2 := 0 -- 16/8-bit mode
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
clkace : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
acei : in gracectrl_in_type;
aceo : out gracectrl_out_type
);
end component;
-----------------------------------------------------------------------------
-- General purpose register
-----------------------------------------------------------------------------
component grgpreg is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer range 1 to 64 := 16;
rstval : integer := 0;
rstval2 : integer := 0;
extrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gprego : out std_logic_vector(nbits-1 downto 0);
resval : in std_logic_vector(nbits-1 downto 0) := (others => '0')
);
end component;
component grgprbank is
generic (
pindex: integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
regbits: integer range 1 to 32 := 32;
nregs : integer range 1 to 32 := 1;
rstval: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
rego : out std_logic_vector(nregs*regbits-1 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- EDAC Memory scrubber
-----------------------------------------------------------------------------
type memscrub_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
clrcount: std_logic;
start : std_logic;
end record;
component memscrub is
generic(
hmindex : integer := 0;
hsindex : integer := 0;
ioaddr : integer := 0;
iomask : integer := 16#FFF#;
hirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3;
memwidth: integer := AHBDW;
-- Read block (cache line) burst size, must be even mult of 2
burstlen: integer := 2;
countlen: integer := 8
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
scrubi: in memscrub_in_type
);
end component;
type ahb_mst_iface_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type ahb_mst_iface_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
component ahb_mst_iface is
generic(
hindex : integer;
vendor : integer;
device : integer;
revision : integer);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
msti : in ahb_mst_iface_in_type;
msto : out ahb_mst_iface_out_type
);
end component;
-----------------------------------------------------------------------------
-- Clock gate unit
-----------------------------------------------------------------------------
component grclkgate
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
ungateen : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0); -- Only used with shared FPU
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2)*(ncpu/2-1) downto 0); -- Only used with shared FPU
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic);
end component;
component grclkgate2x
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
clk2xen : integer := 0; -- Enable double clocking
ungateen : integer := 0
);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2x : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0); -- Only used with shared FPU
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_ulogic;
clkahb2x : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2)*(ncpu/2-1) downto 0); -- Only used with shared FPU
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic
);
end component;
component ahbwbax is
generic (
ahbbits: integer;
blocksz: integer := 16;
mstmode: integer := 0
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
-- Wide-side slave inputs
wi_hready: in std_ulogic;
wi_hsel: in std_ulogic;
wi_htrans: in std_logic_vector(1 downto 0);
wi_hsize: in std_logic_vector(2 downto 0);
wi_hburst: in std_logic_vector(2 downto 0);
wi_hwrite: in std_ulogic;
wi_haddr: in std_logic_vector(31 downto 0);
wi_hwdata: in std_logic_vector(AHBDW-1 downto 0);
wi_hmbsel: in std_logic_vector(0 to NAHBAMR-1);
wi_hmaster: in std_logic_vector(3 downto 0);
wi_hprot: in std_logic_vector(3 downto 0);
wi_hmastlock: in std_ulogic;
-- Wide-side slave outputs
wo_hready: out std_ulogic;
wo_hresp : out std_logic_vector(1 downto 0);
wo_hrdata: out std_logic_vector(AHBDW-1 downto 0);
-- Narrow-side slave inputs
ni_hready: out std_ulogic;
ni_htrans: out std_logic_vector(1 downto 0);
ni_hsize: out std_logic_vector(2 downto 0);
ni_hburst: out std_logic_vector(2 downto 0);
ni_hwrite: out std_ulogic;
ni_haddr: out std_logic_vector(31 downto 0);
ni_hwdata: out std_logic_vector(31 downto 0);
ni_hmbsel: out std_logic_vector(0 to NAHBAMR-1);
ni_hmaster: out std_logic_vector(3 downto 0);
ni_hprot : out std_logic_vector(3 downto 0);
ni_hmastlock: out std_ulogic;
-- Narrow-side slave outputs
no_hready: in std_ulogic;
no_hresp: in std_logic_vector(1 downto 0);
no_hrdata: in std_logic_vector(31 downto 0)
);
end component;
component ahbswba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_type;
ahbsi_slv: out ahb_slv_in_type;
ahbso_slv: in ahb_slv_out_type
);
end component;
component ahbswbav is
generic (
slvmask: integer;
ahbbits: integer;
blocksz: integer
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_vector;
ahbsi_slv: out ahb_slv_in_vector_type(NAHBSLV-1 downto 0);
ahbso_slv: in ahb_slv_out_vector
);
end component;
component ahbmwba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbmo_mst : in ahb_mst_out_type;
ahbmi_mst: out ahb_mst_in_type;
ahbmo_bus: out ahb_mst_out_type;
ahbmi_bus: in ahb_mst_in_type
);
end component;
-----------------------------------------------------------------------------
-- GRPULSE
-----------------------------------------------------------------------------
component grpulse
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1; -- Interrupt index
nchannel: Integer := 24; -- Number of channels
npulse: Integer := 8; -- Channels with pulses
imask: Integer := 16#ff0000#; -- Interrupt mask
ioffset: Integer := 8; -- Interrupt offset
invertpulse: Integer := 0; -- Invert pulses
cntrwidth: Integer := 10; -- Width of counter
syncrst: Integer := 1; -- Only synchronous reset
oepol: Integer := 1); -- Output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpioi: in gpio_in_type;
gpioo: out gpio_out_type);
end component;
-----------------------------------------------------------------------------
-- GRTIMER
-----------------------------------------------------------------------------
component grtimer is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1;
sepirq: Integer := 1; -- separate interrupts
sbits: Integer := 10; -- scaler bits
ntimers: Integer range 1 to 7 := 2; -- number of timers
nbits: Integer := 32; -- timer bits
wdog: Integer := 0;
glatch: Integer := 0;
gextclk: Integer := 0;
gset: Integer := 0);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpti: in gptimer_in_type;
gpto: out gptimer_out_type);
end component;
-----------------------------------------------------------------------------
-- GRVERSION
-----------------------------------------------------------------------------
component grversion
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
versionnr: Integer := 16#0123#;
revisionnr: Integer := 16#4567#);
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AHBFROM - Microsemi/Actel Flash ROM
-----------------------------------------------------------------------------
component ahbfrom is
generic (
tech: integer := 0;
hindex: integer := 0;
haddr: integer := 0;
hmask: integer := 16#fff#;
width8: integer := 0;
memoryfile: string := "from.mem";
progfile: string := "from.ufc");
port (
rstn: in std_ulogic;
clk: in std_ulogic;
ahbi: in ahb_slv_in_type;
ahbo: out ahb_slv_out_type);
end component;
-----------------------------------------------------------------------------
-- Interrupt generator
-----------------------------------------------------------------------------
component irqgen
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ngen : integer range 1 to 15 := 1
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
-- function nandtree(v : std_logic_vector) return std_ulogic;
end;
package body misc is
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_membar(memaddr, prefetch, cache, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_iobar(memaddr, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
-- function nandtree(v : std_logic_vector) return std_ulogic is
-- variable a : std_logic_vector(v'length-1 downto 0);
-- variable b : std_logic_vector(v'length downto 0);
-- begin
--
-- a := v; b(0) := '1';
--
-- for i in 0 to v'length-1 loop
-- b(i+1) := a(i) nand b(i);
-- end loop;
--
-- return b(v'length);
--
-- end;
end;
| gpl-2.0 | 0963ec5171f5da526ba333f79c0d3895 | 0.507555 | 3.739605 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-avnet-xc2v1500/leon3mp.vhd | 1 | 19,036 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
clk125 : in std_logic;
errorn : out std_logic;
flash_rstn : out std_logic;
addr : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(15 downto 0);
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
romsn : out std_logic;
ddr_clk : out std_logic_vector(1 downto 0);
ddr_clkb : out std_logic_vector(1 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_logic; -- ddr write enable
ddr_rasb : out std_logic; -- ddr ras
ddr_casb : out std_logic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1+CFG_PCI;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, clkml, rstn, rstraw, pciclk, clkddr, ddrlock : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, rst, ndsuact : std_logic;
signal tck, tckn, tms, tdi, tdo : std_logic;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
signal lresetn, lclk125, lock : std_logic;
constant BOARD_FREQ : integer := 40000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
constant DDR_FREQ : integer := 125; --(CFG_DDRSP_FREQ/10)*10; -- DDR frequency in MHz
signal stati : ahbstat_in_type;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, CFG_PCI,
CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ, 0)
port map (lclk, pci_clk, clkm, open, open, open, pciclk, cgi, cgo);
resetn_pad : clkpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
flash_rstn_pad : outpad generic map (tech => padtech)
port map (flash_rstn, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- dcomgen : if CFG_AHB_UART = 1 generate
-- dcom0: ahbuart -- Debug UART
-- generic map (hindex => NCPU, pindex => 7, paddr => 7)
-- port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
-- end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ramaddr => 16#C00#, rammask => 16#FFF#, iomask => 0,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (addr, memo.address(28 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
writen_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk125, lclk125);
ddr0 : ddrspa generic map (
fabtech => virtex2, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => DDR_FREQ,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000 )
port map (lresetn, rstn, lclk125, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk <= ddr_clkv(1 downto 0); ddr_clkb <= ddr_clkbv(1 downto 0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 16)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
nopads : if CFG_AHB_UART = 0 generate
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
end generate;
upads : if CFG_AHB_UART = 1 generate
u1i.rxd <= u1o.txd;
end generate;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
-- pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
-- port map (pci_clk, pciclk);
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 0)-- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 7, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet Virtex2 XC2V1500 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 92fe4d874e5eb3d0c86d7b672c1c87a6 | 0.562198 | 3.527145 | false | false | false | false |
jkff90/verification | packages/altera/altera_avalon_components_pkg.vhd | 1 | 31,544 | -- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-- $File: //acds/rel/13.1/ip/sopc/components/verification/lib/altera_avalon_components_pkg.vhd $
-- $Revision: #1 $
-- $Date: 2013/08/11 $
-- $Author: swbranch $
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.all;
package altera_avalon_components_pkg is
-----------------------------------------------------------------------------
-- Avalon Interrupt Source
-----------------------------------------------------------------------------
type irq_source_method_id is (IRQ_SRC_SET_IRQ,
IRQ_SRC_CLEAR_IRQ);
function conv_std_logic (
method : irq_source_method_id
) return std_logic;
component altera_avalon_interrupt_source_api_wrapper
generic (AV_DATA_W : integer := 32;
AV_ADDR_W : integer := 8
);
port (
api_clk : in std_logic;
api_reset : in std_logic;
api_call_method : in std_logic;
api_call_data : in std_logic;
api_call_valid : in std_logic;
api_return_method : out std_logic;
api_return_data : out std_logic;
api_return_valid : out std_logic;
av_clk : in std_logic;
av_reset : in std_logic;
avs_waitrequest : out std_logic;
avs_readdatavalid : out std_logic;
avs_readdata : out std_logic_vector(AV_DATA_W-1 downto 0);
avs_write : in std_logic;
avs_read : in std_logic;
avs_address : in std_logic_vector(AV_ADDR_W-1 downto 0);
avs_writedata : in std_logic_vector(AV_DATA_W-1 downto 0);
irq : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Avalon Interrupt Sink
-----------------------------------------------------------------------------
type irq_sink_method_id is (IRQ_SINK_GET_IRQ,
IRQ_SINK_CLEAR_IRQ);
function conv_std_logic (
method : irq_sink_method_id
) return std_logic;
component altera_avalon_interrupt_sink_api_wrapper
generic (AV_DATA_W : integer := 32;
AV_ADDR_W : integer := 8;
AV_IRQ_W : integer := 1
);
port (
api_clk : in std_logic;
api_reset : in std_logic;
api_call_method : in std_logic;
api_call_data : in std_logic;
api_call_valid : in std_logic;
api_return_method : out std_logic;
api_return_data : out std_logic_vector(AV_IRQ_W-1 downto 0);
api_return_valid : out std_logic;
av_clk : in std_logic;
av_reset : in std_logic;
avm_waitrequest : in std_logic;
avm_readdatavalid : in std_logic;
avm_readdata : in std_logic_vector(AV_DATA_W-1 downto 0);
avm_write : out std_logic;
avm_read : out std_logic;
avm_address : out std_logic_vector(AV_ADDR_W-1 downto 0);
avm_writedata : out std_logic_vector(AV_DATA_W-1 downto 0);
irq : in std_logic_vector(AV_IRQ_W-1 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- Avalon Streaming Source API Wrapper
-----------------------------------------------------------------------------
type st_source_signal_index is (
ST_SRC_SIGNAL_READY,
ST_SRC_SIGNAL_NOT_READY,
ST_SRC_SIGNAL_TRANS_COMPLETE,
ST_SRC_SIGNAL_DRIVING_TRANS,
ST_SRC_SIGNAL_RESERVED_4,
ST_SRC_SIGNAL_RESERVED_5,
ST_SRC_SIGNAL_RESERVED_6,
ST_SRC_SIGNAL_RESERVED_7);
type st_source_method_id is (
ST_SRC_INIT,
ST_SRC_SET_RESP_TIMEOUT,
ST_SRC_PUSH_TRANS,
ST_SRC_GET_TRANS_QUEUE_SIZE,
ST_SRC_GET_RESP_QUEUE_SIZE,
ST_SRC_SET_TRANS_DATA,
ST_SRC_SET_TRANS_CHANNEL,
ST_SRC_SET_TRANS_IDLES,
ST_SRC_SET_TRANS_SOP,
ST_SRC_SET_TRANS_EOP,
ST_SRC_SET_TRANS_ERROR,
ST_SRC_SET_TRANS_EMPTY,
ST_SRC_POP_RESP,
ST_SRC_GET_RESP_LATENCY,
ST_SRC_GET_SRC_READY,
ST_SRC_GET_SRC_TRANS_COMPLETE);
function conv_integer (
sig : st_source_signal_index
) return integer;
function conv_std_logic (
method : st_source_method_id
) return std_logic_vector;
component altera_avalon_st_source_api_wrapper
generic (
ST_SYMBOL_W : integer := 8;
ST_NUMSYMBOLS : integer := 4;
ST_CHANNEL_W : integer := 0;
ST_ERROR_W : integer := 0;
ST_EMPTY_W : integer := 0;
ST_READY_LATENCY: integer := 0;
ST_MAX_CHANNELS : integer := 1;
USE_PACKET : integer := 1;
USE_CHANNEL : integer := 1;
USE_ERROR : integer := 1;
USE_READY : integer := 1;
USE_VALID : integer := 1;
USE_EMPTY : integer := 1;
API_CALL_DATA_W : integer := 32;
API_RETURN_DATA_W : integer := 32
);
port (
api_clk : in std_logic;
api_reset : in std_logic;
api_call_method : in std_logic_vector(7 downto 0);
api_call_data : in std_logic_vector(API_CALL_DATA_W-1 downto 0);
api_call_valid : in std_logic;
api_return_method : out std_logic_vector(7 downto 0);
api_return_data : out std_logic_vector(31 downto 0);
api_return_valid : out std_logic;
api_event_data : out std_logic_vector(7 downto 0);
api_event_valid : out std_logic;
av_clk : in std_logic;
av_reset : in std_logic;
src_data : out std_logic_vector(
ST_SYMBOL_W*ST_NUMSYMBOLS-1 downto 0);
src_channel : out std_logic_vector(ST_CHANNEL_W-1 downto 0);
src_valid : out std_logic;
src_startofpacket : out std_logic;
src_endofpacket : out std_logic;
src_error : out std_logic_vector(ST_ERROR_W-1 downto 0);
src_empty : out std_logic_vector(ST_EMPTY_W-1 downto 0);
src_ready : in std_logic
);
end component;
-----------------------------------------------------------------------------
-- Avalon Streaming Sink
-----------------------------------------------------------------------------
type st_sink_signal_index is (
ST_SINK_SIGNAL_TRANS_RECEIVED,
ST_SINK_SIGNAL_READY_ASSERT,
ST_SINK_SIGNAL_READY_DEASSERT,
ST_SINK_SIGNAL_RESERVED_3,
ST_SINK_SIGNAL_RESERVED_4,
ST_SINK_SIGNAL_RESERVED_5,
ST_SINK_SIGNAL_RESERVED_6,
ST_SINK_SIGNAL_RESERVED_7
);
type st_sink_method_id is (
ST_SINK_INIT,
ST_SINK_SET_READY,
ST_SINK_POP_TRANS,
ST_SINK_GET_TRANS_IDLES,
ST_SINK_GET_TRANS_DATA,
ST_SINK_GET_TRANS_CHANNEL,
ST_SINK_GET_TRANS_SOP,
ST_SINK_GET_TRANS_EOP,
ST_SINK_GET_TRANS_ERROR,
ST_SINK_GET_TRANS_EMPTY,
ST_SINK_GET_TRANS_QUEUE_SIZE
);
function conv_integer (
sig : st_sink_signal_index
) return integer;
function conv_std_logic (
method : st_sink_method_id
) return std_logic_vector;
component altera_avalon_st_sink_api_wrapper
generic (
ST_SYMBOL_W : integer := 8;
ST_NUMSYMBOLS : integer := 4;
ST_CHANNEL_W : integer := 0;
ST_ERROR_W : integer := 0;
ST_EMPTY_W : integer := 0;
ST_READY_LATENCY: integer := 0;
ST_MAX_CHANNELS : integer := 1;
USE_PACKET : integer := 1;
USE_CHANNEL : integer := 1;
USE_ERROR : integer := 1;
USE_READY : integer := 1;
USE_VALID : integer := 1;
USE_EMPTY : integer := 1;
API_CALL_DATA_W : integer := 32;
API_RETURN_DATA_W : integer := 32
);
port (
api_clk : in std_logic;
api_reset : in std_logic;
api_call_method : in std_logic_vector(7 downto 0);
api_call_data : in std_logic_vector(31 downto 0);
api_call_valid : in std_logic;
api_return_method : out std_logic_vector(7 downto 0);
api_return_data : out std_logic_vector(API_RETURN_DATA_W downto 0);
api_return_valid : out std_logic;
api_event_data : out std_logic_vector(7 downto 0);
api_event_valid : out std_logic;
av_clk : in std_logic;
av_reset : in std_logic;
sink_data : in std_logic_vector(
ST_SYMBOL_W*ST_NUMSYMBOLS-1 downto 0);
sink_channel : in std_logic_vector(ST_CHANNEL_W-1 downto 0);
sink_valid : in std_logic;
sink_startofpacket : in std_logic;
sink_endofpacket : in std_logic;
sink_error : in std_logic_vector(ST_ERROR_W-1 downto 0);
sink_empty : in std_logic_vector(ST_EMPTY_W-1 downto 0);
sink_ready : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Avalon MM Master
-----------------------------------------------------------------------------
type mm_mstr_signal_index is (
MM_MSTR_SIGNAL_FATAL_ERROR ,
MM_MSTR_SIGNAL_RESPONSE_COMPLETE ,
MM_MSTR_SIGNAL_COMMAND_ISSUED ,
MM_MSTR_SIGNAL_ALL_TRANS_COMPLETE ,
MM_MSTR_SIGNAL_RESERVED_4 ,
MM_MSTR_SIGNAL_RESERVED_5 ,
MM_MSTR_SIGNAL_RESERVED_6 ,
MM_MSTR_SIGNAL_RESERVED_7
);
type mm_mstr_method_id is (
MM_MSTR_INIT ,
MM_MSTR_SET_RESP_TIMEOUT ,
MM_MSTR_SET_CMD_TIMEOUT ,
MM_MSTR_ALL_TRANS_COMPLETE ,
MM_MSTR_GET_CMD_ISSUE_QUEUE_SIZE ,
MM_MSTR_GET_CMD_PEND_QUEUE_SIZE ,
MM_MSTR_GET_RESP_QUEUE_SIZE ,
MM_MSTR_PUSH_CMD ,
MM_MSTR_POP_RESP ,
MM_MSTR_SET_CMD_DATA ,
MM_MSTR_SET_CMD_ADDRESS ,
MM_MSTR_SET_CMD_BYTE_ENABLE ,
MM_MSTR_SET_CMD_BURST_COUNT ,
MM_MSTR_SET_CMD_IDLE ,
MM_MSTR_SET_CMD_REQUEST ,
MM_MSTR_SET_CMD_RESERVED_1 ,
MM_MSTR_GET_RESP_REQUEST ,
MM_MSTR_GET_RESP_DATA ,
MM_MSTR_GET_RESP_ADDRESS ,
MM_MSTR_GET_RESP_BYTE_ENABLE ,
MM_MSTR_GET_RESP_BURST_SIZE ,
MM_MSTR_GET_RESP_LATENCY ,
MM_MSTR_GET_RESP_WAIT_TIME ,
MM_MSTR_SET_CMD_INIT_LATENCY ,
MM_MSTR_SET_CMD_BURST_SIZE
);
function conv_integer (
sig : mm_mstr_signal_index
) return integer;
function conv_std_logic (
method : mm_mstr_method_id
) return std_logic_vector;
component altera_avalon_mm_master_bfm_api_wrapper
generic (
AV_ADDRESS_W : integer := 32;
AV_SYMBOL_W : integer := 8;
AV_NUMSYMBOLS : integer := 4;
AV_BURSTCOUNT_W : integer := 3;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_ADDRESS : integer := 1;
USE_BYTE_ENABLE : integer := 1;
USE_BURSTCOUNT : integer := 1;
USE_READ_DATA : integer := 1;
USE_READ_DATA_VALID : integer := 1;
USE_WRITE_DATA : integer := 1;
USE_BEGIN_TRANSFER : integer := 1;
USE_BEGIN_BURST_TRANSFER : integer := 1;
USE_WAIT_REQUEST : integer := 1;
AV_FIX_READ_LATENCY : integer := 0;
AV_MAX_PENDING_READS : integer := 1;
AV_BURST_LINEWRAP : integer := 0;
AV_BURST_BNDR_ONLY : integer := 0;
API_CALL_DATA_W : integer := 64;
API_RETURN_DATA_W : integer := 64
);
port (
api_clk : in std_logic;
api_reset : in std_logic;
api_call_method : in std_logic_vector(7 downto 0);
api_call_data : in std_logic_vector(API_CALL_DATA_W-1 downto 0);
api_call_valid : in std_logic;
api_return_method : out std_logic_vector(7 downto 0);
api_return_data : out std_logic_vector(API_RETURN_DATA_W-1 downto 0);
api_return_valid : out std_logic;
api_event_data : out std_logic_vector(7 downto 0);
api_event_valid : out std_logic;
avm_clk : in std_logic;
avm_reset : in std_logic;
avm_waitrequest : in std_logic;
avm_readdatavalid : in std_logic;
avm_readdata : in std_logic_vector((AV_SYMBOL_W*AV_NUMSYMBOLS)-1 downto 0);
avm_write : out std_logic;
avm_read : out std_logic;
avm_address : out std_logic_vector(AV_ADDRESS_W-1 downto 0);
avm_byteenable : out std_logic_vector(AV_NUMSYMBOLS-1 downto 0);
avm_burstcount : out std_logic_vector(AV_BURSTCOUNT_W-1 downto 0);
avm_beginbursttransfer : out std_logic;
avm_begintransfer : out std_logic;
avm_writedata : out std_logic_vector((AV_SYMBOL_W*AV_NUMSYMBOLS)-1 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- Avalon MM Slave
-----------------------------------------------------------------------------
type mm_slv_signal_index is (
MM_SLV_SIGNAL_FATAL_ERROR ,
MM_SLV_SIGNAL_ERROR_EXCEED_MAX_PENDING_READS,
MM_SLV_SIGNAL_COMMAND_RECEIVED ,
MM_SLV_SIGNAL_RESP_ISSUED ,
MM_SLV_SIGNAL_RESERVED_4 ,
MM_SLV_SIGNAL_RESERVED_5 ,
MM_SLV_SIGNAL_RESERVED_6 ,
MM_SLV_SIGNAL_RESERVED_7
);
type mm_slv_method_id is (
MM_SLV_INIT ,
MM_SLV_SET_RESP_TIMEOUT ,
MM_SLV_GET_CMD_QUEUE_SIZE ,
MM_SLV_GET_RESP_QUEUE_SIZE ,
MM_SLV_PUSH_RESP ,
MM_SLV_POP_CMD ,
MM_SLV_SET_RESP_DATA ,
MM_SLV_SET_RESP_BURST_SIZE ,
MM_SLV_SET_RESP_LATENCY ,
MM_SLV_SET_INTERFACE_WAIT_TIME ,
MM_SLV_GET_CMD_REQUEST ,
MM_SLV_GET_CMD_DATA ,
MM_SLV_GET_CMD_ADDRESS ,
MM_SLV_GET_CMD_BYTE_ENABLE ,
MM_SLV_GET_CMD_BURST_COUNT ,
MM_SLV_GET_CMD_BURST_CYCLE
);
function conv_integer (
sig : mm_slv_signal_index
) return integer;
function conv_std_logic (
method : mm_slv_method_id
) return std_logic_vector;
component altera_avalon_mm_slave_bfm_api_wrapper
generic (
AV_ADDRESS_W : integer := 32;
AV_SYMBOL_W : integer := 8;
AV_NUMSYMBOLS : integer := 4;
AV_BURSTCOUNT_W : integer := 3;
USE_READ : integer := 1;
USE_WRITE : integer := 1;
USE_ADDRESS : integer := 1;
USE_BYTE_ENABLE : integer := 1;
USE_BURSTCOUNT : integer := 1;
USE_READ_DATA : integer := 1;
USE_READ_DATA_VALID : integer := 1;
USE_WRITE_DATA : integer := 1;
USE_BEGIN_TRANSFER : integer := 1;
USE_BEGIN_BURST_TRANSFER : integer := 1;
USE_WAIT_REQUEST : integer := 1;
AV_FIX_READ_LATENCY : integer := 0;
AV_MAX_PENDING_READS : integer := 1;
AV_BURST_LINEWRAP : integer := 0;
AV_BURST_BNDR_ONLY : integer := 0;
AV_READ_WAIT_TIME : integer := 0;
AV_WRITE_WAIT_TIME : integer := 0;
API_CALL_DATA_W : integer := 64;
API_RETURN_DATA_W : integer := 64
);
port (
api_clk : in std_logic;
api_reset : in std_logic;
api_call_method : in std_logic_vector(7 downto 0);
api_call_data : in std_logic_vector(API_CALL_DATA_W-1 downto 0);
api_call_valid : in std_logic;
api_return_method : out std_logic_vector(7 downto 0);
api_return_data : out std_logic_vector(API_RETURN_DATA_W-1 downto 0);
api_return_valid : out std_logic;
api_event_data : out std_logic_vector(7 downto 0);
api_event_valid : out std_logic;
avs_clk : in std_logic;
avs_reset : in std_logic;
avs_waitrequest : out std_logic;
avs_readdatavalid : out std_logic;
avs_readdata : out std_logic_vector((AV_SYMBOL_W*AV_NUMSYMBOLS)-1 downto 0);
avs_write : in std_logic;
avs_read : in std_logic;
avs_address : in std_logic_vector(AV_ADDRESS_W-1 downto 0);
avs_byteenable : in std_logic_vector(AV_NUMSYMBOLS-1 downto 0);
avs_burstcount : in std_logic_vector(AV_BURSTCOUNT_W-1 downto 0);
avs_beginbursttransfer : in std_logic;
avs_begintransfer : in std_logic;
avs_writedata : in std_logic_vector((AV_SYMBOL_W*AV_NUMSYMBOLS)-1 downto 0)
);
end component;
end altera_avalon_components_pkg;
package body altera_avalon_components_pkg is
-----------------------------------------------------------------------------
-- Avalon Interrupt Source
-----------------------------------------------------------------------------
function conv_std_logic (
method : irq_source_method_id
) return std_logic is
begin
case method is
when IRQ_SRC_SET_IRQ => return '0';
when IRQ_SRC_CLEAR_IRQ => return '1';
when others => return 'X';
end case;
end function conv_std_logic;
-----------------------------------------------------------------------------
-- Avalon Interrupt Sink
-----------------------------------------------------------------------------
function conv_std_logic (
method : irq_sink_method_id
) return std_logic is
begin
case method is
when IRQ_SINK_GET_IRQ => return '0';
when IRQ_SINK_CLEAR_IRQ => return '1';
when others => return 'X';
end case;
end function conv_std_logic;
-----------------------------------------------------------------------------
-- Avalon ST Source
-----------------------------------------------------------------------------
function conv_integer (
sig : st_source_signal_index
) return integer is
begin
case sig is
when ST_SRC_SIGNAL_READY => return 0;
when ST_SRC_SIGNAL_NOT_READY => return 1;
when ST_SRC_SIGNAL_TRANS_COMPLETE => return 2;
when ST_SRC_SIGNAL_DRIVING_TRANS => return 3;
when ST_SRC_SIGNAL_RESERVED_4 => return 4;
when ST_SRC_SIGNAL_RESERVED_5 => return 5;
when ST_SRC_SIGNAL_RESERVED_6 => return 6;
when ST_SRC_SIGNAL_RESERVED_7 => return 7;
when others => return -1;
end case;
end function conv_integer;
function conv_std_logic (
method : st_source_method_id
) return std_logic_vector is
begin
case method is
when ST_SRC_INIT => return X"00";
when ST_SRC_SET_RESP_TIMEOUT => return X"01";
when ST_SRC_PUSH_TRANS => return X"02";
when ST_SRC_GET_TRANS_QUEUE_SIZE => return X"03";
when ST_SRC_GET_RESP_QUEUE_SIZE => return X"04";
when ST_SRC_SET_TRANS_DATA => return X"05";
when ST_SRC_SET_TRANS_CHANNEL => return X"06";
when ST_SRC_SET_TRANS_IDLES => return X"07";
when ST_SRC_SET_TRANS_SOP => return X"08";
when ST_SRC_SET_TRANS_EOP => return X"09";
when ST_SRC_SET_TRANS_ERROR => return X"0A";
when ST_SRC_SET_TRANS_EMPTY => return X"0B";
when ST_SRC_POP_RESP => return X"0C";
when ST_SRC_GET_RESP_LATENCY => return X"0D";
when ST_SRC_GET_SRC_READY => return X"0E";
when ST_SRC_GET_SRC_TRANS_COMPLETE => return X"0F";
when others => return X"FF";
end case;
end function conv_std_logic;
-----------------------------------------------------------------------------
-- Avalon ST Sink
-----------------------------------------------------------------------------
function conv_integer (
sig : st_sink_signal_index
) return integer is
begin
case sig is
when ST_SINK_SIGNAL_TRANS_RECEIVED => return 0;
when ST_SINK_SIGNAL_READY_ASSERT => return 1;
when ST_SINK_SIGNAL_READY_DEASSERT => return 2;
when ST_SINK_SIGNAL_RESERVED_3 => return 3;
when ST_SINK_SIGNAL_RESERVED_4 => return 4;
when ST_SINK_SIGNAL_RESERVED_5 => return 5;
when ST_SINK_SIGNAL_RESERVED_6 => return 6;
when ST_SINK_SIGNAL_RESERVED_7 => return 7;
when others => return -1;
end case;
end function conv_integer;
function conv_std_logic (
method : st_sink_method_id
) return std_logic_vector is
begin
case method is
when ST_SINK_INIT => return X"00";
when ST_SINK_SET_READY => return X"01";
when ST_SINK_POP_TRANS => return X"02";
when ST_SINK_GET_TRANS_IDLES => return X"03";
when ST_SINK_GET_TRANS_DATA => return X"04";
when ST_SINK_GET_TRANS_CHANNEL => return X"05";
when ST_SINK_GET_TRANS_SOP => return X"06";
when ST_SINK_GET_TRANS_EOP => return X"07";
when ST_SINK_GET_TRANS_ERROR => return X"08";
when ST_SINK_GET_TRANS_EMPTY => return X"09";
when ST_SINK_GET_TRANS_QUEUE_SIZE => return X"0A";
when others => return X"FF";
end case;
end function conv_std_logic;
-----------------------------------------------------------------------------
-- Avalon MM Master
-----------------------------------------------------------------------------
function conv_integer (
sig : mm_mstr_signal_index
) return integer is
begin
case sig is
when MM_MSTR_SIGNAL_FATAL_ERROR => return 0;
when MM_MSTR_SIGNAL_RESPONSE_COMPLETE => return 1;
when MM_MSTR_SIGNAL_COMMAND_ISSUED => return 2;
when MM_MSTR_SIGNAL_ALL_TRANS_COMPLETE => return 3;
when MM_MSTR_SIGNAL_RESERVED_4 => return 4;
when MM_MSTR_SIGNAL_RESERVED_5 => return 5;
when MM_MSTR_SIGNAL_RESERVED_6 => return 6;
when MM_MSTR_SIGNAL_RESERVED_7 => return 7;
when others => return -1;
end case;
end function conv_integer;
function conv_std_logic (
method : mm_mstr_method_id
) return std_logic_vector is
begin
case method is
when MM_MSTR_INIT => return X"00";
when MM_MSTR_SET_RESP_TIMEOUT => return X"01";
when MM_MSTR_SET_CMD_TIMEOUT => return X"02";
when MM_MSTR_ALL_TRANS_COMPLETE => return X"03";
when MM_MSTR_GET_CMD_ISSUE_QUEUE_SIZE => return X"04";
when MM_MSTR_GET_CMD_PEND_QUEUE_SIZE => return X"05";
when MM_MSTR_GET_RESP_QUEUE_SIZE => return X"06";
when MM_MSTR_PUSH_CMD => return X"07";
when MM_MSTR_POP_RESP => return X"08";
when MM_MSTR_SET_CMD_DATA => return X"09";
when MM_MSTR_SET_CMD_ADDRESS => return X"0A";
when MM_MSTR_SET_CMD_BYTE_ENABLE => return X"0B";
when MM_MSTR_SET_CMD_BURST_COUNT => return X"0C";
when MM_MSTR_SET_CMD_IDLE => return X"0D";
when MM_MSTR_SET_CMD_REQUEST => return X"0E";
when MM_MSTR_SET_CMD_RESERVED_1 => return X"0F";
when MM_MSTR_GET_RESP_REQUEST => return X"10";
when MM_MSTR_GET_RESP_DATA => return X"11";
when MM_MSTR_GET_RESP_ADDRESS => return X"12";
when MM_MSTR_GET_RESP_BYTE_ENABLE => return X"13";
when MM_MSTR_GET_RESP_BURST_SIZE => return X"14";
when MM_MSTR_GET_RESP_LATENCY => return X"15";
when MM_MSTR_GET_RESP_WAIT_TIME => return X"16";
when MM_MSTR_SET_CMD_INIT_LATENCY => return X"17";
when MM_MSTR_SET_CMD_BURST_SIZE => return X"18";
when others => return X"FF";
end case;
end function conv_std_logic;
-----------------------------------------------------------------------------
-- Avalon MM Slave
-----------------------------------------------------------------------------
function conv_integer (
sig : mm_slv_signal_index
) return integer is
begin
case sig is
when MM_SLV_SIGNAL_FATAL_ERROR => return 0;
when MM_SLV_SIGNAL_ERROR_EXCEED_MAX_PENDING_READS => return 1;
when MM_SLV_SIGNAL_COMMAND_RECEIVED => return 2;
when MM_SLV_SIGNAL_RESP_ISSUED => return 3;
when MM_SLV_SIGNAL_RESERVED_4 => return 4;
when MM_SLV_SIGNAL_RESERVED_5 => return 5;
when MM_SLV_SIGNAL_RESERVED_6 => return 6;
when MM_SLV_SIGNAL_RESERVED_7 => return 7;
when others => return -1;
end case;
end function conv_integer;
function conv_std_logic (
method : mm_slv_method_id
) return std_logic_vector is
begin
case method is
when MM_SLV_INIT => return X"00";
when MM_SLV_SET_RESP_TIMEOUT => return X"01";
when MM_SLV_GET_CMD_QUEUE_SIZE => return X"02";
when MM_SLV_GET_RESP_QUEUE_SIZE => return X"03";
when MM_SLV_PUSH_RESP => return X"04";
when MM_SLV_POP_CMD => return X"05";
when MM_SLV_SET_RESP_DATA => return X"06";
when MM_SLV_SET_RESP_BURST_SIZE => return X"07";
when MM_SLV_SET_RESP_LATENCY => return X"08";
when MM_SLV_SET_INTERFACE_WAIT_TIME => return X"09";
when MM_SLV_GET_CMD_REQUEST => return X"0A";
when MM_SLV_GET_CMD_DATA => return X"0B";
when MM_SLV_GET_CMD_ADDRESS => return X"0C";
when MM_SLV_GET_CMD_BYTE_ENABLE => return X"0D";
when MM_SLV_GET_CMD_BURST_COUNT => return X"0E";
when MM_SLV_GET_CMD_BURST_CYCLE => return X"0F";
when others => return X"FF";
end case;
end function conv_std_logic;
end package body altera_avalon_components_pkg;
| gpl-3.0 | 564bd73bfe21808672ffa17f6d65c3ac | 0.44411 | 4.125556 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_cmd_split.vhd | 2 | 22,474 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
entity axi_dma_cmd_split is
generic (
C_ADDR_WIDTH : integer range 32 to 64 := 32;
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
C_INCLUDE_S2MM : integer range 0 to 1 := 0
);
port (
clock : in std_logic;
sgresetn : in std_logic;
clock_sec : in std_logic;
aresetn : in std_logic;
-- command coming from _MNGR
s_axis_cmd_tvalid : in std_logic;
s_axis_cmd_tready : out std_logic;
s_axis_cmd_tdata : in std_logic_vector ((2*C_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0);
-- split command to DM
s_axis_cmd_tvalid_s : out std_logic;
s_axis_cmd_tready_s : in std_logic;
s_axis_cmd_tdata_s : out std_logic_vector ((C_ADDR_WIDTH+CMD_BASE_WIDTH+8)-1 downto 0);
-- Tvalid from Datamover
tvalid_from_datamover : in std_logic;
status_in : in std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
tvalid_unsplit : out std_logic;
status_out : out std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
-- Tlast of stream data from Datamover
tlast_stream_data : in std_logic;
tready_stream_data : in std_logic;
tlast_unsplit : out std_logic;
tlast_unsplit_user : out std_logic
);
end entity axi_dma_cmd_split;
architecture implementation of axi_dma_cmd_split is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
type SPLIT_MM2S_STATE_TYPE is (
IDLE,
SEND,
SPLIT
);
signal mm2s_cs : SPLIT_MM2S_STATE_TYPE;
signal mm2s_ns : SPLIT_MM2S_STATE_TYPE;
signal mm2s_cmd : std_logic_vector (2*C_ADDR_WIDTH+CMD_BASE_WIDTH+46-1 downto 0);
signal command_ns : std_logic_vector (2*C_ADDR_WIDTH+CMD_BASE_WIDTH-1 downto 0);
signal command : std_logic_vector (2*C_ADDR_WIDTH+CMD_BASE_WIDTH-1 downto 0);
signal cache_info : std_logic_vector (31 downto 0);
signal vsize_data : std_logic_vector (22 downto 0);
signal vsize_data_int : std_logic_vector (22 downto 0);
signal vsize : std_logic_vector (22 downto 0);
signal counter : std_logic_vector (22 downto 0);
signal counter_tlast : std_logic_vector (22 downto 0);
signal split_cmd : std_logic_vector (31 downto 0);
signal stride_data : std_logic_vector (22 downto 0);
signal vsize_over : std_logic;
signal cmd_proc_cdc_from : std_logic;
signal cmd_proc_cdc_to : std_logic;
signal cmd_proc_cdc : std_logic;
signal cmd_proc_ns : std_logic;
ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF cmd_proc_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF cmd_proc_cdc : SIGNAL IS "true";
signal cmd_out : std_logic;
signal cmd_out_ns : std_logic;
signal split_out : std_logic;
signal split_out_ns : std_logic;
signal command_valid : std_logic;
signal command_valid_ns : std_logic;
signal command_ready : std_logic;
signal reset_lock : std_logic;
signal reset_lock_tlast : std_logic;
signal tvalid_unsplit_int : std_logic;
signal tlast_stream_data_int : std_logic;
signal ready_for_next_cmd : std_logic;
signal ready_for_next_cmd_tlast : std_logic;
signal ready_for_next_cmd_tlast_cdc_from : std_logic;
signal ready_for_next_cmd_tlast_cdc_to : std_logic;
signal ready_for_next_cmd_tlast_cdc : std_logic;
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc : SIGNAL IS "true";
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal tlast_int : std_logic;
signal eof_bit : std_logic;
signal eof_bit_cdc_from : std_logic;
signal eof_bit_cdc_to : std_logic;
signal eof_bit_cdc : std_logic;
signal eof_set : std_logic;
signal over_ns, over : std_logic;
signal cmd_in : std_logic;
signal status_out_int : std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
begin
s_axis_cmd_tvalid_s <= command_valid;
command_ready <= s_axis_cmd_tready_s;
s_axis_cmd_tdata_s <= command (103 downto 96) & command (71 downto 0);
REGISTER_STATE_MM2S : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cs <= IDLE;
cmd_proc_cdc_from <= '0';
cmd_out <= '0';
command <= (others => '0');
command_valid <= '0';
split_out <= '0';
over <= '0';
else
mm2s_cs <= mm2s_ns;
cmd_proc_cdc_from <= cmd_proc_ns;
cmd_out <= cmd_out_ns;
command <= command_ns;
command_valid <= command_valid_ns;
split_out <= split_out_ns;
over <= over_ns;
end if;
end if;
end process REGISTER_STATE_MM2S;
-- grab the MM2S command coming from MM2S_mngr
REGISTER_MM2S_CMD : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cmd <= (others => '0');
s_axis_cmd_tready <= '0';
cache_info <= (others => '0');
vsize_data <= (others => '0');
vsize_data_int <= (others => '0');
stride_data <= (others => '0');
eof_bit_cdc_from <= '0';
cmd_in <= '0';
elsif (s_axis_cmd_tvalid = '1' and ready_for_next_cmd = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd_tlast_cdc = '1') then -- when there is no processing being done, means it is ready to accept
mm2s_cmd <= s_axis_cmd_tdata;
s_axis_cmd_tready <= '1';
cache_info <= s_axis_cmd_tdata (149 downto 118);
vsize_data <= s_axis_cmd_tdata (117 downto 95);
vsize_data_int <= s_axis_cmd_tdata (117 downto 95) - '1';
stride_data <= s_axis_cmd_tdata (94 downto 72);
eof_bit_cdc_from <= s_axis_cmd_tdata (30);
cmd_in <= '1';
else
mm2s_cmd <= mm2s_cmd; --split_cmd;
vsize_data <= vsize_data;
vsize_data_int <= vsize_data_int;
stride_data <= stride_data;
cache_info <= cache_info;
s_axis_cmd_tready <= '0';
eof_bit_cdc_from <= eof_bit_cdc_from;
cmd_in <= '0';
end if;
end if;
end process REGISTER_MM2S_CMD;
REGISTER_DECR_VSIZE : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
vsize <= "00000000000000000000000";
elsif (command_valid = '1' and command_ready = '1' and (vsize < vsize_data_int)) then -- sending a cmd out to DM
vsize <= vsize + '1';
elsif (cmd_proc_cdc_from = '0') then -- idle or when all cmd are sent to DM
vsize <= "00000000000000000000000";
else
vsize <= vsize;
end if;
end if;
end process REGISTER_DECR_VSIZE;
vsize_over <= '1' when (vsize = vsize_data_int) else '0';
-- eof_set <= eof_bit when (vsize = vsize_data_int) else '0';
REGISTER_SPLIT : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
split_cmd <= (others => '0');
elsif (s_axis_cmd_tvalid = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd = '1' and ready_for_next_cmd_tlast_cdc = '1') then
split_cmd <= s_axis_cmd_tdata (63 downto 32); -- capture the ba when a new cmd arrives
elsif (split_out = '1') then -- add stride to previous ba
split_cmd <= split_cmd + stride_data;
else
split_cmd <= split_cmd;
end if;
end if;
end process REGISTER_SPLIT;
MM2S_MACHINE : process(mm2s_cs,
s_axis_cmd_tvalid,
cmd_proc_cdc_from,
vsize_over, command_ready,
cache_info, mm2s_cmd,
split_cmd, eof_set,
cmd_in, command
)
begin
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
mm2s_ns <= mm2s_cs;
command_ns <= command;
-- Default signal assignment
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
if (cmd_in = '1' and cmd_proc_cdc_from = '0') then
cmd_proc_ns <= '1'; -- new command has come in and i need to start processing
mm2s_ns <= SEND;
over_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
else
mm2s_ns <= IDLE;
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
end if;
-------------------------------------------------------------------
when SEND =>
cmd_out_ns <= '1';
command_ns <= command;
if (vsize_over = '1' and command_ready = '1') then
mm2s_ns <= IDLE;
cmd_proc_ns <= '1';
command_valid_ns <= '0';
split_out_ns <= '0';
over_ns <= '1';
elsif (command_ready = '0') then --(command_valid = '1' and command_ready = '0') then
mm2s_ns <= SEND;
command_valid_ns <= '1';
cmd_proc_ns <= '1';
split_out_ns <= '0';
over_ns <= '0';
else
mm2s_ns <= SPLIT;
command_valid_ns <= '0';
cmd_proc_ns <= '1';
over_ns <= '0';
split_out_ns <= '0';
end if;
-------------------------------------------------------------------
when SPLIT =>
cmd_proc_ns <= '1';
mm2s_ns <= SEND;
command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
cmd_out_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
SWALLOW_TVALID : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
counter <= (others => '0');
-- tvalid_unsplit_int <= '0';
reset_lock <= '1';
ready_for_next_cmd <= '0';
elsif (vsize_data_int = "00000000000000000000000") then
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '1';
reset_lock <= '0';
elsif ((tvalid_from_datamover = '1') and (counter < vsize_data_int)) then
counter <= counter + '1';
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '0';
reset_lock <= '0';
elsif ((counter = vsize_data_int) and (reset_lock = '0') and (tvalid_from_datamover = '1')) then
counter <= (others => '0');
-- tvalid_unsplit_int <= '1';
ready_for_next_cmd <= '1';
else
counter <= counter;
-- tvalid_unsplit_int <= '0';
if (cmd_proc_cdc_from = '1') then
ready_for_next_cmd <= '0';
else
ready_for_next_cmd <= ready_for_next_cmd;
end if;
end if;
end if;
end process SWALLOW_TVALID;
tvalid_unsplit_int <= tvalid_from_datamover when (counter = vsize_data_int) else '0'; --tvalid_unsplit_int;
SWALLOW_TDATA : process(clock)
begin
if(clock'EVENT and clock = '1')then
if (sgresetn = '0' or cmd_in = '1') then
tvalid_unsplit <= '0';
status_out_int <= (others => '0');
else
tvalid_unsplit <= tvalid_unsplit_int;
if (tvalid_from_datamover = '1') then
status_out_int (C_DM_STATUS_WIDTH-2 downto 0) <= status_in (C_DM_STATUS_WIDTH-2 downto 0) or status_out_int (C_DM_STATUS_WIDTH-2 downto 0);
else
status_out_int <= status_out_int;
end if;
if (tvalid_unsplit_int = '1') then
status_out_int (C_DM_STATUS_WIDTH-1) <= status_in (C_DM_STATUS_WIDTH-1);
end if;
end if;
end if;
end process SWALLOW_TDATA;
status_out <= status_out_int;
SWALLOW_TLAST_GEN : if C_INCLUDE_S2MM = 0 generate
begin
eof_set <= '1'; --eof_bit when (vsize = vsize_data_int) else '0';
CDC_CMD_PROC1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => cmd_proc_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => cmd_proc_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => eof_bit_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => eof_bit_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC : process (clock_sec)
begin
if (clock_sec'EVENT and clock_sec = '1') then
if (aresetn = '0') then
-- cmd_proc_cdc_to <= '0';
-- cmd_proc_cdc <= '0';
-- eof_bit_cdc_to <= '0';
-- eof_bit_cdc <= '0';
ready_for_next_cmd_tlast_cdc_from <= '0';
else
-- cmd_proc_cdc_to <= cmd_proc_cdc_from;
-- cmd_proc_cdc <= cmd_proc_cdc_to;
-- eof_bit_cdc_to <= eof_bit_cdc_from;
-- eof_bit_cdc <= eof_bit_cdc_to;
ready_for_next_cmd_tlast_cdc_from <= ready_for_next_cmd_tlast;
end if;
end if;
end process CDC_CMD_PROC;
CDC_CMDTLAST_PROC : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => ready_for_next_cmd_tlast_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock,
scndry_resetn => '0',
scndry_out => ready_for_next_cmd_tlast_cdc,
scndry_vect_out => open
);
--CDC_CMDTLAST_PROC : process (clock)
-- begin
-- if (clock'EVENT and clock = '1') then
-- if (sgresetn = '0') then
-- ready_for_next_cmd_tlast_cdc_to <= '0';
-- ready_for_next_cmd_tlast_cdc <= '0';
-- else
-- ready_for_next_cmd_tlast_cdc_to <= ready_for_next_cmd_tlast_cdc_from;
-- ready_for_next_cmd_tlast_cdc <= ready_for_next_cmd_tlast_cdc_to;
-- end if;
-- end if;
--end process CDC_CMDTLAST_PROC;
SWALLOW_TLAST : process(clock_sec)
begin
if(clock_sec'EVENT and clock_sec = '1')then
if(aresetn = '0')then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '0';
reset_lock_tlast <= '1';
ready_for_next_cmd_tlast <= '1';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and vsize_data_int = "00000000000000000000000") then
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '1';
reset_lock_tlast <= '0';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and (counter_tlast < vsize_data_int)) then
counter_tlast <= counter_tlast + '1';
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '0';
reset_lock_tlast <= '0';
elsif ((counter_tlast = vsize_data_int) and (reset_lock_tlast = '0') and (tlast_stream_data = '1' and tready_stream_data = '1')) then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '1';
ready_for_next_cmd_tlast <= '1';
else
counter_tlast <= counter_tlast;
tlast_stream_data_int <= '0';
if (cmd_proc_cdc = '1') then
ready_for_next_cmd_tlast <= '0';
else
ready_for_next_cmd_tlast <= ready_for_next_cmd_tlast;
end if;
end if;
end if;
end process SWALLOW_TLAST;
tlast_unsplit <= tlast_stream_data when (counter_tlast = vsize_data_int and eof_bit_cdc = '1') else '0';
tlast_unsplit_user <= tlast_stream_data when (counter_tlast = vsize_data_int) else '0';
-- tlast_unsplit <= tlast_stream_data; -- when (counter_tlast = vsize_data_int) else '0';
end generate SWALLOW_TLAST_GEN;
SWALLOW_TLAST_GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
eof_set <= eof_bit_cdc_from;
ready_for_next_cmd_tlast_cdc <= '1';
end generate SWALLOW_TLAST_GEN_S2MM;
end implementation;
| gpl-3.0 | 92dc7e296ce0192ae98dc9c444d0cfc4 | 0.502047 | 3.773971 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep2s60-sdr/leon3mp.vhd | 1 | 20,639 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- Shared bus
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(31 downto 0);
-- SRAM
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector(3 downto 0);
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
-- FLASH
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
byten : out std_ulogic;
wpn : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic; -- sdram clock enable
sdcsn : out std_logic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector(1 downto 0); -- sdram bank address
-- debug support unit
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
signal dsubre : std_ulogic;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
noclkfb => CFG_CLK_NOFB, freq => freq)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => sdclkl, pciclk => open,
cgi => cgi, cgo => cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 : if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, gnd(0), gnd(0), gnd(0), open, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2);
apbo(0) <= apb_none;
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0));
sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0));
end generate;
wpn <= '1'; byten <= '0';
nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, vcc(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, vcc(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
memb_pad : outpadv generic map (width => 4, tech => padtech)
port map (mben, memo.mben);
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpad generic map (tech => padtech)
port map (rwen, memo.wrn(0));
roen_pad : outpad generic map (tech => padtech)
port map (ramoen, memo.ramoen(0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2C60 SDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 3c82eeeba4c86e234e1981870b651164 | 0.538156 | 3.758012 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/FIFO_image_filter_img_0_data_stream_1_V.vhd | 4 | 4,629 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_data_stream_1_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_0_data_stream_1_V_shiftReg;
architecture rtl of FIFO_image_filter_img_0_data_stream_1_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_0_data_stream_1_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_0_data_stream_1_V is
component FIFO_image_filter_img_0_data_stream_1_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_0_data_stream_1_V_shiftReg : FIFO_image_filter_img_0_data_stream_1_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | 1de997ec6812774d209bc96785572fe3 | 0.537697 | 3.449329 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/dsu3.vhd | 1 | 2,458 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: Combined LEON3 debug support and AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3 is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end;
architecture rtl of dsu3 is
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
x0 : dsu3x generic map (hindex, haddr, hmask, ncpu, tbits, tech, irq, kbytes, 0, testen)
port map (rst, gnd, clk, ahbmi, ahbsi, ahbso, dbgi, dbgo, dsui, dsuo, vcc);
end;
| gpl-2.0 | d3191b74e5e1bf6a1eb2cacc28e095f5 | 0.593979 | 3.781538 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_p_src_cols_V_2_loc_channel.vhd | 2 | 4,676 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_cols_V_2_loc_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_cols_V_2_loc_channel_shiftReg;
architecture rtl of FIFO_image_filter_p_src_cols_V_2_loc_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_cols_V_2_loc_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_cols_V_2_loc_channel is
component FIFO_image_filter_p_src_cols_V_2_loc_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_cols_V_2_loc_channel_shiftReg : FIFO_image_filter_p_src_cols_V_2_loc_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | d6c9dfa59a0582af6fe6683cb9e020c8 | 0.540633 | 3.443299 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/spi/spi.vhd | 1 | 8,094 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Pacakge: spi
-- File: spi.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: SPI interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package spi is
type spi_in_type is record
miso : std_ulogic;
mosi : std_ulogic;
sck : std_ulogic;
spisel : std_ulogic;
astart : std_ulogic;
cstart : std_ulogic;
ignore : std_ulogic;
end record;
type spi_in_vector is array (natural range <>) of spi_in_type;
constant spi_in_none : spi_in_type := ('0', '0', '0', '0', '0', '0', '0');
type spi_out_type is record
miso : std_ulogic;
misooen : std_ulogic;
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
sckoen : std_ulogic;
ssn : std_logic_vector(7 downto 0); -- used by GE/OC SPI core
enable : std_ulogic;
astart : std_ulogic;
aready : std_ulogic;
end record;
type spi_out_vector is array (natural range <>) of spi_out_type;
constant spi_out_none : spi_out_type := ('0', '0', '0', '0', '0', '0',
(others => '0'), '0', '0', '0');
-- SPI master/slave controller
component spictrl
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
netlist : integer := 0;
syncram : integer range 0 to 1 := 1;
memtech : integer := 0;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
syncrst : integer range 0 to 1 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0;
ignore : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
spii : in spi_in_type;
spio : out spi_out_type;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end component;
-- SPI to AHB bridge
type spi2ahb_in_type is record
haddr : std_logic_vector(31 downto 0);
hmask : std_logic_vector(31 downto 0);
en : std_ulogic;
end record;
type spi2ahb_out_type is record
dma : std_ulogic;
wr : std_ulogic;
prot : std_ulogic;
end record;
component spi2ahb
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end component;
component spi2ahb_apb
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end component;
component spi2ahbx
generic (
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
--
spi2ahbi : in spi2ahb_in_type;
spi2ahbo : out spi2ahb_out_type
);
end component;
type spimctrl_in_type is record
miso : std_ulogic;
mosi : std_ulogic;
cd : std_ulogic;
end record;
type spimctrl_out_type is record
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
csn : std_ulogic;
cdcsnoen : std_ulogic;
errorn : std_ulogic;
ready : std_ulogic;
initialized : std_ulogic;
end record;
constant spimctrl_out_none : spimctrl_out_type :=
('0', '1', '0', '1', '1', '1', '0', '0');
component spimctrl
generic (
hindex : integer := 0;
hirq : integer := 0;
faddr : integer := 16#000#;
fmask : integer := 16#fff#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
spliten : integer := 0;
oepol : integer := 0;
sdcard : integer range 0 to 1 := 0;
readcmd : integer range 0 to 255 := 16#0B#;
dummybyte : integer range 0 to 1 := 1;
dualoutput : integer range 0 to 1 := 0;
scaler : integer range 1 to 512 := 1;
altscaler : integer range 1 to 512 := 1;
pwrupcnt : integer := 0;
maxahbaccsz : integer range 0 to 256 := AHBDW;
offset : integer := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
spii : in spimctrl_in_type;
spio : out spimctrl_out_type
);
end component;
end;
| gpl-2.0 | ba4c51674d18ab748048d39db0391f51 | 0.507536 | 3.748958 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/i2c/i2cslv.vhd | 1 | 20,242 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cslv
-- File: i2cslv.vhd
-- Author: Jan Andersson - Gaisler Research
-- [email protected]
--
-- Description: Simple I2C-slave with AMBA APB interface
--
-- Documentation of generics:
--
-- [hardaddr]
-- If this generic is set to 1 the core uses i2caddr as the hard coded address.
-- If hardaddr is set to 0 the core's address can be changed via the SLVADDR
-- register.
--
-- [tenbit]
-- Support for ten bit addresses.
--
-- [i2caddr]
-- The slave's (initial) i2c address.
--
-- [oepol]
-- Output enable polarity
--
-- [filter]
-- Length of filters used on SCL and SDA
--
-- The slave has four different modes operation. The mode is defined by the
-- value of the bits RMODE and TMODE.
-- RMODE TMODE I2CSLAVE Mode
-- 0 0 0
-- 0 1 1
-- 1 0 2
-- 1 1 3
--
-- RMODE 0:
-- The slave accepts one byte and NAKs all other transfers until software has
-- acknowledged the received byte.
-- RMODE 1:
-- The slave accepts one byte and keeps SCL low until software has acknowledged
-- the received byte
-- TMODE 0:
-- The slave transmits the same byte to all if the master requests more than
-- one byte in the transfer. The slave then NAKs all read requests unless the
-- Transmit Always Valid (TAV) bit in the control register is set.
-- TMODE 1:
-- The slave transmits one byte and then keeps SCL low until software has
-- acknowledged that the byte has been transmitted.
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity i2cslv is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0; -- interrupt index
-- I2C configuration
hardaddr : integer range 0 to 1 := 0; -- See description above
tenbit : integer range 0 to 1 := 0;
i2caddr : integer range 0 to 1023 := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2cslv;
architecture rtl of i2cslv is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Core version
constant I2CSLV_REV : integer := 0;
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2CSLV, 0, I2CSLV_REV, pirq),
1 => apb_iobar(paddr, pmask));
-- Register addresses
constant SLV_ADDR : std_logic_vector(7 downto 2) := "000000";
constant CTRL_ADDR : std_logic_vector(7 downto 2) := "000001";
constant STS_ADDR : std_logic_vector(7 downto 2) := "000010";
constant MSK_ADDR : std_logic_vector(7 downto 2) := "000011";
constant RD_ADDR : std_logic_vector(7 downto 2) := "000100";
constant TD_ADDR : std_logic_vector(7 downto 2) := "000101";
-- Core configuration
constant TENBIT_SUPPORT : integer := tenbit;
constant I2CADDRLEN : integer := 7 + tenbit*3;
constant HARDCADDR : integer := hardaddr;
constant I2CSLVADDR : std_logic_vector((I2CADDRLEN-1) downto 0) :=
conv_std_logic_vector(i2caddr, I2CADDRLEN);
-- Misc constants
constant I2C_READ : std_ulogic := '1'; -- R/Wn bit
constant I2C_WRITE : std_ulogic := '0';
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant I2C_LOW : std_ulogic := OEPOL_LEVEL; -- OE
constant I2C_HIZ : std_ulogic := not OEPOL_LEVEL;
constant I2C_ACK : std_ulogic := '0';
constant TENBIT_ADDR_START : std_logic_vector(4 downto 0) := "11110";
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type ctrl_reg_type is record -- Control register
rmode : std_ulogic; -- Receive mode
tmode : std_ulogic; -- Transmit mode
tv : std_ulogic; -- Transmit valid
tav : std_ulogic; -- Transmit always valid
en : std_ulogic; -- Enable
end record;
type sts_reg_type is record -- Status/Mask registers
rec : std_ulogic; -- Received byte
tra : std_ulogic; -- Transmitted byte
nak : std_ulogic; -- NAK'd address
end record;
type slvaddr_reg_type is record -- Slave address register
tba : std_ulogic; -- 10-bit address
slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0);
end record;
type i2cslv_reg_bank is record -- APB registers
slvaddr : slvaddr_reg_type;
ctrl : ctrl_reg_type;
sts : sts_reg_type;
msk : sts_reg_type;
receive : std_logic_vector(7 downto 0);
transmit : std_logic_vector(7 downto 0);
end record;
type i2c_in_array is array (filter downto 0) of i2c_in_type;
type slv_state_type is (idle, checkaddr, check10bitaddr, sclhold,
movebyte, handshake);
type i2cslv_reg_type is record
slvstate : slv_state_type;
--
reg : i2cslv_reg_bank;
irq : std_ulogic;
-- Transfer phase
active : boolean;
addr : boolean;
transmit : boolean;
receive : boolean;
-- Shift register
sreg : std_logic_vector(7 downto 0);
cnt : std_logic_vector(2 downto 0);
-- Synchronizers for inputs SCL and SDA
scl : std_ulogic;
sda : std_ulogic;
i2ci : i2c_in_array;
-- Output enables
scloen : std_ulogic;
sdaoen : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Subprograms
-----------------------------------------------------------------------------
-- purpose: Compares the first byte of a received address with the slave's
-- address. The tba input determines if the slave is using a ten bit address.
function compaddr1stb (
ibyte : std_logic_vector(7 downto 0); -- I2C byte
sr : slvaddr_reg_type) -- slave address register
return boolean is
variable correct : std_logic_vector(7 downto 1);
begin -- compaddr1stb
if sr.tba = '1' then
correct(7 downto 3) := TENBIT_ADDR_START;
correct(2 downto 1):= sr.slvaddr((I2CADDRLEN-1) downto (I2CADDRLEN-2));
else
correct(7 downto 1) := sr.slvaddr(6 downto 0);
end if;
return ibyte(7 downto 1) = correct(7 downto 1);
end compaddr1stb;
-- purpose: Compares the 2nd byte of a ten bit address with the slave address
function compaddr2ndb (
ibyte : std_logic_vector(7 downto 0); -- I2C byte
slvaddr : std_logic_vector((I2CADDRLEN-1) downto 0)) -- slave address
return boolean is
begin -- compaddr2ndb
return ibyte((I2CADDRLEN-3) downto 0) = slvaddr((I2CADDRLEN-3) downto 0);
end compaddr2ndb;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Register interface
signal r, rin : i2cslv_reg_type;
begin
comb: process (r, rstn, apbi, i2ci)
variable v : i2cslv_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable apbaddr : std_logic_vector(5 downto 0);
variable apbout : std_logic_vector(31 downto 0);
variable sclfilt : std_logic_vector(filter-1 downto 0);
variable sdafilt : std_logic_vector(filter-1 downto 0);
variable tba : boolean;
begin -- process comb
v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
v.i2ci(0) := i2ci; v.i2ci(filter downto 1) := r.i2ci(filter-1 downto 0);
tba := false;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when SLV_ADDR =>
apbout(31) := r.reg.slvaddr.tba;
apbout((I2CADDRLEN-1) downto 0) := r.reg.slvaddr.slvaddr;
when CTRL_ADDR =>
apbout(4 downto 0) := r.reg.ctrl.rmode & r.reg.ctrl.tmode &
r.reg.ctrl.tv & r.reg.ctrl.tav & r.reg.ctrl.en;
when STS_ADDR =>
apbout(2 downto 0) := r.reg.sts.rec & r.reg.sts.tra & r.reg.sts.nak;
when MSK_ADDR =>
apbout(2 downto 0) := r.reg.msk.rec & r.reg.msk.tra & r.reg.msk.nak;
when RD_ADDR =>
v.reg.sts.rec := '0';
apbout(7 downto 0) := r.reg.receive;
when TD_ADDR =>
apbout(7 downto 0) := r.reg.transmit;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when SLV_ADDR =>
if HARDCADDR = 0 then
if TENBIT_SUPPORT = 1 then
v.reg.slvaddr.tba := apbi.pwdata(31);
end if;
v.reg.slvaddr.slvaddr := apbi.pwdata((I2CADDRLEN-1) downto 0);
end if;
when CTRL_ADDR =>
v.reg.ctrl.rmode := apbi.pwdata(4);
v.reg.ctrl.tmode := apbi.pwdata(3);
v.reg.ctrl.tv := apbi.pwdata(2);
v.reg.ctrl.tav := apbi.pwdata(1);
v.reg.ctrl.en := apbi.pwdata(0);
when STS_ADDR =>
v.reg.sts.tra := r.reg.sts.tra and not apbi.pwdata(1);
v.reg.sts.nak := r.reg.sts.nak and not apbi.pwdata(0);
when MSK_ADDR =>
v.reg.msk.rec := apbi.pwdata(2);
v.reg.msk.tra := apbi.pwdata(1);
v.reg.msk.nak := apbi.pwdata(0);
when TD_ADDR =>
v.reg.transmit := apbi.pwdata(7 downto 0);
when others => null;
end case;
end if;
----------------------------------------------------------------------------
-- Bus filtering
----------------------------------------------------------------------------
for i in 0 to filter-1 loop
sclfilt(i) := r.i2ci(i+1).scl; sdafilt(i) := r.i2ci(i+1).sda;
end loop; -- i
if andv(sclfilt) = '1' then v.scl := '1'; end if;
if orv(sclfilt) = '0' then v.scl := '0'; end if;
if andv(sdafilt) = '1' then v.sda := '1'; end if;
if orv(sdafilt) = '0' then v.sda := '0'; end if;
---------------------------------------------------------------------------
-- I2C slave control FSM
---------------------------------------------------------------------------
case r.slvstate is
when idle =>
-- Release bus
if (r.scl and not v.scl) = '1' then
v.sdaoen := I2C_HIZ;
end if;
when checkaddr =>
tba := r.reg.slvaddr.tba = '1';
if compaddr1stb(r.sreg, r.reg.slvaddr) then
if r.sreg(0) = I2C_READ then
if (not tba or (tba and r.active)) then
if r.reg.ctrl.tv = '1' then
-- Transmit data
v.transmit := true;
v.slvstate := handshake;
else
-- No data to transmit, NAK
if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then
v.irq := '1';
end if;
v.reg.sts.nak := '1';
v.slvstate := idle;
end if;
else
-- Ten bit address with R/Wn = 1 and slave not previously
-- addressed.
v.slvstate := idle;
end if;
else
v.receive := not tba;
v.slvstate := handshake;
end if;
else
-- Slave address did not match
v.active := false;
v.slvstate := idle;
end if;
v.sreg := r.reg.transmit;
when check10bitaddr =>
if compaddr2ndb(r.sreg, r.reg.slvaddr.slvaddr) then
-- Slave has been addressed with a matching 10 bit address
-- If we receive a repeated start condition, matching address
-- and R/Wn = 1 we will transmit data. Without start condition we
-- will receive data.
v.addr := true;
v.active := true;
v.receive := true;
v.slvstate := handshake;
else
v.slvstate := idle;
end if;
when sclhold =>
-- This state is used when the device has been addressed to see if SCL
-- should be kept low until the receive register is free or the
-- transmit register is filled. It is also used when a data byte has
-- been transmitted or received to SCL low until software acknowledges
-- the transfer.
if (r.scl and not v.scl) = '1' then
v.scloen := I2C_LOW;
v.sdaoen := I2C_HIZ;
end if;
if ((r.receive and (not r.reg.sts.rec or not r.reg.ctrl.rmode) = '1') or
(r.transmit and (r.reg.ctrl.tv or not r.reg.ctrl.tmode) = '1')) then
v.slvstate := movebyte;
v.scloen := I2C_HIZ;
-- Falling edge that should be detected in movebyte may have passed
if r.transmit and v.scl = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
end if;
end if;
v.sreg := r.reg.transmit;
when movebyte =>
if (r.scl and not v.scl) = '1' then
if r.transmit then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
else
v.sdaoen := I2C_HIZ;
end if;
end if;
if (not r.scl and v.scl) = '1' then
v.sreg := r.sreg(6 downto 0) & r.sda;
if r.cnt = "111" then
if r.addr then
v.slvstate := checkaddr;
elsif r.receive nor r.transmit then
v.slvstate := check10bitaddr;
else
v.slvstate := handshake;
end if;
v.cnt := (others => '0');
else
v.cnt := r.cnt + 1;
end if;
end if;
when handshake =>
-- Falling edge
if (r.scl and not v.scl) = '1' then
if r.addr then
v.sdaoen := I2C_LOW;
elsif r.receive then
-- Receive, send ACK/NAK
-- Acknowledge byte if core has room in receive register
-- This code assumes that the core's receive register is free if we are
-- in RMODE 1. This should always be the case unless software has
-- reconfigured the core during operation.
if r.reg.sts.rec = '0' then
v.sdaoen := I2C_LOW;
v.reg.receive := r.sreg;
if r.reg.msk.rec = '1' then
v.irq := '1';
end if;
v.reg.sts.rec := '1';
else
-- NAK the byte, the master must abort the transfer
v.sdaoen := I2C_HIZ;
v.slvstate := idle;
end if;
else
-- Transmit, release bus
v.sdaoen := I2C_HIZ;
-- Byte transmitted, unset TV unless TAV is set.
v.reg.ctrl.tv := r.reg.ctrl.tav;
-- Set status bit and check if interrupt should be generated
if (not v.reg.sts.tra and r.reg.msk.tra) = '1' then
v.irq := '1';
end if;
v.reg.sts.tra := '1';
end if;
if not r.addr and r.receive and v.sdaoen = I2C_HIZ then
if (not v.reg.sts.nak and r.reg.msk.nak) = '1' then
v.irq := '1';
end if;
v.reg.sts.nak := '1';
end if;
end if;
-- Risinge edge
if (not r.scl and v.scl) = '1' then
if r.addr then
v.slvstate := movebyte;
else
if r.receive then
-- RMODE 0: Be ready to accept one more byte which will be NAK'd if
-- software has not read the receive register
-- RMODE 1: Keep SCL low until software has acknowledged received byte
if r.reg.ctrl.rmode = '0' then
v.slvstate := movebyte;
else
v.slvstate := sclhold;
end if;
else
-- Transmit, check ACK/NAK from master
-- If the master NAKs the transmitted byte the transfer has ended and
-- we should wait for the master's next action. If the master ACKs the
-- byte the core will act depending on tmode:
-- TMODE 0:
-- If the master ACKs the byte we must continue to transmit and will
-- transmit the same byte on all requests.
-- TMODE 1:
-- IF the master ACKs the byte we will keep SCL low until software has
-- put new transmit data into the transmit register.
if r.sda = I2C_ACK then
if r.reg.ctrl.tmode = '0' then
v.slvstate := movebyte;
else
v.slvstate := sclhold;
end if;
else
v.slvstate := idle;
end if;
end if;
end if;
v.addr := false;
v.sreg := r.reg.transmit;
end if;
end case;
if r.reg.ctrl.en = '1' then
-- STOP condition
if (r.scl and v.scl and not r.sda and v.sda) = '1' then
v.active := false;
v.slvstate := idle;
end if;
-- START or repeated START condition
if (r.scl and v.scl and r.sda and not v.sda) = '1' then
v.slvstate := movebyte;
v.cnt := (others => '0');
v.addr := true;
v.transmit := false;
v.receive := false;
end if;
end if;
----------------------------------------------------------------------------
-- Reset and idle operation
----------------------------------------------------------------------------
if rstn = '0' then
v.slvstate := idle;
v.reg.slvaddr.slvaddr := I2CSLVADDR;
if TENBIT_SUPPORT = 1 then v.reg.slvaddr.tba := '1';
else v.reg.slvaddr.tba := '0'; end if;
v.reg.ctrl.en := '0';
v.reg.sts := ('0', '0', '0');
v.scl := '0';
v.active := false;
v.scloen := I2C_HIZ; v.sdaoen := I2C_HIZ;
end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Update registers
rin <= v;
-- Update outputs
apbo.prdata <= apbout;
apbo.pirq <= irq;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
i2co.scl <= '0';
i2co.scloen <= r.scloen;
i2co.sda <= '0';
i2co.sdaoen <= r.sdaoen;
i2co.enable <= r.reg.ctrl.en;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"i2cslv" & tost(pindex) & ": I2C slave rev " &
tost(I2CSLV_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
| gpl-2.0 | 694e25ee4e5c3606565c8cb0d6bca958 | 0.521194 | 3.851218 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/i2c/i2c2ahb.vhd | 1 | 3,031 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb
-- File: i2c2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb;
architecture rtl of i2c2ahb is
signal i2c2ahbi : i2c2ahb_in_type;
begin
bridge : i2c2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
i2ci => i2ci,
i2co => i2co,
i2c2ahbi => i2c2ahbi,
i2c2ahbo => open);
i2c2ahbi.en <= '1';
i2c2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
i2c2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
i2c2ahbi.slvaddr <= conv_std_logic_vector(i2cslvaddr, 7);
i2c2ahbi.cfgaddr <= conv_std_logic_vector(i2ccfgaddr, 7);
end architecture rtl;
| gpl-2.0 | 4b1c6542c18dd6d386b40e5e71080c10 | 0.584955 | 3.582742 | false | false | false | false |
gtaylormb/opl3_fpga | fpga/bd/opl3_cpu/ip/opl3_cpu_auto_pc_0/blk_mem_gen_v8_3_2/hdl/blk_mem_gen_v8_3.vhd | 4 | 21,487 | `protect begin_protected
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`protect end_protected
| lgpl-3.0 | 47583181ea575aca7872ad3a5f0304ce | 0.940057 | 1.869085 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/inferred/ddrphy_datapath.vhd | 1 | 9,238 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy_datapath
-- File: ddrphy_datapath.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR/DDR2 PHY data path (digital part of phy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ddrphy_datapath is
generic (
regtech: integer := 0;
dbits: integer;
abits: integer;
bankbits: integer range 2 to 3 := 2;
ncs: integer;
nclk: integer;
-- Enable extra resync stage clocked by clkresync
resync: integer range 0 to 2 := 0
);
port (
clk0: in std_ulogic;
clk90: in std_ulogic;
clk180: in std_ulogic;
clk270: in std_ulogic;
clkresync: in std_ulogic;
ddr_clk: out std_logic_vector(nclk-1 downto 0);
ddr_clkb: out std_logic_vector(nclk-1 downto 0);
ddr_dq_in: in std_logic_vector(dbits-1 downto 0);
ddr_dq_out: out std_logic_vector(dbits-1 downto 0);
ddr_dq_oen: out std_logic_vector(dbits-1 downto 0);
ddr_dqs_in90: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_in90n: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_out: out std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_oen: out std_logic_vector(dbits/8-1 downto 0);
ddr_cke: out std_logic_vector(ncs-1 downto 0);
ddr_csb: out std_logic_vector(ncs-1 downto 0);
ddr_web: out std_ulogic;
ddr_rasb: out std_ulogic;
ddr_casb: out std_ulogic;
ddr_ad: out std_logic_vector(abits-1 downto 0);
ddr_ba: out std_logic_vector(bankbits-1 downto 0);
ddr_dm: out std_logic_vector(dbits/8-1 downto 0);
ddr_odt: out std_logic_vector(ncs-1 downto 0);
-- Control signals synchronous to clk0
dqin: out std_logic_vector(dbits*2-1 downto 0);
dqout: in std_logic_vector(dbits*2-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (bankbits-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0); -- Clk enable control signal to memory
odt : in std_logic_vector(ncs-1 downto 0);
dqs_en : in std_ulogic; -- Run dqs strobe (active low)
dqs_oen : in std_ulogic; -- DQS output enable (active low)
ddrclk_en : in std_logic_vector(nclk-1 downto 0) -- Enable/stop ddr_clk
);
end;
architecture rtl of ddrphy_datapath is
signal vcc,gnd: std_ulogic;
signal dqs_en_inv,dqs_en_inv180: std_ulogic;
signal dqcaptr,dqcaptf: std_logic_vector(dbits-1 downto 0);
signal dqsyncr,dqsyncf: std_logic_vector(dbits-1 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- DDR interface clock signal
-----------------------------------------------------------------------------
-- 90 degree shifted relative to master clock, gated by ddrclk_en
genclk: for x in 0 to nclk-1 generate
clkreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => ddrclk_en(x), d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clk(x));
clkbreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => gnd, d2 => ddrclk_en(x), ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clkb(x));
end generate;
-----------------------------------------------------------------------------
-- Control signals RAS,CAS,WE,BA,ADDR,CS,ODT,CKE
-----------------------------------------------------------------------------
rasreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => rasn, q => ddr_rasb);
casreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => casn, q => ddr_casb);
wereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => wen, q => ddr_web);
genba: for x in 0 to bankbits-1 generate
bareg: grdff generic map (tech => regtech)
port map (clk => clk0, d => ba(x), q => ddr_ba(x));
end generate;
gencs: for x in 0 to ncs-1 generate
csreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => csn(x), q => ddr_csb(x));
ckereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => cke(x), q => ddr_cke(x));
odtreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => odt(x), q => ddr_odt(x));
end generate;
genaddr: for x in 0 to abits-1 generate
addrreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => addr(x), q => ddr_ad(x));
end generate;
-----------------------------------------------------------------------------
-- Outgoing data, output enable, DQS, DQSOEN, DM
-----------------------------------------------------------------------------
gendqout: for x in 0 to dbits-1 generate
dqoutreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqout(x+dbits), d2 => dqout(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dq_out(x));
dqoenreg: grdff
generic map (tech => regtech)
port map (clk => clk0, d => oen, q => ddr_dq_oen(x));
end generate;
-- dqs_en -> invert -> delay -> +90-deg DDR-regs -> dqs_out
-- In total oen is delayed 5/4 cycles. We use 1/2 cycle delay
-- instead of 1 cycle delay to get better timing margin to DDR regs.
-- DQSOEN is delayed one cycle just like ctrl sigs
dqs_en_inv <= not dqs_en;
dqseninv180reg: grdff
generic map (tech => regtech)
port map (clk => clk180, d => dqs_en_inv, q => dqs_en_inv180);
gendqsout: for x in 0 to dbits/8-1 generate
dqsreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqs_en_inv180, d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_dqs_out(x));
dqsoenreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqs_oen, q => ddr_dqs_oen(x));
end generate;
gendm: for x in 0 to dbits/8-1 generate
dmreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dm(x+dbits/8), d2 => dm(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dm(x));
end generate;
-----------------------------------------------------------------------------
-- Incoming data
-----------------------------------------------------------------------------
gendqin: for x in 0 to dbits-1 generate
-- capture using dqs+90
-- Note: The ddr_ireg delivers both edges on c1 rising edge, therefore c1
-- is connected to inverted clock (c1 rising edge == dqs falling edge)
dqcaptreg: ddr_ireg generic map (tech => regtech)
port map (d => ddr_dq_in(x),
c1 => ddr_dqs_in90n(x/8), c2 => ddr_dqs_in90(x/8), ce => vcc, r => gnd, s => gnd,
q1 => dqcaptf(x), q2 => dqcaptr(x));
-- optional extra resync stage
ifresync: if resync=1 generate
genresync: for x in 0 to dbits-1 generate
dqsyncrreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptr(x), q => dqsyncr(x));
dqsyncfreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptf(x), q => dqsyncf(x));
end generate;
end generate;
noresync: if resync/=1 generate
dqsyncr <= dqcaptr;
dqsyncf <= dqcaptf;
end generate;
-- sample in clk0 domain
gensamp: if resync/=2 generate
dqinregr: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncr(x), q => dqin(x+dbits));
dqinregf: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncf(x), q => dqin(x));
end generate;
nosamp: if resync=2 generate
dqin(x+dbits) <= dqsyncr(x);
dqin(x) <= dqsyncf(x);
end generate;
end generate;
end;
| gpl-2.0 | 7222e677ce121c2e12c10d46922a3aa7 | 0.545573 | 3.627012 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/game_cores/cl_text.vhd | 1 | 3,957 | --------------------------------------------------------------------------------
--
-- Title : cl_text.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for main text
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.array8x8;
entity cl_text is
generic(
constant yend : std_logic_vector(4 downto 0); --! Y end area
constant ystart : std_logic_vector(4 downto 0); --! Y start area
constant xend : std_logic_vector(6 downto 0); --! X end area
constant xstart : std_logic_vector(6 downto 0) --! X start area
);
port(
-- system signals:
clk : in std_logic; --! clock
reset : in std_logic; --! system reset
-- control signals:
addr_rnd : in std_logic_vector(4 downto 0); --! address round
display : in std_logic; --! display enable
cntgames : in std_logic; --! games counter enable
win : in std_logic; --! win value
lose : in std_logic; --! lose value
game : in std_logic; --! game value
flash : in std_logic_vector(2 downto 0); --! RGB blinking
-- vga XoY:
x_char : in std_logic_vector(9 downto 0); --! X line: 0:79
y_char : in std_logic_vector(8 downto 0); --! Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0) --! RGB Colour
);
end cl_text;
architecture cl_text of cl_text is
component ctrl_8x16_rom is
port(
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end component;
component cl_select_text is
port(
x_char : in std_logic_vector(6 downto 0);
y_char : in std_logic_vector(4 downto 0);
win : in std_logic;
lose : in std_logic;
game : in std_logic;
cntgames: in std_logic;
addr_rnd: in std_logic_vector(4 downto 0);
ch_data : out std_logic_vector(7 downto 0)
);
end component;
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal data : std_logic;
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal color : std_logic_vector(2 downto 0):="111";
signal addr_rom : std_logic_vector(10 downto 0);
signal data_rom : std_logic_vector(7 downto 0);
signal data_box : std_logic_vector(7 downto 0);
begin
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
x_select_text: cl_select_text
port map (
x_char => x_in,
y_char => y_in,
win => win,
lose => lose,
game => game,
cntgames=> cntgames,
addr_rnd=> addr_rnd,
ch_data => data_box
);
addr_rom <= data_box(6 downto 0) & y_char(3 downto 0) when rising_edge(clk);
x_char_rom: ctrl_8x16_rom
port map (
clk => clk,
addr => addr_rom,
data => data_rom
);
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
color <= flash when (x_in > "0011001") and (y_in = "10000") else "100" when (y_in < "00111") else "010";
pr_sw_sel: process(clk, reset) is
begin
if reset = '0' then
data <= '0';
elsif rising_edge(clk) then
if display = '0' then
data <= '0';
else
data <= data_rom(to_integer(unsigned(x_del)));
end if;
end if;
end process;
g_rgb: for ii in 0 to 2 generate
begin
rgb(ii) <= data and color(ii);
end generate;
end cl_text; | mit | 2c1fcf04dfea623c785e001dfa4499fa | 0.528431 | 2.93546 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/police/example_design/police_exdes.vhd | 1 | 4,324 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: police_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY police_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END police_exdes;
ARCHITECTURE xilinx OF police_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT police IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : police
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | 97efd2604f23824ab54b111d897fb7e6 | 0.574468 | 4.809789 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/misc/ahbram.vhd | 1 | 9,173 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram is
constant abits : integer := log2ext(kbytes) + 8 - maccsz/64;
constant dw : integer := maccsz;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits-1+log2(dw/8) downto 0);
size : std_logic_vector(2 downto 0);
prdata : std_logic_vector((dw-1)*pipe downto 0);
pwrite : std_ulogic;
pready : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'),
size => (others => '0'), prdata => (others => '0'), pwrite => '0',
pready => '1');
signal r, c : reg_type;
signal ramsel : std_logic_vector(dw/8-1 downto 0);
signal write : std_logic_vector(dw/8-1 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(dw-1 downto 0);
signal hwdata : std_logic_vector(dw-1 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(dw/8-1 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
variable hrdata : std_logic_vector(dw-1 downto 0);
variable seldata : std_logic_vector(dw-1 downto 0);
variable raddr : std_logic_vector(3 downto 2);
variable adsel : std_logic;
begin
v := r; v.hready := '1'; bs := (others => '0');
v.pready := r.hready;
if pipe=0 then
adsel := r.hwrite or not r.hready;
else
adsel := r.hwrite or r.pwrite;
v.hready := r.hready or not r.pwrite;
end if;
if adsel = '1' then
haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8));
else
haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8));
bs := (others => '0');
end if;
raddr := (others => '0');
v.pwrite := '0';
if pipe/=0 and (r.hready='1' or r.pwrite='0') then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
if ahbsi.hready = '1' then
if pipe=0 then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.size := ahbsi.hsize(2 downto 0);
v.hwrite := ahbsi.hwrite and v.hsel;
if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then
v.hready := '0';
v.pwrite := r.hwrite;
end if;
end if;
if r.hwrite = '1' then
case r.size is
when HSIZE_BYTE =>
bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1';
when HSIZE_HWORD =>
for i in 0 to dw/16-1 loop
if i = conv_integer(r.addr(log2(dw/16) downto 1)) then
bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1');
end if;
end loop; -- i
when HSIZE_WORD =>
if dw = 32 then bs := (others => '1');
else
for i in 0 to dw/32-1 loop
if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then
bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_DWORD =>
if dw = 32 then null;
elsif dw = 64 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_4WORD =>
if dw < 128 then null;
elsif dw = 128 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when others => --HSIZE_8WORD
if dw < 256 then null;
else bs := (others => '1'); end if;
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
-- Duplicate read data on word basis, unless CORE_ACDM is enabled
if CORE_ACDM = 0 then
if dw = 32 then
seldata := ramdata;
elsif dw = 64 then
if r.size = HSIZE_DWORD then seldata := ramdata; else
if r.addr(2) = '0' then
seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else
seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0);
end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
end if;
elsif dw = 128 then
if r.size = HSIZE_4WORD then
seldata := ramdata;
elsif r.size = HSIZE_DWORD then
if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
else
raddr := r.addr(3 downto 2);
case raddr is
when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4);
when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4);
when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4);
when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0);
end case;
seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0);
end if;
else
seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size);
end if;
else
seldata := ramdata;
end if;
if pipe = 0 then
v.prdata := (others => '0');
hrdata := seldata;
else
v.prdata := seldata;
hrdata := r.prdata;
end if;
if (not RESET_ALL) and (rst = '0') then
v.hwrite := RES.hwrite; v.hready := RES.hready;
end if;
write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop;
ramaddr <= haddr; c <= v;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hready <= r.hready;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
-- Select correct write data
hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2),
conv_std_logic_vector(log2(dw/8), 3));
aram : syncrambw generic map (tech, abits, dw, scantest) port map (
clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin);
reg : process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| gpl-2.0 | 1cd3795fa95497a9cea3e2fd071f656d | 0.555216 | 3.36377 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep1c20/leon3mp.vhd | 1 | 21,066 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 25 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clkout : out std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
-- Shared bus
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
-- SRAM
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector(3 downto 0);
iosn : out std_ulogic;
-- FLASH
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_logic; -- sdram clock enable
sdcsn : out std_logic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector(1 downto 0); -- sdram bank address
-- debug support unit
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- for smsc lan chip
eth_aen : out std_logic;
eth_readn : out std_logic;
eth_writen: out std_logic;
eth_nbe : out std_logic_vector(3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
signal lclk, lclkout : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal dsubre : std_ulogic;
component clkgen_ep1c20board is
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
freq : integer := 50000);
port (
clkin : in std_logic;
clkout : out std_logic;
clk : out std_logic;
clkn : out std_logic;
sdclk : out std_logic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component smc_mctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2;
oepol : integer := 0;
syncrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type;
eth_aen : out std_ulogic; -- for smsc lan chip
eth_readn : out std_ulogic; -- for smsc lan chip
eth_writen: out std_ulogic; -- for smsc lan chip
eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
);
end component;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; --cgi.pllref <= lclk; --pllref; -- clk; --'0';
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkout_pad : outpad generic map (tech => padtech, slew => 1) port map (clkout, lclkout);
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clkgen0 : clkgen_ep1c20board
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN, CFG_CLK_NOFB)
port map (lclk, lclkout, clkm, open, sdclkl, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2);
apbo(0) <= apb_none;
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo,
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0));
sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0));
end generate;
nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo2.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo2.sdcsn(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, vcc(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpad generic map (tech => padtech)
port map (ramsn, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpad generic map (tech => padtech)
port map (rwen, memo.wrn(0));
roen_pad : outpad generic map (tech => padtech)
port map (ramoen, memo.ramoen(0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- for smc lan chip
eth_aen_pad : outpad generic map (tech => padtech)
port map (eth_aen, s_eth_aen);
eth_readn_pad : outpad generic map (tech => padtech)
port map (eth_readn, s_eth_readn);
eth_writen_pad : outpad generic map (tech => padtech)
port map (eth_writen, s_eth_writen);
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
port map (eth_nbe, s_eth_nbe);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
----
----
-- invert signal for input via a key
dsubre <= not dsubren;
-- for smc lan chip
eth_lclk <= vcc(0);
eth_nads <= gnd(0);
eth_ncycle <= vcc(0);
eth_wnr <= vcc(0);
eth_nvlbus <= vcc(0);
eth_nrdyrtn <= vcc(0);
eth_ndatacs <= vcc(0);
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP1C20 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | cac09cca6cd439f15e9208cfd6df472c | 0.538261 | 3.753742 | false | false | false | false |
Luisda199824/ProcesadorMonociclo | TB_Sumador32B.vhd | 1 | 1,259 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TB_Sumador32B IS
END TB_Sumador32B;
ARCHITECTURE behavior OF TB_Sumador32B IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Sumador32B
PORT(
A : IN std_logic_vector(31 downto 0);
B : IN std_logic_vector(31 downto 0);
SumOut : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(31 downto 0) := (others => '0');
signal B : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal SumOut : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Sumador32B PORT MAP (
A => A,
B => B,
SumOut => SumOut
);
-- Stimulus process
stim_proc: process
begin
A <= "00000000000000000000000000000001";
B <= "00000000000000000000000000000001";
wait for 20 ns;
A <= "00000000010100000000000000000001";
B <= "00000000001000000000000000000001";
wait for 20 ns;
A <= "00000000000111110000000000000001";
B <= "00000000000000001111110000000001";
wait for 20 ns;
A <= "00000000000000000000001111000001";
B <= "00000000000000000000001111000001";
wait;
end process;
END;
| mit | e9d53146216d69c1a3dde128fbbf78e5 | 0.640985 | 3.838415 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/police/example_design/police_prod.vhd | 1 | 9,901 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: police_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : police.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 12
-- C_READ_WIDTH_A : 12
-- C_WRITE_DEPTH_A : 6400
-- C_READ_DEPTH_A : 6400
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 12
-- C_READ_WIDTH_B : 12
-- C_WRITE_DEPTH_B : 6400
-- C_READ_DEPTH_B : 6400
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY police_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END police_prod;
ARCHITECTURE xilinx OF police_prod IS
COMPONENT police_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : police_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | 204ea0698ab92d43b0113ddb0c35fabc | 0.494496 | 3.828693 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/unisim/ddr_unisim.vhd | 1 | 12,067 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: unisim_iddr_reg
-- File: unisim_iddr_reg.vhd
-- Author: David Lindh, Jiri Gaisler - Gaisler Research
-- Description: Xilinx DDR input register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.iddr;
--pragma translate_on
entity unisim_iddr_reg is
generic (tech : integer := virtex4;arch : integer := 0);
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end;
architecture rtl of unisim_iddr_reg is
attribute BOX_TYPE : string;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
attribute BOX_TYPE of IDDR : component is "PRIMITIVE";
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preQ1, preQ2 : std_ulogic;
signal D_delay : std_ulogic;
begin
V7 : if (tech = virtex7) or (tech = kintex7) generate
U0 : IDDR generic map( DDR_CLK_EDGE => "SAME_EDGE_PIPELINED")
Port map( Q1 => Q1, Q2 => Q2, C => C1, CE => CE,
D => D, R => R, S => S);
end generate;
V4 : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate
U0 : IDDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE")
Port map( Q1 => Q1, Q2 => preQ2, C => C1, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1, preQ2, R)
begin
if R='1' then --asynchronous reset, active high
Q2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
S6 : if (tech = spartan6) generate
noalign : if arch = 0 generate
U0 : IDDR2 generic map( DDR_ALIGNMENT => "NONE")
Port map( Q0 => Q1, Q1 => preQ2, C0 => C1, C1 => C2, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1)
begin
if C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
align : if arch /= 0 generate
U0 : IDDR2 generic map( DDR_ALIGNMENT => "C0")
Port map( Q0 => preQ1, Q1 => Q2, C0 => C1, C1 => C2, CE => CE,
D => D, R => R, S => S);
q3reg : process (C1)
begin
if C1'event and C1='1' then --Clock event - posedge
Q1 <= preQ1;
end if;
end process;
end generate;
end generate;
V2 : if tech = virtex2 or tech = spartan3 generate
-- CE and S inputs inactive for virtex 2
q1reg : process (C1, D, R)
begin
if R='1' then --asynchronous reset, active high
Q1 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q1 <= D;
end if;
end process;
q2reg : process (C1, D, R)
begin
if R='1' then --asynchronous reset, active high
preQ2 <= '0';
elsif C1'event and C1='0' then --Clock event - negedge
preQ2 <= D;
end if;
end process;
q3reg : process (C1, preQ2, R)
begin
if R='1' then --asynchronous reset, active high
Q2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
Q2 <= preQ2;
end if;
end process;
end generate;
-- S6 : if tech = spartan6 generate
--
-- x0 : IFDDRRSE port map (
-- Q0 => Q1, Q1 => Q2, C0 => C1, C1 => C2, CE => CE,
-- D => D, R => R, S => S);
--
-- end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.oddr;
use unisim.oddr2;
--use unisim.FDDRRSE;
--pragma translate_on
entity unisim_oddr_reg is
generic (tech : integer := virtex4; arch : integer := 0);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of unisim_oddr_reg is
attribute BOX_TYPE : string;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
ODDR : component is "PRIMITIVE";
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "ASYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
ODDR2 : component is "PRIMITIVE";
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
attribute BOX_TYPE of
FDDRRSE : component is "PRIMITIVE";
signal preD2 : std_ulogic;
begin
V7 : if (tech = virtex7) or (tech = kintex7) generate
U0 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE")
port map(
Q => Q, C => C1, CE => CE, D1 => D1,
D2 => D2, R => R, S => S);
end generate;
V4 : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate
d2r : if arch = 0 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
end generate;
nod2r : if arch /= 0 generate
preD2 <= D2;
end generate;
U0 : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE" -- ,INIT => '0'
, SRTYPE => "ASYNC")
port map(
Q => Q,
C => C1,
CE => CE,
D1 => D1,
D2 => preD2,
R => R,
S => S);
end generate;
V2 : if tech = virtex2 or tech = spartan3 generate
d2r : if arch = 0 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
end generate;
nod2r : if arch /= 0 generate
preD2 <= D2;
end generate;
c_dm : component FDDRRSE
-- generic map( INIT => '0')
port map(
Q => Q,
D0 => D1,
D1 => preD2,
C0 => C1,
C1 => C2,
CE => CE,
R => R,
S => S);
end generate;
s6 : if tech = spartan6 generate
d2r : if arch = 0 generate
d2reg : process (C1, D2, R)
begin
if R='1' then --asynchronous reset, active high
preD2 <= '0';
elsif C1'event and C1='1' then --Clock event - posedge
preD2 <= D2;
end if;
end process;
end generate;
nod2r : if arch /= 0 generate
preD2 <= D2;
end generate;
c_dm : component ODDR2
generic map (
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC")
port map (
Q => Q,
C0 => C1,
C1 => C2,
CE => CE,
D0 => D1,
D1 => D2,
R => R,
S => S);
end generate;
end ;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.fd;
--use unisim.FDDRRSE;
--pragma translate_on
entity oddrv2 is
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of oddrv2 is
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component FDDRRSE
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preD2 : std_ulogic;
begin
rf : FD port map ( Q => preD2, C => C1, D => D2);
rr : FDDRRSE port map ( Q => Q, C0 => C1, C1 => C2,
CE => CE, D0 => D1, D1 => preD2, R => R, S => R);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.fd;
use unisim.oddr2;
--pragma translate_on
entity oddrc3e is
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of oddrc3e is
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal preD2 : std_ulogic;
begin
rf : FD port map ( Q => preD2, C => C1, D => D2);
rr : ODDR2 port map ( Q => Q, C0 => C1, C1 => C2,
CE => CE, D0 => D1, D1 => preD2, R => R, S => R);
end;
| gpl-2.0 | 9ff2b5e7b15e24e74a9d25cfb4622606 | 0.51993 | 3.408757 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/inferred/lpddr2_phy_inferred.vhd | 1 | 9,958 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: generic_lpddr2phy_wo_pads
-- File: lpddr2_phy_inferred.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic LPDDR2/LPDDR3 PHY (simulation only), without pads
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clkswitch is
port (clk1,clk2,sel: in std_ulogic;
clko: out std_ulogic);
end;
architecture sim of clkswitch is
signal c1en,c2en: std_ulogic := '0';
begin
clko <= (clk1 and c1en) or (clk2 and c2en);
p1: process(clk1)
begin
if falling_edge(clk1) then
c1en <= (not sel) and (not c2en);
end if;
end process;
p2: process(clk2)
begin
if falling_edge(clk2) then
c2en <= (sel) and (not c1en);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity generic_lpddr2phy_wo_pads is
generic (
tech : integer := 0;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0;
oepol: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- clkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture beh of generic_lpddr2phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
signal extclkb,extclkn,extclk,intclkb,intclkn,intclk: std_ulogic;
signal gextclk,gextclkn: std_ulogic;
signal clkoutb,clkoutn: std_ulogic;
signal llockb,llockn,llock: std_ulogic;
signal dqsout,dqsoen,dqsand,dqoen,dqsien,dqsiend: std_ulogic;
signal dqsin,dqsind: std_logic_vector(dbits/8-1 downto 0);
signal tmeas: time := 0 ns;
signal tdqsck: time := 0 ns;
begin
bootpll: sim_pll
generic map (clkmul => clkratio,
clkdiv1 => 1, clkphase1 => 180,
clkdiv2 => 1, clkphase2 => 90,
clkdiv3 => clkratio, clkphase3 => 0)
port map (i => clkin2, o1 => extclkb, o2 => intclkb,
o3 => clkoutb, lock => llockb, rst => rst);
pll0: sim_pll
generic map (clkmul => clkratio,
clkdiv1 => 1, clkphase1 => 180,
clkdiv2 => 1, clkphase2 => 90,
clkdiv3 => clkratio, clkphase3 => 0)
port map (i => clkin, o1 => extclkn, o2 => intclkn,
o3 => clkoutn, lock => llockn, rst => rst);
llock <= llockb and llockn;
lock <= llock;
clkout2 <= '0';
cs0: entity work.clkswitch port map (extclkn, extclkb, boot, extclk);
cs1: entity work.clkswitch port map (intclkn, intclkb, boot, intclk);
cs2: entity work.clkswitch port map (clkoutn, clkoutb, boot, clkout);
gextclk <= extclk and (llock and not ckstop);
gextclkn <= not gextclk;
dqsout <= gextclk and dqsand;
ddr_dqs_out <= (others => dqsout);
ddr_dqs_oen <= (others => dqsoen);
ddr_dq_oen <= (others => dqoen);
ddr_clk <= (others => gextclk);
ddr_clkb <= (others => gextclkn);
dqsiend <= dqsien after tdqsck;
dqsin <= ddr_dqs_in when dqsiend='1' else (others => '0');
dqsind <= dqsin after tmeas * 0.25;
wrreq <= wrpend(1+clkratio-1-1 downto 1-1);
outregs: process(clkoutret,intclk,dqsind)
variable phase: integer;
variable wrpend_samp: std_logic_vector(1 downto 0);
variable rdpend_prev: std_ulogic;
type intarr is array(natural range <>) of integer;
variable dl: intarr(dbits/8-1 downto 0) := (others => 0);
variable dqq: std_logic_vector(3*dbits*2-1 downto 0);
variable lt: time := 0 ns;
variable dqsind_prev: std_logic_vector(dbits/8-1 downto 0) := (others => '0');
variable i: integer;
begin
if dqsind /= dqsind_prev then
for x in dqsind'range loop
if (dqsind(x)='1' and dqsind_prev(x)='0') or (dqsind(x)='0' and dqsind_prev(x)='1') then
for y in 5 downto 1 loop
dqq(x*8+dbits*y+7 downto x*8+dbits*y) := dqq(x*8+dbits*(y-1)+7 downto x*8+dbits*(y-1));
end loop;
dqq(x*8+7 downto x*8) := ddr_dq_in(x*8+7 downto x*8);
if dqsind(x)='0' then
dl(x) := dl(x)+1;
end if;
end if;
end loop;
dqsind_prev := dqsind;
end if;
if rising_edge(clkoutret) then
dqsien <= rdpend(1);
phase := 0;
wrpend_samp := wrpend(1 downto 0);
rdvalid <= (others => '0');
dqin <= (others => '-');
i := clkratio;
for x in dl'range loop
if dl(x)<i then i:=dl(x); end if;
end loop;
for x in dl'range loop
dl(x) := dl(x)-i;
end loop;
for x in 2*i-1 downto 0 loop
for y in dbits/8-1 downto 0 loop
dqin(x*dbits+y*8+7 downto x*dbits+y*8) <= dqq((x+dl(y))*dbits+y*8+7 downto (x+dl(y))*dbits+y*8);
end loop;
end loop;
rdvalid(i-1 downto 0) <= (others => '1');
end if;
if falling_edge(clkoutret) then
dqsoen <= not (wrpend_samp(1) or wrpend_samp(0));
rdpend_prev := rdpend(0);
end if;
if rising_edge(intclk) then
dqsand <= wrpend_samp(0);
dqoen <= not wrpend_samp(0);
tmeas <= now - lt;
lt := now;
end if;
if rising_edge(intclk) or falling_edge(intclk) then
-- DDR outputs
ddr_ca <= ca(ca'high-10*phase downto ca'high-10*phase-9);
ddr_dm <= dm(dm'high-dbits/8*phase downto dm'high+1-dbits/8*(phase+1));
ddr_dq_out <= dqout(dqout'high-dbits*phase downto dqout'high+1-dbits*(phase+1));
if rising_edge(intclk) then
-- SDR outputs
ddr_cke <= cke(cke'high-ncs*(phase/2) downto cke'high+1-ncs*(phase/2+1));
ddr_csb <= csn(csn'high-ncs*(phase/2) downto csn'high+1-ncs*(phase/2+1));
end if;
if phase < 2*clkratio-1 then
phase := phase+1;
end if;
end if;
end process;
dqsckproc: process
variable t: time;
begin
wait until dqsien='1';
loop
t := now;
if dqsin/=(dqsin'range => '0') then
wait until dqsin=(dqsin'range => '0');
end if;
wait until dqsin=(dqsin'range => '1');
tdqsck <= tdqsck + (now-t)-0.25*tmeas;
wait until dqsin=(dqsin'range => 'X') and dqsien='1';
end loop;
end process;
end;
| gpl-2.0 | 7c04331dd2653f414bb44a9aeca3c6ef | 0.571099 | 3.367602 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/game_over/example_design/game_over_prod.vhd | 1 | 9,926 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: game_over_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : game_over.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 12
-- C_READ_WIDTH_A : 12
-- C_WRITE_DEPTH_A : 19200
-- C_READ_DEPTH_A : 19200
-- C_ADDRA_WIDTH : 15
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 12
-- C_READ_WIDTH_B : 12
-- C_WRITE_DEPTH_B : 19200
-- C_READ_DEPTH_B : 19200
-- C_ADDRB_WIDTH : 15
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY game_over_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END game_over_prod;
ARCHITECTURE xilinx OF game_over_prod IS
COMPONENT game_over_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : game_over_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | 81787a5d98596c37a79343f698268c7b | 0.495063 | 3.827998 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ddr/ddrpkg.vhd | 1 | 36,341 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ddrpkg
-- File: ddrpkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Components and types for DDR SDRAM controllers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
package ddrpkg is
type ddrctrl_in_type is record
-- Data signals
data : std_logic_vector (127 downto 0);-- data in
cb : std_logic_vector(63 downto 0); -- checkbits in
-- Bus/timing control signals
datavalid : std_logic; -- Data-valid signal (DDR2,LPDDR2,LPDDR3)
writereq : std_logic; -- Write-data request (LPDDR2,LPDDR3)
-- Calibration and configuration
regrdata : std_logic_vector(63 downto 0); -- PHY-specific reg in (DDR2)
end record;
constant ddrctrl_in_none : ddrctrl_in_type :=
((others => '0'), (others => '0'), '0', '0', (others => '0'));
type ddrctrl_out_type is record
-- Control signals to memory
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en (DDR1,DDR2,LPDDR1)
rasn : std_ulogic; -- row addr stb (DDR1,DDR2,LPDDR1)
casn : std_ulogic; -- col addr stb (DDR1,DDR2,LPDDR1)
address : std_logic_vector(14 downto 0); -- address out (DDR1,DDR2,LPDDR1)
ba : std_logic_vector (2 downto 0); -- bank address (DDR1,DDR2,LPDDR1)
odt : std_logic_vector(1 downto 0); -- On Die Termination (DDR2,LPDDR3)
ca : std_logic_vector(19 downto 0); -- Ctrl/Addr bus (LPDDR2,LPDDR3)
-- Data signals
data : std_logic_vector(127 downto 0); -- data out
dqm : std_logic_vector(15 downto 0); -- data i/o mask
cb : std_logic_vector(63 downto 0); -- checkbits
cbdqm : std_logic_vector(7 downto 0); -- checkbits data mask
-- Bus/timing control signals
bdrive : std_ulogic; -- bus drive (DDR1,DDR2,LPDDR1)
qdrive : std_ulogic; -- bus drive (DDR1,DDR2,LPDDR1)
nbdrive : std_ulogic; -- bdrive 1 cycle early (DDR2)
sdck : std_logic_vector(2 downto 0); -- Clock enable (DDR1,LPDDR1,LPDDR2,LPDDR3)
moben : std_logic; -- Mobile DDR mode (DDR1/LPDDR1)
oct : std_logic; -- On Chip Termination (DDR2)
dqs_gate : std_logic; -- DQS gate control (DDR2)
read_pend : std_logic_vector(7 downto 0); -- Read pending within 7...0
-- cycles (not including phy
-- delays) (DDR2,LPDDR2,LPDDR3)
wrpend : std_logic_vector(7 downto 0); -- Write pending (LPDDR2,LPDDR3)
boot : std_ulogic; -- Boot clock selection (LPDDR2,LPDDR3)
-- Calibration and configuration
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration (DDR2)
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay (DDR2)
cal_pll : std_logic_vector(1 downto 0); -- (enable,inc/dec) pll phase (DDR2)
cal_rst : std_logic; -- calibration reset (DDR2)
conf : std_logic_vector(63 downto 0); -- Conf. interface (DDR1,LPDDR1)
cbcal_en : std_logic_vector(3 downto 0); -- CB enable delay calib (DDR2)
cbcal_inc : std_logic_vector(3 downto 0); -- CB inc/dec delay (DDR2)
regwdata : std_logic_vector(63 downto 0); -- Reg Write data (DDR2)
regwrite : std_logic_vector(1 downto 0); -- Reg write strobe (DDR2)
-- Status outputs to front-end
ce : std_ulogic; -- Error corrected
end record;
constant ddrctrl_out_none : ddrctrl_out_type :=
((others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
'0', '0', '0', (others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0' );
-----------------------------------------------------------------------------
-- DDR2SPA types and components
-----------------------------------------------------------------------------
-- DDR2 controller without PHY
component ddr2spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
hwidth : in std_ulogic
);
end component;
-- DDR2 controller with PHY
component ddr2spa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
TRFC : integer := 130;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
readdly : integer := 1;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer := 0;
dqsse : integer range 0 to 1 := 0;
burstlen : integer range 4 to 128 := 8;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
ftbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
nclk : integer range 1 to 3 := 3;
scantest : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkref200 : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits+ftbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
ce : out std_logic
);
end component;
-- DDR2 PHY with just data or checkbits+data on same bus, including pads
component ddr2phy_wrap_cbd is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2 ;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
ctrl2en : integer := 0;
resync : integer := 0;
custombits : integer := 8;
extraio : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+(dbits+padbits+chkbits)/8-1 downto 0);-- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-- DDR2 PHY with just data or checkbits+data on same bus, not including pads
component ddr2phy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2 ;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1: integer := 0;
cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
resync : integer := 0;
custombits : integer := 8;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-- DDR2 PHY with separate checkbit and data buses, including pads
component ddr2phy_wrap
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
cben : integer := 0;
chkbits : integer := 8;
ctrl2en : integer := 0;
resync : integer := 0;
custombits : integer := 8;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- DDRSPA types and components
-----------------------------------------------------------------------------
-- DDR/LPDDR controller, without PHY
component ddr1spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer := 0;
ft : integer := 0;
ddr400 : integer := 1;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type
);
end component;
-- DDR/LPDDR controller with PHY
component ddrspa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer range 0 to 1 := 0;
ddr400 : integer := 1;
scantest : integer := 0;
phyiconf : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data
);
end component;
-- DDR/LPDDR PHY, including pads
component ddrphy_wrap
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
scantest : integer := 0;
phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic;
clkread : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0);-- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-- DDR/LPDDR PHY with data and checkbits on same bus, including pads
component ddrphy_wrap_cbd is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
chkbits : integer := 0;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
scantest : integer := 0;
phyiconf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-- DDR/LPDDR PHY with data and checkbits on same bus, without pads
component ddrphy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
component lpddr2phy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
dbits : integer := 16;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
padbits : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic; -- input clock
clkin2 : in std_ulogic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkout2 : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0); -- ddr cmd/addr
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-----------------------------------------------------------------------------
-- Other components using DDRxSPA sub-components
-----------------------------------------------------------------------------
type ddravl_slv_in_type is record
burstbegin : std_ulogic;
addr : std_logic_vector(31 downto 0);
wdata : std_logic_vector(256 downto 0);
be : std_logic_vector(32 downto 0);
read_req : std_ulogic;
write_req : std_ulogic;
size : std_logic_vector(3 downto 0);
end record;
type ddravl_slv_out_type is record
ready : std_ulogic;
rdata_valid : std_ulogic;
rdata : std_logic_vector(256 downto 0);
end record;
constant ddravl_slv_in_none: ddravl_slv_in_type :=
('0',(others => '0'),(others => '0'),(others => '0'),'0','0',(others => '0'));
component ahb2avl_async is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
avldbits : integer := 32;
avlabits : integer := 20
);
port (
rst_ahb : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
rst_avl : in std_ulogic;
clk_avl : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type
);
end component;
end package;
| gpl-2.0 | f8ca1fd2253dc3eb3a83c88c91d204db | 0.495006 | 3.808132 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/sim/delay_wire.vhd | 1 | 2,510 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Delayed bidirectional wire
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity delay_wire is
generic(
data_width : integer := 1;
delay_atob : real := 0.0;
delay_btoa : real := 0.0
);
port(
a : inout std_logic_vector(data_width-1 downto 0);
b : inout std_logic_vector(data_width-1 downto 0);
x : in std_logic_vector(data_width-1 downto 0) := (others => '0')
);
end delay_wire;
architecture rtl of delay_wire is
signal a_dly,b_dly : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
constant zvector : std_logic_vector(data_width-1 downto 0) := (others => 'Z');
function errinj(a,b: std_logic_vector) return std_logic_vector is
variable r: std_logic_vector(a'length-1 downto 0);
begin
r := a;
for k in a'length-1 downto 0 loop
if (a(k)='0' or a(k)='1') and b(k)='1' then
r(k) := not a(k);
end if;
end loop;
return r;
end;
begin
process(a)
begin
if a'event then
if b_dly = zvector then
a_dly <= transport a after delay_atob*1 ns;
else
a_dly <= (others => 'Z');
end if;
end if;
end process;
process(b)
begin
if b'event then
if a_dly = zvector then
b_dly <= transport errinj(b,x) after delay_btoa*1 ns;
else
b_dly <= (others => 'Z');
end if;
end if;
end process;
a <= b_dly; b <= a_dly;
end;
| gpl-2.0 | f2f88a4e5d2db705eff76d434622e987 | 0.576096 | 3.627168 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/police/simulation/police_synth.vhd | 1 | 6,820 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: police_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY police_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE police_synth_ARCH OF police_synth IS
COMPONENT police_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: police_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | f8548198e6e53fceb2fca0b0fab1f4a2 | 0.580059 | 3.801561 | false | false | false | false |
Yuriu5/MiniBlaze | src/hw1/spec_reg_pkg.vhd | 1 | 3,951 | -- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : spec_reg_pkg
-- Date : 07/07/2016
--
-- Description : Mapping of the special register bank
--
-- --------------------------------------------------------------------------------
-- Modifications
-- --------------------------------------------------------------------------------
-- Date : Ver. : Author : Modification comments
-- --------------------------------------------------------------------------------
-- : : :
-- 07/07/2016 : 1.0 : B.Lemoine : First draft
-- : : :
-- **********************************************************************************
-- MIT License
--
-- Copyright (c) 07/07/2016, Benjamin Lemoine
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- **********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package spec_reg_pkg is
-- Addr of special register in the bank
constant Addr_PC : std_logic_vector(3 downto 0) := x"0";
constant Addr_MSR : std_logic_vector(3 downto 0) := x"1";
constant Addr_EAR : std_logic_vector(3 downto 0) := x"2";
constant Addr_ESR : std_logic_vector(3 downto 0) := x"3";
constant Addr_BTR : std_logic_vector(3 downto 0) := x"4";
constant Addr_FSR : std_logic_vector(3 downto 0) := x"5";
constant Addr_EDR : std_logic_vector(3 downto 0) := x"6";
constant Addr_PID : std_logic_vector(3 downto 0) := x"7";
constant Addr_ZPR : std_logic_vector(3 downto 0) := x"8";
constant Addr_TLBLO : std_logic_vector(3 downto 0) := x"9";
constant Addr_TLBHI : std_logic_vector(3 downto 0) := x"A";
constant Addr_TLBX : std_logic_vector(3 downto 0) := x"B";
constant Addr_TLBSX : std_logic_vector(3 downto 0) := x"C";
constant Addr_PVR : std_logic_vector(3 downto 0) := x"D";
-- Machine special register (MSR)
constant MSR_BE : natural := 0;
constant MSR_IE : natural := 1;
constant MSR_C : natural := 2;
constant MSR_BIP : natural := 3;
constant MSR_FSL : natural := 4;
constant MSR_ICE : natural := 5;
constant MSR_DZO : natural := 6;
constant MSR_DCE : natural := 7;
constant MSR_EE : natural := 8;
constant MSR_EIP : natural := 9;
constant MSR_PVR : natural := 10;
constant MSR_UM : natural := 11;
constant MSR_UMS : natural := 12;
constant MSR_VM : natural := 13;
constant MSR_VMS : natural := 14;
constant MSR_CC : natural := 31;
end spec_reg_pkg; | mit | 0bfe4775fcb82950bae0279690e89e93 | 0.529486 | 4.060637 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_s2mm_basic_wrap.vhd | 5 | 49,570 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_s2mm_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_reset;
use axi_sg_v4_1.axi_sg_cmd_status;
use axi_sg_v4_1.axi_sg_scc_wr;
use axi_sg_v4_1.axi_sg_addr_cntl;
use axi_sg_v4_1.axi_sg_wrdata_cntl;
use axi_sg_v4_1.axi_sg_wr_status_cntl;
Use axi_sg_v4_1.axi_sg_skid2mm_buf;
Use axi_sg_v4_1.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_s2mm_basic_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0); --
-- S2MM Halt request input control ---------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------------
-- S2MM Error discrete output --------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------------
-- Optional Command/Status Interface Clock and Reset Inputs -------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ------------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
---------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(7 downto 0); --
s2mm_sts_wstrb : out std_logic_vector(0 downto 0); --
s2mm_sts_wlast : out std_logic; --
--------------------------------------------------------------------
-- Address posting controls ----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
--------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_sg_s2mm_basic_wrap;
architecture implementation of axi_sg_s2mm_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 256 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 256 := C_S2MM_SDATA_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (C_TAG_WIDTH+C_S2MM_ADDR_WIDTH+32);
Constant S2MM_STS_WIDTH : integer := 8; -- always 8 for S2MM Basic Version
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := 1;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := 1;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant S2MM_BURST_SIZE : integer range 16 to 256 := 16;
Constant WR_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2;-- 2 added for going
-- full thresholding
-- in WSC
Constant SEL_ADDR_WIDTH : integer := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := 1;
Constant OMIT_S2MM_DRE : integer range 0 to 1 := 0;
Constant OMIT_INDET_BTT : integer := 0;
Constant SF_BYTES_RCVD_WIDTH : integer := 1;
Constant ZEROS_8_BIT : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal skid2wdc_wvalid : std_logic := '0';
signal wdc2skid_wready : std_logic := '0';
signal skid2wdc_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2wdc_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2wdc_wlast : std_logic := '0';
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
begin --(architecture implementation)
-- Debug Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE2222" ; -- 32 bit Constant indicating S2MM Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(19) <= '0' ; -- OKAY not used by TB
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wstrb <= sig_skid2axi_wstrb ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= sg_ctl (3 downto 0); -- SG Cache from register
s2mm_awuser <= sg_ctl (7 downto 4); -- SG Cache from register
sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
-- No Realigner in S2MM Basic
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_sg_v4_1.axi_sg_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1.axi_sg_scc_wr
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_ADDR_FIFO_DEPTH => WR_ADDR_CNTL_FIFO_DEPTH ,
--C_ADDR_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => s2mm_allow_addr_req ,
addr_req_posted => s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_S2MM_STRM_SKID_BUF : entity axi_sg_v4_1.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => S2MM_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => s2mm_aclk ,
-- arst => sig_mmap_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => s2mm_strm_wvalid ,
-- s_ready => s2mm_strm_wready ,
-- s_data => s2mm_strm_wdata ,
-- s_strb => s2mm_strm_wstrb ,
-- s_last => s2mm_strm_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => skid2wdc_wvalid ,
-- m_ready => wdc2skid_wready ,
-- m_data => skid2wdc_wdata ,
-- m_strb => skid2wdc_wstrb ,
-- m_last => skid2wdc_wlast
--
-- );
--
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_sg_v4_1.axi_sg_wrdata_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_REALIGNER_INCLUDED => OMIT_S2MM_DRE ,
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_skid2axi_wdata,-- sig_data2skid_wdata ,
data2skid_wstrb => sig_skid2axi_wstrb,-- sig_data2skid_wstrb ,
data2skid_wlast => sig_skid2axi_wlast,-- sig_data2skid_wlast ,
data2skid_wvalid => sig_skid2axi_wvalid,-- sig_data2skid_wvalid ,
skid2data_wready => sig_axi2skid_wready,-- sig_skid2data_wready ,
s2mm_strm_wvalid => s2mm_strm_wvalid, --skid2wdc_wvalid ,
s2mm_strm_wready => s2mm_strm_wready, --wdc2skid_wready ,
s2mm_strm_wdata => s2mm_strm_wdata, --skid2wdc_wdata ,
s2mm_strm_wstrb => s2mm_strm_wstrb, --skid2wdc_wstrb ,
s2mm_strm_wlast => s2mm_strm_wlast, --skid2wdc_wlast ,
s2mm_strm_eop => s2mm_strm_wlast, --skid2wdc_wlast ,
s2mm_stbs_asserted => ZEROS_8_BIT ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
-- I_S2MM_MMAP_SKID_BUF : entity axi_sg_v4_1.axi_sg_skid2mm_buf
-- generic map (
--
-- C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
-- C_SDATA_WIDTH => S2MM_SDATA_WIDTH ,
-- C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- ACLK => s2mm_aclk ,
-- ARST => sig_stream_rst ,
--
-- -- Slave Side (Wr Data Controller Input Side )
-- S_ADDR_LSB => sig_data2skid_addr_lsb,
-- S_VALID => sig_data2skid_wvalid ,
-- S_READY => sig_skid2data_wready ,
-- S_Data => sig_data2skid_wdata ,
-- S_STRB => sig_data2skid_wstrb ,
-- S_Last => sig_data2skid_wlast ,
--
-- -- Master Side (MMap Write Data Output Side)
-- M_VALID => sig_skid2axi_wvalid ,
-- M_READY => sig_axi2skid_wready ,
-- M_Data => sig_skid2axi_wdata ,
-- M_STRB => sig_skid2axi_wstrb ,
-- M_Last => sig_skid2axi_wlast
--
-- );
--
end implementation;
| gpl-3.0 | 8ad551eee14ed452dae56e30f955aa9b | 0.439661 | 4.074805 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-xc6s/testbench.vhd | 1 | 12,405 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
library hynix;
use hynix.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(31 downto 24);
signal pio : std_logic_vector(17 downto 0);
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal wdogn : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal erx_dv, erx_dv_d, etx_en: std_logic:='0';
signal erxd, erxd_d, etxd: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdint : std_ulogic;
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic := '0';
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal clk2 : std_ulogic := '0';
signal clk125 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(9 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
signal erx_er : std_logic := '0';
signal erx_col : std_logic := '0';
signal erx_crs : std_logic := '1';
signal etx_er : std_logic := '0';
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 4 ns;
--erx_clk <= not erx_clk after 4 ns;
clk2 <= '0'; --not clk2 after 5 ns;
rst <= dsurst and wdogn;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
ps2clk <= "HH"; ps2data <= "HH";
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
wdogn <= 'H';
switch(7) <= '1';
switch(8) <= '0';
emdio <= 'H';
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, clk2, clk125, wdogn, address(24 downto 0), data,
oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_we, ddr_ras, ddr_csb ,ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, txd2, rxd2, ctsn2, rtsn2, pio, genio,
switch, led, erx_clk, emdio, erxd(3 downto 0)'delayed(1 ns), erx_dv'delayed(1 ns), emdint,
etx_clk, etxd(3 downto 0), etx_en, emdc,
ps2clk, ps2data, iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spw_clk, spw_rxdp, spw_rxdn,
spw_rxsp, spw_rxsn, spw_txdp, spw_txdn, spw_txsp, spw_txsn,
spi_sel_n, spi_clk, spi_mosi
);
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
ddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr2mem0 : for i in 0 to 0 generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => false, PUSCheckFlag => false,
index => i, bbits => 16, fname => sdramfile, fdelay => 340)
port map (DQ => ddr_dq(i*16+15 downto i*16),
LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2),
UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1),
LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas,
RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba(1 downto 0),
ADDR => ddr_ad(12 downto 0), CKE => ddr_cke,
CLK => ddr_clk, CLKB => ddr_clkb, UDM => ddr_dm(i*2+1));
end generate;
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(address => 1)
port map(rst, emdio, open, erx_clk, erxd_d, erx_dv_d,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, clk125);
end generate;
rcxclkp : process(erx_clk) is
begin
erxd <= erxd_d;
erx_dv <= erx_dv_d;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 201 us;
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
iuerr : process
begin
wait until dsurst = '1';
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-2.0 | 5b103dd6d0cba7e1d9a6d93be994fcee | 0.582104 | 2.953571 | false | false | false | false |
Yuriu5/MiniBlaze | src/hw1/ALU.vhd | 1 | 8,041 | -- **********************************************************************************
-- Project : MiniBlaze
-- Author : Benjamin Lemoine
-- Module : ALU
-- Date : 07/07/2016
--
-- Description : Arithmetic Logic Unit
--
-- --------------------------------------------------------------------------------
-- Modifications
-- --------------------------------------------------------------------------------
-- Date : Ver. : Author : Modification comments
-- --------------------------------------------------------------------------------
-- : : :
-- 07/07/2016 : 1.0 : B.Lemoine : First draft
-- : : :
-- **********************************************************************************
-- MIT License
--
-- Copyright (c) 07/07/2016, Benjamin Lemoine
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- **********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.ALU_pkg.all;
entity ALU is
generic(
DATA_WIDTH : natural := 32
);
port(
param_i : in t_param_alu;
carry_i : in std_logic;
operandA_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
operandB_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
operandD_o : out std_logic_vector(DATA_WIDTH - 1 downto 0);
status_o : out t_status_alu_out
);
end ALU;
architecture rtl of ALU is
begin
p_alu : process(param_i, carry_i, operandA_i, operandB_i)
variable result : signed(DATA_WIDTH downto 0) := (others => '0');
variable result_add : signed(DATA_WIDTH downto 0) := (others => '0');
variable result_mult : signed(2*(DATA_WIDTH-1)+1 downto 0) := (others => '0');
variable carry_in : std_logic := '0';
variable carry_out : std_logic := '0';
variable zero_out : std_logic := '0';
variable negative_out : std_logic := '0';
variable overflow_out : std_logic := '0';
variable parity_out : std_logic := '0';
variable result_out : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
variable operandA_sext8 : std_logic_vector(DATA_WIDTH - 9 downto 0) := (others => '0');
variable operandA_signed : signed(DATA_WIDTH - 1 downto 0) := (others => '0');
variable operandB_signed : signed(DATA_WIDTH - 1 downto 0) := (others => '0');
variable operandA_unsigned : unsigned(DATA_WIDTH - 1 downto 0) := (others => '0');
variable operandB_unsigned : unsigned(DATA_WIDTH - 1 downto 0) := (others => '0');
variable operandA : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
variable operandB : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
variable dbg : std_logic_vector(0 downto 0);
begin
operandA_sext8 := (others => operandA_i(7));
operandA_signed := signed(operandA_i);
operandB_signed := signed(operandB_i);
operandA_unsigned := unsigned(operandA_i);
operandB_unsigned := unsigned(operandB_i);
operandA := operandA_i;
operandB := operandB_i;
-- Chose carry in
case param_i.ctrl_op.whichCarry is
when CARRY_INPUT =>
carry_in := carry_i;
when CARRY_ONE =>
carry_in := '1';
when CARRY_ZERO =>
carry_in := '0';
when CARRY_ARITH =>
carry_in := operandA(operandA'left);
end case;
if param_i.ctrl_op.negOperandA = '1' then
operandA := not operandA;
end if;
if param_i.ctrl_op.negOperandB = '1' then
operandB := not operandB;
end if;
result_add := signed(add(operandA, operandB, carry_in));
result_mult := signed(multiply(operandA, operandB));
case param_i.operation is
when OP_PTA =>
result := operandA_signed(31) & operandA_signed;
when OP_PTB =>
result := operandB_signed(31) & operandB_signed;
when OP_ADD =>
result := result_add;
when OP_AND =>
result := signed('0' & (operandA and operandB));
when OP_OR =>
result := signed('0' & (operandA or operandB));
when OP_SHIFT =>
result := operandA_signed(0) & carry_in & operandA_signed(operandA_signed'left downto 1);
when OP_XOR =>
result := signed('0' & (operandA xor operandB));
when OP_SEXT8 =>
result := '0' & signed(operandA_sext8) & signed(operandA(7 downto 0));
when OP_SEXT16 =>
result := '0' & resize(operandA_signed(15 downto 0), DATA_WIDTH);
when OP_MULT =>
case param_i.ctrl_op.multType is
when LSW => result := result_mult(DATA_WIDTH downto 0);
when HSW => result := result_mult(2*(DATA_WIDTH-1)+1) & result_mult(2*(DATA_WIDTH-1)+1 downto DATA_WIDTH);
end case;
when OP_BS =>
case param_i.ctrl_op.ctrlShift is
when LEFT_SHIFT => result := '0' & shift_left(operandA_signed, to_integer(operandB_unsigned(4 downto 0)));
when RIGHT_SHIFT_ARITH => result := '0' & shift_right(operandA_signed, to_integer(operandB_unsigned(4 downto 0))); -- Insert left most b
when RIGHT_SHIFT_LOGIC => result := '0' & signed(shift_right(operandA_unsigned, to_integer(operandB_unsigned(4 downto 0)))); -- Insert 0
when others => result := (others => '0');
end case;
when others =>
result := (others => '0');
assert false report "Unknown operation for ALU" severity error;
end case;
carry_out := result(DATA_WIDTH);
result_out := std_logic_vector(result(DATA_WIDTH-1 downto 0));
zero_out := is_zero(result_out);
negative_out := is_negative(result_out);
overflow_out := (not carry_out and result_out(result_out'left)) or (carry_out and not result_out(result_out'left));
parity_out := '0'; -- TODO
-- Mapping output
status_o.carry <= carry_out;
status_o.zero <= zero_out;
status_o.negative <= negative_out;
status_o.overflow <= overflow_out;
status_o.parity <= parity_out;
operandD_o <= result_out;
end process;
end rtl;
| mit | 48328532aeee8447ca04a542fabac357 | 0.511379 | 4.125705 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-terasic-de4/ddr2if.vhd | 1 | 9,346 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity ddr2if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
burstlen: integer := 8
);
port (
pll_ref_clk : in std_ulogic;
global_reset_n : in std_ulogic;
mem_a : out std_logic_vector(13 downto 0);
mem_ba : out std_logic_vector(2 downto 0);
mem_ck : out std_logic_vector(1 downto 0);
mem_ck_n : out std_logic_vector(1 downto 0);
mem_cke : out std_logic;
mem_cs_n : out std_logic;
mem_dm : out std_logic_vector(7 downto 0);
mem_ras_n : out std_logic;
mem_cas_n : out std_logic;
mem_we_n : out std_logic;
mem_dq : inout std_logic_vector(63 downto 0);
mem_dqs : inout std_logic_vector(7 downto 0);
mem_dqs_n : inout std_logic_vector(7 downto 0);
mem_odt : out std_logic;
ahb_clk : in std_ulogic;
ahb_rst : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
oct_rdn : in std_logic;
oct_rup : in std_logic
);
end;
architecture rtl of ddr2if is
component ddr2ctrl is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
avl_ready : out std_logic; -- avl.waitrequest_n
avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avl_rdata_valid : out std_logic; -- .readdatavalid
avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
avl_wdata : in std_logic_vector(255 downto 0) := (others => '0'); -- .writedata
avl_be : in std_logic_vector(31 downto 0) := (others => '0'); -- .byteenable
avl_read_req : in std_logic := '0'; -- .read
avl_write_req : in std_logic := '0'; -- .write
avl_size : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end component ddr2ctrl;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr : std_logic_vector(1 downto 0);
signal ras_n_arr, cas_n_arr, we_n_arr, odt_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
signal rdata, wdata : std_logic_vector(255 downto 0);
signal be: std_logic_vector(31 downto 0);
begin
vcc <= '1';
mem_ras_n <= ras_n_arr(0);
mem_cas_n <= cas_n_arr(0);
mem_we_n <= we_n_arr(0);
mem_ck <= ck_p_arr;
mem_ck_n <= ck_n_arr;
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
mem_odt <= odt_arr(0);
avlso.rdata(255 downto 0) <= rdata(255 downto 0);
wdata <= avlsi.wdata(255 downto 0);
be <= avlsi.be(31 downto 0);
ctrl0: ddr2ctrl
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_a => mem_a,
mem_ba => mem_ba,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_ras_n => ras_n_arr,
mem_cas_n => cas_n_arr,
mem_we_n => we_n_arr,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
mem_odt => odt_arr,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(24 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => rdata,
avl_wdata => wdata,
avl_be => be,
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size(2 downto 0),
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rdn => oct_rdn,
oct_rup => oct_rup
);
avlso.rdata(avlso.rdata'high downto 256) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
avldbits => 256,
avlabits => 25
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
| gpl-2.0 | 4d4093eb467efcdb7f980c018bbddd7b | 0.445538 | 3.7384 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/unisim/clkgen_virtex.vhd | 1 | 21,645 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.CLKDLL;
use unisim.BUFGDLL;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture rtl of clkgen_virtex is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, dll0rst, dll0lock, dll1lock : std_logic;
signal dll1rst : std_logic_vector(0 to 3);
signal clk0B, clkint, CLK2XL, CLKDV, CLK180, pciclkint : std_logic;
begin
gnd <= '0'; clk <= clk_i; clkn <= not clk_i;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0rst <= not cgi.pllrst;
dll0 : CLKDLL
port map (CLKIN => clkint, CLKFB => clk_k, CLK0 => clk_j, CLK180 => CLK180,
CLK2X => CLK2XL, CLKDV => CLKDV, LOCKED => dll0lock, RST => dll0rst);
clk0B <= CLK2XL when clk_mul/clk_div = 2
else CLKDV when clk_div/clk_mul = 2 else clk_j;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB = 0) generate
cgo.clklock <= dll1lock;
dll1 : CLKDLL
port map (CLKIN => clk_i, CLKFB => cgi.pllref, RST => dll1rst(0), CLK0 => sdclk,
CLK2X => clk2x, LOCKED => dll1lock);
rstdel : process (clk_i)
begin
if dll0lock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_i) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if not ((SDRAMEN /= 0) and (NOCLKFB = 0)) generate
sdclk <= clk_i; cgo.clklock <= dll0lock;
end generate;
cgo.pcilock <= '1';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.IBUFG;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex2 clock generator ---------------------------------------
------------------------------------------------------------------
entity clkgen_virtex2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex2 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IBUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint, pciclkl, pciclkfb, pciclk0 : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
p2 : if (PCIDLL /= 0) and ( PCIDLL /= 1) generate
x1 : IBUFG port map (I => pciclkint, O => pciclkl);
dll0 : DCM
generic map (CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => PCIDLL)
port map ( CLKIN => pciclkint, CLKFB => pciclkfb,
DSSEN => gnd, PSCLK => gnd,
RST => gnd, PSEN => gnd, PSINCDEC => gnd, CLK0 => pciclk0);
x2 : BUFG port map (I => pciclk0, O => pciclkfb);
pciclk <= pciclkfb;
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
bufg3 : BUFG port map (I => clk_x, O => clk_i2);
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex2" & ": virtex-2 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex2" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkmul_virtex2 is
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end;
architecture struct of clkmul_virtex2 is
-- attribute CLKFX_MULTIPLY : string;
-- attribute CLKFX_DIVIDE : string;
-- attribute CLKIN_PERIOD : string;
--
-- attribute CLKFX_MULTIPLY of dll0: label is "5";
-- attribute CLKFX_DIVIDE of dll0: label is "4";
-- attribute CLKIN_PERIOD of dll0: label is "20";
--
-- attribute CLKFX_MULTIPLY of dll1: label is "4";
-- attribute CLKFX_DIVIDE of dll1: label is "4";
-- attribute CLKIN_PERIOD of dll1: label is "25";
--
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal gnd, clk_i, clk_j, clk_k, clk_l : std_logic;
signal clk0B, clk_FB, dll0rst, lock : std_logic;
begin
gnd <= '0'; clk <= clk_i;
dll0rst <= not resetin;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clkin, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
LOCKED => resetout, CLKFX => clk0B );
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_spartan3 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 50000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_spartan3 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r, dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= not clk_i when (CLK2XEN = 0) else not clk_p;
clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_j;
clk2xu <= clk_k;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_x, O => clk_k);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "2X")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
clk2xgen : if (CLK2XEN /= 0) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_k;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => sdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_spartan3e" & ": spartan3/e sdram/pci clock generator, version " & tost(VERSION),
"clkgen_spartan3e" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-2.0 | dd6b3021100bb7c5df67968686ab80fc | 0.586602 | 3.281037 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma_reset.vhd | 1 | 41,264 | -------------------------------------------------------------------------------
-- axi_cdma_reset
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_reset.vhd
-- Description: This entity is reset module entity for the AXI DMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_cdma_v4_1;
use axi_cdma_v4_1.axi_cdma_pulse_gen;
use axi_cdma_v4_1.axi_cdma_pkg.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_cdma_reset is
Generic (
C_AXI_LITE_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the AXI Lite Register interface needs to
-- be asynchronous to the CDMA data transport path clocking
-- 0 = Use same clocking as data path (Primary)
-- 1 = Use special AXI Lite clock for the axi lite interface
C_SOFT_RST_TIME_CLKS : integer range 1 to 64 := 8
-- Specifies the time of the soft reset assertion in
-- axi_aclk clock periods.
);
port (
-- Primary Clock and Reset Sources
axi_aclk : in std_logic ;--
axi_resetn : in std_logic ;--
-- AXI Lite Clock and Reset Sources
axi_lite_aclk : in std_logic ;--
axi_lite_resetn : in std_logic ;--
-- HW Reset out to the axi4-lite bus side interface logic
rst2lite_bside_reset : Out std_logic ;
-- HW Reset out to the axi4-lite core side interface logic
rst2lite_cside_reset : Out std_logic ;
-- HW Reset out to the register module logic
rst2reg_reset : Out std_logic ;
-- HW Reset out to the simple controller module logic
rst2cntlr_reset : Out std_logic ;
-- HW Reset out to the SG controller module logic
rst2sgcntlr_reset : Out std_logic ;
-- HW Reset out to the SG module
rst2sg_resetn : Out std_logic ;
-- HW Reset out to the datamover module
rst2dm_resetn : Out std_logic ;
-- Soft Reset Request from Register module
reg2rst_soft_reset_in : in std_logic ;
-- Soft Reset clear to the Register module
rst2reg_soft_reset_clr : Out std_logic ;
-- Halt request to the Simple Controller
rst2cntlr_halt : Out std_logic ;
-- Halt complete from the Simple Controller
cntlr2rst_halt_cmplt : in std_logic ;
-- Halt request to the SG Controller
rst2sg_halt : Out std_logic ;
-- Halt complete from the SG Controller
sg2rst_halt_cmplt : in std_logic ;
-- Halt request to the DataMover MM2S function
rst2dm_mm2s_halt : Out std_logic ;
-- Halt complete from the DataMover MM2S function
dm2rst_mm2s_halt_cmplt : in std_logic ;
-- Halt request to the DataMover S2MM function
rst2dm_s2mm_halt : Out std_logic ;
-- Halt complete from the DataMover S2MM function
dm2rst_s2mm_halt_cmplt : in std_logic
);
end axi_cdma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant INCLUDE_SYNCHRONIZERS : integer := 1 ;
Constant NO_SYNCHRONIZERS : integer := 0 ;
Constant POSITIVE_EDGE_TRIGGER : integer := 1 ;
Constant NEGATIVE_EDGE_TRIGGER : integer := 0 ;
Constant TWO_CLKS : integer := 2 ;
Constant ONE_CLK : integer := 1 ;
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant POR_WIDTH : integer := 8 ;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sig_local_hw_reset_reg : std_logic := '0';
signal sig_lite_bside_hw_reset_reg : std_logic := '0';
signal sig_lite_cside_hw_reset_reg : std_logic := '0';
signal sig_composite_reg_reset : std_logic := '0';
signal sig_composite_cntlr_reset : std_logic := '0';
signal sig_composite_sgcntlr_reset : std_logic := '0';
signal sig_composite_sg_reset_n : std_logic := '0';
signal sig_composite_dm_reset_n : std_logic := '0';
signal sig_dm_soft_reset_n : std_logic := '0';
signal sig_rst2reg_soft_reset : std_logic := '0';
signal sig_rst2reg_soft_reset_trig : std_logic := '0';
signal sig_rst2reg_soft_reset_clr : std_logic := '0';
signal sig_soft_reset : std_logic := '0';
signal sig_soft_reset_reg : std_logic := '0';
signal sig_trig_soft_reset : std_logic := '0';
signal sig_halt_request : std_logic := '0';
signal sig_halt_cmplt : std_logic := '0';
signal sig_axi_por_reg1 : std_logic := '0';
signal sig_axi_por_reg2 : std_logic := '0';
signal sig_axi_por_reg3 : std_logic := '0';
signal sig_axi_por_reg4 : std_logic := '0';
signal sig_axi_por_reg5 : std_logic := '0';
signal sig_axi_por_reg6 : std_logic := '0';
signal sig_axi_por_reg7 : std_logic := '0';
signal sig_axi_por_reg8 : std_logic := '0';
signal sig_axi_por2rst : std_logic := '0';
signal sig_axi_por2rst_out : std_logic := '0';
signal sig_axilite_por_reg1 : std_logic := '0';
signal sig_axilite_por_reg2 : std_logic := '0';
signal sig_axilite_por_reg3 : std_logic := '0';
signal sig_axilite_por_reg4 : std_logic := '0';
signal sig_axilite_por_reg5 : std_logic := '0';
signal sig_axilite_por_reg6 : std_logic := '0';
signal sig_axilite_por_reg7 : std_logic := '0';
signal sig_axilite_por_reg8 : std_logic := '0';
signal sig_axilite_por2rst : std_logic := '0';
signal sig_axilite_por2rst_out : std_logic := '0';
-- Register duplication attribute assignments to control fanout
-- on reset signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_lite_bside_hw_reset_reg : signal is "TRUE";
Attribute KEEP of sig_lite_cside_hw_reset_reg : signal is "TRUE";
Attribute KEEP of sig_composite_reg_reset : signal is "TRUE";
Attribute KEEP of sig_composite_cntlr_reset : signal is "TRUE";
Attribute KEEP of sig_composite_sgcntlr_reset : signal is "TRUE";
Attribute KEEP of sig_composite_sg_reset_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_lite_bside_hw_reset_reg : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_lite_cside_hw_reset_reg : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_composite_reg_reset : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_composite_cntlr_reset : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_composite_sgcntlr_reset : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_composite_sg_reset_n : signal is "no";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Assign Reset Output Ports
rst2lite_bside_reset <= sig_lite_bside_hw_reset_reg ;
rst2lite_cside_reset <= sig_lite_cside_hw_reset_reg ;
rst2reg_reset <= sig_composite_reg_reset ;
rst2cntlr_reset <= sig_composite_cntlr_reset ;
rst2sgcntlr_reset <= sig_composite_sgcntlr_reset ;
rst2sg_resetn <= sig_composite_sg_reset_n ;
rst2dm_resetn <= sig_composite_dm_reset_n ;
-- Assign the soft Reset Request and Clear Ports
sig_rst2reg_soft_reset <= reg2rst_soft_reset_in ;
rst2reg_soft_reset_clr <= sig_rst2reg_soft_reset_clr ;
-- Assign the Halt and Halt Cmplt Ports
rst2cntlr_halt <= sig_halt_request;
rst2sg_halt <= sig_halt_request;
rst2dm_mm2s_halt <= sig_halt_request;
rst2dm_s2mm_halt <= sig_halt_request;
------------------------------------------------------------
-- Start Power On Reset (POR) Logic
------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: AXI_POR_REG1
--
-- Process Description:
-- This process generates an 4-clock wide pulse that
-- only occurs immediately after FPGA initialization. This
-- pulse is used to initialize reset logic synchronous to
-- the Main axi_aclk Clock until the Bus Reset occurs.
--
-------------------------------------------------------------
AXI_POR_REG1 : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
sig_axi_por_reg1 <= '1';
sig_axi_por_reg2 <= sig_axi_por_reg1;
sig_axi_por_reg3 <= sig_axi_por_reg2;
sig_axi_por_reg4 <= sig_axi_por_reg3;
sig_axi_por_reg5 <= sig_axi_por_reg4;
sig_axi_por_reg6 <= sig_axi_por_reg5;
sig_axi_por_reg7 <= sig_axi_por_reg6;
sig_axi_por_reg8 <= sig_axi_por_reg7;
sig_axi_por2rst_out <= sig_axi_por2rst ;
end if;
end process AXI_POR_REG1;
sig_axi_por2rst <= not(sig_axi_por_reg1 and
sig_axi_por_reg2 and
sig_axi_por_reg3 and
sig_axi_por_reg4 and
sig_axi_por_reg5 and
sig_axi_por_reg6 and
sig_axi_por_reg7 and
sig_axi_por_reg8 );
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: AXILITE_POR_REG1
--
-- Process Description:
-- This process generates an 8-clock wide pulse that
-- only occurs immediately after FPGA initialization. This
-- pulse is used to initialize reset logic synchronous to
-- the axi_lite_aclk Clock until the Bus Reset occurs.
--
-------------------------------------------------------------
AXILITE_POR_REG1 : process (axi_lite_aclk)
begin
if (axi_lite_aclk'event and axi_lite_aclk = '1') then
sig_axilite_por_reg1 <= '1';
sig_axilite_por_reg2 <= sig_axilite_por_reg1;
sig_axilite_por_reg3 <= sig_axilite_por_reg2;
sig_axilite_por_reg4 <= sig_axilite_por_reg3;
sig_axilite_por_reg5 <= sig_axilite_por_reg4;
sig_axilite_por_reg6 <= sig_axilite_por_reg5;
sig_axilite_por_reg7 <= sig_axilite_por_reg6;
sig_axilite_por_reg8 <= sig_axilite_por_reg7;
sig_axilite_por2rst_out <= sig_axilite_por2rst ;
end if;
end process AXILITE_POR_REG1;
sig_axilite_por2rst <= not(sig_axilite_por_reg1 and
sig_axilite_por_reg2 and
sig_axilite_por_reg3 and
sig_axilite_por_reg4 and
sig_axilite_por_reg5 and
sig_axilite_por_reg6 and
sig_axilite_por_reg7 and
sig_axilite_por_reg8);
------------------------------------------------------------
-- End of Power On Reset (POR) Logic
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Reset Logic Distribution
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_AXI_LITE_SYNC2AXI
--
-- If Generate Description:
-- Generate resets based on AXI Lite clock being the same
-- as the main axi4 clock (synchronous).
--
--
------------------------------------------------------------
GEN_AXI_LITE_SYNC2AXI : if (C_AXI_LITE_IS_ASYNC = 0) generate
begin
sig_composite_dm_reset_n <= axi_resetn and axi_lite_resetn and sig_dm_soft_reset_n;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SYNC_SOFT_RST_FLOP
--
-- Process Description:
-- FLOP for registering the input axi_resetn (inverted).
--
-------------------------------------------------------------
IMP_SYNC_SOFT_RST_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
If (sig_axi_por2rst_out = '1') Then
sig_local_hw_reset_reg <= '1';
sig_composite_reg_reset <= '1';
sig_composite_cntlr_reset <= '1';
sig_composite_sgcntlr_reset <= '1';
sig_composite_sg_reset_n <= '0';
sig_dm_soft_reset_n <= '0';
else
sig_local_hw_reset_reg <= not(axi_resetn) or not(axi_lite_resetn);
sig_composite_reg_reset <= not(axi_resetn) or not(axi_lite_resetn) or sig_soft_reset;
sig_composite_cntlr_reset <= not(axi_resetn) or not(axi_lite_resetn) or sig_soft_reset;
sig_composite_sgcntlr_reset <= not(axi_resetn) or not(axi_lite_resetn) or sig_soft_reset;
sig_composite_sg_reset_n <= axi_resetn and axi_lite_resetn and not(sig_soft_reset);
sig_dm_soft_reset_n <= not(sig_soft_reset);
End if;
end if;
end process IMP_SYNC_SOFT_RST_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SYNC_AXI_LITE_HW_RST_FLOP
--
-- Process Description:
-- FLOP for registering the reset for the AXi Lite Interface.
-- Since the axi_lite_aclk is the same as the axi_aclk,
-- the Bus side and Core side resets can be the same.
-- Note that soft reset is excluded from the AXI Lite reset
-- generation logic.
--
-------------------------------------------------------------
IMP_SYNC_AXI_LITE_HW_RST_FLOP : process (axi_lite_aclk)
begin
if (axi_lite_aclk'event and axi_lite_aclk = '1') then
if (sig_axilite_por2rst = '1') then
sig_lite_bside_hw_reset_reg <= '1';
sig_lite_cside_hw_reset_reg <= '1';
else
sig_lite_bside_hw_reset_reg <= not(axi_lite_resetn) or
not(axi_resetn);
sig_lite_cside_hw_reset_reg <= not(axi_lite_resetn) or
not(axi_resetn);
end if;
end if;
end process IMP_SYNC_AXI_LITE_HW_RST_FLOP;
end generate GEN_AXI_LITE_SYNC2AXI;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_AXI_LITE_ASYNC2AXI
--
-- If Generate Description:
-- Generate resets based on AXI Lite clock being different
-- from the main axi4 clock (asynchronous).
--
--
------------------------------------------------------------
GEN_AXI_LITE_ASYNC2AXI : if (C_AXI_LITE_IS_ASYNC = 1) generate
ATTRIBUTE async_reg : STRING;
signal sig_axi_lite_rst_rsync_min_pulse : std_logic := '0';
signal sig_axi_lite_rst_reg : std_logic := '0';
signal sig_axi_lite_rst_rsync : std_logic := '0';
signal sig_axi_lite_rst_rsync_d1_cdc_tig : std_logic := '0';
signal sig_axi_lite_rst_rsync_d2 : std_logic := '0';
signal sig_axi_rst_rsync_min_pulse : std_logic := '0';
signal sig_axi_rst_reg : std_logic := '0';
signal sig_axi_rst_rsync : std_logic := '0';
signal sig_axi_rst_rsync_d1_cdc_tig : std_logic := '0';
signal sig_axi_rst_rsync_d2 : std_logic := '0';
signal sig_cside2bside_rsync_d1_cdc_tig : std_logic := '0';
signal sig_cside2bside_rsync_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF sig_axi_lite_rst_rsync_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF sig_axi_lite_rst_rsync_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF sig_axi_rst_rsync_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF sig_axi_rst_rsync_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF sig_cside2bside_rsync_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF sig_cside2bside_rsync_d2 : SIGNAL IS "true";
begin
----------------------------------------------------------------
-- AXI Lite RESET to AXI Clock synchronizers
----------------------------------------------------------------
-- Assign a composite reset derived from the AXI Lite Resetn
-- that consistes of a minimum pulse width reset or the resync'd
-- AXI Lite Reset, whichever is asserted longer.
sig_axi_lite_rst_rsync <= sig_axi_lite_rst_rsync_d2 or
sig_axi_lite_rst_rsync_min_pulse;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LITE2AXI_RSYNC
--
-- Process Description:
-- First stage Synchronizer for the AXI_LITE RESETN to AXI
-- clock domain.
--
-------------------------------------------------------------
IMP_LITE2AXI_RSYNC : process (axi_lite_aclk)
begin
if (axi_lite_aclk'event and axi_lite_aclk = '1') then
if (sig_axilite_por2rst = '1') then
sig_axi_lite_rst_reg <= '1';
else
sig_axi_lite_rst_reg <= not(axi_lite_resetn);
end if;
end if;
end process IMP_LITE2AXI_RSYNC;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ALITE_RST_RESYNC
--
-- Process Description:
-- Second stage synchronizers for the axi lite resetn to
-- AXi clock domain.
--
-------------------------------------------------------------
IMP_ALITE_RST_RESYNC : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_axi_lite_rst_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_aclk,
scndry_resetn => '0',
scndry_out => sig_axi_lite_rst_rsync_d2,
scndry_vect_out => open
);
-- IMP_ALITE_RST_RESYNC : process (axi_aclk)
-- begin
-- if (axi_aclk'event and axi_aclk = '1') then
-- if (sig_axi_por2rst = '1') then
--
-- sig_axi_lite_rst_rsync_d1_cdc_tig <= '1';
-- sig_axi_lite_rst_rsync_d2 <= '1';
--
-- else
--
-- sig_axi_lite_rst_rsync_d1_cdc_tig <= sig_axi_lite_rst_reg;
-- sig_axi_lite_rst_rsync_d2 <= sig_axi_lite_rst_rsync_d1_cdc_tig;
--
-- end if;
-- end if;
-- end process IMP_ALITE_RST_RESYNC;
----------------------------------------------------------------
-- AXI RESET to AXI Lite Clock synchronizers
----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_AXI_RST_REG
--
-- Process Description:
-- First stage register for synchronizer for AXI_RESETN to
-- AXI Lite Clock Domain.
--
-------------------------------------------------------------
IMP_AXI_RST_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_axi_por2rst = '1') then
sig_axi_rst_reg <= '1';
else
sig_axi_rst_reg <= not(axi_resetn);
end if;
end if;
end process IMP_AXI_RST_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_AXI2LITE_RSYNC
--
-- Process Description:
-- Second stage Synchronizers for the AXI_RESETN to AXI
-- Lite clock domain.
--
-------------------------------------------------------------
IMP_AXI2LITE_RSYNC : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_axi_rst_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_lite_aclk,
scndry_resetn => '0',
scndry_out => sig_axi_rst_rsync_d2,
scndry_vect_out => open
);
-- IMP_AXI2LITE_RSYNC : process (axi_lite_aclk)
-- begin
-- if (axi_lite_aclk'event and axi_lite_aclk = '1') then
-- if (sig_axilite_por2rst = '1') then
--
-- sig_axi_rst_rsync_d1_cdc_tig <= '1';
-- sig_axi_rst_rsync_d2 <= '1';
--
-- else
--
-- sig_axi_rst_rsync_d1_cdc_tig <= sig_axi_rst_reg;
-- sig_axi_rst_rsync_d2 <= sig_axi_rst_rsync_d1_cdc_tig;
--
-- end if;
--
-- end if;
-- end process IMP_AXI2LITE_RSYNC;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_AXI_LITE_DELAY
--
-- Process Description:
-- Special Synchronizers for ensuring the Bus side always
-- comes out of reset after the C_side does.
--
-------------------------------------------------------------
IMP_AXI_LITE_DELAY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_lite_cside_hw_reset_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_lite_aclk,
scndry_resetn => '0',
scndry_out => sig_cside2bside_rsync_d2,
scndry_vect_out => open
);
-- IMP_AXI_LITE_DELAY : process (axi_lite_aclk)
-- begin
-- if (axi_lite_aclk'event and axi_lite_aclk = '1') then
-- if (sig_axilite_por2rst = '1') then
--
-- sig_cside2bside_rsync_d1_cdc_tig <= '1';
-- sig_cside2bside_rsync_d2 <= '1';
--
-- else
--
-- sig_cside2bside_rsync_d1_cdc_tig <= sig_lite_cside_hw_reset_reg;
-- sig_cside2bside_rsync_d2 <= sig_cside2bside_rsync_d1_cdc_tig;
--
-- end if;
--
-- end if;
-- end process IMP_AXI_LITE_DELAY;
sig_axi_rst_rsync <= sig_axi_rst_rsync_d2 or
sig_cside2bside_rsync_d2;
------------------------------------------------------------
-- Instance: I_AXI_LITE_RST_RSYNC
--
-- Description:
-- This PulsGen synchronizes the AXI Lite Reset to the Main
-- AXI Clock and assures a minimum reset pulse width.
--
------------------------------------------------------------
I_AXI_LITE_RST_RSYNC : entity axi_cdma_v4_1.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => INCLUDE_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => NEGATIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => C_SOFT_RST_TIME_CLKS
)
port map (
Clk_In => axi_aclk ,
--Rst_In => LOGIC_LOW ,
Rst_In => sig_axi_por2rst ,
Sig_in => axi_lite_resetn ,
--Pulse_Out => sig_axi_lite_rst_rsync
Pulse_Out => sig_axi_lite_rst_rsync_min_pulse
);
------------------------------------------------------------
-- Instance: I_AXI_RST_RSYNC
--
-- Description:
-- This PulsGen synchronizes the AXI Reset to the AXI Lite
-- Clock
--
------------------------------------------------------------
I_AXI_RST_RSYNC : entity axi_cdma_v4_1.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => INCLUDE_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => NEGATIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => C_SOFT_RST_TIME_CLKS
)
port map (
Clk_In => axi_lite_aclk ,
-- Rst_In => LOGIC_LOW ,
Rst_In => sig_axilite_por2rst ,
Sig_in => axi_resetn ,
Pulse_Out => sig_axi_rst_rsync_min_pulse
);
sig_composite_dm_reset_n <= axi_resetn and
not(sig_axi_lite_rst_rsync) and
sig_dm_soft_reset_n;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ASYNC_SOFT_RST_FLOP
--
-- Process Description:
-- FLOP for registering the input axi_resetn (inverted).
--
-------------------------------------------------------------
IMP_ASYNC_SOFT_RST_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_axi_por2rst = '1') then
sig_local_hw_reset_reg <= '1';
sig_composite_reg_reset <= '1';
sig_composite_cntlr_reset <= '1';
sig_composite_sgcntlr_reset <= '1';
sig_composite_sg_reset_n <= '0';
sig_dm_soft_reset_n <= '0';
else
sig_local_hw_reset_reg <= not(axi_resetn) or
--not(sig_axi_lite_rst_rsync);
sig_axi_lite_rst_rsync;
sig_composite_reg_reset <= not(axi_resetn) or
sig_axi_lite_rst_rsync or
sig_soft_reset;
sig_composite_cntlr_reset <= not(axi_resetn) or
sig_axi_lite_rst_rsync or
sig_soft_reset;
sig_composite_sgcntlr_reset <= not(axi_resetn) or
sig_axi_lite_rst_rsync or
sig_soft_reset;
sig_composite_sg_reset_n <= axi_resetn and
not(sig_axi_lite_rst_rsync) and
not(sig_soft_reset);
sig_dm_soft_reset_n <= not(sig_soft_reset);
end if;
end if;
end process IMP_ASYNC_SOFT_RST_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ASYNC_ALITE_BSIDE_RST
--
-- Process Description:
-- FLOP for registering the reset for the AXi Lite
-- Bus side Interface.
-- Note that soft reset is excluded from the AXI Lite reset
-- generation logic.
--
-------------------------------------------------------------
IMP_ASYNC_ALITE_BSIDE_RST : process (axi_lite_aclk)
begin
if (axi_lite_aclk'event and axi_lite_aclk = '1') then
if (sig_axilite_por2rst = '1') then
sig_lite_bside_hw_reset_reg <= '1';
else
sig_lite_bside_hw_reset_reg <= not(axi_lite_resetn) or
sig_axi_rst_rsync_min_pulse or
sig_axi_rst_rsync;
end if;
end if;
end process IMP_ASYNC_ALITE_BSIDE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ASYNC_ALITE_CSIDE_RST
--
-- Process Description:
-- FLOP for registering the reset for the AXi Lite
-- Core side Interface.
-- Note that soft reset is excluded from the AXI Lite reset
-- generation logic.
--
-- Note that the Core side of the AXI Lite interface is
-- clocked with axi_aclk which is async to axi_lite_aclk in
-- this IfGen case.
--
-------------------------------------------------------------
IMP_ASYNC_ALITE_CSIDE_RST : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
If (sig_axi_por2rst_out = '1') Then
sig_lite_cside_hw_reset_reg <= '1';
else
sig_lite_cside_hw_reset_reg <= not(axi_resetn) or
sig_axi_lite_rst_rsync;
End if;
end if;
end process IMP_ASYNC_ALITE_CSIDE_RST;
end generate GEN_AXI_LITE_ASYNC2AXI;
-------------------------------------------------------------------------------
-- Pulse Generator Logic for Soft Reset
-------------------------------------------------------------------------------
sig_trig_soft_reset <= sig_halt_cmplt;
------------------------------------------------------------
-- Instance: I_SOFT_RST_PULSEGEN
--
-- Description:
-- Generates a active high pulse for the specified number
-- of clock periods
--
------------------------------------------------------------
I_SOFT_RST_PULSEGEN : entity axi_cdma_v4_1.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => C_SOFT_RST_TIME_CLKS
)
port map (
Clk_In => axi_aclk ,
Rst_In => sig_local_hw_reset_reg ,
Sig_in => sig_trig_soft_reset ,
Pulse_Out => sig_soft_reset
);
------------------------------------------------------------
-- Instance: I_SOFT_RST_CLR_PULSE
--
-- Description:
-- Generates a active high pulse for 2 clocks when soft reset
-- is deasserted.
--
------------------------------------------------------------
I_SOFT_RST_CLR_PULSE : entity axi_cdma_v4_1.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => NEGATIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => TWO_CLKS
)
port map (
Clk_In => axi_aclk ,
Rst_In => sig_local_hw_reset_reg ,
Sig_in => sig_soft_reset ,
Pulse_Out => sig_rst2reg_soft_reset_clr
);
-------------------------------------------------------------------------------
-- Halt Request and Complete Logic
-------------------------------------------------------------------------------
------------------------------------------------------------
-- Instance: I_SOFT_RST_POS_EDGE_DTCT
--
-- Description:
-- Generates a active high pulse for 1 clocks when soft reset
-- request from the register module is asserted.
--
------------------------------------------------------------
I_SOFT_RST_POS_EDGE_DTCT : entity axi_cdma_v4_1.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => ONE_CLK
)
port map (
Clk_In => axi_aclk ,
Rst_In => sig_local_hw_reset_reg ,
Sig_in => sig_rst2reg_soft_reset ,
Pulse_Out => sig_rst2reg_soft_reset_trig
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_FLOP
--
-- Process Description:
-- Implements the flop for the Halt Request that is a
-- precurser to a soft reset.
--
-------------------------------------------------------------
IMP_HALT_REQ_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_local_hw_reset_reg = '1' or
sig_soft_reset = '1') then
sig_halt_request <= '0';
elsif (sig_rst2reg_soft_reset_trig = '1') then
sig_halt_request <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_HALT_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_CMPLT_FLOP
--
-- Process Description:
-- Implements the flop for the Halt Completion from all
-- modules.
--
-------------------------------------------------------------
IMP_HALT_CMPLT_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_local_hw_reset_reg = '1' or
sig_soft_reset = '1' or
sig_halt_request = '0') then
sig_halt_cmplt <= '0';
else
sig_halt_cmplt <= cntlr2rst_halt_cmplt and
sg2rst_halt_cmplt and
dm2rst_mm2s_halt_cmplt and
dm2rst_s2mm_halt_cmplt;
end if;
end if;
end process IMP_HALT_CMPLT_FLOP;
end implementation;
| gpl-3.0 | 56165b4d0111c5e5def6fa7505a29042 | 0.434689 | 4.46242 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/syncreg.vhd | 1 | 2,378 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncreg
-- File: syncreg.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Technology wrapper for sync registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity syncreg is
generic (
tech : integer := 0;
stages : integer range 1 to 5 := 2
);
port (
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic
);
end;
architecture tmap of syncreg is
begin
sync0 : if has_syncreg(tech) = 0 generate
--syncreg : block
-- signal c : std_logic_vector(stages-1 downto 0);
--begin
-- x0 : process(clk)
-- begin
-- if rising_edge(clk) then
-- for i in 0 to stages-1 loop
-- c(i) <= d;
-- if i /= 0 then c(i) = c(i-1); end if;
-- end loop;
-- end if;
-- end process;
-- q <= c(stages-1);
--end block syncreg;
syncreg : block
signal c : std_logic_vector(stages downto 0);
begin
c(0) <= d;
syncregs : for i in 1 to stages generate
dff : grdff
generic map(tech => tech)
port map(clk => clk, d => c(i-1), q => c(i));
end generate;
q <= c(stages);
end block syncreg;
end generate;
end;
| gpl-2.0 | da10c2a8ccab99b3b6076b76e48519d2 | 0.555929 | 3.976589 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_p_src_rows_V_channel.vhd | 2 | 4,628 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_rows_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_rows_V_channel_shiftReg;
architecture rtl of FIFO_image_filter_p_src_rows_V_channel_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_rows_V_channel is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_rows_V_channel is
component FIFO_image_filter_p_src_rows_V_channel_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_rows_V_channel_shiftReg : FIFO_image_filter_p_src_rows_V_channel_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | a2cc5ceb9aea1a4b447f499e50ee600e | 0.539326 | 3.490196 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/rtl_game_int.vhd | 1 | 3,226 | --------------------------------------------------------------------------------
--
-- Title : rtl_game_int.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Main block for VGA game
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.all;
entity rtl_game_int is
port(
-- system signals
reset : in std_logic; --! system reset
clk : in std_logic; --! pixel CLK ~25 MHz;
-- ps/2 signals
ps2_clk : in std_logic; --! PS/2 CLOCK
ps2_data : in std_logic; --! PS/2 SERIAL DATA
-- vga output signals
h_vga : out std_logic; --! horizontal
v_vga : out std_logic; --! vertical
rgb : out std_logic_vector(2 downto 0); --! rBG Colour
-- test leds signals
leds : out std_logic_vector(8 downto 1) --! 8 LEDs
);
end rtl_game_int;
architecture rtl_game_int of rtl_game_int is
signal data_keyboard : key_data;
signal data_new : std_logic;
signal disp : std_logic;
signal h_sync : std_logic;
signal v_sync : std_logic;
signal dataX : std_logic_vector(9 downto 0);
signal dataY : std_logic_vector(8 downto 0);
signal led : std_logic_vector(8 downto 1);
constant yend : std_logic_vector(4 downto 0):="11000"; -- Y end area
constant ystart : std_logic_vector(4 downto 0):="10000"; -- Y start area
constant xend : std_logic_vector(6 downto 0):="0011000"; -- X end area
constant xstart : std_logic_vector(6 downto 0):="0010000"; -- X start area
begin
leds(6 downto 1) <= led(6 downto 1);
leds(7) <= ps2_data;
leds(8) <= data_new;
h_vga <= h_sync after 1 ns when rising_edge(clk);
v_vga <= v_sync after 1 ns when rising_edge(clk);
---------------- stage 0: KEYBOARD CTRL ----------------
x_keyboard: ctrl_key_decoder
port map(
-- system signals:
clk => clk,
-- keyboard in:
ps2_clk => ps2_clk,
ps2_data => ps2_data,
-- keyboard out:
keys_out => data_keyboard,
new_key => data_new
);
---------------- stage 1: VGA CTRL ----------------
x_vga_ctrl640x480 : vga_ctrl640x480
port map(
-- system signals:
clk => clk,
reset => reset,
-- Horizontal and Vertical sync:
h_sync => h_sync,
v_sync => v_sync,
-- Display
disp => disp,
-- vga XoY coordinates:
x_out => dataX,
y_out => dataY
);
---------------- stage 2: MAIN BLOCK ----------------
x_rtl_game_int : ctrl_game_block
generic map(
yend => yend,
ystart => ystart,
xend => xend,
xstart => xstart
)
port map(
-- system signals:
clk => clk,
reset => reset,
-- keyboard:
push_keys => data_keyboard,
-- vga XoY coordinates:
display => disp,
x_char => dataX,
y_char => dataY,
-- output vga scheme:
rgb => rgb,
leds => led
);
end rtl_game_int; | mit | 21eb10edc421e941c48628941e7b803c | 0.50465 | 3.049149 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_prod.vhd | 1 | 9,975 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 12
-- C_READ_WIDTH_A : 12
-- C_WRITE_DEPTH_A : 57600
-- C_READ_DEPTH_A : 57600
-- C_ADDRA_WIDTH : 16
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 12
-- C_READ_WIDTH_B : 12
-- C_WRITE_DEPTH_B : 57600
-- C_READ_DEPTH_B : 57600
-- C_ADDRB_WIDTH : 16
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | a2726d4ebcdbba55a4dcd74a583697cb | 0.495439 | 3.775549 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-atlys/config.vhd | 1 | 7,187 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020765#;
constant CFG_ETH_ENL : integer := 16#003456#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (16);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 1;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 16;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#03#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (30000);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 705dce0e33b11874177044dcdaa902cb | 0.650063 | 3.572068 | false | false | false | false |
mistryalok/Zedboard | learning/training/my/adder/hls/adder/solution1/syn/vhdl/adder_AXI_CTRL_s_axi.vhd | 1 | 13,809 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity adder_AXI_CTRL_s_axi is
generic (
C_ADDR_WIDTH : INTEGER := 6;
C_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
a :out STD_LOGIC_VECTOR(31 downto 0);
b :out STD_LOGIC_VECTOR(31 downto 0);
c :in STD_LOGIC_VECTOR(31 downto 0);
c_ap_vld :in STD_LOGIC);
end entity adder_AXI_CTRL_s_axi;
--------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/SC)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- others - reserved
-- 0x10 : Data signal of a
-- bit 31~0 - a[31:0] (Read/Write)
-- 0x14 : reserved
-- 0x18 : Data signal of b
-- bit 31~0 - b[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of c
-- bit 31~0 - c[31:0] (Read)
-- 0x24 : Control signal of c
-- bit 0 - c_ap_vld (Read/COR)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of adder_AXI_CTRL_s_axi is
constant ADDR_BITS : INTEGER := 6;
constant ADDR_AP_CTRL : INTEGER :=16#00#;
constant ADDR_GIE : INTEGER :=16#04#;
constant ADDR_IER : INTEGER :=16#08#;
constant ADDR_ISR : INTEGER :=16#0c#;
constant ADDR_A_DATA_0 : INTEGER :=16#10#;
constant ADDR_A_CTRL : INTEGER :=16#14#;
constant ADDR_B_DATA_0 : INTEGER :=16#18#;
constant ADDR_B_CTRL : INTEGER :=16#1c#;
constant ADDR_C_DATA_0 : INTEGER :=16#20#;
constant ADDR_C_CTRL : INTEGER :=16#24#;
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write FSM states
signal wstate, wnext, rstate, rnext: states;
-- Local signal
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : STD_LOGIC;
signal int_isr : STD_LOGIC;
signal int_a : UNSIGNED(31 downto 0);
signal int_b : UNSIGNED(31 downto 0);
signal int_c : UNSIGNED(31 downto 0);
signal int_c_ap_vld : STD_LOGIC;
begin
-- axi write
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
wstate <= wridle;
else
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- axi read
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
rstate <= rdidle;
else
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (1 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier, others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr, others => '0');
when ADDR_A_DATA_0 =>
rdata_data <= RESIZE(int_a(31 downto 0), 32);
when ADDR_B_DATA_0 =>
rdata_data <= RESIZE(int_b(31 downto 0), 32);
when ADDR_C_DATA_0 =>
rdata_data <= RESIZE(int_c(31 downto 0), 32);
when ADDR_C_CTRL =>
rdata_data <= (0 => int_c_ap_vld, others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- internal registers
interrupt <= int_gie and int_isr;
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
a <= STD_LOGIC_VECTOR(int_a);
b <= STD_LOGIC_VECTOR(int_b);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (ap_done = '1' and int_auto_restart = '1') then
int_ap_start <= '1'; -- auto restart
else
int_ap_start <= '0'; -- self clear
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr <= '0';
elsif (ACLK_EN = '1') then
if (int_ier = '1' and ap_done = '1') then
int_isr <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr <= int_isr xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_A_DATA_0) then
int_a(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_a(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_B_DATA_0) then
int_b(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_b(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_c <= (others => '0');
elsif (ACLK_EN = '1') then
if (c_ap_vld = '1') then
int_c <= UNSIGNED(c); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_c_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (c_ap_vld = '1') then
int_c_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_C_CTRL) then
int_c_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
end architecture behave;
| gpl-3.0 | 9702b0148b03d11679d15f63ee35e5f8 | 0.452676 | 3.787438 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_reset.vhd | 12 | 23,104 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_reset.vhd
--
-- Description:
-- This file implements the DataMover Reset module.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_reset is
generic (
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0
-- 0 = Use Synchronous Command/Statys User Interface
-- 1 = Use Asynchronous Command/Statys User Interface
);
port (
-- Primary Clock and Reset Inputs -----------------
--
primary_aclk : in std_logic; --
primary_aresetn : in std_logic; --
---------------------------------------------------
-- Async operation clock and reset from User ------
-- Used for Command/Status User interface --
-- synchronization when C_STSCMD_IS_ASYNC = 1 --
--
secondary_awclk : in std_logic; --
secondary_aresetn : in std_logic; --
---------------------------------------------------
-- Halt request input control -------------------------------
halt_req : in std_logic; --
-- Active high soft shutdown request (can be a pulse) --
--
-- Halt Complete status flag --
halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------------------
--
flush_stop_request : Out std_logic; --
-- Active high soft stop request to modules --
--
data_cntlr_stopped : in std_logic; --
-- Active high flag indicating the data controller is flushed and stopped --
--
addr_cntlr_stopped : in std_logic; --
-- Active high flag indicating the address controller is flushed and stopped --
--
aux1_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 1 module --
-- Tie high if unused --
--
aux2_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 2 module --
-- Tie high if unused --
------------------------------------------------------------------------------------
-- HW Reset outputs to reset groups -------------------------------------
--
cmd_stat_rst_user : Out std_logic; --
-- The reset to the Command/Status Module User interface side --
--
cmd_stat_rst_int : Out std_logic; --
-- The reset to the Command/Status Module internal interface side --
--
mmap_rst : Out std_logic; --
-- The reset to the Memory Map interface side --
--
stream_rst : Out std_logic --
-- The reset to the Stream interface side --
--------------------------------------------------------------------------
);
end entity axi_sg_reset;
architecture implementation of axi_sg_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals
signal sig_cmd_stat_rst_user_n : std_logic := '0';
signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0';
signal sig_cmd_stat_rst_int_reg_n : std_logic := '0';
signal sig_mmap_rst_reg_n : std_logic := '0';
signal sig_stream_rst_reg_n : std_logic := '0';
signal sig_syncd_sec_rst : std_logic := '0';
-- soft shutdown support
signal sig_internal_reset : std_logic := '0';
signal sig_s_h_halt_reg : std_logic := '0';
signal sig_halt_cmplt : std_logic := '0';
-- additional CDC synchronization signals
signal sig_sec_neg_edge_plus_delay : std_logic := '0';
signal sig_secondary_aresetn_reg : std_logic := '0';
signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0';
signal sig_prim2sec_rst_reg2_n : std_logic := '0';
begin --(architecture implementation)
-- Assign outputs
cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n);
cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
mmap_rst <= not(sig_mmap_rst_reg_n) or
sig_syncd_sec_rst;
stream_rst <= not(sig_stream_rst_reg_n) or
sig_syncd_sec_rst;
-- Internal logic Implmentation
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Synchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_syncd_sec_rst <= '0';
sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from);
end generate GEN_SYNC_CMDSTAT_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Asynchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
signal sig_sec_reset_in_reg_n : std_logic := '0';
-- Secondary reset pulse stretcher
signal sig_secondary_dly1 : std_logic := '0';
signal sig_secondary_dly2 : std_logic := '0';
signal sig_neg_edge_detect : std_logic := '0';
signal sig_sec2prim_reset : std_logic := '0';
signal sig_sec2prim_reset_reg : std_logic := '0';
signal sig_sec2prim_reset_reg2 : std_logic := '0';
signal sig_sec2prim_rst_syncro1 : std_logic := '0';
signal sig_sec2prim_rst_syncro2 : std_logic := '0';
begin
-- Generate the reset in the primary clock domain. Use the longer
-- of the pulse stretched reset or the actual reset.
sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or
sig_sec2prim_rst_syncro2;
-- Check for falling edge of secondary_aresetn input
sig_neg_edge_detect <= '1'
when (sig_sec_reset_in_reg_n = '1' and
secondary_aresetn = '0')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSE_STRETCH_FLOPS
--
-- Process Description:
-- This process implements a 3 clock wide pulse whenever the
-- secondary reset is asserted
--
-------------------------------------------------------------
IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
If (sig_secondary_dly2 = '1') Then
sig_secondary_dly1 <= '0' ;
sig_secondary_dly2 <= '0' ;
Elsif (sig_neg_edge_detect = '1') Then
sig_secondary_dly1 <= '1';
else
sig_secondary_dly2 <= sig_secondary_dly1 ;
End if;
end if;
end process IMP_PUSE_STRETCH_FLOPS;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_NEG_EDGE
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- negative edge detection,
--
-------------------------------------------------------------
SYNC_NEG_EDGE : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or
sig_secondary_dly1 or
sig_secondary_dly2;
end if;
end process SYNC_NEG_EDGE;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO
--
-- Process Description:
-- This process registers the secondary reset input to
-- the primary clock domain.
--
-------------------------------------------------------------
SEC2PRIM_RST_SYNCRO : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_sec2prim_reset_reg <= sig_sec_neg_edge_plus_delay ;
sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg;
end if;
end process SEC2PRIM_RST_SYNCRO;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SEC_RST
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- secondary reset input,
--
-------------------------------------------------------------
REG_SEC_RST : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_secondary_aresetn_reg <= secondary_aresetn;
end if;
end process REG_SEC_RST;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO_2
--
-- Process Description:
-- Second stage (destination) synchronizers for the secondary
-- reset CDC to the primary clock.
--
-------------------------------------------------------------
SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
-- CDC sig_sec2prim_rst_syncro1 <= not(secondary_aresetn);
sig_sec2prim_rst_syncro1 <= not(sig_secondary_aresetn_reg);
sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1;
end if;
end process SEC2PRIM_RST_SYNCRO_2;
-- Generate the Command and Status side reset
sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and
sig_prim2sec_rst_reg2_n;
-- CDC sig_cmd_stat_rst_user_reg_n_cdc_from;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RESET_ASYNC
--
-- Process Description:
-- This process registers the secondary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_RESET_ASYNC : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_reset_in_reg_n <= secondary_aresetn;
end if;
end process REG_RESET_ASYNC;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_PRIM2SEC_RST
--
-- Process Description:
-- Second (destination clock) stage synchronizers for CDC of
-- primary reset input,
--
-------------------------------------------------------------
SYNC_PRIM2SEC_RST : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from;
sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to;
end if;
end process SYNC_PRIM2SEC_RST;
--
end generate GEN_ASYNC_CMDSTAT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_PRIM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_PRIM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn;
end if;
end process REG_CMDSTAT_PRIM_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_INT_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status internal interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_INT_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_int_reg_n <= primary_aresetn;
end if;
end process REG_CMDSTAT_INT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_MMAP_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Memory Map interface reset.
--
-------------------------------------------------------------
REG_MMAP_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_rst_reg_n <= primary_aresetn;
end if;
end process REG_MMAP_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_STREAM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Stream interface reset.
--
-------------------------------------------------------------
REG_STREAM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_stream_rst_reg_n <= primary_aresetn;
end if;
end process REG_STREAM_RESET;
-- Soft Shutdown logic ------------------------------------------------------
sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
flush_stop_request <= sig_s_h_halt_reg;
halt_cmplt <= sig_halt_cmplt;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_HALT_REQ
--
-- Process Description:
-- Implements a sample and hold flop for the halt request
-- input. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
REG_HALT_REQ : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_s_h_halt_reg <= '0';
elsif (halt_req = '1') then
sig_s_h_halt_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process REG_HALT_REQ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_CMPLT
--
-- Process Description:
-- Implements a the flop for the halt complete status
-- output. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
IMP_HALT_CMPLT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_halt_cmplt <= '0';
elsif (data_cntlr_stopped = '1' and
addr_cntlr_stopped = '1' and
aux1_stopped = '1' and
aux2_stopped = '1') then
sig_halt_cmplt <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_HALT_CMPLT;
end implementation;
| gpl-3.0 | e407e21615cf8ed64c1a4d96585feddf | 0.412526 | 5.476179 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys2/testbench.vhd | 1 | 7,981 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008, 2009, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 16; -- ram data width (8/16/32)
sramdepth : integer := 23; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "sram.srec"; -- ram contents
constant sdramfile : string := "sdram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 1);
signal data : std_logic_vector(31 downto 0);
signal mben : std_logic_vector(3 downto 0);
signal pio : std_logic_vector(17 downto 0);
signal ramsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal errorn : std_logic;
signal ps2clk : std_logic;
signal ps2data : std_logic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic;
signal vid_g : std_logic;
signal vid_b : std_logic;
signal switch : std_logic_vector(7 downto 0); -- switches
signal button : std_logic_vector(2 downto 0);
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst; dsuen <= '1'; dsubre <= '0';
rxd1 <= 'H';
ps2clk <= 'H'; ps2data <= 'H';
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
address(1 downto 0) <= "00";
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (rst, clk, errorn, address(19 downto 2), data,
ramsn, mben, oen, writen,
dsubre, dsuact, txd1, rxd1, pio, --switch, button,
ps2clk, ps2data,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b
);
sram0 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => sdramfile)
port map (address(19 downto 2), data(31-i*16 downto 16-i*16),
mben(i*2), mben(i*2+1), ramsn(i), writen, oen);
end generate;
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '0' then wait on errorn; end if;
assert (to_x01(errorn) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait for 2500 ns;
dsurst <= '0';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
| gpl-2.0 | 30c624d9a4d9099081ee5de2814dd9f9 | 0.558326 | 3.059026 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/greth/greth_mb.vhd | 1 | 13,695 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_mb
-- File: greth_mb.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link and dual AHB master interfaces
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth_mb is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, revision, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
signal irq : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
signal lmdio_oe : std_ulogic;
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
signal ehwdata : std_logic_vector(31 downto 0);
signal ehrdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahb,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi2.hgrant(ehindex),
ehready => ahbmi2.hready,
ehresp => ahbmi2.hresp,
ehrdata => ehrdata,
--edcl ahb mst out
ehbusreq => ahbmo2.hbusreq,
ehlock => ahbmo2.hlock,
ehtrans => ahbmo2.htrans,
ehaddr => ahbmo2.haddr,
ehwrite => ahbmo2.hwrite,
ehsize => ahbmo2.hsize,
ehburst => ahbmo2.hburst,
ehprot => ahbmo2.hprot,
ehwdata => ehwdata,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => ethi.rmii_clk,
tx_clk => ethi.tx_clk,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd(3 downto 0),
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd(3 downto 0),
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => lmdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable);
etho.mdio_oe <= ahbmi.testoen when (scanen = 1) and (ahbmi.testen = '1')
else lmdio_oe;
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
ehrdata <= ahbreadword(ahbmi2.hrdata);
ahbmo2.hwdata <= ahbdrivedata(ehwdata);
ahbmo2.hconfig <= ehconfig;
ahbmo2.hindex <= ehindex;
ahbmo2.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
ft1 : if ft /= 0 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
edclramft1 : if (edcl /= 0) and (edclft /= 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100 Mbit Ethernet MAC rev " & tost(REVISION)
& tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz) & " kbyte " & tost(txfifosize) & " txfifo," &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
| gpl-2.0 | 85e823deac79f23b80c188a7b4bfb149 | 0.539832 | 4.081967 | false | false | false | false |
Luisda199824/ProcesadorMonociclo | PSR.vhd | 1 | 655 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( nzvc : in STD_LOGIC_VECTOR (3 downto 0);
rst : in STD_LOGIC;
clk : in STD_LOGIC;
ncwp: in STD_LOGIC;
cond : in STD_LOGIC_VECTOR (3 downto 0);
carry : out STD_LOGIC;
cwp : out STD_LOGIC;
icc : out STD_LOGIC_VECTOR (3 downto 0));
end PSR;
architecture Behavioral of PSR is
begin
process(rst, clk, nzvc, cond, ncwp)
begin
if rst='1' then
carry <= '0';
cwp <= '0';
icc <= "0000";
else
if rising_edge(clk) then
carry<=nzvc(0);
end if;
cwp <= ncwp;
icc <= nzvc;
end if;
end process;
end Behavioral; | mit | 65ec6b2bdf0bbb03b803c51660253e46 | 0.578626 | 2.963801 | false | false | false | false |
borti4938/sd2snes | verilog/sd2snes_sdd1/SDD1_Core.vhd | 2 | 7,319 | ----------------------------------------------------------------------------------
-- Company: Traducciones Magno
-- Engineer: Magno
--
-- Create Date: 22.03.2018 20:46:09
-- Design Name:
-- Module Name: SDD1_Core - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SDD1_Core is
Port( clk : in STD_LOGIC;
-- configuration received from DMA
DMA_Conf_Valid : in STD_LOGIC;
DMA_Transfer_End : in STD_LOGIC;
-- data input from ROM
ROM_Data_tready : out STD_LOGIC;
ROM_Data_tvalid : in STD_LOGIC;
ROM_Data_tdata : in STD_LOGIC_VECTOR(15 downto 0);
ROM_Data_tkeep : in STD_LOGIC_VECTOR(1 downto 0);
-- data output to DMA
DMA_Data_tready : in STD_LOGIC;
DMA_Data_tvalid : out STD_LOGIC;
DMA_Data_tdata : out STD_LOGIC_VECTOR(7 downto 0);
-- DBG
FSM_Avoid_Collision : in STD_LOGIC;
FSM_Start_Decompression : in STD_LOGIC;
FSM_End_Decompression : in STD_LOGIC;
ROM_CE : in STD_LOGIC;
ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
ROM_DATA : in STD_LOGIC_VECTOR(15 downto 0));
end SDD1_Core;
architecture Behavioral of SDD1_Core is
COMPONENT Input_Manager
Port( clk : in STD_LOGIC;
-- control data
DMA_Conf_Valid : in STD_LOGIC;
DMA_In_Progress : in STD_LOGIC;
Header_Valid : out STD_LOGIC;
Header_BPP : out STD_LOGIC_VECTOR(1 downto 0);
Header_Context : out STD_LOGIC_VECTOR(1 downto 0);
-- data input from ROM
ROM_Data_tready : out STD_LOGIC;
ROM_Data_tvalid : in STD_LOGIC;
ROM_Data_tdata : in STD_LOGIC_VECTOR(15 downto 0);
ROM_Data_tkeep : in STD_LOGIC_VECTOR(1 downto 0);
-- Golomb decoded value
Decoded_Bit_tready : in STD_LOGIC;
Decoded_Bit_tuser : in STD_LOGIC_VECTOR(7 downto 0);
Decoded_Bit_tvalid : out STD_LOGIC;
Decoded_Bit_tdata : out STD_LOGIC;
Decoded_Bit_tlast : out STD_LOGIC;
--DEBUG
ROM_CE : in STD_LOGIC;
ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
ROM_DATA : in STD_LOGIC_VECTOR(15 downto 0));
END COMPONENT;
COMPONENT Probability_Estimator
Port( clk : in STD_LOGIC;
-- control data
DMA_In_Progress : in STD_LOGIC;
Header_Valid : in STD_LOGIC;
Header_Context : in STD_LOGIC_VECTOR(1 downto 0);
-- run data from input manager
Decoded_Bit_tready : out STD_LOGIC;
Decoded_Bit_tuser : out STD_LOGIC_VECTOR(7 downto 0);
Decoded_Bit_tvalid : in STD_LOGIC;
Decoded_Bit_tdata : in STD_LOGIC;
Decoded_Bit_tlast : in STD_LOGIC;
-- estimated bit value
BPP_Bit_tready : in STD_LOGIC;
BPP_Bit_tuser : in STD_LOGIC_VECTOR(9 downto 0);
BPP_Bit_tvalid : out STD_LOGIC;
BPP_Bit_tdata : out STD_LOGIC);
END COMPONENT;
COMPONENT Output_Manager
Port( clk : in STD_LOGIC;
-- configuration received from DMA
DMA_In_Progress : out STD_LOGIC;
DMA_Transfer_End : in STD_LOGIC;
Header_Valid : in STD_LOGIC;
Header_BPP : in STD_LOGIC_VECTOR(1 downto 0);
-- data input from Probability Estimator
BPP_Bit_tready : out STD_LOGIC;
BPP_Bit_tuser : out STD_LOGIC_VECTOR(9 downto 0);
BPP_Bit_tvalid : in STD_LOGIC;
BPP_Bit_tdata : in STD_LOGIC;
-- data output to DMA
DMA_Data_tready : in STD_LOGIC;
DMA_Data_tvalid : out STD_LOGIC;
DMA_Data_tdata : out STD_LOGIC_VECTOR(7 downto 0) );
END COMPONENT;
signal DMA_In_Progress : STD_LOGIC := '0';
signal Header_Valid : STD_LOGIC := '0';
signal Header_BPP : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal Header_Context : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal Decoded_Bit_tready : STD_LOGIC := '0';
signal Decoded_Bit_tuser : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal Decoded_Bit_tvalid : STD_LOGIC := '0';
signal Decoded_Bit_tdata : STD_LOGIC := '0';
signal Decoded_Bit_tlast : STD_LOGIC := '0';
signal BPP_Bit_tready : STD_LOGIC := '0';
signal BPP_Bit_tuser : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
signal BPP_Bit_tvalid : STD_LOGIC := '0';
signal BPP_Bit_tdata : STD_LOGIC := '0';
signal DBG_Cnt : STD_LOGIC_VECTOR(17 downto 0) := (others => '0');
begin
-- get data from ROM and decode it into N-order Golomb runs
IM : Input_Manager
Port map(clk => clk,
-- control data
DMA_Conf_Valid => DMA_Conf_Valid,
DMA_In_Progress => DMA_In_Progress,
Header_Valid => Header_Valid,
Header_BPP => Header_BPP,
Header_Context => Header_Context,
-- data input from ROM
ROM_Data_tready => ROM_Data_tready,
ROM_Data_tvalid => ROM_Data_tvalid,
ROM_Data_tdata => ROM_Data_tdata,
ROM_Data_tkeep => ROM_Data_tkeep,
-- Golomb decoded value
Decoded_Bit_tready => Decoded_Bit_tready,
Decoded_Bit_tuser => Decoded_Bit_tuser,
Decoded_Bit_tvalid => Decoded_Bit_tvalid,
Decoded_Bit_tdata => Decoded_Bit_tdata,
Decoded_Bit_tlast => Decoded_Bit_tlast,
ROM_CE => ROM_CE,
ROM_ADDR => ROM_ADDR,
ROM_DATA => ROM_DATA );
-- get Golomb data and context to decode pixel
PE : Probability_Estimator
Port map(clk => clk,
-- control data
DMA_In_Progress => DMA_In_Progress,
Header_Valid => Header_Valid,
Header_Context => Header_Context,
-- run data from input manager
Decoded_Bit_tready => Decoded_Bit_tready,
Decoded_Bit_tuser => Decoded_Bit_tuser,
Decoded_Bit_tvalid => Decoded_Bit_tvalid,
Decoded_Bit_tdata => Decoded_Bit_tdata,
Decoded_Bit_tlast => Decoded_Bit_tlast,
-- estimated bit value
BPP_Bit_tready => BPP_Bit_tready,
BPP_Bit_tuser => BPP_Bit_tuser,
BPP_Bit_tvalid => BPP_Bit_tvalid,
BPP_Bit_tdata => BPP_Bit_tdata );
OM : Output_Manager
Port map(clk => clk,
-- configuration received from DMA
DMA_In_Progress => DMA_In_Progress,
DMA_Transfer_End => DMA_Transfer_End,
Header_Valid => Header_Valid,
Header_BPP => Header_BPP,
-- data input from Probability Estimator
BPP_Bit_tready => BPP_Bit_tready,
BPP_Bit_tuser => BPP_Bit_tuser,
BPP_Bit_tvalid => BPP_Bit_tvalid,
BPP_Bit_tdata => BPP_Bit_tdata,
-- data output to DMA
DMA_Data_tready => DMA_Data_tready,
DMA_Data_tvalid => DMA_Data_tvalid,
DMA_Data_tdata => DMA_Data_tdata );
end Behavioral;
| gpl-2.0 | df25b52f3e018d0f810c18d4a5144e8b | 0.591884 | 2.980049 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-terasic-de0-nano/clkgen_de0.vhd | 1 | 3,543 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity clkgen_de0 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of clkgen_de0 is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
| gpl-2.0 | 840b27b59298883c15e32bc3a8280bd1 | 0.594694 | 3.675311 | false | false | false | false |
Subsets and Splits