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marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/memctrl/srctrl.vhd | 1 | 16,113 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: srctrl
-- File: srctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Marko Isomaki - Gaisler Research
-- Description: 32-bit SRAM memory controller with read-modify-write
-- Supports also 64-bit AHB read/write accesses
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
entity srctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0; -- read-modify-write enable
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of srctrl is
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SRCTRL, 0, VERSION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ramaddr, '1', '1', rammask),
6 => ahb_membar(ioaddr, '0', '0', iomask),
others => zero32);
type srcycletype is (idle, read1, read2, write1, write2, write3, rmw1, rmw2, rmw3);
type prom8cycletype is (idle, read1, read2);
function byteswap (rdata, wdata : std_logic_vector(31 downto 0); addr, size : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(31 downto 0);
variable a : std_logic_vector(1 downto 0);
begin
tmp := rdata; a := addr(1 downto 0);
if size(0) = '0' then
case a is
when "00" => tmp(31 downto 24) := wdata(31 downto 24);
when "01" => tmp(23 downto 16) := wdata(23 downto 16);
when "10" => tmp(15 downto 8) := wdata(15 downto 8);
when others => tmp(7 downto 0) := wdata(7 downto 0);
end case;
else
if addr(1) = '0' then tmp(31 downto 16) := wdata(31 downto 16);
else tmp(15 downto 0) := wdata(15 downto 0); end if;
end if;
return(tmp);
end;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 2);
bdrive : std_ulogic;
nbdrive : std_ulogic;
srstate : srcycletype;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(63 downto 0);
hwdata : std_logic_vector(63 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hresp : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0);
read : std_ulogic;
oen : std_ulogic;
ramsn : std_ulogic;
romsn : std_ulogic;
vramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
vromsn : std_logic_vector(1 downto 0);
writen : std_ulogic;
wen : std_logic_vector(3 downto 0);
mben : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
iosn : std_ulogic;
-- 8-bit prom access
pr8state : prom8cycletype;
data8 : std_logic_vector(23 downto 0);
ready8 : std_ulogic;
bwidth : std_logic_vector(1 downto 0);
end record;
signal r, ri : reg_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
ctrl : process(rst, ahbsi, r, sri, rbdrive)
variable v : reg_type; -- local variables for registers
variable dqm : std_logic_vector(3 downto 0);
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable roms : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hrdata : std_logic_vector(63 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable vramws, vromws, viows : std_logic_vector(3 downto 0);
-- 8-bit prom access
variable romsn : std_ulogic;
variable bdrive : std_ulogic;
variable oen : std_ulogic;
variable writen : std_ulogic;
variable hready : std_ulogic;
variable ws : std_logic_vector(3 downto 0);
variable prom8sel : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable sbdrive : std_ulogic;
begin
-- Variable default settings to avoid latches
v := r; v.hresp := HRESP_OKAY; v.hrdata(31 downto 0) := sri.data;
hrdata := r.hrdata;
vramws := conv_std_logic_vector(ramws, 4); vbdrive := rbdrive;
vromws := conv_std_logic_vector(romws, 4);
viows := conv_std_logic_vector(iows, 4);
v.bwidth := sri.bwidth;
if (prom8en = 1) and (r.bwidth = "00") then prom8sel := '1';
else prom8sel := '0'; end if;
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.htrans := ahbsi.htrans; v.hburst := ahbsi.hburst;
v.hsel := '1'; v.hmbsel := ahbsi.hmbsel(0 to 2);
v.haddr := ahbsi.haddr; v.hready := '0';
else
v.hsel := '0';
end if;
end if;
if (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size;
htrans := r.htrans; hwrite := r.hwrite;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
end if;
-- chip-select decoding
adec := haddr(banksz+14 downto banksz+13);
rams := '0' & decode(adec);
case srbanks is
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others => null;
end case;
roms := haddr(romasel) & not haddr(romasel);
-- generate write strobes
if rmw = 1 then dqm := "0000"; else
case r.size is
when "00" =>
case r.haddr(1 downto 0) is
when "00" => dqm := "1110";
when "01" => dqm := "1101";
when "10" => dqm := "1011";
when others => dqm := "0111";
end case;
when "01" =>
if r.haddr(1) = '0' then dqm := "1100"; else dqm := "0011"; end if;
when others => dqm := "0000";
end case;
end if;
-- main FSM
case r.srstate is
when idle =>
if (v.hsel = '1') and not
(((v.ramsn or r.romsn) = '0') or ((v.romsn or r.ramsn) = '0')) and not
((v.hmbsel(0) and not hwrite and prom8sel) = '1' and prom8en = 1)
then
v.hready := '0';
v.ramsn := not v.hmbsel(1); v.romsn := not v.hmbsel(0);
v.iosn := not v.hmbsel(2);
v.read := not hwrite;
if hwrite = '1' then
if (rmw = 1) and (hsize(1) = '0') and (v.hmbsel(1) = '1') then
v.srstate := rmw1; v.read := '1';
else v.srstate := write1; end if;
elsif ahbsi.htrans = "10" then v.srstate := read1;
else v.srstate := read2; end if;
v.oen := not v.read;
else
v.ramsn := '1'; v.romsn := '1'; v.bdrive := '1'; v.oen := '1';
v.iosn := '1';
end if;
if v.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
when read1 =>
v.srstate := read2;
v.hrdata(63 downto 32) := r.hrdata(31 downto 0);
when read2 =>
v.ws := r.ws -1; v.oen := '0';
if r.ws = "0000" then
if (r.size /= "11") or (r.haddr(2) = '1') or (AHBDW = 32) then
v.srstate := idle; v.hready := '1'; v.haddr := ahbsi.haddr;
v.ramsn := not (ahbsi.hmbsel(1) and ahbsi.htrans(1));
v.romsn := not (ahbsi.hmbsel(0) and ahbsi.htrans(1));
v.oen := not (ahbsi.hsel(hindex) and ahbsi.htrans(1) and not ahbsi.hwrite);
else
v.srstate := read1; v.haddr(2) := '1';
if v.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
end if;
end if;
when write1 =>
if r.romsn = '0' then v.ws := vromws;
elsif v.iosn = '0' then v.ws := viows;
else v.ws := vramws; end if;
v.srstate := write2; v.bdrive := '0'; v.wen := dqm; v.writen := '0';
v.hwdata(31 downto 0) := ahbsi.hwdata(31 downto 0);
if not ((r.size = "11") and (r.haddr(2) = '1')) then
v.hwdata(63 downto 32) := ahbsi.hwdata(63 mod AHBDW downto 32 mod AHBDW);
end if;
when write2 =>
if r.ws = "0000" then
if (r.size /= "11") or (r.haddr(2) = '1') or (AHBDW = 32) then
v.srstate := idle; v.bdrive := '1'; v.hready := '1';
else
v.srstate := write3;
end if;
v.wen := "1111"; v.writen := '1';
end if;
v.ws := r.ws -1;
when write3 =>
v.haddr(2) := '1'; v.hwdata(63 downto 32) := r.hwdata(31 downto 0);
v.srstate := write1;
when rmw1 =>
if (rmw = 1) then v.oen := '0';
v.srstate := rmw2;
v.hwdata(31 downto 0) := ahbsi.hwdata(31 downto 0);
v.hwdata(63 downto 32) := ahbsi.hwdata(63 mod AHBDW downto 32 mod AHBDW);
end if;
when rmw2 =>
if (rmw = 1) then
v.ws := r.ws -1;
if r.ws = "0000" then v.oen := '1'; v.srstate := rmw3; end if;
end if;
when rmw3 =>
if (rmw = 1) then
v.hwdata(63 downto 32) := byteswap(r.hrdata(31 downto 0), r.hwdata(63 downto 32), r.haddr, r.size);
v.srstate := write2; v.bdrive := '0'; v.wen := dqm; v.writen := '0';
end if;
if r.romsn = '0' then v.ws := vromws; else v.ws := vramws; end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- 8-bit PROM access FSM
if prom8en = 1 then
hready := '0'; ws := v.ws; v.ready8 := '0';
bdrive := '1'; oen := '1'; writen := '1'; romsn := '1';
if r.ready8 = '1' then
v.data8 := r.data8(15 downto 0) & r.hrdata(31 downto 24);
case r.size is
when "00" => hrdata(31 downto 0) := r.hrdata(31 downto 24) &
r.hrdata(31 downto 24) & r.hrdata(31 downto 24) & r.hrdata(31 downto 24);
when "01" => hrdata(31 downto 0) := r.data8(7 downto 0) & r.hrdata(31 downto 24) &
r.data8(7 downto 0) & r.hrdata(31 downto 24);
when others => hrdata(31 downto 0) := r.data8 & r.hrdata(31 downto 24);
end case;
end if;
case r.pr8state is
when idle =>
if ( (v.hsel and v.hmbsel(0) and not hwrite and prom8sel) = '1')
then
romsn := '0'; v.pr8state := read1; oen := '0';
end if;
when read1 =>
oen := '0'; romsn := '0'; v.pr8state := read2; ws := vromws;
when read2 =>
oen := '0'; ws := r.ws - 1; romsn := '0';
if r.ws = "0000" then
v.haddr(1 downto 0) := r.haddr(1 downto 0) + 1;
if (r.size = "00") or ((r.size = "01") and (r.haddr(0) = '1'))
or r.haddr(1 downto 0) = "11"
then
hready := '1'; v.pr8state := idle; oen := '1';
else
v.pr8state := read1;
end if;
v.ready8 := '1';
end if;
when others =>
v.pr8state := idle;
end case;
v.romsn := v.romsn and romsn; v.bdrive := v.bdrive and bdrive;
v.oen := v.oen and oen; v.writen := v.writen and writen;
v.hready := v.hready or hready; v.ws := ws;
end if;
if (v.oen or v.ramsn) = '0' then v.ramoen := not rams;
else v.ramoen := (others => '1'); end if;
if v.romsn = '0' then v.vromsn := not roms;
else v.vromsn := (others => '1'); end if;
if v.ramsn = '0' then v.vramsn := not rams;
else v.vramsn := (others => '1'); end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wen; end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then sbdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else sbdrive := r.bdrive; vbdrive := (others => v.bdrive); end if;
if (r.size /= "11") or (AHBDW = 32) then hrdata(63 downto 32) := hrdata(31 downto 0); end if;
-- reset
if rst = '0' then
v.srstate := idle; v.hsel := '0'; v.writen := '1';
v.wen := (others => '1'); v.hready := '1'; v.read := '1';
v.ws := (others => '0');
if prom8en = 1 then v.pr8state := idle; end if;
end if;
ribdrive <= vbdrive;
ri <= v;
sro.address <= r.haddr;
sro.bdrive <= (others => sbdrive);
sro.vbdrive <= rbdrive;
sro.ramsn <= "111" & r.vramsn;
sro.ramoen <= "111" & r.ramoen;
sro.romsn <= "111111" & r.vromsn;
sro.iosn <= r.iosn;
sro.wrn <= r.wen;
sro.oen <= r.oen;
sro.read <= r.read;
sro.data <= r.hwdata(63 downto 32);
sro.writen <= r.writen;
sro.ramn <= r.ramsn;
sro.romn <= r.romsn;
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
end process;
sdo.sdcsn <= "11"; sdo.sdcke <= "11"; sdo.sdwen <= '1'; sdo.rasn <= '1';
sdo.casn <= '1'; sdo.dqm <= (others => '1'); sdo.address <= (others => '0');
sdo.data <= (others => '0'); sdo.conf <= (others => '0'); sdo.odt <= (others => '0');
sdo.cal_pll <= (others => '0'); sdo.cal_inc <= (others => '0');
sdo.cal_en <= (others => '0'); sdo.sdck <= (others => '0');
sdo.ba <= (others => '0'); sdo.cb <= (others => '0');
sdo.vbdrive <= (others => '0'); sdo.qdrive <= '0'; sdo.bdrive <= '0';
sdo.oct <= '0';
sdo.ce <= '0'; sdo.moben <= '0'; sdo.cal_rst <= '0';
sdo.xsdcsn <= (others => '0'); sdo.vcbdrive <= (others => '0');
sdo.cbdqm <= (others => '0'); sdo.cbcal_en <= (others => '0');
sdo.cbcal_inc <= (others => '0'); sdo.read_pend <= (others => '0');
sdo.regwdata <= (others => '0'); sdo.regwrite <= (others => '0');
sro.mben <= r.mben;
sro.sdram_en <= '0';
sro.rs_edac_en <= '0';
sro.ce <= '0';
sro.sddata <= (others => '0');
sro.svbdrive <= (others => '0');
sro.sa <= (others => '0');
sro.cb <= (others => '0');
sro.scb <= (others => '0');
sro.vcdrive <= (others => '0');
sro.svcdrive <= (others => '0');
sro.scb <= (others => '0');
regs : process(clk,rst)
begin
if rising_edge(clk) then r <= ri; rbdrive <= ribdrive; end if;
if rst = '0' then
r.ramsn <= '1';
r.romsn <= '1'; r.oen <= '1';
r.bdrive <= '1'; r.nbdrive <= '0';
r.vramsn <= (others => '1'); r.vromsn <= (others => '1');
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("srctrl" & tost(hindex) &
": 32-bit PROM/SRAM controller rev " & tost(VERSION));
-- pragma translate_on
end;
| gpl-2.0 | 93ec658e79c69b2a9f289199dbd6a761 | 0.558431 | 3.069143 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_skid_buf.vhd | 12 | 16,812 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_dma_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER range 8 to 256 := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- System Ports
ACLK : In std_logic ; --
ARST : In std_logic ; --
--
-- Shutdown control (assert for 1 clk pulse) --
skid_stop : In std_logic ; --
-- Slave Side (Stream Data Input) --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_Data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
S_Last : In std_logic ; --
--
-- Master Side (Stream Data Output --
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_Data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
M_Last : Out std_logic --
);
end entity axi_dma_skid_buf;
architecture implementation of axi_dma_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_s_last_xfered : std_logic := '0';
signal sig_m_last_xfered : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_Last <= sig_last_reg_out;
M_Data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_Data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_Data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
--sig_data_reg_out <= (others => '0'); -- CR585409
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
--sig_data_reg_out <= sig_data_skid_mux_out; -- CR585409
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-- CR585409 - To lower reset fanout and improve FPGA fmax timing
-- resets have been removed from AXI Stream data buses
DATA_OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process DATA_OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_s_last_xfered <= sig_s_ready_dup and
s_valid and
sig_slast_with_stop;
sig_sready_stop <= (sig_s_last_xfered and
sig_stop_request) or
sig_sready_stop_reg;
sig_m_last_xfered <= sig_m_valid_dup and
m_ready and
sig_last_reg_out;
sig_mvalid_stop <= (sig_m_last_xfered and
sig_stop_request) or
sig_mvalid_stop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_s_last_xfered = '1' and
sig_stop_request = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_m_last_xfered = '1' and
sig_stop_request = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
| gpl-3.0 | 76fb41231c97b7c4c9f2114decc53869 | 0.506008 | 4.099488 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/side/simulation/side_synth.vhd | 1 | 6,808 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: side_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY side_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE side_synth_ARCH OF side_synth IS
COMPONENT side_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: side_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | 9a0ecebb0d425179ef500f48426972d1 | 0.579318 | 3.807606 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_rst_module.vhd | 3 | 24,245 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_rst_module.vhd
-- Description: This entity is the top level reset module entity for the
-- AXI VDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_dma_rst_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000
-- Scatter Gather clock frequency in hertz
);
port (
-----------------------------------------------------------------------
-- Clock Sources
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ;
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_s2mm_aclk : in std_logic ; --
--
----------------------------------------------------------------------- --
-- Hard Reset --
----------------------------------------------------------------------- --
axi_resetn : in std_logic ; --
----------------------------------------------------------------------- --
-- Soft Reset --
----------------------------------------------------------------------- --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- MM2S Soft Reset Support --
----------------------------------------------------------------------- --
mm2s_all_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_halt : out std_logic := '0' ; --
mm2s_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- S2MM Soft Reset Support --
----------------------------------------------------------------------- --
s2mm_all_idle : in std_logic ; --
s2mm_stop : in std_logic ; --
s2mm_halt : out std_logic := '0' ; --
s2mm_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- MM2S Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_mm2s_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_mm2s_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
mm2s_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
mm2s_cntrl_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
mm2s_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
mm2s_prmry_resetn : out std_logic := '1' ; --
--
--
----------------------------------------------------------------------- --
-- S2MM Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_s2mm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_s2mm_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
s2mm_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
s2mm_sts_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
s2mm_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
s2mm_prmry_resetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Scatter Gather Distributed Reset Out
----------------------------------------------------------------------- --
-- AXI Scatter Gather Reset Out
m_axi_sg_aresetn : out std_logic := '1' ; --
-- AXI Scatter Gather Datamover Reset Out
dm_m_axi_sg_aresetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Hard Reset Out --
----------------------------------------------------------------------- --
m_axi_sg_hrdresetn : out std_logic := '1' ; --
s_axi_lite_resetn : out std_logic := '1' --
);
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of s_axi_lite_resetn : signal is "TRUE";
Attribute KEEP of m_axi_sg_hrdresetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of s_axi_lite_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of m_axi_sg_hrdresetn : signal is "no";
end axi_dma_rst_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_rst_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
ATTRIBUTE async_reg : STRING;
signal hrd_resetn_i_cdc_tig : std_logic := '1';
signal hrd_resetn_i_d1_cdc_tig : std_logic := '1';
--ATTRIBUTE async_reg OF hrd_resetn_i_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF hrd_resetn_i_d1_cdc_tig : SIGNAL IS "true";
-- Soft reset support
signal mm2s_soft_reset_clr : std_logic := '0';
signal s2mm_soft_reset_clr : std_logic := '0';
signal soft_reset_clr_i : std_logic := '0';
signal mm2s_soft_reset_done : std_logic := '0';
signal s2mm_soft_reset_done : std_logic := '0';
signal mm2s_scndry_resetn_i : std_logic := '0';
signal s2mm_scndry_resetn_i : std_logic := '0';
signal dm_mm2s_scndry_resetn_i : std_logic := '0';
signal dm_s2mm_scndry_resetn_i : std_logic := '0';
signal sg_hard_reset : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Register hard reset in
REG_HRD_RST : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => sg_hard_reset,
scndry_vect_out => open
);
m_axi_sg_hrdresetn <= sg_hard_reset;
--REG_HRD_RST : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- hrd_resetn_i_cdc_tig <= axi_resetn;
-- m_axi_sg_hrdresetn <= hrd_resetn_i_cdc_tig;
-- end if;
-- end process REG_HRD_RST;
-- Regsiter hard reset out for axi lite interface
REG_HRD_RST_OUT : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s_axi_lite_resetn,
scndry_vect_out => open
);
--REG_HRD_RST_OUT : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- hrd_resetn_i_d1_cdc_tig <= hrd_resetn_i_cdc_tig;
-- s_axi_lite_resetn <= hrd_resetn_i_d1_cdc_tig;
-- end if;
-- end process REG_HRD_RST_OUT;
dm_mm2s_scndry_resetn <= dm_mm2s_scndry_resetn_i;
dm_s2mm_scndry_resetn <= dm_s2mm_scndry_resetn_i;
-- mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface (default)
MAP_SG_FOR_BOTH : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 1 generate
begin
-- both must be low before sg reset is asserted.
m_axi_sg_aresetn <= mm2s_scndry_resetn_i or s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i or dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_BOTH;
-- Only s2mm channel included therefore map secondary resets to
-- from s2mm reset module to scatter gather interface
MAP_SG_FOR_S2MM : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 1 generate
begin
m_axi_sg_aresetn <= s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_S2MM;
-- Only mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface
MAP_SG_FOR_MM2S : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= mm2s_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i;
end generate MAP_SG_FOR_MM2S;
-- Invalid configuration for axi dma - simply here for completeness
MAP_NO_SG : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= '1';
dm_m_axi_sg_aresetn <= '1';
end generate MAP_NO_SG;
s2mm_scndry_resetn <= s2mm_scndry_resetn_i;
mm2s_scndry_resetn <= mm2s_scndry_resetn_i;
-- Generate MM2S reset signals
GEN_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
RESET_I : entity axi_dma_v7_1.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_mm2s_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => mm2s_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => mm2s_all_idle ,
stop => mm2s_stop ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
-- Secondary Reset
scndry_resetn => mm2s_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => mm2s_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_mm2s_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_mm2s_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => mm2s_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => mm2s_cntrl_reset_out_n
);
-- Sample an hold mm2s soft reset done to use in
-- combined reset done to DMACR
MM2S_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
mm2s_soft_reset_done <= '0';
elsif(mm2s_soft_reset_clr = '1')then
mm2s_soft_reset_done <= '1';
end if;
end if;
end process MM2S_SOFT_RST_DONE;
end generate GEN_RESET_FOR_MM2S;
-- No MM2S therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_prmry_reset_out_n <= '1';
mm2s_cntrl_reset_out_n <= '1';
dm_mm2s_scndry_resetn_i <= '1';
dm_mm2s_prmry_resetn <= '1';
mm2s_prmry_resetn <= '1';
mm2s_scndry_resetn_i <= '1';
mm2s_halt <= '0';
mm2s_soft_reset_clr <= '0';
mm2s_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_MM2S;
-- Generate S2MM reset signals
GEN_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
RESET_I : entity axi_dma_v7_1.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_s2mm_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => s2mm_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => s2mm_all_idle ,
stop => s2mm_stop ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
-- Secondary Reset
scndry_resetn => s2mm_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => s2mm_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_s2mm_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_s2mm_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => s2mm_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => s2mm_sts_reset_out_n
);
-- Sample an hold s2mm soft reset done to use in
-- combined reset done to DMACR
S2MM_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
s2mm_soft_reset_done <= '0';
elsif(s2mm_soft_reset_clr = '1')then
s2mm_soft_reset_done <= '1';
end if;
end if;
end process S2MM_SOFT_RST_DONE;
end generate GEN_RESET_FOR_S2MM;
-- No SsMM therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_prmry_reset_out_n <= '1';
dm_s2mm_scndry_resetn_i <= '1';
dm_s2mm_prmry_resetn <= '1';
s2mm_prmry_resetn <= '1';
s2mm_scndry_resetn_i <= '1';
s2mm_halt <= '0';
s2mm_soft_reset_clr <= '0';
s2mm_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_S2MM;
-- When both mm2s and s2mm are done then drive soft reset clear and
-- also clear s_h registers above
soft_reset_clr_i <= s2mm_soft_reset_done and mm2s_soft_reset_done;
soft_reset_clr <= soft_reset_clr_i;
end implementation;
| gpl-3.0 | c55b1f573dba62915c85ba753745a634 | 0.421901 | 4.431548 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_1_0/synth/design_1_axi_gpio_1_0.vhd | 1 | 10,010 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY design_1_axi_gpio_1_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_axi_gpio_1_0;
ARCHITECTURE design_1_axi_gpio_1_0_arch OF design_1_axi_gpio_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_gpio_1_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_gpio_1_0_arch : ARCHITECTURE IS "design_1_axi_gpio_1_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_gpio_1_0_arch: ARCHITECTURE IS "design_1_axi_gpio_1_0,axi_gpio,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=1,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 1,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_gpio_1_0_arch;
| gpl-3.0 | 22b80e969f4ebcb39f64d97778a8b342 | 0.686613 | 3.154743 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ddr/ddr2buf.vhd | 1 | 6,717 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2buf
-- File: ddr2buf.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Convenience wrapper for syncram2p with data width conversion
--------------------------------------------------------------------------------
-- 2^rabits x rdbits determines amount of RAM.
--
-- If 2^wabits x wdbits is larger than this, the lowest bits of waddress are
-- used for sub-size writes. writebig ignores these lower bits and writes the
-- full data vector at once.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity ddr2buf is
generic (tech : integer := 0; wabits : integer := 6; wdbits : integer := 8;
rabits : integer := 6; rdbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((rabits-1) downto 0);
dataout : out std_logic_vector((rdbits-1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
writebig : in std_ulogic;
waddress : in std_logic_vector((wabits-1) downto 0);
datain : in std_logic_vector((wdbits-1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end;
architecture rtl of ddr2buf is
function xlog2(x: integer) return integer is
variable q,r: integer;
begin
r := 0; q := 1;
while x > q loop
q := q+q; r := r+1;
end loop;
return r;
end xlog2;
function xmax(a,b: integer) return integer is
begin
if a>b then return a; else return b; end if;
end xmax;
function xmin(a,b: integer) return integer is
begin
if a<b then return a; else return b; end if;
end xmin;
constant membits : integer := (2**rabits) * rdbits;
constant wabitsbig : integer := xlog2(membits/wdbits);
constant wdbitsbig : integer := wdbits;
constant wabitssml : integer := wabits;
constant wdbitssml : integer := membits / (2**wabits);
constant totdwidth: integer := xmax(wdbitsbig,rdbits);
constant partdwidth: integer := wdbitssml;
constant nrams : integer := totdwidth/partdwidth;
constant dbits : integer := wdbitssml;
constant abits : integer := xlog2(membits/(dbits*nrams));
constant rdratio : integer := rdbits/dbits;
constant wdratio : integer := wdbitsbig/dbits;
type dv_type is array (0 to nrams-1) of std_logic_vector(dbits-1 downto 0);
signal do: dv_type;
signal di: dv_type;
signal we: std_logic_vector(0 to nrams-1);
signal prev_raddress: std_logic_vector(rabits-1 downto 0);
begin
regs: process(rclk)
begin
if rising_edge(rclk) then
prev_raddress <= raddress;
end if;
end process;
comb: process(prev_raddress,write,writebig,waddress,datain,do)
type rdvx_type is array (0 to totdwidth/rdbits-1) of std_logic_vector(rdbits-1 downto 0);
variable rdvx: rdvx_type;
variable vdo: std_logic_vector((rdbits-1) downto 0);
variable vdi: dv_type;
variable vwe: std_logic_vector(0 to nrams-1);
variable we1: std_logic_vector(0 to wdbitsbig/wdbitssml-1);
variable we2: std_logic_vector(0 to wdratio-1);
begin
vdi := (others => (others => '0'));
vwe := (others => '0');
-- Generate rdvx from do
for x in 0 to nrams-1 loop
if rdbits > dbits then
rdvx(x/rdratio)(rdbits-1-(x mod rdratio)*dbits downto rdbits-dbits-(x mod rdratio)*dbits) := do(x);
else
for y in 0 to dbits/rdbits-1 loop
rdvx(x*dbits/rdbits + y) := do(x)(dbits-1-y*rdbits downto dbits-rdbits-y*rdbits);
end loop;
end if;
end loop;
-- Generate dataout from rdvx and prev_address
vdo := rdvx(totdwidth/rdbits-1);
if totdwidth > rdbits then
for x in 0 to totdwidth/rdbits-2 loop
if prev_raddress(log2(totdwidth/rdbits)-1 downto 0) =
std_logic_vector(to_unsigned(x,log2(totdwidth/rdbits))) then
vdo := rdvx(x);
end if;
end loop;
end if;
-- Generate vdi from datain
for x in 0 to nrams-1 loop
vdi(x) := datain(wdbits-(x mod wdratio)*dbits-1 downto wdbits-(x mod wdratio)*dbits-dbits);
end loop;
-- Generate we2 from write/writebig
we2 := (others => writebig);
if wdbitsbig > wdbitssml then
for x in 0 to wdbitsbig/wdbitssml-1 loop
if write='1' and waddress(log2(wdbitsbig/wdbitssml)-1 downto 0) =
std_logic_vector(to_unsigned(x,log2(wdbitsbig/wdbitssml))) then
we2(x*wdbitssml/dbits to (x+1)*wdbitssml/dbits-1) := (others => '1');
end if;
end loop;
else
if write='1' then we2:=(others => '1'); end if;
end if;
-- Generate write-enable from we2
vwe := (others => '0');
if totdwidth > wdbitsbig then
for x in 0 to totdwidth/wdbitsbig-1 loop
if waddress(log2(totdwidth/wdbitssml)-1 downto log2(wdbitsbig/wdbitssml))=
std_logic_vector(to_unsigned(x,log2(totdwidth/wdbitsbig))) then
vwe(x*wdratio to (x+1)*wdratio-1) := we2;
end if;
end loop;
else
vwe := we2;
end if;
dataout <= vdo;
di <= vdi;
we <= vwe;
end process;
ramgen: for x in 0 to nrams-1 generate
r: syncram_2p generic map (tech,abits,dbits,sepclk,wrfst,testen)
port map (rclk => rclk,renable => renable,
raddress => raddress((rabits-1) downto (rabits-abits)),
dataout => do(x),wclk => wclk,write => we(x),
waddress => waddress((wabits-1) downto (wabits-abits)),
datain => di(x), testin => testin);
end generate;
end;
| gpl-2.0 | 5131920e6a7a82e61e87cf3cfbfa6c42 | 0.619026 | 3.674508 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/grlib/amba/dma2ahb.vhd | 1 | 25,629 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB (Entity & architecture declarations)
--
-- File name : dma2ahb.vhd
--
-- Purpose : AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : The AMBA AHB interface has been reduced in function to support
-- only what is required. The following features are constrained:
-- Optionally generates HSIZE=BYTE, HWORD and WORD
-- Only generates HPROT="0011"
-- Allways generates HBURST=HBURST_SINGLE, HBURST_INCR
-- Optionally generates HBURST_INCR4, HBURST_INCR8, HBURST_INCR16
--
-- Generates the following on reponses on DMA interface:
-- HRESP=HRESP_OKAY => DMAOut.Ready
-- HRESP=HRESP_ERROR => DMAOut.Fault
-- HRESP=HRESP_RETRY => DMAOut.Retry (normally not used)
-- HRESP=HRESP_SPLIT => DMAOut.Retry (normally not used)
--
-- Assumes pipelined data input (after OKAY asserted).
--
-- Only big-endianness is supported.
--
-- Supports Early Bus Termination with automatic restart.
-- Supports Retry/Split with automatic restart.
--
-- Library : gaisler
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.1 SH 1 Jul 2003 New version
-- 0.2 SH 21 Jul 2003 Combinatorial response introduced
-- 0.3 SH 25 Jan 2004 Support for interrupted bursts introduced
-- (early burst termination)
-- Optimised coding
-- Idle transfer initiated in 1st error phase
-- 1.3 SH 1 Oct 2004 Ported to GRLIB
-- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts
-- Support for record types
-- 1.5 SH 1 Sep 2005 New library gaisler
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.6 SH 1 Nov 2005 DMAOut.Grant asserted only while HREADY high
-- 1.8 SH 10 Nov 2005 Re-ported to GRLIB
-- 1.8.1 SH 12 Dec 2005 Ensured no HTRANS=seq occurs after idle
-- 1.9 SH 1 Jan 2006 Resolve retry/early burst termination
-- 1.9.2 SH 3 Jan 2006 DelDataPhase dealyed with HREADY signal
-- 1.9.3 SH 24 Feb 2006 Added syncrst generic
-- 1.9.4 MI 27 Mar 2007 Driving HSIZE with address
-- 1.9.5 SH 14 Dec 2007 Automatic 1kbyte boundary crossing (merged)
-- 1.9.6 JA 14 Dec 2007 Support for halfword and byte bursts
-- 1.9.7 MI 4 Aug 2008 Support for Lock
-- 1.9.8 SH 16 Apr 2009 Address recovery after SPLIT/RETRY moved
-- 1.9.9 SH 9 Oct 2009 HPROT defult to 0x3
-- 2.0 SH 4 Mar 2011 DMAOut.Grant masked while ReAddrPhase set
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.STDLIB.all;
use GRLIB.DMA2AHB_Package.all;
entity DMA2AHB is
generic(
hindex: in Integer := 0;
vendorid: in Integer := 0;
deviceid: in Integer := 0;
version: in Integer := 0;
syncrst: in Integer := 1;
boundary: in Integer := 1);
port(
-- AMBA AHB system signals
HCLK: in Std_ULogic; -- system clock
HRESETn: in Std_ULogic; -- asynchronous reset
-- Direct Memory Access Interface
DMAIn: in DMA_In_Type;
DMAOut: out DMA_OUt_Type;
-- AMBA AHB Master Interface
AHBIn: in AHB_Mst_In_Type;
AHBOut: out AHB_Mst_Out_Type);
end entity DMA2AHB;
--============================== Architecture ================================--
architecture RTL of DMA2AHB is
--=========================================================================--
-- Configuration GRLIB
-----------------------------------------------------------------------------
constant HConfig: AHB_Config_Type := (
0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
others => (others => '0'));
--=========================================================================--
-----------------------------------------------------------------------------
-- Local signals
-----------------------------------------------------------------------------
signal Address: Std_Logic_Vector(31 downto 0);
signal AddressSave: Std_Logic_Vector(31 downto 0);
signal ActivePhase: Std_ULogic; -- ongoing access
signal AddressPhase: Std_ULogic; -- address phase
signal DataPhase: Std_ULogic; -- data phase
signal ReDataPhase: Std_ULogic; -- restart first
signal ReAddrPhase: Std_ULogic; -- restart second
signal IdlePhase: Std_ULogic; -- idle phase
signal EarlyPhase: Std_ULogic; -- early termination
signal BoundaryPhase: Std_ULogic; -- boundary crossing
signal SingleAcc: Std_ULogic; -- single access
signal WriteAcc: Std_ULogic; -- write access
signal DelDataPhase: Std_ULogic; -- restart first
signal DelAddrPhase: Std_ULogic; -- restart second
signal AHBInHGRANTx: Std_ULogic; -- decoded grant
begin
--=========================================================================--
-- AMBA AHB master interface
-----------------------------------------------------------------------------
AHBOut.HIRQ <= (others => '0');
AHBOut.HCONFIG <= HConfig;
AHBOut.HINDEX <= hindex;
AHBInHGRANTx <= AHBIn.HGRANT(hindex);
--=========================================================================--
-----------------------------------------------------------------------------
-- AMBA AHB Master interface with fast issuing of accesses
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Fixed AMBA AHB signals
-----------------------------------------------------------------------------
AHBOut.HPROT <= "0011";
-----------------------------------------------------------------------------
-- Combinatorial paths
-----------------------------------------------------------------------------
AHBOut.HADDR <= Address; -- internal to external
AHBOut.HWDATA <= ahbdrivedata(DMAIn.Data); -- combinatorial path
DMAOut.OKAY <= '1' when AHBIn.HREADY='1' and
DataPhase ='1' and
AHBIN.HRESP=HRESP_OKAY else
'0';
DMAOut.Retry <= '1' when AHBIn.HREADY='0' and
DataPhase ='1' and
(AHBIN.HRESP=HRESP_RETRY or
AHBIN.HRESP=HRESP_SPLIT) else
'0';
DMAOut.Fault <= '1' when AHBIn.HREADY='0' and
DataPhase ='1' and
AHBIN.HRESP=HRESP_ERROR else
'0';
DMAOut.Grant <= '0' when ReDataPhase='1' or ReAddrPhase='1' else
'1' when AHBIn.HREADY='1' and
AHBInHGRANTx='1' and
DMAIn.Request='1' else
'0';
AHBOut.HBUSREQ <= '0' when IdlePhase='1' else
'1' when DMAIn.Request='1' else
'1' when DMAIn.Burst='1' else
'1' when ReDataPhase='1' else
'1' when ReAddrPhase='1' else
'0';
AHBOut.HLOCK <= '0' when IdlePhase='1' else
'1' when (DMAIn.Lock and
(DMAIn.Request or ReDataPhase)) = '1'else
'0';
-----------------------------------------------------------------------------
-- The AMBA AHB interfacing is done in this process
-----------------------------------------------------------------------------
AHBMaster: process(HCLK, HRESETn)
variable BoundaryCrossing: Std_ULogic;
variable AddressInc: Std_Logic_Vector(3 downto 0);
--------------------------------------------------------------------------
-- This procedure is used to define all reset values for the
-- asynchronous or synchronous reset statements in this process. This
-- is done to avoid source code duplication.
--------------------------------------------------------------------------
procedure Reset is
begin
ActivePhase <= '0';
EarlyPhase <= '0';
AddressPhase <= '0';
DataPhase <= '0';
ReDataPhase <= '0';
ReAddrPhase <= '0';
DelDataPhase <= '0';
DelAddrPhase <= '0';
BoundaryPhase <= '0';
IdlePhase <= '0';
EarlyPhase <= '0';
SingleAcc <= '0';
WriteAcc <= '0';
Address <= (others => '0');
AddressSave <= (others => '0');
DMAOut.Ready <= '0';
DMAOut.Data <= (others => '0');
AHBOut.HSIZE <= HSIZE_BYTE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HWRITE <= '0';
end Reset; ---------------------------------------------------------------
begin
if HRESETn='0' and syncrst=0 then -- asynchronous reset
Reset;
elsif Rising_Edge(HCLK) then
if DMAIn.Reset='1' or -- functional reset
(syncrst/=0 and HRESETn='0') then -- synchronous reset
Reset;
else -- no reset
--------------------------------------------------------------------
-- Temporary variables
--------------------------------------------------------------------
BoundaryCrossing := '0';
AddressInc := (others => '0');
--------------------------------------------------------------------
-- AMBA AHB interface - data phase handling
--------------------------------------------------------------------
-- indicate when no more activies are pending
if AddressPhase='0' and DataPhase='0' and
ReDataPhase='0' and ReAddrPhase='0' and
DMAIn.Burst='0' then
ActivePhase <= '0';
end if;
if AHBIn.HREADY='0' and DataPhase='1' then
-- error check
if AHBIN.HRESP=HRESP_ERROR then
DataPhase <= '0'; -- data phase aborted
end if;
-- split or retry check
if AHBIN.HRESP=HRESP_SPLIT or
AHBIN.HRESP=HRESP_RETRY then
ReDataPhase <= DataPhase; -- restart phases
ReAddrPhase <= AddressPhase or ReAddrPhase;
AddressPhase <= '0'; -- addr phase aborted
DataPhase <= '0'; -- data phase aborted
end if;
end if;
if AHBIn.HREADY='1' and DataPhase='1' then
-- sample AHB input data at end of data phase
DMAOut.Data <= ahbreadword(AHBIn.HRDATA);
DataPhase <= '0'; -- data phase ends
DMAOut.Ready <= '1';
else
-- remove acknowledgement after one cycle
DMAOut.Ready <= '0';
end if;
--------------------------------------------------------------------
-- AMBA AHB interface - address phase handling
--------------------------------------------------------------------
-- initialize data phase on AHB after previous address phase
if AddressPhase='1' and AHBIn.HREADY='1' then
DataPhase <= '1'; -- data phase start
end if;
-- address generation on AHB
if AHBIn.HREADY='1' then
if AddressPhase='1' then
-- burst continuation, sequential transfer
AddressInc(conv_integer(DMAIn.Size)) := '1';
if boundary=1 then -- automatic boundary
Address <= Address + AddressInc;
AddressSave <= Address;
if Address(9 downto 2)="11111111" then
BoundaryCrossing := '1';
BoundaryPhase <= '1';
end if;
else
Address(31 downto 10) <= DMAIn.Address(31 downto 10);
Address( 9 downto 0) <= Address(9 downto 0) + AddressInc;
AddressSave(9 downto 0) <= Address(9 downto 0);
end if;
if DMAIn.Size=HSIZE8 then
AHBOut.HSIZE <= HSIZE_BYTE;
elsif DMAIn.Size=HSIZE16 then
AHBOut.HSIZE <= HSIZE_HWORD;
else
AHBOut.HSIZE <= HSIZE_WORD;
end if;
elsif AHBInHGRANTx='1' and ActivePhase='0' and DMAIn.Request='1' then
-- start of burst, non-sequential transfer
-- start of single, non-sequential transfer
if boundary=1 then -- automatic boundary
Address <= DMAIn.Address;
AddressSave <= DMAIn.Address;
BoundaryCrossing := '0';
BoundaryPhase <= '0';
else
Address <= DMAIn.Address;
AddressSave(9 downto 0) <= DMAIn.Address(9 downto 0);
end if;
if DMAIn.Size=HSIZE8 then
AHBOut.HSIZE <= HSIZE_BYTE;
elsif DMAIn.Size=HSIZE16 then
AHBOut.HSIZE <= HSIZE_HWORD;
else
AHBOut.HSIZE <= HSIZE_WORD;
end if;
end if;
end if;
-- address generation on AHB
if AHBIn.HREADY='1' then
IdlePhase <= '0'; -- one clock cycle only
end if;
-- initialize address phase on AHB
if AHBIn.HREADY='1' then
-- granted the AHB bus
if AHBInHGRANTx='1' then
if ReDataPhase='1' then
ReDataPhase <= '0';
AddressPhase <= '1'; -- address phase start
EarlyPhase <= '0';
AHBOut.HTRANS <= HTRANS_NONSEQ;
if SingleAcc='1' then
AHBOut.HBURST <= HBURST_SINGLE;
else
AHBOut.HBURST <= HBURST_INCR;
end if;
AHBOut.HWRITE <= WriteAcc;
-- go back with address
if boundary=1 then
Address <= AddressSave;
else
Address(9 downto 0) <= AddressSave(9 downto 0);
end if;
elsif ReAddrPhase='1' then
AddressPhase <= '1'; -- address phase start
ReAddrPhase <= '0';
if AddressPhase='1' then
if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then
-- new bursts, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
BoundaryPhase <= '0';
else
-- burst continuation, sequential transfer
AHBOut.HTRANS <= HTRANS_SEQ;
end if;
else
AHBOut.HTRANS <= HTRANS_NONSEQ;
end if;
EarlyPhase <= '0';
if SingleAcc='1' then
AHBOut.HBURST <= HBURST_SINGLE;
else
AHBOut.HBURST <= HBURST_INCR;
end if;
AHBOut.HWRITE <= WriteAcc;
elsif EarlyPhase='1' then
-- early terminated burst resumed
AddressPhase <= '1'; -- address phase start
EarlyPhase <= '0';
AHBOut.HTRANS <= HTRANS_NONSEQ;
AHBOut.HBURST <= HBURST_INCR;
AHBOut.HWRITE <= WriteAcc;
elsif DMAIn.Request='1' and DMAIn.Burst='1' then
AddressPhase <= '1'; -- address phase start
if ActivePhase='1' then
-- burst continuation, sequential transfer
if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then
-- new bursts, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
BoundaryPhase <= '0';
else
-- burst continuation, sequential transfer
AHBOut.HTRANS <= HTRANS_SEQ;
end if;
else
-- start of burst, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
if DMAIn.Beat ="00" then
AHBOut.HBURST <= HBURST_INCR;
elsif DMAIn.Beat ="01" then
AHBOut.HBURST <= HBURST_INCR4;
elsif DMAIn.Beat ="10" then
AHBOut.HBURST <= HBURST_INCR8;
else
AHBOut.HBURST <= HBURST_INCR16;
end if;
AHBOut.HWRITE <= DMAIn.Store;
ActivePhase <= '1';
SingleAcc <= '0';
WriteAcc <= DMAIn.Store;
end if;
elsif DMAIn.Request='0' and DMAIn.Burst='1' and ActivePhase='1' then
-- burst in wait state
AddressPhase <= '0'; -- no address phase
AHBOut.HTRANS <= HTRANS_BUSY;
elsif DMAIn.Request='1' and DMAIn.Burst='0' then
-- start of single, non-sequential transfer
AddressPhase <= '1'; -- address phase start
ActivePhase <= '1';
SingleAcc <= '1';
WriteAcc <= DMAIn.Store;
AHBOut.HTRANS <= HTRANS_NONSEQ;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= DMAIn.Store;
else
-- drive idle transfer as default master
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
-- not granted the AHB bus, but early burst termination
elsif (DMAIn.Request='1' or DMAIn.Burst='1') and ActivePhase='1'then
-- must restart a burst transfer since grant removed
AddressPhase <= '0'; -- no address phase
EarlyPhase <= '1';
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
-- not granted the AHB bus
else
-- drive idle transfer as default master
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
elsif AHBIn.HREADY='0' and DataPhase='1' then
if AHBIN.HRESP=HRESP_ERROR or
AHBIN.HRESP=HRESP_SPLIT or
AHBIN.HRESP=HRESP_RETRY then
-- drive idle transfer due to error, retry or split
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
IdlePhase <= '1';
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
end if;
end if;
if AHBIn.HREADY='1' then -- delay one phase
DelDataPhase <= ReDataPhase;
DelAddrPhase <= ReAddrPhase;
end if;
-- temporary variables cleared
BoundaryCrossing := '0';
AddressInc := (others => '0');
else
null;
end if;
end process AHBMaster;
end architecture RTL; --======================================================--
| gpl-2.0 | 2abd8cad4ae222a4b4992e06d3f503bc | 0.405907 | 5.677669 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/iopad_ddr.vhd | 1 | 4,909 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad_ddr, iopad_ddrv, iopad_ddrvv
-- File: iopad_ddr.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Wrapper that instantiates an iopad connected to DDR register.
-- Special case for easic90 tech since this tech requires that
-- oe is directly connected between DDR register and pad.
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.all;
entity iopad_ddr is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
oepol : integer := 0);
port (
pad : inout std_ulogic;
i1, i2 : in std_ulogic; -- Input H and L
en : in std_ulogic; -- Output enable
o1, o2 : out std_ulogic; -- Output H and L
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddr is
signal oe, oen, d, q : std_ulogic;
begin
def: if (tech /= easic90) generate
p : iopad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad, q, en, d);
ddrregi : ddr_ireg generic map (tech)
port map (o1, o2, c1, c2, ce, d, r, s);
ddrrego : ddr_oreg generic map (tech)
port map (q, c1, c2, ce, i1, i2, r, s);
oe <= '0'; oen <= '0'; -- Not used in this configuration
end generate def;
nex : if (tech = easic90) generate
oen <= not en when oepol /= padoen_polarity(tech) else en;
p : nextreme_iopad generic map (level, slew, voltage, strength)
port map (pad, q, oe, d);
ddrregi : nextreme_iddr_reg
port map (ck => c1, d => d, qh => o1, ql => o2, rstb => r);
ddrrego : nextreme_oddr_reg
port map (ck => c1, dh => i1, dl => i2, doe => oen, q => q,
oe => oe, rstb => r);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_ddrv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddrv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ddr generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i1(j), i2(j), en, o1(j), o2(j), c1, c2, ce, r, s);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_ddrvv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic);
end;
architecture rtl of iopad_ddrvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ddr generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i1(j), i2(j), en(j), o1(j), o2(j), c1, c2, ce, r, s);
end generate;
end;
| gpl-2.0 | 9c551f3e3fd28135668d5f2dd578426c | 0.580159 | 3.380854 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/police/simulation/police_tb.vhd | 1 | 4,343 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: police_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY police_tb IS
END ENTITY;
ARCHITECTURE police_tb_ARCH OF police_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
police_synth_inst:ENTITY work.police_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | 56605094d99ae9bf862b148c542edc95 | 0.619388 | 4.639957 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/unisim/sysmon_unisim.vhd | 1 | 6,571 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity:
-- File: sysmon_unisim.vhd
-- Author: Jan Andersson - Gaisler Research
-- Description: Xilinx System Monitor
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.SYSMON;
-- pragma translate_on
-------------------------------------------------------------------------------
-- Virtex 5 System Monitor
-------------------------------------------------------------------------------
entity sysmon_virtex5 is
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end sysmon_virtex5;
architecture struct of sysmon_virtex5 is
component SYSMON
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt"
);
port (
ALM : out std_logic_vector(2 downto 0);
BUSY : out std_ulogic;
CHANNEL : out std_logic_vector(4 downto 0);
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic;
EOC : out std_ulogic;
EOS : out std_ulogic;
JTAGBUSY : out std_ulogic;
JTAGLOCKED : out std_ulogic;
JTAGMODIFIED : out std_ulogic;
OT : out std_ulogic;
CONVST : in std_ulogic;
CONVSTCLK : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
RESET : in std_ulogic;
VAUXN : in std_logic_vector(15 downto 0);
VAUXP : in std_logic_vector(15 downto 0);
VN : in std_ulogic;
VP : in std_ulogic
);
end component;
begin -- struct
sysmon0 : SYSMON
generic map (INIT_40 => INIT_40, INIT_41 => INIT_41, INIT_42 => INIT_42,
INIT_43 => INIT_43, INIT_44 => INIT_44, INIT_45 => INIT_45,
INIT_46 => INIT_46, INIT_47 => INIT_47, INIT_48 => INIT_48,
INIT_49 => INIT_49, INIT_4A => INIT_4A, INIT_4B => INIT_4B,
INIT_4C => INIT_4C, INIT_4D => INIT_4D, INIT_4E => INIT_4E,
INIT_4F => INIT_4F, INIT_50 => INIT_50, INIT_51 => INIT_51,
INIT_52 => INIT_52, INIT_53 => INIT_53, INIT_54 => INIT_54,
INIT_55 => INIT_55, INIT_56 => INIT_56, INIT_57 => INIT_57,
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end struct;
| gpl-2.0 | e50a4a80a746d0fc7ec3af4a7198fa4a | 0.533404 | 3.573138 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-c5ekit/testbench.vhd | 1 | 19,705 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- Clock and reset
diff_clkin_top_125_p: in std_ulogic;
diff_clkin_bot_125_p: in std_ulogic;
clkin_50_fpga_right: in std_ulogic;
clkin_50_fpga_top: in std_ulogic;
clkout_sma: out std_ulogic;
cpu_resetn: in std_ulogic;
-- DDR3
ddr3_ck_p: out std_ulogic;
ddr3_ck_n: out std_ulogic;
ddr3_cke: out std_ulogic;
ddr3_rstn: out std_ulogic;
ddr3_csn: out std_ulogic;
ddr3_rasn: out std_ulogic;
ddr3_casn: out std_ulogic;
ddr3_wen: out std_ulogic;
ddr3_ba: out std_logic_vector(2 downto 0);
ddr3_a : out std_logic_vector(13 downto 0);
ddr3_dqs_p: inout std_logic_vector(3 downto 0);
ddr3_dqs_n: inout std_logic_vector(3 downto 0);
ddr3_dq: inout std_logic_vector(31 downto 0);
ddr3_dm: out std_logic_vector(3 downto 0);
ddr3_odt: out std_ulogic;
ddr3_oct_rzq: in std_ulogic;
-- LPDDR2
lpddr2_ck_p: out std_ulogic;
lpddr2_ck_n: out std_ulogic;
lpddr2_cke: out std_ulogic;
lpddr2_a: out std_logic_vector(9 downto 0);
lpddr2_dqs_p: inout std_logic_vector(1 downto 0);
lpddr2_dqs_n: inout std_logic_vector(1 downto 0);
lpddr2_dq: inout std_logic_vector(15 downto 0);
lpddr2_dm: out std_logic_vector(1 downto 0);
lpddr2_csn: out std_ulogic;
lpddr2_oct_rzq: in std_ulogic;
-- Flash and SSRAM interface
fm_a: out std_logic_vector(26 downto 1);
fm_d: in std_logic_vector(15 downto 0);
flash_clk: out std_ulogic;
flash_resetn: out std_ulogic;
flash_cen: out std_ulogic;
flash_advn: out std_ulogic;
flash_wen: out std_ulogic;
flash_oen: out std_ulogic;
flash_rdybsyn: in std_ulogic;
ssram_clk: out std_ulogic;
ssram_oen: out std_ulogic;
sram_cen: out std_ulogic;
ssram_bwen: out std_ulogic;
ssram_bwan: out std_ulogic;
ssram_bwbn: out std_ulogic;
ssram_adscn: out std_ulogic;
ssram_adspn: out std_ulogic;
ssram_zzn: out std_ulogic; -- Name incorrect, this is active high
ssram_advn: out std_ulogic;
-- EEPROM
eeprom_scl : out std_ulogic;
eeprom_sda : inout std_ulogic;
-- UART
uart_rxd : in std_ulogic;
uart_rts : in std_ulogic; -- Note CTS and RTS mixed up on PCB
uart_txd : out std_ulogic;
uart_cts : out std_ulogic;
-- USB UART Interface
usb_uart_rstn : in std_ulogic; -- inout
usb_uart_ri : in std_ulogic;
usb_uart_dcd : in std_ulogic;
usb_uart_dtr : out std_ulogic;
usb_uart_dsr : in std_ulogic;
usb_uart_txd : out std_ulogic;
usb_uart_rxd : in std_ulogic;
usb_uart_rts : in std_ulogic;
usb_uart_cts : out std_ulogic;
usb_uart_gpio2 : in std_ulogic;
usb_uart_suspend : in std_ulogic;
usb_uart_suspendn : in std_ulogic;
-- Ethernet port A
eneta_rx_clk: in std_ulogic;
eneta_tx_clk: in std_ulogic;
eneta_intn: in std_ulogic;
eneta_resetn: out std_ulogic;
eneta_mdio: inout std_ulogic;
eneta_mdc: out std_ulogic;
eneta_rx_er: in std_ulogic;
eneta_tx_er: out std_ulogic;
eneta_rx_col: in std_ulogic;
eneta_rx_crs: in std_ulogic;
eneta_tx_d: out std_logic_vector(3 downto 0);
eneta_rx_d: in std_logic_vector(3 downto 0);
eneta_gtx_clk: out std_ulogic;
eneta_tx_en: out std_ulogic;
eneta_rx_dv: in std_ulogic;
-- Ethernet port B
enetb_rx_clk: in std_ulogic;
enetb_tx_clk: in std_ulogic;
enetb_intn: in std_ulogic;
enetb_resetn: out std_ulogic;
enetb_mdio: inout std_ulogic;
enetb_mdc: out std_ulogic;
enetb_rx_er: in std_ulogic;
enetb_tx_er: out std_ulogic;
enetb_rx_col: in std_ulogic;
enetb_rx_crs: in std_ulogic;
enetb_tx_d: out std_logic_vector(3 downto 0);
enetb_rx_d: in std_logic_vector(3 downto 0);
enetb_gtx_clk: out std_ulogic;
enetb_tx_en: out std_ulogic;
enetb_rx_dv: in std_ulogic;
-- LEDs, switches, GPIO
user_led : out std_logic_vector(3 downto 0);
user_dipsw : in std_logic_vector(3 downto 0);
dip_3p3V : in std_ulogic;
user_pb : in std_logic_vector(3 downto 0);
overtemp_fpga : out std_ulogic;
header_p : in std_logic_vector(5 downto 0); -- inout
header_n : in std_logic_vector(5 downto 0); -- inout
header_d : in std_logic_vector(7 downto 0); -- inout
-- LCD
lcd_data : in std_logic_vector(7 downto 0); -- inout
lcd_wen : out std_ulogic;
lcd_csn : out std_ulogic;
lcd_d_cn : out std_ulogic;
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- hsmc_clk_in0: in std_ulogic;
-- hsmc_clk_out0: out std_ulogic;
-- hsmc_clk_in_p: in std_logic_vector(2 downto 1);
-- hsmc_clk_out_p: out std_logic_vector(2 downto 1);
-- hsmc_d: in std_logic_vector(3 downto 0); -- inout
-- hsmc_tx_d_p: out std_logic_vector(16 downto 0);
-- hsmc_rx_d_p: in std_logic_vector(16 downto 0);
-- hsmc_rx_led: out std_ulogic;
-- hsmc_tx_led: out std_ulogic;
-- hsmc_scl: out std_ulogic;
-- hsmc_sda: in std_ulogic; -- inout
-- hsmc_prsntn: in std_ulogic;
-- MAX V CPLD interface
max5_csn: out std_ulogic;
max5_wen: out std_ulogic;
max5_oen: out std_ulogic;
max5_ben: out std_logic_vector(3 downto 0);
max5_clk: out std_ulogic;
-- USB Blaster II
usb_clk : in std_ulogic;
usb_data : in std_logic_vector(7 downto 0); -- inout
usb_addr : in std_logic_vector(1 downto 0); -- inout
usb_scl : in std_ulogic; -- inout
usb_sda : in std_ulogic; -- inout
usb_resetn : in std_ulogic;
usb_oen : in std_ulogic;
usb_rdn : in std_ulogic;
usb_wrn : in std_ulogic;
usb_full : out std_ulogic;
usb_empty : out std_ulogic;
fx2_resetn : in std_ulogic
);
end component;
signal clk125, clk50, clkout: std_ulogic := '0';
signal rst: std_ulogic;
signal user_led: std_logic_vector(3 downto 0);
signal address : std_logic_vector(26 downto 1);
signal data : std_logic_vector(15 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
constant lresp : boolean := false;
signal eneta_rx_clk, eneta_tx_clk, enetb_rx_clk, enetb_tx_clk: std_ulogic;
signal eneta_intn, eneta_resetn, enetb_intn, enetb_resetn: std_ulogic;
signal eneta_mdio, enetb_mdio: std_logic;
signal eneta_mdc, enetb_mdc: std_ulogic;
signal eneta_rx_er, eneta_rx_col, eneta_rx_crs, eneta_rx_dv: std_ulogic;
signal enetb_rx_er, enetb_rx_col, enetb_rx_crs, enetb_rx_dv: std_ulogic;
signal eneta_rx_d, enetb_rx_d: std_logic_vector(7 downto 0);
signal eneta_tx_d, enetb_tx_d: std_logic_vector(7 downto 0);
signal eneta_tx_en, eneta_tx_er, enetb_tx_en, enetb_tx_er: std_ulogic;
signal lpddr2_ck, lpddr2_ck_n, lpddr2_cke, lpddr2_cs_n: std_ulogic;
signal lpddr2_ca: std_logic_vector(9 downto 0);
signal lpddr2_dm, lpddr2_dqs, lpddr2_dqs_n: std_logic_vector(3 downto 0);
signal lpddr2_dq: std_logic_vector(31 downto 0);
begin
-- clock and reset
clk125 <= not clk125 after 4 ns;
clk50 <= not clk50 after 10 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
d3 : leon3mp
generic map ( fabtech, memtech, padtech, disas, dbguart, pclow )
port map (
-- Clock and reset
diff_clkin_top_125_p => clk125,
diff_clkin_bot_125_p => clk125,
clkin_50_fpga_right => clk50,
clkin_50_fpga_top => clk50,
clkout_sma => clkout,
cpu_resetn => rst,
-- DDR3
ddr3_ck_p => open,
ddr3_ck_n => open,
ddr3_cke => open,
ddr3_rstn => open,
ddr3_csn => open,
ddr3_rasn => open,
ddr3_casn => open,
ddr3_wen => open,
ddr3_ba => open,
ddr3_a => open,
ddr3_dqs_p => open,
ddr3_dqs_n => open,
ddr3_dq => open,
ddr3_dm => open,
ddr3_odt => open,
ddr3_oct_rzq => '0',
-- LPDDR2
lpddr2_ck_p => lpddr2_ck,
lpddr2_ck_n => lpddr2_ck_n,
lpddr2_cke => lpddr2_cke,
lpddr2_a => lpddr2_ca,
lpddr2_dqs_p => lpddr2_dqs(1 downto 0),
lpddr2_dqs_n => lpddr2_dqs_n(1 downto 0),
lpddr2_dq => lpddr2_dq(15 downto 0),
lpddr2_dm => lpddr2_dm(1 downto 0),
lpddr2_csn => lpddr2_cs_n,
lpddr2_oct_rzq => '0',
-- Flash and SSRAM interface
fm_a => address(26 downto 1),
fm_d => data,
flash_clk => open,
flash_resetn => open,
flash_cen => romsn,
flash_advn => open,
flash_wen => rwen,
flash_oen => oen,
flash_rdybsyn => '1',
ssram_clk => open,
ssram_oen => open,
sram_cen => open,
ssram_bwen => open,
ssram_bwan => open,
ssram_bwbn => open,
ssram_adscn => open,
ssram_adspn => open,
ssram_zzn => open,
ssram_advn => open,
-- EEPROM
eeprom_scl => open,
eeprom_sda => open,
-- UART
uart_rxd => rxd1,
uart_rts => '1',
uart_txd => txd1,
uart_cts => open,
-- USB UART Interface
usb_uart_rstn => '1',
usb_uart_ri => '0',
usb_uart_dcd => '1',
usb_uart_dtr => open,
usb_uart_dsr => '1',
usb_uart_txd => open,
usb_uart_rxd => '1',
usb_uart_rts => '1',
usb_uart_cts => open,
usb_uart_gpio2 => '0',
usb_uart_suspend => '0',
usb_uart_suspendn => '1',
-- Ethernet port A
eneta_rx_clk => eneta_rx_clk,
eneta_tx_clk => eneta_tx_clk,
eneta_intn => eneta_intn,
eneta_resetn => eneta_resetn,
eneta_mdio => eneta_mdio,
eneta_mdc => eneta_mdc,
eneta_rx_er => eneta_rx_er,
eneta_tx_er => eneta_tx_er,
eneta_rx_col => eneta_rx_col,
eneta_rx_crs => eneta_rx_crs,
eneta_tx_d => eneta_tx_d(3 downto 0),
eneta_rx_d => eneta_rx_d(3 downto 0),
eneta_gtx_clk => open,
eneta_tx_en => eneta_tx_en,
eneta_rx_dv => eneta_rx_dv,
-- Ethernet port B
enetb_rx_clk => enetb_rx_clk,
enetb_tx_clk => enetb_tx_clk,
enetb_intn => enetb_intn,
enetb_resetn => enetb_resetn,
enetb_mdio => enetb_mdio,
enetb_mdc => enetb_mdc,
enetb_rx_er => enetb_rx_er,
enetb_tx_er => enetb_tx_er,
enetb_rx_col => enetb_rx_col,
enetb_rx_crs => enetb_rx_crs,
enetb_tx_d => enetb_tx_d(3 downto 0),
enetb_rx_d => enetb_rx_d(3 downto 0),
enetb_gtx_clk => open,
enetb_tx_en => enetb_tx_en,
enetb_rx_dv => enetb_rx_dv,
-- LEDs, switches, GPIO
user_led => user_led,
user_dipsw => "1111",
dip_3p3V => '0',
user_pb => "0000",
overtemp_fpga => open,
header_p => "000000",
header_n => "000000",
header_d => "00000000",
-- LCD
lcd_data => "00000000",
lcd_wen => open,
lcd_csn => open,
lcd_d_cn => open,
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- hsmc_clk_in0 => '0',
-- hsmc_clk_out0 => open,
-- hsmc_clk_in_p => "00",
-- hsmc_clk_out_p => open,
-- hsmc_d => "0000",
-- hsmc_tx_d_p => open,
-- hsmc_rx_d_p => (others => '0'),
-- hsmc_rx_led => open,
-- hsmc_tx_led => open,
-- hsmc_scl => open,
-- hsmc_sda => '0',
-- hsmc_prsntn => '0',
-- MAX V CPLD interface
max5_csn => open,
max5_wen => open,
max5_oen => open,
max5_ben => open,
max5_clk => open,
-- USB Blaster II
usb_clk => '0',
usb_data => (others => '0'),
usb_addr => "00",
usb_scl => '0',
usb_sda => '0',
usb_resetn => '0',
usb_oen => '0',
usb_rdn => '0',
usb_wrn => '0',
usb_full => open,
usb_empty => open,
fx2_resetn => '1'
);
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data,
romsn, romsn, romsn, rwen, oen);
-- ROMSN is pulled down by the MAX V system controller after FPGA programming
-- completed (bug?)
romsn <= 'L';
data <= buskeep(data), (others => 'H') after 250 ns;
error <= user_led(3);
eneta_mdio <= 'H';
enetb_mdio <= 'H';
eneta_tx_d(7 downto 4) <= "0000";
enetb_tx_d(7 downto 4) <= "0000";
p1: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 0)
port map(rst, eneta_mdio, eneta_tx_clk, eneta_rx_clk, eneta_rx_d, eneta_rx_dv,
eneta_rx_er, eneta_rx_col, eneta_rx_crs, eneta_tx_d, eneta_tx_en, eneta_tx_er, eneta_mdc,
'0');
p2: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(rst, enetb_mdio, enetb_tx_clk, enetb_rx_clk, enetb_rx_d, enetb_rx_dv,
enetb_rx_er, enetb_rx_col, enetb_rx_crs, enetb_tx_d, enetb_tx_en, enetb_tx_er, enetb_mdc,
'0');
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod generic map (width => 16)
port map ( rst, clk50, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | c5f242da648393cb3fff28df73aaa722 | 0.572291 | 3.014841 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/ptf/pt_pkg.vhd | 1 | 29,021 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Package: pt_pkg
-- File: pt_pkg.vhd
-- Author: Nils-Johan Wessman, Aeroflex Gaisler
-- Description: PCI Test Framework - Main package
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
--use grlib.amba.all;
--use grlib.testlib.all;
use grlib.stdlib.all;
package pt_pkg is
-----------------------------------------------------------------------------
-- Constants and PCI signal
-----------------------------------------------------------------------------
-- Constants for PCI commands
constant INT_ACK : std_logic_vector(3 downto 0) := "0000";
constant SPEC_CYCLE : std_logic_vector(3 downto 0) := "0001";
constant IO_READ : std_logic_vector(3 downto 0) := "0010";
constant IO_WRITE : std_logic_vector(3 downto 0) := "0011";
constant MEM_READ : std_logic_vector(3 downto 0) := "0110";
constant MEM_WRITE : std_logic_vector(3 downto 0) := "0111";
constant CONF_READ : std_logic_vector(3 downto 0) := "1010";
constant CONF_WRITE : std_logic_vector(3 downto 0) := "1011";
constant MEM_R_MULT : std_logic_vector(3 downto 0) := "1100";
constant DAC : std_logic_vector(3 downto 0) := "1101";
constant MEM_R_LINE : std_logic_vector(3 downto 0) := "1110";
constant MEM_W_INV : std_logic_vector(3 downto 0) := "1111";
type bar_type is array(0 to 5) of std_logic_vector(31 downto 0);
constant bar_init : bar_type := ((others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'));
type config_header_type is record
devid : std_logic_vector(15 downto 0);
vendid : std_logic_vector(15 downto 0);
status : std_logic_vector(15 downto 0);
command : std_logic_vector(15 downto 0);
class_code : std_logic_vector(23 downto 0);
revid : std_logic_vector(7 downto 0);
bist : std_logic_vector(7 downto 0);
header_type : std_logic_vector(7 downto 0);
lat_timer : std_logic_vector(7 downto 0);
cache_lsize : std_logic_vector(7 downto 0);
bar : bar_type;
cis_p : std_logic_vector(31 downto 0);
subid : std_logic_vector(15 downto 0);
subvendid : std_logic_vector(15 downto 0);
exp_rom_ba : std_logic_vector(31 downto 0);
max_lat : std_logic_vector(7 downto 0);
min_gnt : std_logic_vector(7 downto 0);
int_pin : std_logic_vector(7 downto 0);
int_line : std_logic_vector(7 downto 0);
end record;
constant config_init : config_header_type := (
devid => conv_std_logic_vector(16#0BAD#,16),
vendid => conv_std_logic_vector(16#AFFE#,16),
status => (others => '0'),
command => (others => '0'),
class_code => conv_std_logic_vector(16#050000#,24),
revid => conv_std_logic_vector(16#01#,8),
bist => (others => '0'),
header_type => (others => '0'),
lat_timer => (others => '0'),
cache_lsize => (others => '0'),
bar => bar_init,
cis_p => (others => '0'),
subid => (others => '0'),
subvendid => (others => '0'),
exp_rom_ba => (others => '0'),
max_lat => (others => '0'),
min_gnt => (others => '0'),
int_pin => (others => '0'),
int_line => (others => '0'));
-- These types defines the TB PCI bus
type pci_ad_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
par : std_logic;
end record;
constant ad_const : pci_ad_type := (
ad => (others => 'Z'),
cbe => (others => 'Z'),
par => 'Z');
type pci_ifc_type is record
frame : std_logic;
irdy : std_logic;
trdy : std_logic;
stop : std_logic;
devsel : std_logic;
idsel : std_logic_vector(20 downto 0);
lock : std_logic;
end record;
constant ifc_const : pci_ifc_type := (
frame => 'H',
irdy => 'H',
trdy => 'H',
stop => 'H',
lock => 'H',
idsel => (others => 'L'),
devsel => 'H');
type pci_err_type is record
perr : std_logic;
serr : std_logic;
end record;
constant err_const : pci_err_type := (
perr => 'H',
serr => 'H');
type pci_arb_type is record
req : std_logic_vector(20 downto 0);
gnt : std_logic_vector(20 downto 0);
end record;
constant arb_const : pci_arb_type := (
req => (others => 'H'),
gnt => (others => 'H'));
type pci_syst_type is record
clk : std_logic;
rst : std_logic;
end record;
constant syst_const : pci_syst_type := (
clk => 'H',
rst => 'H');
type pci_ext64_type is record
ad : std_logic_vector(63 downto 32);
cbe : std_logic_vector(7 downto 4);
par64 : std_logic;
req64 : std_logic;
ack64 : std_logic;
end record;
constant ext64_const : pci_ext64_type := (
ad => (others => 'Z'),
cbe => (others => 'Z'),
par64 => 'Z',
req64 => 'Z',
ack64 => 'Z');
--type pci_int_type is record
-- inta : std_logic;
-- intb : std_logic;
-- intc : std_logic;
-- intd : std_logic;
--end record;
--constant int_const : pci_int_type := (
-- inta => 'H',
-- intb => 'H',
-- intc => 'H',
-- intd => 'H');
constant int_const : std_logic_vector(3 downto 0) := "HHHH";
type pci_cache_type is record
sbo : std_logic;
sdone : std_logic;
end record;
constant cache_const : pci_cache_type := (
sbo => 'U',
sdone => 'U');
type pci_type is record
ad : pci_ad_type;
ifc : pci_ifc_type;
err : pci_err_type;
arb : pci_arb_type;
syst : pci_syst_type;
ext64 : pci_ext64_type;
--int : pci_int_type;
int : std_logic_vector(3 downto 0);
cache : pci_cache_type;
end record;
constant pci_idle : pci_type := ( ad_const, ifc_const, err_const, arb_const,
syst_const, ext64_const, int_const, cache_const);
-----------------------------------------------------------------------------
-- Types for PCI master
-----------------------------------------------------------------------------
type pt_pci_access_type is record
addr : std_logic_vector(31 downto 0);
cbe_cmd : std_logic_vector(3 downto 0);
data : std_logic_vector(31 downto 0);
cbe_data : std_logic_vector(3 downto 0);
ws : integer;
status : integer range 0 to 3;
id : integer;
debug : integer range 0 to 3;
last : boolean;
idle : boolean;
list_res : boolean;
valid : boolean;
parerr : integer range 0 to 2;
cod : integer range 0 to 2; -- Cancel on disconnect
end record;
type pt_pci_master_in_type is record
req : std_logic;
add : boolean;
remove : boolean;
rmall : boolean;
get_res : boolean;
add_res : boolean;
acc : pt_pci_access_type;
end record;
type pt_pci_master_out_type is record
ack : std_logic;
res_found : std_logic;
acc : pt_pci_access_type;
valid : boolean;
end record;
-----------------------------------------------------------------------------
-- PCI master procedures
-----------------------------------------------------------------------------
procedure pt_pci_master_sync_with_core(
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
procedure pt_add_idle_nb(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false);
procedure pt_add_idle(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type);
-----------------------------------------------------------------------------
-- Types for PCI target
-----------------------------------------------------------------------------
type pt_pci_response_type is record
addr : std_logic_vector(31 downto 0);
retry : integer;
ws : integer;
diswithout : integer;
diswith : integer;
abort : integer;
parerr : integer;
debug : integer;
valid : boolean;
end record;
type pt_pci_target_in_type is record
req : std_logic;
insert: std_logic;
remove: std_logic;
rmall : std_logic;
addr : std_logic_vector(31 downto 0);
resp : pt_pci_response_type;
end record;
type pt_pci_target_out_type is record
ack : std_logic;
resp : pt_pci_response_type;
valid : std_logic;
end record;
-----------------------------------------------------------------------------
-- PCI target procedures
-----------------------------------------------------------------------------
procedure pt_pci_target_sync_with_core(
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type);
procedure pt_insert_resp(
constant addr : std_logic_vector(31 downto 0);
constant retry : integer;
constant waits : integer;
constant discon: integer;
constant parerr: integer;
constant abort : integer;
constant debug : integer;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type);
procedure pt_remove_resp(
constant addr : std_logic_vector(31 downto 0);
constant rmall : boolean;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component pt_pci_master -- A PCI master that is accessed through a Testbench vector
generic (
slot : integer := 0; -- Slot number for this unit
tval : time := 7 ns); -- Output delay for signals that are driven by this unit
port (
pciin : in pci_type;
pciout : out pci_type;
dbgi : in pt_pci_master_in_type;
dbgo : out pt_pci_master_out_type
);
end component;
component pt_pci_target -- Represents a simple memory on the PCI bus
generic (
slot : integer := 0; -- Slot number for this unit
abits : integer := 10; -- Memory size. Size is 2^abits 32-bit words
bars : integer := 1; -- Number of bars for this target. Min 1, Max 6
resptime : integer := 2; -- The initial response time in clks for this target
latency : integer := 0; -- The latency in clks for every dataphase for a burst access
rbuf : integer := 8; -- The maximum no of words this target can transfer in a continuous burst
stopwd : boolean := true; -- Target disconnect type. true = disconnect WITH data, false = disconnect WITHOUT data
tval : time := 7 ns; -- Output delay for signals that are driven by this unit
conf : config_header_type := config_init; -- The reset condition of the configuration space of this target
dbglevel : integer := 1); -- Debug level. Higher value means more debug information
port (
pciin : in pci_type;
pciout : out pci_type;
dbgi : in pt_pci_target_in_type;
dbgo : out pt_pci_target_out_type
);
end component;
component pt_pci_arb
generic (
slots : integer := 5; -- The number of slots in the test system
tval : time := 7 ns); -- Output delay for signals that are driven by this unit
port (
systclk : in pci_syst_type;
ifcin : in pci_ifc_type;
arbin : in pci_arb_type;
arbout : out pci_arb_type);
end component;
--component pt_pci_monitor is
-- generic (dbglevel : integer := 1); -- Debug level. Higher value means more debug information
-- port (pciin : in pci_type);
--end component;
end package pt_pkg;
package body pt_pkg is
-----------------------------------------------------------------------------
-- PCI master procedures
-----------------------------------------------------------------------------
procedure pt_pci_master_sync_with_core(
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
dbgi.req <= '1';
wait until dbgo.ack = '1';
dbgi.req <= '0';
wait until dbgo.ack = '0';
end procedure pt_pci_master_sync_with_core;
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= addr;
dbgi.acc.cbe_cmd <= cbe_cmd;
dbgi.acc.data <= data;
dbgi.acc.cbe_data <= cbe_data;
dbgi.acc.ws <= waits;
dbgi.acc.last <= last;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= addr;
dbgi.acc.cbe_cmd <= cbe_cmd;
dbgi.acc.data <= data;
dbgi.acc.cbe_data <= cbe_data;
dbgi.acc.ws <= waits;
dbgi.acc.last <= last;
dbgi.acc.parerr <= parerr;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_acc_nb(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= addr;
dbgi.acc.cbe_cmd <= cbe_cmd;
dbgi.acc.data <= data;
dbgi.acc.cbe_data <= cbe_data;
dbgi.acc.ws <= waits;
dbgi.acc.last <= last;
dbgi.acc.parerr <= parerr;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= cod;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
pt_add_acc_nb(addr, cbe_cmd , data, cbe_data, waits, last, parerr, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant parerr : integer;
constant cod : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
pt_add_acc_nb(addr, cbe_cmd , data, cbe_data, waits, last, parerr, cod, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
procedure pt_add_acc(
constant addr : std_logic_vector(31 downto 0);
constant cbe_cmd : std_logic_vector(3 downto 0);
constant data : std_logic_vector(31 downto 0);
constant cbe_data : std_logic_vector(3 downto 0);
constant waits : integer;
constant last : boolean;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
pt_add_acc_nb(addr, cbe_cmd , data, cbe_data, waits, last, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
procedure pt_add_idle_nb(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type;
constant list_res : boolean := false) is
begin
dbgi.add <= true;
dbgi.remove <= false;
dbgi.get_res <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= waits;
dbgi.acc.idle <= true;
dbgi.acc.list_res <= list_res;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.acc.valid <= false;
end procedure;
procedure pt_add_idle(
constant waits : integer;
constant id : integer;
constant debug : integer;
signal dbgi : out pt_pci_master_in_type;
signal dbgo : in pt_pci_master_out_type) is
begin
-- Add acc
pt_add_idle_nb(waits, id, debug, dbgi, dbgo, true);
while true loop
dbgi.get_res <= true;
dbgi.add <= false;
dbgi.remove <= false;
dbgi.add_res <= false;
dbgi.acc.id <= id;
dbgi.acc.addr <= (others => '0');
dbgi.acc.cbe_cmd <= (others => '0');
dbgi.acc.data <= (others => '0');
dbgi.acc.cbe_data <= (others => '0');
dbgi.acc.ws <= 0;
dbgi.acc.idle <= false;
dbgi.acc.list_res <= false;
dbgi.acc.valid <= true;
dbgi.acc.debug <= debug;
dbgi.acc.cod <= 0;
pt_pci_master_sync_with_core(dbgi, dbgo);
dbgi.add <= false;
dbgi.get_res <= false;
dbgi.acc.valid <= false;
if dbgo.valid = false then
while dbgo.res_found /= '1' loop
wait until dbgo.res_found = '1';
end loop;
else
exit;
end if;
end loop;
end procedure;
-----------------------------------------------------------------------------
-- PCI target procedures
-----------------------------------------------------------------------------
procedure pt_pci_target_sync_with_core(
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type) is
begin
dbgi.req <= '1';
wait until dbgo.ack = '1';
dbgi.req <= '0';
wait until dbgo.ack = '0';
end procedure pt_pci_target_sync_with_core;
procedure pt_insert_resp(
constant addr : std_logic_vector(31 downto 0);
constant retry : integer;
constant waits : integer;
constant discon: integer;
constant parerr: integer;
constant abort : integer;
constant debug : integer;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type) is
begin
dbgi.insert <= '1';
dbgi.remove <= '0';
dbgi.resp.addr <= addr;
dbgi.resp.retry <= retry;
dbgi.resp.ws <= waits;
dbgi.resp.parerr <= parerr;
dbgi.resp.abort <= abort;
dbgi.resp.debug <= debug;
if discon = 1 then
dbgi.resp.diswith <= 1;
elsif discon = 2 then
dbgi.resp.diswithout <= 1;
else
dbgi.resp.diswith <= 0;
dbgi.resp.diswithout <= 0;
end if;
pt_pci_target_sync_with_core(dbgi, dbgo);
dbgi.insert <= '0';
end procedure;
procedure pt_remove_resp(
constant addr : std_logic_vector(31 downto 0);
constant rmall : boolean;
signal dbgi : out pt_pci_target_in_type;
signal dbgo : in pt_pci_target_out_type) is
begin
dbgi.insert <= '0';
dbgi.remove <= '1';
if rmall = true then dbgi.rmall <= '1';
else dbgi.rmall <= '0'; end if;
dbgi.addr <= addr;
pt_pci_target_sync_with_core(dbgi, dbgo);
dbgi.remove <= '0';
dbgi.rmall <= '0';
end procedure;
end pt_pkg;
| gpl-2.0 | f694cac9e5e571ba9e81212d8e4c949b | 0.54688 | 3.556059 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/pwm_test/ctrl_jazz.vhd | 1 | 1,160 | --------------------------------------------------------------------------------
--
-- Title : rtl_game_int.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Debounce module: remove glitches
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ctrl_jazz is
port(
clk : in std_logic; --! clock
button : in std_logic; --! button in
reset : in std_logic; --! reset
clrbutton : out std_logic --! button out
);
end ctrl_jazz;
architecture ctrl_jazz of ctrl_jazz is
signal gcnt : std_logic_vector(23 downto 0);
signal glbut : std_logic;
begin
CLRBUTTON <= glbut;
glbut <= gcnt(23) when rising_edge(clk);
pr_glitches: process(clk, reset) is
begin
if reset = '0' then
gcnt <= (others => '0');
elsif rising_edge(clk) then
if button = '0' then
gcnt <= gcnt + '1';
else
gcnt <= (others => '0');
end if;
end if;
end process;
end ctrl_jazz; | mit | d5fbffd6127b50b4942f6925841f8bdb | 0.485345 | 3.314286 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/uart/dcom_uart.vhd | 1 | 11,543 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcom_uart
-- File: dcom_uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Asynchronous UART with baud-rate detection.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity dcom_uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end;
architecture rtl of dcom_uart is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBUART, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, stopbit);
type txfsmtype is (idle, data, stopbit);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
dready : std_ulogic; -- data ready
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
thempty : std_ulogic; -- transmitter hold register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
frame : std_ulogic; -- framing error
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(10 downto 0);
thold : std_logic_vector(7 downto 0);
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx data filtering buffer
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(17 downto 0);
brate : std_logic_vector(17 downto 0);
tcnt : std_logic_vector(1 downto 0); -- autobaud counter
rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer
fedge : std_ulogic; -- rx falling edge
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : uartregs := (
rxen => '0', dready => '0', rsempty => '1', tsempty => '1', thempty => '1',
break => '0', ovf => '0', frame => '0', rhold => (others => '0'),
rshift => (others => '0'), tshift => (others => '1'), thold => (others => '0'),
txstate => idle, txclk => (others => '0'), txtick => '0', rxstate => idle,
rxclk => (others => '0'), rxdb => (others => '0'), rxtick => '0', tick => '0',
scaler => "111111111111111011", brate => (others => '1'), tcnt => (others => '0'),
rxf => (others => '0'), fedge => '0');
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti, ui )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(17 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable irxd : std_ulogic;
variable v : uartregs;
begin
v := r;
v.txtick := '0'; v.rxtick := '0'; v.tick := '0'; rdata := (others => '0');
v.rxdb(1) := r.rxdb(0);
-- scaler
if r.tcnt = "11" then scaler := r.scaler - 1;
else scaler := r.scaler + 1; end if;
if r.tcnt /= "11" then
if (r.rxdb(1) and not r.rxdb(0)) = '1' then v.fedge := '1'; end if;
if (r.fedge) = '1' then
v.scaler := scaler;
if (v.scaler(17) and not r.scaler(16)) = '1' then
v.scaler := "111111111111111011";
v.fedge := '0'; v.tcnt := "00";
end if;
end if;
if (r.rxdb(1) and r.fedge and not r.rxdb(0)) = '1' then
if (r.brate(17 downto 4)> r.scaler(17 downto 4)) then
v.brate := r.scaler; v.tcnt := "00";
end if;
v.scaler := "111111111111111011";
if (r.brate(17 downto 4) = r.scaler(17 downto 4)) then
v.tcnt := r.tcnt + 1;
if r.tcnt = "10" then
v.brate := "0000" & r.scaler(17 downto 4);
v.scaler := v.brate; v.rxen := '1';
end if;
end if;
end if;
else
if (r.break and r.rxdb(1)) = '1' then
v.scaler := "111111111111111011";
v.brate := (others => '1'); v.tcnt := "00";
v.break := '0'; v.rxen := '0';
end if;
end if;
if r.rxen = '1' then
v.scaler := scaler;
v.tick := scaler(15) and not r.scaler(15);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- read/write registers
if uarti.read = '1' then v.dready := '0'; end if;
case apbi.paddr(3 downto 2) is
when "01" =>
rdata(9 downto 0) := r.tcnt & r.rxdb(0) & r.frame & '0' & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
when "10" =>
rdata(1 downto 0) := (r.tcnt(1) or r.tcnt(0)) & r.rxen;
when others =>
rdata(17 downto 0) := r.brate;
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.tcnt := apbi.pwdata(1) & apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(17 downto 0);
v.scaler := apbi.pwdata(17 downto 0);
when others =>
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk; v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk; v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
v.rxf(1 downto 0) := r.rxf(0) & ui.rxd; -- meta-stability filter
if ((r.tcnt /= "11") and (r.scaler(0 downto 0) = "1")) or
((r.tcnt = "11") and (r.tick = '1'))
then v.rxf(4 downto 2) := r.rxf(3 downto 1); end if;
v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or
(r.rxf(3) and r.rxf(2));
irxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if (r.rxen and (not r.thempty) and r.txtick) = '1' then
v.tshift := "10" & r.thold & '0'; v.txstate := data;
v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmitt data frame
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1);
if r.tshift(10 downto 1) = "1111111110" then
v.tshift(0) := '1'; v.txstate := stopbit;
end if;
end if;
when stopbit => -- transmitt stop bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if uarti.write = '1' then
v.thold := uarti.data(7 downto 0); v.thempty := '0';
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb(1) and (not irxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if irxd = '0' then
v.rshift := irxd & r.rshift(7 downto 1); v.rxstate := data;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.rshift := irxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
v.rxstate := stopbit;
end if;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if irxd = '1' then
v.rsempty := '0';
if v.dready = '0' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
else
if r.rshift = "00000000" then
v.break := '1'; -- break
else
v.frame := '1'; -- framing error
end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
-- reset operation
if not RESET_ALL and rst = '0' then
v.frame := RES.frame; v.rsempty := RES.rsempty;
v.ovf := RES.ovf; v.break := RES.break; v.thempty := RES.thempty;
v.tsempty := RES.tsempty; v.dready := RES.dready; v.fedge := RES.fedge;
v.txstate := RES.txstate; v.rxstate := RES.rxstate; v.tshift(0) := RES.tshift(0);
v.scaler := RES.scaler; v.brate := RES.brate;
v.rxen := RES.rxen; v.tcnt := RES.tcnt;
v.txclk := RES.txclk; v.rxclk := RES.rxclk;
end if;
-- update registers
rin <= v;
-- drive outputs
uo.txd <= r.tshift(0);
uo.scaler(31 downto 18) <= (others => '0');
uo.scaler(17 downto 0) <= r.brate;
uo.rtsn <= '0';
uo.rxen <= andv(r.tcnt);
uarto.dready <= r.dready;
uarto.tsempty <= r.tsempty;
uarto.thempty <= r.thempty;
uarto.lock <= r.tcnt(1) and r.tcnt(0);
uarto.enable <= r.rxen;
uarto.data <= r.rhold;
uo.txen <= '1'; uo.flow <= '0';
apbo.prdata <= rdata;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers not reset
r.rxf <= rin.rxf;
end if;
end if;
end process;
end;
| gpl-2.0 | 837affca44b18cfe14ed24b2a964cbfa | 0.538681 | 3.296117 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml605/svga2ch7301c.vhd | 1 | 7,595 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk100 : in std_ulogic;
clk125 : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
clkvga : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, vgaclk, clk40, clk65, clk50, clk25 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
signal clkval40 : std_logic_vector(1 downto 0);
signal clkval65 : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
clkvga <= vgaclk;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk)
begin -- process
if rising_edge(vgaclk) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25 when clksel = "00" else clk40 when clksel = "01"
else clk50 when clksel = "10" else clk65;
-- Generate clocks
clkdiv : process(clk100, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk100) then
clkval <= clkval + 1;
end if;
end process;
clkdiv65 : process(clk125, rstn)
begin
if rstn = '0' then clkval65 <= "00"; clkval40 <= "00";
elsif rising_edge(clk125) then
clkval65 <= clkval65 + 1;
if clkval40 = "10" then clkval40 <= "00";
else clkval40 <= clkval40 + 1; end if;
end if;
end process;
clk25 <= clkval(1);
clk50 <= clkval(0);
clk40 <= clkval40(1);
clk65 <= clkval65(0);
end rtl;
| gpl-2.0 | 1cd0ed389058060f917cb1d64bbd8daa | 0.560105 | 3.630497 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml40x/testbench.vhd | 1 | 9,927 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
signal sysace_clk_in : std_ulogic := '0';
constant ct : integer := clkperiod/2;
signal plb_error : std_logic;
signal opb_error : std_logic;
signal flash_a23 : std_ulogic;
signal sram_flash_addr : std_logic_vector(22 downto 0);
signal sram_flash_data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_flash_oe_n : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_ce : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal sram_zz : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(26 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_int_n : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal tft_lcd_clk : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal usb_csn : std_logic;
signal flash_cex : std_logic;
signal iic_scl : std_logic;
signal iic_sda : std_logic;
signal sace_usb_a : std_logic_vector(6 downto 0);
signal sace_mpce : std_ulogic;
signal sace_usb_d : std_logic_vector(15 downto 0);
signal sace_usb_oen : std_ulogic;
signal sace_usb_wen : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxsp : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txdp : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txsp : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal datazz : std_logic_vector(0 to 3);
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
sysace_clk_in <= not sysace_clk_in after 15 ns;
rxd1 <= 'H';
sram_clk_fb <= sram_clk; ddr_clk_fb <= ddr_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl <= 'H'; iic_sda <= 'H';
flash_cex <= not flash_ce;
sace_usb_d <= (others => 'H'); sysace_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, sysace_clk_in, plb_error, opb_error, flash_a23,
sram_flash_addr, sram_flash_data, sram_cen, sram_bw, sram_flash_oe_n,
sram_flash_we_n, flash_ce, sram_clk, sram_clk_fb, sram_mode, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_int_n,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, ps2_keyb_clk,
ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, tft_lcd_clk, vid_blankn, vid_syncn,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b,
usb_csn,
iic_scl, iic_sda,
sace_usb_a, sace_mpce, sace_usb_d, sace_usb_oen, sace_usb_wen,
sysace_mpirq
);
datazz <= "HHHH";
u0 : cy7c1354 generic map (fname => sramfile)
port map(
Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data,
Addr => sram_flash_addr(17 downto 0), Mode => sram_mode,
Clk => sram_clk, CEN_n => gnd, AdvLd_n => sram_adv_ld_n,
Bwa_n => sram_bw(3), Bwb_n => sram_bw(2),
Bwc_n => sram_bw(1), Bwd_n => sram_bw(0),
Rw_n => sram_flash_we_n, Oe_n => sram_flash_oe_n,
Ce1_n => sram_cen,
Ce2 => vcc,
Ce3_n => gnd,
Zz => sram_zz);
sram_zz <= '0';
u1 : mt46v16m16
generic map (index => 1, fname => sdramfile, bbits => 32)
PORT MAP(
Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
Dm => ddr_dm(1 downto 0));
u2 : mt46v16m16
generic map (index => 0, fname => sdramfile, bbits => 32)
PORT MAP(
Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
Dm => ddr_dm(3 downto 2));
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(31-i*8 downto 24-i*8),
flash_cex, sram_bw(i), sram_flash_oe_n);
end generate;
phy_mii_data <= 'H';
p0: phy
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv,
phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl, iic_sda);
plb_error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(plb_error) = '1' then wait on plb_error; end if;
assert (to_x01(plb_error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, plb_error, sram_flash_addr(19 downto 0), sram_flash_data,
iosn, sram_flash_oe_n, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
| gpl-2.0 | cfc2345ba30aac9dab91c40de90d4963 | 0.61912 | 2.99457 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/memctrl/sdmctrl.vhd | 1 | 25,493 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdmctrl
-- File: sdmctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: SDRAM memory controller to fit with LEON2 memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
entity sdmctrl is
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end;
architecture rtl of sdmctrl is
constant WPROTEN : boolean := (wprot /= 0);
constant SDINVCLK : boolean := (invclk /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle, sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
burst : std_ulogic;
busy : std_ulogic;
bdelay : std_ulogic;
wprothit : std_ulogic;
startsd : std_ulogic;
aload : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
bsel : std_ulogic;
haddr : std_logic_vector(31 downto 10);
-- only needed to keep address lines from switch too much
address : std_logic_vector(16 downto 2); -- memory address
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
end record;
signal r, ri : reg_type;
begin
ctrl : process(rst, apbi, sdi, wpo, r)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable haddr : std_logic_vector(31 downto 0);
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable busy : std_ulogic;
variable aload : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable hresp : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable lline : std_logic_vector(2 downto 0);
variable rline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable arefresh : std_logic;
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.busy := '0'; hresp := HRESP_OKAY;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
rline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
arefresh := '0';
if sdi.hready = '1' then v.hsel := sdi.hsel; end if;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '1' then v.hready := '0'; end if;
end if;
if fast = 1 then haddr := sdi.rhaddr; else haddr := sdi.haddr; end if;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
-- main state
case sdi.hsize is
when "00" =>
case sdi.rhaddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if sdi.rhaddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then
dqm := dqm(3 downto 0) & "1111";
end if;
-- main FSM
case r.mstate is
when midle =>
if (v.hsel and sdi.nhtrans(1)) = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle) and (sdi.idle = '1')
then
if fast = 1 then v.startsd := '1'; else startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) --and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := r.startsd or startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, sdi.rhaddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
if (sdi.srdis = '0') and (r.cfg.bsize = "111") then adec := not adec; end if;
rams := adec & not adec;
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
-- sdram access FSM
case r.sdstate is
when sidle =>
v.bdelay := '0';
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; v.haddr := sdi.rhaddr(31 downto 10);
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
end if;
if WPROTEN then
v.wprothit := wpo.wprothit;
if wpo.wprothit = '1' then hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if sdi.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '1';
if sdi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '0'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (sdi.rhtrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := sdi.htrans(0) and sdi.htrans(1) and r.hready;
if ((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '0'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.sdwen = '1') and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if r.trfc = "0000" then v.sdstate := sidle; end if;
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else
if r.trfc = "0000" then v.sdstate := sidle; end if;
end if;
when wr5 =>
if r.trfc = "0000" then v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if sdi.htrans /= "11" then
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if sdi.htrans /= "11" then -- v.rasn := '0'; v.sdwen := '0';
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (sdi.htrans = "11") and (r.casn = '1') then
if sdi.rhaddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (sdi.htrans /= "11") or (r.sdcsn = "11") or
((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (sdi.rhaddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1') -- and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1') -- and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1') then -- and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
end if;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" =>
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
end if;
when "111" => -- Load Ext-Mode Reg
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
end if;
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (sdi.idle and sdi.enable) = '1' and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if sdi.enable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- APB register access
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
if pageburst = 2 then v.cfg.pageburst := apbi.pwdata(17); end if;
if sdi.enable = '1' then
v.cfg.command(2 downto 1) := apbi.pwdata(20 downto 19);
end if;
v.cfg.csize := apbi.pwdata(22 downto 21);
v.cfg.bsize := apbi.pwdata(25 downto 23);
v.cfg.casdel := apbi.pwdata(26);
v.cfg.trfc := apbi.pwdata(29 downto 27);
v.cfg.trp := apbi.pwdata(30);
v.cfg.renable := apbi.pwdata(31);
when "10" =>
v.cfg.refresh := apbi.pwdata(26 downto 12);
v.refresh := (others => '0');
when "11" =>
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := apbi.pwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := apbi.pwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
if sdi.enable = '1' then
v.cfg.command(0) := apbi.pwdata(29);
end if;
v.cfg.txsr := apbi.pwdata(23 downto 20);
v.cfg.pmode := apbi.pwdata(18 downto 16);
v.cfg.ds(3 downto 2) := apbi.pwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := apbi.pwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := apbi.pwdata( 2 downto 0);
end if;
when others =>
end case;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
case apbi.paddr(3 downto 2) is
when "01" =>
regsd(31 downto 19) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command(2 downto 1);
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
when "11" =>
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(30) := r.cfg.command(0);
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
when others =>
regsd(26 downto 12) := r.cfg.refresh;
end case;
sdmo.prdata <= regsd;
-- synchronise with sram/prom controller
if fast = 0 then
if (r.sdstate < wr4) or (v.hsel = '1') then v.busy := '1';end if;
else
if (r.sdstate < wr4) or (r.startsd = '1') then v.busy := '1';end if;
end if;
v.busy := v.busy or r.bdelay;
busy := v.busy or r.busy;
v.aload := r.busy and not v.busy;
aload := v.aload;
-- generate memory address
sdmo.address <= v.address;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.startsd := '0';
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
end if;
ri <= v;
sdmo.bdrive <= v.bdrive;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdmo.busy <= busy;
sdmo.aload <= aload;
sdmo.hready <= r.hready;
sdmo.vhready <= v.hready;
sdmo.hresp <= hresp;
sdmo.hsel <= r.hsel;
sdmo.bsel <= r.bsel;
end process;
regs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri;
if rst = '0' then
r.icnt <= (others => '0');
end if;
end if;
if rst = '0' then
r.bdrive <= '0';
r.sdcsn <= (others => '1');
end if;
end process;
end;
| gpl-2.0 | 7419cd66b9b1e0fd42baeb25810c6d92 | 0.525242 | 3.132588 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_Block_proc.vhd | 2 | 17,400 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_Block_proc is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_4 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_5 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_6 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_7 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_8 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_9 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_10 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_11 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end;
architecture behav of image_filter_Block_proc is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_20 : BOOLEAN;
signal ap_sig_bdd_46 : BOOLEAN;
signal p_src_rows_V_fu_31_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal p_src_cols_V_fu_35_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_return_0_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_1_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_2_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_3_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_4_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_5_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_6_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_7_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_8_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_9_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_10_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_return_11_preg : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_return_0_preg assign process. --
ap_return_0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_0_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_0_preg <= p_src_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_10_preg assign process. --
ap_return_10_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_10_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_10_preg <= p_src_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_11_preg assign process. --
ap_return_11_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_11_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_11_preg <= p_src_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_1_preg assign process. --
ap_return_1_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_1_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_1_preg <= p_src_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_2_preg assign process. --
ap_return_2_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_2_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_2_preg <= p_src_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_3_preg assign process. --
ap_return_3_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_3_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_3_preg <= p_src_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_4_preg assign process. --
ap_return_4_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_4_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_4_preg <= p_src_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_5_preg assign process. --
ap_return_5_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_5_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_5_preg <= p_src_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_6_preg assign process. --
ap_return_6_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_6_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_6_preg <= p_src_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_7_preg assign process. --
ap_return_7_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_7_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_7_preg <= p_src_rows_V_fu_31_p1;
end if;
end if;
end if;
end process;
-- ap_return_8_preg assign process. --
ap_return_8_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_8_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_8_preg <= p_src_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- ap_return_9_preg assign process. --
ap_return_9_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_9_preg <= ap_const_lv12_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_9_preg <= p_src_cols_V_fu_35_p1;
end if;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_46)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_return_0 assign process. --
ap_return_0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_rows_V_fu_31_p1, ap_return_0_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_0 <= p_src_rows_V_fu_31_p1;
else
ap_return_0 <= ap_return_0_preg;
end if;
end process;
-- ap_return_1 assign process. --
ap_return_1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_cols_V_fu_35_p1, ap_return_1_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_1 <= p_src_cols_V_fu_35_p1;
else
ap_return_1 <= ap_return_1_preg;
end if;
end process;
-- ap_return_10 assign process. --
ap_return_10_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_rows_V_fu_31_p1, ap_return_10_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_10 <= p_src_rows_V_fu_31_p1;
else
ap_return_10 <= ap_return_10_preg;
end if;
end process;
-- ap_return_11 assign process. --
ap_return_11_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_cols_V_fu_35_p1, ap_return_11_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_11 <= p_src_cols_V_fu_35_p1;
else
ap_return_11 <= ap_return_11_preg;
end if;
end process;
-- ap_return_2 assign process. --
ap_return_2_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_rows_V_fu_31_p1, ap_return_2_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_2 <= p_src_rows_V_fu_31_p1;
else
ap_return_2 <= ap_return_2_preg;
end if;
end process;
-- ap_return_3 assign process. --
ap_return_3_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_rows_V_fu_31_p1, ap_return_3_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_3 <= p_src_rows_V_fu_31_p1;
else
ap_return_3 <= ap_return_3_preg;
end if;
end process;
-- ap_return_4 assign process. --
ap_return_4_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_cols_V_fu_35_p1, ap_return_4_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_4 <= p_src_cols_V_fu_35_p1;
else
ap_return_4 <= ap_return_4_preg;
end if;
end process;
-- ap_return_5 assign process. --
ap_return_5_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_cols_V_fu_35_p1, ap_return_5_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_5 <= p_src_cols_V_fu_35_p1;
else
ap_return_5 <= ap_return_5_preg;
end if;
end process;
-- ap_return_6 assign process. --
ap_return_6_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_rows_V_fu_31_p1, ap_return_6_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_6 <= p_src_rows_V_fu_31_p1;
else
ap_return_6 <= ap_return_6_preg;
end if;
end process;
-- ap_return_7 assign process. --
ap_return_7_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_rows_V_fu_31_p1, ap_return_7_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_7 <= p_src_rows_V_fu_31_p1;
else
ap_return_7 <= ap_return_7_preg;
end if;
end process;
-- ap_return_8 assign process. --
ap_return_8_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_cols_V_fu_35_p1, ap_return_8_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_8 <= p_src_cols_V_fu_35_p1;
else
ap_return_8 <= ap_return_8_preg;
end if;
end process;
-- ap_return_9 assign process. --
ap_return_9_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_bdd_46, p_src_cols_V_fu_35_p1, ap_return_9_preg)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_46))) then
ap_return_9 <= p_src_cols_V_fu_35_p1;
else
ap_return_9 <= ap_return_9_preg;
end if;
end process;
-- ap_sig_bdd_20 assign process. --
ap_sig_bdd_20_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_20 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_46 assign process. --
ap_sig_bdd_46_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_46 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
p_src_cols_V_fu_35_p1 <= cols(12 - 1 downto 0);
p_src_rows_V_fu_31_p1 <= rows(12 - 1 downto 0);
end behav;
| gpl-3.0 | 095aff0a96d28786779dfb3b2d224a7d | 0.539425 | 2.925845 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/spi/spi_flash.vhd | 1 | 20,125 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi_flash
-- File: spi_flash.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description:
--
-- SPI flash simulation models.
--
-- +--------------------------------------------------------+
-- | ftype | Memory device |
-- +--------+-----------------------------------------------+
-- | 1 | SD card |
-- +--------+-----------------------------------------------+
-- | 3 | Simple SPI |
-- +--------+-----------------------------------------------+
-- | 4 | SPI memory device |
-- +--------+-----------------------------------------------+
--
-- For ftype => 4, the memoffset generic can be used to specify an address
-- offset that till be automatically be removed by the memory model. For
-- instance, memoffset => 16#1000# and an access to 0x1000 will read the
-- internal memory array at offset 0x0. This is a quick hack to support booting
-- from SPIMCTRL that has an offset specified and not having to modify the
-- SREC.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib, gaisler;
use grlib.stdlib.all;
use grlib.stdio.all;
--use gaisler.sim.all;
entity spi_flash is
generic (
ftype : integer := 0; -- Flash type
debug : integer := 0; -- Debug output
fname : string := "prom.srec"; -- File to read from
readcmd : integer := 16#0B#; -- SPI memory device read command
dummybyte : integer := 1;
dualoutput : integer := 0;
memoffset : integer := 0); -- Addr. offset automatically removed
-- by Flash model
port (
sck : in std_ulogic;
di : inout std_logic;
do : inout std_logic;
csn : inout std_logic;
-- Test control inputs
sd_cmd_timeout : in std_ulogic := '0';
sd_data_timeout : in std_ulogic := '0'
);
end spi_flash;
architecture sim of spi_flash is
-- Description: Simple, incomplete, model of SD card
procedure simple_sd_model (
constant dbg : in integer;
signal sck : in std_ulogic;
signal di : in std_ulogic;
signal do : out std_ulogic;
signal csn : in std_ulogic;
-- Test control inputs
signal cmd_to : in std_ulogic; -- force command response timeout
signal data_to : in std_ulogic) is -- force data token timeout
type sd_state_type is (idle, wait_cmd55, wait_acmd41, wait_cmd16,
wait_cmd17);
type response_type is array (0 to 10) of std_logic_vector(7 downto 0);
variable state : sd_state_type := idle;
variable received_command : std_ulogic := '0';
variable respond : std_ulogic := '0';
variable response : response_type;
variable resp_size : integer;
variable indata : std_logic_vector(7 downto 0);
variable command : std_logic_vector(47 downto 0);
variable index : integer;
variable bcnt : integer;
constant CMD0 : std_logic_vector(5 downto 0) := "000000";
constant CMD16 : std_logic_vector(5 downto 0) := "010000";
constant CMD17 : std_logic_vector(5 downto 0) := "010001";
constant CMD55 : std_logic_vector(5 downto 0) := "110111";
constant ACMD41 : std_logic_vector(5 downto 0) := "101001";
constant R1 : std_logic_vector(7 downto 0) := X"00";
constant DATA_TOKEN : std_logic_vector(7 downto 0) := X"FE";
constant DATA_ERR_TOKEN : std_logic_vector(7 downto 0) := X"01";
begin -- simple_sd_model
loop
if csn /= '0' then wait until csn = '0'; end if;
index := 0; command := (others => '0');
-- Receive data
do <= '1';
while received_command = '0' and csn = '0' loop
wait until rising_edge(sck);
indata := indata(6 downto 0) & di;
index := index + 1;
if index = 8 then -- Received a byte
command := command(39 downto 0) & indata;
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received byte: " &
tost(indata));
end if;
if (command(47 downto 46) = "01" and command(7 downto 0) = X"95") then
received_command := '1';
end if;
index := 0;
end if;
end loop;
if received_command = '1' then
case state is
when idle =>
if command(45 downto 40) = CMD0 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD0");
end if;
if cmd_to = '0' then
state := wait_cmd55;
end if;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_cmd55 =>
if command(45 downto 40) = CMD55 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD55");
end if;
state := wait_acmd41;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_acmd41 =>
if command(45 downto 40) = ACMD41 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD41");
end if;
if cmd_to = '0' then
state := wait_cmd16;
else
state := idle;
end if;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_cmd16 =>
if command(45 downto 40) = CMD16 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD16");
Print(time'image(now) & ": simple_sd_model: BLOCKLEN set to " &
tost(conv_integer(command(39 downto 8))));
end if;
state := wait_cmd17;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
when wait_cmd17 =>
if command(45 downto 40) = CMD17 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD17");
Print(time'image(now) & ": simple_sd_model: Read from address " &
tost(conv_integer(command(39 downto 8))));
end if;
response(0) := R1;
response(1) := (others => '1');
response(2) := (others => '1');
response(3) := DATA_TOKEN;
-- Data response is address
response(4) := command(39 downto 32);
response(5) := command(31 downto 24);
response(6) := command(23 downto 16);
response(7) := command(15 downto 8);
if data_to = '1' then
resp_size := 1;
else
resp_size := 8;
end if;
respond := not cmd_to;
elsif command(45 downto 40) = CMD0 then
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received CMD0");
end if;
if cmd_to = '0' then
state := wait_cmd55;
end if;
response(0) := R1;
response(1) := (others => '1');
resp_size := 2;
respond := not cmd_to;
else
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: received unexpected CMD" &
tost(conv_integer(command(45 downto 40))));
end if;
end if;
end case;
received_command := '0';
end if;
if respond = '1' then
bcnt := 0;
while resp_size > bcnt loop
if dbg /= 0 then
Print(time'image(now) & ": simple_sd_model: Responding with " &
tost(response(bcnt)));
end if;
index := 0;
while index < 8 loop
wait until falling_edge(sck);
do <= response(bcnt)(7);
response(bcnt)(7 downto 1) := response(bcnt)(6 downto 0);
index := index + 1;
end loop;
bcnt := bcnt + 1;
end loop;
respond := '0';
wait until rising_edge(sck);
else
do <= '1';
end if;
end loop;
end simple_sd_model;
-- purpose: Simple, incomplete, model of SPI Flash device
procedure simple_spi_flash_model (
constant dbg : in integer;
constant readcmd : in integer;
constant dummybyte : in boolean;
constant dualoutput : in boolean;
signal sck : in std_ulogic;
signal di : inout std_ulogic;
signal do : out std_ulogic;
signal csn : in std_ulogic) is
constant readinst : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(readcmd, 8);
variable received_command : std_ulogic := '0';
variable respond : std_ulogic := '0';
variable response : std_logic_vector(31 downto 0);
variable indata : std_logic_vector(7 downto 0);
variable command : std_logic_vector(39 downto 0);
variable index : integer;
begin -- simple_spi_flash_model
di <= 'Z'; do <= 'Z';
loop
if csn /= '0' then wait until csn = '0'; end if;
index := 0; command := (others => '0');
while received_command = '0' and csn = '0' loop
wait until rising_edge(sck);
indata := indata(6 downto 0) & di;
index := index + 1;
if index = 8 then
command := command(31 downto 0) & indata;
if dbg /= 0 then
Print(time'image(now) & ": simple_spi_flash_model: received byte: " &
tost(indata));
end if;
if ((dummybyte and command(39 downto 32) = readinst) or
(not dummybyte and command(31 downto 24) = readinst)) then
received_command := '1';
end if;
index := 0;
end if;
end loop;
if received_command = '1' then
response := (others => '0');
if dummybyte then
response(23 downto 0) := command(31 downto 8);
else
response(23 downto 0) := command(23 downto 0);
end if;
index := 31 - conv_integer(response(1 downto 0)) * 8;
response(1 downto 0) := (others => '0');
while csn = '0' loop
while index >= 0 and csn = '0' loop
wait until falling_edge(sck) or csn = '1';
if dualoutput then
do <= response(index);
di <= response(index-1);
index := index - 2;
else
do <= response(index);
index := index - 1;
end if;
end loop;
index := 31;
response := response + 4;
end loop;
if dualoutput then
di <= 'Z';
end if;
received_command := '0';
else
do <= '1';
end if;
end loop;
end simple_spi_flash_model;
-- purpose: SPI memory device that reads input from prom.srec
procedure spi_memory_model (
constant dbg : in integer;
constant readcmd : in integer;
constant dummybyte : in boolean;
constant dualoutput : in boolean;
signal sck : in std_ulogic;
signal di : inout std_ulogic;
signal do : inout std_ulogic;
signal csn : in std_ulogic) is
constant readinst : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(readcmd, 8);
variable received_command : std_ulogic := '0';
variable respond : std_ulogic := '0';
variable response : std_logic_vector(31 downto 0);
variable address : std_logic_vector(23 downto 0);
variable indata : std_logic_vector(7 downto 0);
variable command : std_logic_vector(39 downto 0);
variable index : integer;
file fload : text open read_mode is fname;
variable fline : line;
variable fchar : character;
variable rtype : std_logic_vector(3 downto 0);
variable raddr : std_logic_vector(31 downto 0);
variable rlen : std_logic_vector(7 downto 0);
variable rdata : std_logic_vector(0 to 127);
variable wordaddr : integer;
type mem_type is array (0 to 8388607) of std_logic_vector(31 downto 0);
variable mem : mem_type := (others => (others => '1'));
begin -- spi_memory_model
di <= 'Z'; do <= 'Z';
-- Load memory data from file
while not endfile(fload) loop
readline(fload, fline);
read(fline, fchar);
if fchar /= 'S' or fchar /= 's' then
hread(fline, rtype);
hread(fline, rlen);
raddr := (others => '0');
case rtype is
when "0001" =>
hread(fline, raddr(15 downto 0));
when "0010" =>
hread(fline, raddr(23 downto 0));
when "0011" =>
hread(fline, raddr);
raddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(fline, rdata);
for i in 0 to 3 loop
mem(conv_integer(raddr(31 downto 2)+i)) :=
rdata(i*32 to i*32+31);
end loop;
end if;
end loop;
loop
if csn /= '0' then wait until csn = '0'; end if;
index := 0; command := (others => '0');
while received_command = '0' and csn = '0' loop
wait until rising_edge(sck);
indata := indata(6 downto 0) & di;
index := index + 1;
if index = 8 then
command := command(31 downto 0) & indata;
if dbg /= 0 then
Print(time'image(now) & ": spi_memory_model: received byte: " &
tost(indata));
end if;
if ((dummybyte and command(39 downto 32) = readinst) or
(not dummybyte and command(31 downto 24) = readinst)) then
received_command := '1';
end if;
index := 0;
end if;
end loop;
if received_command = '1' then
response := (others => '0');
if dummybyte then
address := command(31 downto 8);
else
address := command(23 downto 0);
end if;
if dbg /= 0 then
Print(time'image(now) & ": spi_memory_model: received address: " &
tost(address));
if memoffset /= 0 then
Print(time'image(now) & ": spi_memory_model: address after removed offset " &
tost(address-memoffset));
end if;
end if;
if memoffset /= 0 then
address := address - memoffset;
end if;
index := 31 - conv_integer(address(1 downto 0)) * 8;
while csn = '0' loop
response := mem(conv_integer(address(23 downto 2)));
if dbg /= 0 then
Print(time'image(now) & ": spi_memory_model: responding with data: " &
tost(response(index downto 0)));
end if;
while index >= 0 and csn = '0' loop
wait until falling_edge(sck) or csn = '1';
if dualoutput then
do <= response(index);
di <= response(index-1);
index := index - 2;
else
do <= response(index);
index := index - 1;
end if;
end loop;
index := 31;
address := address + 4;
end loop;
if dualoutput then
di <= 'Z';
end if;
do <= 'Z';
received_command := '0';
else
do <= 'Z';
end if;
end loop;
end spi_memory_model;
signal vdd : std_ulogic := '1';
signal gnd : std_ulogic := '0';
begin -- sim
-- ftype0: if ftype = 0 generate
-- csn <= 'Z';
-- di <= 'Z';
-- flash0 : s25fl064a
-- generic map (tdevice_PU => 1 us,
-- TimingChecksOn => true,
-- MsgOn => debug = 1,
-- UserPreLoad => true)
-- port map (SCK => sck, SI => di, CSNeg => csn, HOLDNeg => vdd,
-- WNeg => vdd, SO => do);
-- end generate ftype0;
ftype1: if ftype = 1 generate
csn <= 'H';
di <= 'Z';
simple_sd_model(debug, sck, di, do, csn, sd_cmd_timeout, sd_data_timeout);
end generate ftype1;
-- ftype2: if ftype = 2 generate
-- csn <= 'Z';
-- di <= 'Z';
-- flash0 : m25p80
-- generic map (TimingChecksOn => false,
-- MsgOn => debug = 1,
-- UserPreLoad => true)
-- port map (C => sck, D => di, SNeg => csn, HOLDNeg => vdd,
-- WNeg => vdd, Q => do);
-- end generate ftype2;
ftype3: if ftype = 3 generate
csn <= 'Z';
simple_spi_flash_model (
dbg => debug,
readcmd => readcmd,
dummybyte => dummybyte /= 0,
dualoutput => dualoutput /= 0,
sck => sck,
di => di,
do => do,
csn => csn);
end generate ftype3;
ftype4: if ftype = 4 generate
spi_memory_model (
dbg => debug,
readcmd => readcmd,
dummybyte => dummybyte /= 0,
dualoutput => dualoutput /= 0,
sck => sck,
di => di,
do => do,
csn => csn);
csn <= 'Z';
end generate ftype4;
notsupported: if ftype > 4 generate
assert false report "spi_flash: no model" severity failure;
end generate notsupported;
end sim;
| gpl-2.0 | 34952040b866603f12628f697a89e32b | 0.488944 | 4.129052 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-sp605/vga_clkgen.vhd | 3 | 1,981 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity vga_clkgen is
port (
resetn : in std_logic;
sel : in std_logic_vector(1 downto 0);
clk25 : in std_logic;
clkm : in std_logic;
clk50 : in std_logic;
clkout : out std_logic
);
end;
architecture struct of vga_clkgen is
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal clk65, clksel : std_logic;
begin
-- 65 MHz clock generator
clkgen65 : clkmul_virtex2 generic map (13, 5) port map (resetn, clk25, clk65);
clk_select : process (clk25, clk50, clk65, sel)
begin
case sel is
when "00" => clksel <= clk25;
when "01" => clksel <= clkm;
when "10" => clksel <= clk50;
when "11" => clksel <= clk65;
when others => clksel <= '0';
end case;
end process;
bufg1 : BUFG port map (I => clksel, O => clkout);
end;
| gpl-2.0 | 552e8d7b7164009f682d38550d4259ad | 0.651691 | 3.675325 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/i2c/i2c2ahb_apb_gen.vhd | 1 | 5,329 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_apb_gen
-- File: i2c2ahb_apb_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Generic wrapper for I2C-slave, see i2c2ahb_apb.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb_apb_gen is
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
--ahbi : in ahb_mst_in_type;
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(AHBDW-1 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(AHBDW-1 downto 0);
-- APB slave interface
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_irq : out std_logic;
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2c2ahb_apb_gen;
architecture rtl of i2c2ahb_apb_gen is
-- AHB signals
signal ahbi : ahb_mst_in_type;
signal ahbo : ahb_mst_out_type;
-- APB signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
ahbi.hgrant(0) <= ahbi_hgrant;
ahbi.hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi.hready <= ahbi_hready;
ahbi.hresp <= ahbi_hresp;
ahbi.hrdata <= ahbi_hrdata;
ahbo_hbusreq <= ahbo.hbusreq;
ahbo_hlock <= ahbo.hlock;
ahbo_htrans <= ahbo.htrans;
ahbo_haddr <= ahbo.haddr;
ahbo_hwrite <= ahbo.hwrite;
ahbo_hsize <= ahbo.hsize;
ahbo_hburst <= ahbo.hburst;
ahbo_hprot <= ahbo.hprot;
ahbo_hwdata <= ahbo.hwdata;
apbi.psel(0) <= apbi_psel;
apbi.psel(1 to NAPBSLV-1) <= (others => '0');
apbi.penable <= apbi_penable;
apbi.paddr <= apbi_paddr;
apbi.pwrite <= apbi_pwrite;
apbi.pwdata <= apbi_pwdata;
apbi.pirq <= (others => '0');
apbi.testen <= '0';
apbi.testrst <= '0';
apbi.scanen <= '0';
apbi.testoen <= '0';
apbo_prdata <= apbo.prdata;
apbo_irq <= apbo.pirq(0);
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2c2ahb_apb
generic map (
hindex => 0,
ahbaddrh => ahbaddrh, ahbaddrl => ahbaddrl,
ahbmaskh => ahbmaskh, ahbmaskl => ahbmaskl,
resen => resen,
pindex => 0, paddr => 0, pmask => 0, pirq => 0,
i2cslvaddr => i2cslvaddr, i2ccfgaddr => i2ccfgaddr,
oepol => oepol, filter => filter)
port map (rstn, clk, ahbi, ahbo, apbi, apbo, i2ci, i2co);
end architecture rtl;
| gpl-2.0 | d747c5ca91e62b167b78594d346f1267 | 0.589416 | 3.261322 | false | false | false | false |
gtaylormb/opl3_fpga | fpga/bd/opl3_cpu/ip/opl3_cpu_rst_opl3_fpga_0_12M_0/sim/opl3_cpu_rst_opl3_fpga_0_12M_0.vhd | 1 | 5,878 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_9;
USE proc_sys_reset_v5_0_9.proc_sys_reset;
ENTITY opl3_cpu_rst_opl3_fpga_0_12M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END opl3_cpu_rst_opl3_fpga_0_12M_0;
ARCHITECTURE opl3_cpu_rst_opl3_fpga_0_12M_0_arch OF opl3_cpu_rst_opl3_fpga_0_12M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF opl3_cpu_rst_opl3_fpga_0_12M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END opl3_cpu_rst_opl3_fpga_0_12M_0_arch;
| lgpl-3.0 | 368eaf8b08d5475d21f962d0caeb2275 | 0.706022 | 3.51976 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_src1_data_stream_1_V.vhd | 2 | 6,292 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FIFO_image_filter_src1_data_stream_1_V is
generic (
MEM_STYLE : string := "block";
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 15;
DEPTH : natural := 20000
);
port (
clk : in std_logic;
reset : in std_logic;
if_full_n : out std_logic;
if_write_ce : in std_logic;
if_write : in std_logic;
if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
if_empty_n : out std_logic;
if_read_ce : in std_logic;
if_read : in std_logic;
if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity;
architecture arch of FIFO_image_filter_src1_data_stream_1_V is
type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal q_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal waddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal raddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal wnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal rnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal push : std_logic;
signal pop : std_logic;
signal usedw : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal full_n : std_logic := '1';
signal empty_n : std_logic := '0';
signal q_tmp : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal show_ahead : std_logic := '0';
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal dout_valid : std_logic := '0';
attribute ram_style: string;
attribute ram_style of mem: signal is MEM_STYLE;
begin
if_full_n <= full_n;
if_empty_n <= dout_valid;
if_dout <= dout_buf;
push <= full_n and if_write_ce and if_write;
pop <= empty_n and if_read_ce and (not dout_valid or if_read);
wnext <= waddr when push = '0' else
(others => '0') when waddr = DEPTH - 1 else
waddr + 1;
rnext <= raddr when pop = '0' else
(others => '0') when raddr = DEPTH - 1 else
raddr + 1;
-- waddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
waddr <= (others => '0');
else
waddr <= wnext;
end if;
end if;
end process;
-- raddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
raddr <= (others => '0');
else
raddr <= rnext;
end if;
end if;
end process;
-- usedw
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
usedw <= (others => '0');
elsif push = '1' and pop = '0' then
usedw <= usedw + 1;
elsif push = '0' and pop = '1' then
usedw <= usedw - 1;
end if;
end if;
end process;
-- full_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
full_n <= '1';
elsif push = '1' and pop = '0' then
if usedw = DEPTH - 1 then
full_n <= '0';
else
full_n <= '1';
end if;
elsif push = '0' and pop = '1' then
full_n <= '1';
end if;
end if;
end process;
-- empty_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
empty_n <= '0';
elsif push = '1' and pop = '0' then
empty_n <= '1';
elsif push = '0' and pop = '1' then
if usedw = 1 then
empty_n <= '0';
else
empty_n <= '1';
end if;
end if;
end if;
end process;
-- mem
process (clk) begin
if clk'event and clk = '1' then
if push = '1' then
mem(to_integer(waddr)) <= if_din;
end if;
end if;
end process;
-- q_buf
process (clk) begin
if clk'event and clk = '1' then
q_buf <= mem(to_integer(rnext));
end if;
end process;
-- q_tmp
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
q_tmp <= (others => '0');
elsif push = '1' then
q_tmp <= if_din;
end if;
end if;
end process;
-- show_ahead
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
show_ahead <= '0';
elsif push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
show_ahead <= '1';
else
show_ahead <= '0';
end if;
end if;
end process;
-- dout_buf
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_buf <= (others => '0');
elsif pop = '1' then
if show_ahead = '1' then
dout_buf <= q_tmp;
else
dout_buf <= q_buf;
end if;
end if;
end if;
end process;
-- dout_valid
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_valid <= '0';
elsif pop = '1' then
dout_valid <= '1';
elsif if_read_ce = '1' and if_read = '1' then
dout_valid <= '0';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 1d27f708ed562024585020e90d13a907 | 0.446599 | 3.799517 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep1c20/testbench.vhd | 1 | 11,804 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clkout : out std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector (3 downto 0);
iosn : out std_ulogic;
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_ulogic; -- sdram clock enable
sdcsn : out std_ulogic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector (1 downto 0);
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
rxd1 : in std_ulogic; -- UART1 rx data
txd1 : out std_ulogic; -- UART1 tx data
-- for smc lan chip
eth_aen : out std_ulogic;
eth_readn : out std_ulogic;
eth_writen : out std_ulogic;
eth_nbe : out std_logic_vector (3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic
);
end component;
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector (3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal sdba : std_logic_vector(1 downto 0);
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
pllref <= clkout;
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech, ncpu,
disas, dbguart, pclow )
port map (rst, clk, clkout, pllref, error, address, data,
ramsn, ramoen, rwen, mben, iosn,
romsn, oen, writen,
sa(11 downto 0), sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm, sdba,
dsutx, dsurx, dsubren, dsuact,
rxd1, txd1,
eth_aen, eth_readn, eth_writen, eth_nbe);
-- optional sdram
sd1 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, rwen, oen);
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn,
rwen, ramoen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 5c6c678608e1c8c02f39eb3816e62dc4 | 0.570739 | 3.218103 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-terasic-de2-115/testbench.vhd | 1 | 10,406 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romdepth : integer := 20; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal sma_clkout : std_ulogic;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 24);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic;
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(35 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col : std_logic := '0';
signal eth_gtxclk, erx_crs, etx_en, etx_er : std_logic :='0';
signal eth_macclk : std_logic := '0';
signal erxd, etxd : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdintn : std_logic := '1';
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_stb : std_logic_vector(0 to CFG_CAN_NUM-1);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsuen <= '1';
dsubre <= '1'; -- inverted on the board
rxd1 <= '1';
can_rxd <= (others => 'H'); bexcn <= '1';
gpio(2 downto 0) <= "LHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
eth_macclk <= not eth_macclk after 4 ns;
ereset <= 'H';
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, sma_clkout, error, address(22 downto 0), data,
sa(12 downto 0), sa(14 downto 13), sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsubre, dsuact,
oen, writen, open, open, romsn, gpio,
emdio, eth_macclk, etx_clk, erx_clk, erxd(3 downto 0), erx_dv, erx_er,
erx_col, erx_crs, emdintn, ereset, etxd(3 downto 0), etx_en, etx_er, emdc,
can_txd, can_rxd, can_stb
);
sd1 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1)) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
-- sram0 : for i in 0 to (sramwidth/8)-1 generate
-- sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
-- port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
-- rwen(0), ramoen(0));
-- end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(address => 16)
port map(ereset, emdio, etx_clk, erx_clk, erxd, erx_dv,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, eth_macclk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
-- test0 : grtestmod
-- port map ( rst, clk, error, address(21 downto 2), data,
-- iosn, oen, writen, brdyn);
-- data <= buskeep(data), (others => 'H') after 250 ns;
data <= buskeep(data) after 5 ns;
-- sd <= buskeep(sd), (others => 'H') after 250 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 01ae42cae48a40a7d5df5d4f30e29375 | 0.582068 | 3.071429 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/misc/apbps2.vhd | 1 | 13,596 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbps2
-- File: apbps2.vhd
-- Author: Marcus Hellqvist, Jiri Gaisler
-- Modified by: Jan Andersson
-- Description: PS/2 keyboard interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity apbps2 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 0;
oepol : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end;
architecture rtl of apbps2 is
constant fifosize : integer := 16;
type rxstates is (idle,start,data,parity,stop);
type txstates is (idle,waitrequest,start,data,parity,stop,ack);
type fifotype is array(0 to fifosize-1) of std_logic_vector(7 downto 0);
type ps2_regs is record
-- status reg
data_ready : std_ulogic; -- data ready
parity_error : std_ulogic; -- parity carry out/ error bit
frame_error : std_ulogic; -- frame error when receiving
kb_inh : std_ulogic; -- keyboard inhibit
rbf : std_ulogic; -- receiver buffer full
tbf : std_ulogic; -- transmitter buffer full
rcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
tcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
-- control reg
rx_en : std_ulogic; -- receive enable
tx_en : std_ulogic; -- transmit enable
rx_irq_en : std_ulogic; -- keyboard interrupt enable
tx_irq_en : std_ulogic; -- transmit interrupt enable
-- others
tx_act : std_ulogic; -- tx active
rxdf : std_logic_vector(4 downto 0); -- rx data filter
rxcf : std_logic_vector(4 downto 0); -- rx clock filter
rx_irq : std_ulogic; -- keyboard interrupt
tx_irq : std_ulogic; -- transmit interrupt
rxfifo : fifotype; -- fifo with 16 bytes
rraddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
rwaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
rxstate : rxstates;
txfifo : fifotype; -- fifo with 16 bytes
traddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
twaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
txstate : txstates;
ps2_clk_syn : std_ulogic; -- ps2 clock synchronized
ps2_data_syn : std_ulogic; -- ps2 data synchronized
ps2_clk_fall : std_ulogic; -- ps2 clock falling edge detector
rshift : std_logic_vector(7 downto 0); -- shift register
rpar : std_ulogic; -- parity check bit
tshift : std_logic_vector(9 downto 0); -- shift register
tpar : std_ulogic; -- transmit parity bit
ps2clk : std_ulogic; -- ps2 clock
ps2data : std_ulogic; -- ps2 data
ps2clkoe : std_ulogic; -- ps2 clock output enable
ps2dataoe : std_ulogic; -- ps2 data output enable
timer : std_logic_vector(16 downto 0); -- timer
reload : std_logic_vector(16 downto 0); -- reload register
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
constant REVISION : integer := 2;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBPS2, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1);
constant INPUT : std_ulogic := conv_std_logic(oepol = 0);
signal r, rin : ps2_regs;
signal ps2_clk, ps2_data : std_ulogic;
begin
ps2_op : process(r, rst, ps2_clk, ps2_data,apbi)
variable v : ps2_regs;
variable rdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r;
rdata := (others => '0'); v.data_ready := '0'; irq := (others => '0'); irq(pirq) := r.rx_irq or r.tx_irq;
v.rx_irq := '0'; v.tx_irq := '0'; v.rbf := r.rcnt(log2x(fifosize)); v.tbf := r.tcnt(log2x(fifosize));
if r.rcnt /= rcntzero then v.data_ready := '1'; end if;
-- Synchronize and filter ps2 input
v.rxdf(0) := ps2_data; v.rxdf(4 downto 1) := r.rxdf(3 downto 0);
v.rxcf(0) := ps2_clk; v.rxcf(4 downto 1) := r.rxcf(3 downto 0);
if (r.rxdf(4) & r.rxdf(4) & r.rxdf(4) & r.rxdf(4)) = r.rxdf(3 downto 0) then
v.ps2_data_syn := r.rxdf(4);
end if;
if (r.rxcf(4) & r.rxcf(4) & r.rxcf(4) & r.rxcf(4)) = r.rxcf(3 downto 0) then
v.ps2_clk_syn := r.rxcf(4);
end if;
if (v.ps2_clk_syn /= r.ps2_clk_syn) and (v.ps2_clk_syn = '0') then
v.ps2_clk_fall := '1';
else
v.ps2_clk_fall := '0';
end if;
-- read registers
case apbi.paddr(3 downto 2) is
when "00" =>
rdata(7 downto 0) := r.rxfifo(conv_integer(r.rraddr));
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
if r.rcnt /= rcntzero then
v.rxfifo(conv_integer(r.rraddr)) := (others => '0');
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "01" =>
rdata(27 + log2x(fifosize) downto 27) := r.rcnt;
rdata(22 + log2x(fifosize) downto 22) := r.tcnt;
rdata(5 downto 0) := r.tbf & r.rbf & r.kb_inh & r.frame_error & r.parity_error & r.data_ready;
when "10" =>
rdata(3 downto 0) := r.tx_irq_en & r.rx_irq_en & r.tx_en & r.rx_en;
when others =>
if fixed = 0 then rdata(r.reload'range) := r.reload; end if;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
if r.tcnt(log2x(fifosize)) = '0' then
v.txfifo(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
v.twaddr := r.twaddr + 1; v.tcnt := r.tcnt + 1;
end if;
when "01" =>
v.kb_inh := apbi.pwdata(3);
v.frame_error := apbi.pwdata(2);
v.parity_error := apbi.pwdata(1);
when "10" =>
v.tx_irq_en := apbi.pwdata(3);
v.rx_irq_en := apbi.pwdata(2);
v.tx_en := apbi.pwdata(1);
v.rx_en := apbi.pwdata(0);
when "11" =>
if fixed = 0 then
v.reload := apbi.pwdata(r.reload'range);
end if;
when others =>
null;
end case;
end if;
case r.txstate is
when idle =>
if r.tx_en = '1' and r.tcnt /= rcntzero then
v.ps2clk := '0'; v.ps2clkoe := OUTPUT; v.tx_act := '1';
v.ps2data := '1'; v.ps2dataoe := OUTPUT; v.txstate := waitrequest;
if fixed = 1 then v.timer := conv_std_logic_vector(fKHz/10,r.timer'length);
else v.timer := r.reload; end if;
end if;
when waitrequest =>
v.timer := r.timer - 1;
if (v.timer(r.timer'left) and not r.timer(r.timer'left)) = '1' then
v.ps2data := '0'; v.txstate := start;
end if;
when start =>
v.ps2clkoe := INPUT; v.ps2clk := '1';
v.tshift := "10" & r.txfifo(conv_integer(r.traddr));
v.traddr := r.traddr + 1; v.tcnt := r.tcnt - 1;
v.tpar := '1';
v.txstate := data;
when data =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tshift(0);
v.tpar := r.tpar xor r.tshift(0);
v.tshift := '1' & r.tshift(9 downto 1);
if v.tshift = "1111111110" then v.txstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tpar; v.txstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
v.ps2data := '1'; v.txstate := ack;
end if;
when ack =>
v.ps2dataoe := INPUT;
if r.ps2_clk_fall = '1' and r.ps2_data_syn = '0'then
v.ps2data := '1'; v.ps2dataoe := OUTPUT; v.tx_irq := r.tx_irq_en;
v.txstate := idle; v.tx_act := '0';
end if;
end case;
-- receiver state machine
case r.rxstate is
when idle =>
if (r.rx_en and not r.tx_act) = '1' then
v.rshift := (others => '1'); v.rxstate := start;
end if;
when start =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '0' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rxstate := data; v.rpar := '0';
v.parity_error := '0'; v.frame_error := '0';
else v.rxstate := idle; end if;
end if;
when data =>
if r.ps2_clk_fall = '1' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rpar := r.rpar xor r.ps2_data_syn;
if r.rshift(0) = '0' then v.rxstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.parity_error := r.rpar xor (not r.ps2_data_syn);
v.rxstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '1' then
v.rx_irq := r.rx_irq_en; v.rxstate := idle;
if (r.rbf or r.parity_error) = '0' then
v.rxfifo(conv_integer(r.rwaddr)) := r.rshift(7 downto 0);
v.rwaddr := r.rwaddr + 1; v.rcnt := r.rcnt + 1;
end if;
else v.frame_error := '1'; v.rxstate := idle; end if;
end if;
end case;
-- keyboard inhibit / high impedance
if v.tx_act = '0' then
if r.rbf = '1' then
v.kb_inh := '1'; v.ps2clk := '0'; v.ps2data := '1';
v.ps2dataoe := OUTPUT; v.ps2clkoe := OUTPUT;
else
v.ps2clk := '1'; v.ps2data := '1'; v.ps2dataoe := INPUT;
v.ps2clkoe := INPUT;
end if;
end if;
if r.tx_act = '1' then
v.rxstate := idle;
end if;
-- reset operations
if rst = '0' then
v.data_ready := '0'; v.kb_inh := '0'; v.parity_error := '0';
v.frame_error := '0'; v.rx_en := '0'; v.tx_act := '0';
v.tx_en := '0'; v.rx_irq := '0'; v.tx_irq := '0';
v.ps2_clk_fall := '0'; v.ps2_clk_syn := '0'; v.ps2_data_syn := '0';
v.rshift := (others => '0'); v.rxstate := idle; v.txstate := idle;
v.rraddr := (others => '0'); v.rwaddr := (others => '0');
v.rcnt := (others => '0'); v.traddr := (others => '0');
v.twaddr := (others => '0'); v.tcnt := (others => '0');
v.tshift := (others => '0'); v.tpar := '0';
if fixed = 0 then
v.reload := conv_std_logic_vector(fKHz/10,r.reload'length);
end if;
end if;
if fixed = 1 then v.reload := (others => '0'); end if;
-- update registers
rin <= v;
-- drive outputs
apbo.prdata <= rdata;
apbo.pirq <= irq;
apbo.pindex <= pindex;
ps2o.ps2_clk_o <= r.ps2clk;
ps2o.ps2_clk_oe <= r.ps2clkoe;
ps2o.ps2_data_o <= r.ps2data;
ps2o.ps2_data_oe <= r.ps2dataoe;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
ps2_data <= to_x01(ps2i.ps2_data_i);
ps2_clk <= to_x01(ps2i.ps2_clk_i);
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbps2_" & tost(pindex) & ": APB PS2 interface rev " &
tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
| gpl-2.0 | ffe3c3ef9e425f2d6a858b7f5818c814 | 0.510003 | 3.349593 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-cpci-xc4v/config.vhd | 1 | 8,221 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (6);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 16;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0059#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000059#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 1;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 3;
constant CFG_PCIVID : integer := 16#1AC8#;
constant CFG_PCIDID : integer := 16#0054#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- GRPCI2 interface
constant CFG_GRPCI2_MASTER : integer := 0;
constant CFG_GRPCI2_TARGET : integer := 0;
constant CFG_GRPCI2_DMA : integer := 0;
constant CFG_GRPCI2_VID : integer := 16#0#;
constant CFG_GRPCI2_DID : integer := 16#0#;
constant CFG_GRPCI2_CLASS : integer := 16#0#;
constant CFG_GRPCI2_RID : integer := 16#0#;
constant CFG_GRPCI2_CAP : integer := 16#40#;
constant CFG_GRPCI2_NCAP : integer := 16#0#;
constant CFG_GRPCI2_BAR0 : integer := 0;
constant CFG_GRPCI2_BAR1 : integer := 0;
constant CFG_GRPCI2_BAR2 : integer := 0;
constant CFG_GRPCI2_BAR3 : integer := 0;
constant CFG_GRPCI2_BAR4 : integer := 0;
constant CFG_GRPCI2_BAR5 : integer := 0;
constant CFG_GRPCI2_FDEPTH : integer := 3;
constant CFG_GRPCI2_FCOUNT : integer := 2;
constant CFG_GRPCI2_ENDIAN : integer := 0;
constant CFG_GRPCI2_DEVINT : integer := 1;
constant CFG_GRPCI2_DEVINTMSK : integer := 16#0#;
constant CFG_GRPCI2_HOSTINT : integer := 1;
constant CFG_GRPCI2_HOSTINTMSK: integer := 16#0#;
constant CFG_GRPCI2_TRACE : integer := 1024;
constant CFG_GRPCI2_TRACEAPB : integer := 0;
constant CFG_GRPCI2_BYPASS : integer := 0;
constant CFG_GRPCI2_EXTCFG : integer := (0);
-- PCI arbiter
constant CFG_PCI_ARB : integer := 1;
constant CFG_PCI_ARBAPB : integer := 1;
constant CFG_PCI_ARB_NGNT : integer := (4);
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (3);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FE#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 1b85192f09474aa498cdce9d1da09412 | 0.651259 | 3.546592 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/outpad_ddr.vhd | 1 | 3,763 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad_ddr, outpad_ddrv
-- File: outpad_ddr.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Wrapper that instantiates a DDR register connected to an
-- output pad. The generic tech wrappers are not used for nextreme
-- since this technology requires that the output enable signal is
-- connected between the DDR register and the pad.
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.all;
entity outpad_ddr is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := x33v;
strength : integer := 12
);
port (
pad : out std_ulogic;
i1, i2 : in std_ulogic;
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of outpad_ddr is
signal q, oe, vcc : std_ulogic;
begin
vcc <= '1';
def: if (tech /= easic90) and (tech /= easic45) generate
ddrreg : ddr_oreg generic map (tech)
port map (q, c1, c2, ce, i1, i2, r, s);
p : outpad generic map (tech, level, slew, voltage, strength)
port map (pad, q);
oe <= '0';
end generate def;
nex : if (tech = easic90) generate
ddrreg : nextreme_oddr_reg
port map (ck => c1, dh => i1, dl => i2, doe => vcc, q => q, oe => oe, rstb => r);
p : nextreme_toutpad generic map (level, slew, voltage, strength)
port map(pad, q, oe);
end generate;
n2x : if (tech = easic45) generate
-- ddrpad : n2x_outpad_ddr generic map (level, slew, voltage, strength)
-- port map ();
--pragma translate_off
assert false report "outpad_ddr: Not yet supported on Nextreme2"
severity failure;
--pragma translate_on
q <= '0'; oe <= '0';
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity outpad_ddrv is
generic (
tech : integer := 0;
level : integer := 0;
slew : integer := 0;
voltage : integer := 0;
strength : integer := 12;
width : integer := 1
);
port (
pad : out std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of outpad_ddrv is
begin
v : for j in width-1 downto 0 generate
x0 : outpad_ddr generic map (tech, level, slew, voltage, strength)
port map (pad(j), i1(j), i2(j), c1, c2, ce, r, s);
end generate;
end;
| gpl-2.0 | dccca78346b3df79b99ae648889f0dc8 | 0.593941 | 3.632239 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-xc3s1000/testbench.vhd | 1 | 7,746 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(19 downto 0);
signal data : std_logic_vector(31 downto 0);
signal mben : std_logic_vector(3 downto 0);
signal pio : std_logic_vector(17 downto 0);
signal ramsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal errorn : std_logic;
signal ps2clk : std_logic;
signal ps2data : std_logic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic;
signal vid_g : std_logic;
signal vid_b : std_logic;
signal switch : std_logic_vector(7 downto 0); -- switches
signal button : std_logic_vector(2 downto 0);
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst; dsuen <= '1'; dsubre <= '0';
rxd1 <= 'H';
ps2clk <= 'H'; ps2data <= 'H';
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
address(1 downto 0) <= "00";
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (rst, clk, errorn, address(19 downto 2), data,
ramsn, mben, oen, writen,
dsubre, dsuact, txd1, rxd1, pio, --switch, button,
ps2clk, ps2data,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b
);
sram0 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => sdramfile)
port map (address(19 downto 2), data(31-i*16 downto 16-i*16),
mben(i*2), mben(i*2+1), ramsn(i), writen, oen);
end generate;
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '0' then wait on errorn; end if;
assert (to_x01(errorn) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait for 2500 ns;
dsurst <= '0';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
| gpl-2.0 | feb9f326fcc2b1963d1709c88cac6a5d | 0.574877 | 3.030516 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/allddr.vhd | 1 | 46,539 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: allddr
-- File: allddr.vhd
-- Author: David Lindh, Jiri Gaisler - Gaisler Research
-- Description: DDR input/output registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allddr is
component unisim_iddr_reg is
generic ( tech : integer := virtex4; arch : integer := 0);
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component gen_iddr_reg
port (
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ec_oddr_reg
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component unisim_oddr_reg
generic (tech : integer := virtex4; arch : integer := 0);
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component gen_oddr_reg
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component axcel_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component axcel_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component nextreme_oddr_reg
port(
CK : in std_ulogic;
DH : in std_ulogic;
DL : in std_ulogic;
DOE : in std_ulogic;
Q : out std_ulogic;
OE : out std_ulogic;
RSTB : in std_ulogic);
end component;
component nextreme_iddr_reg
port(
CK : in std_ulogic;
D : in std_ulogic;
QH : out std_ulogic;
QL : out std_ulogic;
RSTB : in std_ulogic);
end component;
component apa3_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3e_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3e_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3l_oddr_reg is
port(
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component apa3l_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component spartan3e_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component virtex4_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0)
);
end component;
component virtex2_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component stratixii_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component cycloneiii_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end component;
component generic_ddr_phy_wo_pads
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic
);
end component;
component tsmc90_tci_ddr_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clk90_sigi_0 : in std_logic;
rclk_sigi_1 : in std_logic;
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
--ddr_clk_fb_out : out std_logic;
--ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqsin : in std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
ddr_dqsout : out std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
ddr_dqsoen : out std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dqin : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dqout : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dqoen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- ddr address
ba : in std_logic_vector ( 1 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0);
moben : in std_logic;
conf : in std_logic_vector(63 downto 0);
tstclkout : out std_logic_vector(3 downto 0)
);
end component;
component virtex5_ddr2_phy_wo_pads
generic (
MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0; ddelayb8: integer := 0;
ddelayb9 : integer := 0; ddelayb10 : integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := virtex5; eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk : integer := 3; ncs : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- ddr addr
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0)
);
end component;
component stratixii_ddr2_phy
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- PLL locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end component;
component stratixiii_ddr2_phy
generic (
MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := stratix3; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- ddr addrees
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0);
oct : in std_logic
);
end component;
component spartan3a_ddr2_phy
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan3;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end component;
component easic90_ddr2_phy
generic (
tech : integer;
MHz : integer;
clk_mul : integer;
clk_div : integer;
dbits : integer;
rstdelay : integer := 200;
eightbanks : integer range 0 to 1 := 0);
port (
rstn : in std_logic;
clk : in std_logic;
clkout : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_ulogic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic;
ddr_rasb : out std_ulogic;
ddr_casb : out std_ulogic;
ddr_dm : out std_logic_vector (dbits/8-1 downto 0);
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0);
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0);
ddr_ad : out std_logic_vector (13 downto 0);
ddr_ba : out std_logic_vector (1+eightbanks downto 0);
ddr_dq : inout std_logic_vector (dbits-1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0);
dqout : in std_logic_vector (dbits*2-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
odt : in std_logic_vector(1 downto 0);
dqs_gate : in std_ulogic);
end component;
component spartan6_ddr2_phy_wo_pads
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan6;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3; ncs : integer := 2 );
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0);
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0);
ddr_dq_out : out std_logic_vector (dbits-1 downto 0);
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0);
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end component;
component generic_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
eightbanks: integer := 0; abits: integer := 14;
nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic; -- system clock returned
--clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0); -- ddr odt
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector (2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end component;
component n2x_ddr2_phy is
generic (
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
norefclk : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
ctrl2en : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clk270d : in std_logic; -- input clock shifted 270 degrees
-- for operating without PLL
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
rden_pad : inout std_logic_vector(dbits/8-1 downto 0); -- pad delay comp. dummy I/O
addr : in std_logic_vector (abits-1 downto 0); -- ddr address
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
noen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
odt : in std_logic_vector(ncs-1 downto 0);
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_logic;
-- Copy of control signals for 2nd DIMM
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
-- Pass through to pads
dq_control : in std_logic_vector(17 downto 0);
dqs_control : in std_logic_vector(17 downto 0);
ck_control : in std_logic_vector(17 downto 0);
cmd_control : in std_logic_vector(17 downto 0);
compen : in std_logic;
compupd : in std_logic
);
end component;
component ut90nhbd_ddr_phy_wo_pads is
generic (
MHz: integer := 100;
abits: integer := 15;
dbits: integer := 96;
nclk: integer := 3;
ncs: integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_ulogic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component generic_lpddr2phy_wo_pads is
generic (
tech : integer := 0;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- clkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
end;
| gpl-2.0 | 1332af6567d58a17fe2064f1f3bec4fb | 0.538022 | 3.302043 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_exdes.vhd | 1 | 4,384 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END blk_mem_gen_v7_3_exdes;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_v7_3 IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : blk_mem_gen_v7_3
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | b471706d8ade54a2eb26352ea2290276 | 0.574818 | 4.629356 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/image_filter_AXIvideo2Mat.vhd | 2 | 38,251 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_AXIvideo2Mat is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of image_filter_AXIvideo2Mat is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_ST_pp1_stg0_fsm_4 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_ST_st7_fsm_5 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_ST_st8_fsm_6 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_true : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_26 : BOOLEAN;
signal eol_1_reg_184 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_reg_195 : STD_LOGIC_VECTOR (31 downto 0);
signal p_1_reg_206 : STD_LOGIC_VECTOR (11 downto 0);
signal eol_reg_217 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V_2_reg_229 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_s_reg_241 : STD_LOGIC_VECTOR (31 downto 0);
signal eol_2_reg_253 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_75 : BOOLEAN;
signal tmp_data_V_reg_402 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_87 : BOOLEAN;
signal tmp_last_V_reg_410 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond1_fu_319_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_101 : BOOLEAN;
signal i_V_fu_324_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal i_V_reg_426 : STD_LOGIC_VECTOR (11 downto 0);
signal exitcond2_fu_330_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_reg_431 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp1_stg0_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_112 : BOOLEAN;
signal brmerge_fu_344_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_120 : BOOLEAN;
signal ap_reg_ppiten_pp1_it0 : STD_LOGIC := '0';
signal ap_sig_bdd_133 : BOOLEAN;
signal ap_reg_ppiten_pp1_it1 : STD_LOGIC := '0';
signal j_V_fu_335_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_10_fu_363_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_reg_444 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_5_reg_449 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_reg_454 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st7_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_158 : BOOLEAN;
signal ap_sig_bdd_163 : BOOLEAN;
signal axi_last_V_3_reg_264 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V1_reg_153 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st8_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_181 : BOOLEAN;
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_188 : BOOLEAN;
signal axi_data_V_3_reg_276 : STD_LOGIC_VECTOR (31 downto 0);
signal axi_data_V1_reg_163 : STD_LOGIC_VECTOR (31 downto 0);
signal p_s_reg_173 : STD_LOGIC_VECTOR (11 downto 0);
signal eol_1_phi_fu_187_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_phi_fu_198_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal eol_phi_fu_221_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_s_phi_fu_245_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_eol_2_reg_253pp1_it0 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V_1_mux_fu_356_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal eol_3_reg_288 : STD_LOGIC_VECTOR (0 downto 0);
signal sof_1_fu_98 : STD_LOGIC_VECTOR (0 downto 0);
signal not_sof_2_fu_350_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_user_V_fu_310_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (6 downto 0);
signal ap_sig_bdd_119 : BOOLEAN;
signal ap_sig_bdd_211 : BOOLEAN;
signal ap_sig_bdd_144 : BOOLEAN;
signal ap_sig_bdd_229 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((exitcond1_fu_319_p2 = ap_const_lv1_0)))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp1_it0 assign process. --
ap_reg_ppiten_pp1_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp1_it1 assign process. --
ap_reg_ppiten_pp1_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- axi_data_V1_reg_163 assign process. --
axi_data_V1_reg_163_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
axi_data_V1_reg_163 <= tmp_data_V_reg_402;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_6)) then
axi_data_V1_reg_163 <= axi_data_V_3_reg_276;
end if;
end if;
end process;
-- axi_data_V_1_reg_195 assign process. --
axi_data_V_1_reg_195_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
axi_data_V_1_reg_195 <= p_Val2_s_reg_241;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
axi_data_V_1_reg_195 <= axi_data_V1_reg_163;
end if;
end if;
end process;
-- axi_data_V_3_reg_276 assign process. --
axi_data_V_3_reg_276_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
axi_data_V_3_reg_276 <= axi_data_V_1_phi_fu_198_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
axi_data_V_3_reg_276 <= INPUT_STREAM_TDATA;
end if;
end if;
end process;
-- axi_last_V1_reg_153 assign process. --
axi_last_V1_reg_153_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
axi_last_V1_reg_153 <= tmp_last_V_reg_410;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_6)) then
axi_last_V1_reg_153 <= axi_last_V_3_reg_264;
end if;
end if;
end process;
-- axi_last_V_2_reg_229 assign process. --
axi_last_V_2_reg_229_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_144) then
if (ap_sig_bdd_211) then
axi_last_V_2_reg_229 <= eol_1_phi_fu_187_p4;
elsif (ap_sig_bdd_119) then
axi_last_V_2_reg_229 <= INPUT_STREAM_TLAST;
elsif ((ap_true = ap_true)) then
axi_last_V_2_reg_229 <= ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0;
end if;
end if;
end if;
end process;
-- axi_last_V_3_reg_264 assign process. --
axi_last_V_3_reg_264_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
axi_last_V_3_reg_264 <= eol_1_phi_fu_187_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
axi_last_V_3_reg_264 <= INPUT_STREAM_TLAST;
end if;
end if;
end process;
-- eol_1_reg_184 assign process. --
eol_1_reg_184_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
eol_1_reg_184 <= axi_last_V_2_reg_229;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
eol_1_reg_184 <= axi_last_V1_reg_153;
end if;
end if;
end process;
-- eol_2_reg_253 assign process. --
eol_2_reg_253_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_144) then
if (ap_sig_bdd_211) then
eol_2_reg_253 <= axi_last_V_1_mux_fu_356_p2;
elsif (ap_sig_bdd_119) then
eol_2_reg_253 <= INPUT_STREAM_TLAST;
elsif ((ap_true = ap_true)) then
eol_2_reg_253 <= ap_reg_phiprechg_eol_2_reg_253pp1_it0;
end if;
end if;
end if;
end process;
-- eol_3_reg_288 assign process. --
eol_3_reg_288_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
eol_3_reg_288 <= eol_phi_fu_221_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
eol_3_reg_288 <= INPUT_STREAM_TLAST;
end if;
end if;
end process;
-- eol_reg_217 assign process. --
eol_reg_217_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
eol_reg_217 <= eol_2_reg_253;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
eol_reg_217 <= ap_const_lv1_0;
end if;
end if;
end process;
-- p_1_reg_206 assign process. --
p_1_reg_206_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
p_1_reg_206 <= j_V_fu_335_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
p_1_reg_206 <= ap_const_lv12_0;
end if;
end if;
end process;
-- p_Val2_s_reg_241 assign process. --
p_Val2_s_reg_241_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_144) then
if (ap_sig_bdd_211) then
p_Val2_s_reg_241 <= axi_data_V_1_phi_fu_198_p4;
elsif (ap_sig_bdd_119) then
p_Val2_s_reg_241 <= INPUT_STREAM_TDATA;
elsif ((ap_true = ap_true)) then
p_Val2_s_reg_241 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end if;
end if;
end if;
end process;
-- p_s_reg_173 assign process. --
p_s_reg_173_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
p_s_reg_173 <= ap_const_lv12_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_6)) then
p_s_reg_173 <= i_V_reg_426;
end if;
end if;
end process;
-- sof_1_fu_98 assign process. --
sof_1_fu_98_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
sof_1_fu_98 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
sof_1_fu_98 <= ap_const_lv1_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
exitcond2_reg_431 <= exitcond2_fu_330_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
i_V_reg_426 <= i_V_fu_324_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
tmp_10_reg_444 <= tmp_10_fu_363_p1;
tmp_5_reg_449 <= p_Val2_s_phi_fu_245_p4(15 downto 8);
tmp_6_reg_454 <= p_Val2_s_phi_fu_245_p4(23 downto 16);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((INPUT_STREAM_TVALID = ap_const_logic_0)))) then
tmp_data_V_reg_402 <= INPUT_STREAM_TDATA;
tmp_last_V_reg_410 <= INPUT_STREAM_TLAST;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, INPUT_STREAM_TVALID, ap_sig_bdd_75, exitcond1_fu_319_p2, exitcond2_fu_330_p2, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1, ap_sig_bdd_163, eol_3_reg_288, tmp_user_V_fu_310_p1)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_75)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((not((INPUT_STREAM_TVALID = ap_const_logic_0)) and (ap_const_lv1_0 = tmp_user_V_fu_310_p1))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not((INPUT_STREAM_TVALID = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_user_V_fu_310_p1)))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
if (not((exitcond1_fu_319_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_4;
end if;
when ap_ST_pp1_stg0_fsm_4 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0))))) then
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_4;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st7_fsm_5;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_4;
end if;
when ap_ST_st7_fsm_5 =>
if (((ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
ap_NS_fsm <= ap_ST_st7_fsm_5;
elsif ((not(ap_sig_bdd_163) and not((ap_const_lv1_0 = eol_3_reg_288)))) then
ap_NS_fsm <= ap_ST_st8_fsm_6;
else
ap_NS_fsm <= ap_ST_st7_fsm_5;
end if;
when ap_ST_st8_fsm_6 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when others =>
ap_NS_fsm <= "XXXXXXX";
end case;
end process;
-- INPUT_STREAM_TREADY assign process. --
INPUT_STREAM_TREADY_assign_proc : process(INPUT_STREAM_TVALID, ap_sig_cseq_ST_st2_fsm_1, exitcond2_fu_330_p2, ap_sig_cseq_ST_pp1_stg0_fsm_4, brmerge_fu_344_p2, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1, ap_sig_cseq_ST_st7_fsm_5, ap_sig_bdd_163, eol_3_reg_288)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((INPUT_STREAM_TVALID = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = brmerge_fu_344_p2) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))))))) then
INPUT_STREAM_TREADY <= ap_const_logic_1;
else
INPUT_STREAM_TREADY <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, exitcond1_fu_319_p2, ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((exitcond1_fu_319_p2 = ap_const_lv1_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(exitcond1_fu_319_p2, ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((exitcond1_fu_319_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0 <= "X";
ap_reg_phiprechg_eol_2_reg_253pp1_it0 <= "X";
ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
-- ap_sig_bdd_101 assign process. --
ap_sig_bdd_101_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_101 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_112 assign process. --
ap_sig_bdd_112_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_112 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_119 assign process. --
ap_sig_bdd_119_assign_proc : process(exitcond2_fu_330_p2, brmerge_fu_344_p2)
begin
ap_sig_bdd_119 <= ((exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = brmerge_fu_344_p2));
end process;
-- ap_sig_bdd_120 assign process. --
ap_sig_bdd_120_assign_proc : process(INPUT_STREAM_TVALID, exitcond2_fu_330_p2, brmerge_fu_344_p2)
begin
ap_sig_bdd_120 <= ((INPUT_STREAM_TVALID = ap_const_logic_0) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = brmerge_fu_344_p2));
end process;
-- ap_sig_bdd_133 assign process. --
ap_sig_bdd_133_assign_proc : process(img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, exitcond2_reg_431)
begin
ap_sig_bdd_133 <= (((img_data_stream_0_V_full_n = ap_const_logic_0) and (exitcond2_reg_431 = ap_const_lv1_0)) or ((exitcond2_reg_431 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond2_reg_431 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)));
end process;
-- ap_sig_bdd_144 assign process. --
ap_sig_bdd_144_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
ap_sig_bdd_144 <= ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))));
end process;
-- ap_sig_bdd_158 assign process. --
ap_sig_bdd_158_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_158 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_163 assign process. --
ap_sig_bdd_163_assign_proc : process(INPUT_STREAM_TVALID, eol_3_reg_288)
begin
ap_sig_bdd_163 <= ((INPUT_STREAM_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = eol_3_reg_288));
end process;
-- ap_sig_bdd_181 assign process. --
ap_sig_bdd_181_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_181 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_188 assign process. --
ap_sig_bdd_188_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_188 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_211 assign process. --
ap_sig_bdd_211_assign_proc : process(exitcond2_fu_330_p2, brmerge_fu_344_p2)
begin
ap_sig_bdd_211 <= ((exitcond2_fu_330_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = brmerge_fu_344_p2)));
end process;
-- ap_sig_bdd_229 assign process. --
ap_sig_bdd_229_assign_proc : process(exitcond2_fu_330_p2, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it0)
begin
ap_sig_bdd_229 <= ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0));
end process;
-- ap_sig_bdd_26 assign process. --
ap_sig_bdd_26_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_26 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_75 assign process. --
ap_sig_bdd_75_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_75 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_87 assign process. --
ap_sig_bdd_87_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_87 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_pp1_stg0_fsm_4 assign process. --
ap_sig_cseq_ST_pp1_stg0_fsm_4_assign_proc : process(ap_sig_bdd_112)
begin
if (ap_sig_bdd_112) then
ap_sig_cseq_ST_pp1_stg0_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp1_stg0_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_26)
begin
if (ap_sig_bdd_26) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_87)
begin
if (ap_sig_bdd_87) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_188)
begin
if (ap_sig_bdd_188) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_101)
begin
if (ap_sig_bdd_101) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_5 assign process. --
ap_sig_cseq_ST_st7_fsm_5_assign_proc : process(ap_sig_bdd_158)
begin
if (ap_sig_bdd_158) then
ap_sig_cseq_ST_st7_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_6 assign process. --
ap_sig_cseq_ST_st8_fsm_6_assign_proc : process(ap_sig_bdd_181)
begin
if (ap_sig_bdd_181) then
ap_sig_cseq_ST_st8_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- axi_data_V_1_phi_fu_198_p4 assign process. --
axi_data_V_1_phi_fu_198_p4_assign_proc : process(axi_data_V_1_reg_195, p_Val2_s_reg_241, exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))) then
axi_data_V_1_phi_fu_198_p4 <= p_Val2_s_reg_241;
else
axi_data_V_1_phi_fu_198_p4 <= axi_data_V_1_reg_195;
end if;
end process;
axi_last_V_1_mux_fu_356_p2 <= (eol_1_phi_fu_187_p4 or not_sof_2_fu_350_p2);
brmerge_fu_344_p2 <= (sof_1_fu_98 or eol_phi_fu_221_p4);
-- eol_1_phi_fu_187_p4 assign process. --
eol_1_phi_fu_187_p4_assign_proc : process(eol_1_reg_184, axi_last_V_2_reg_229, exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))) then
eol_1_phi_fu_187_p4 <= axi_last_V_2_reg_229;
else
eol_1_phi_fu_187_p4 <= eol_1_reg_184;
end if;
end process;
-- eol_phi_fu_221_p4 assign process. --
eol_phi_fu_221_p4_assign_proc : process(eol_reg_217, eol_2_reg_253, exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))) then
eol_phi_fu_221_p4 <= eol_2_reg_253;
else
eol_phi_fu_221_p4 <= eol_reg_217;
end if;
end process;
exitcond1_fu_319_p2 <= "1" when (p_s_reg_173 = img_rows_V_read) else "0";
exitcond2_fu_330_p2 <= "1" when (p_1_reg_206 = img_cols_V_read) else "0";
i_V_fu_324_p2 <= std_logic_vector(unsigned(p_s_reg_173) + unsigned(ap_const_lv12_1));
img_data_stream_0_V_din <= tmp_10_reg_444;
-- img_data_stream_0_V_write assign process. --
img_data_stream_0_V_write_assign_proc : process(exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
img_data_stream_0_V_write <= ap_const_logic_1;
else
img_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_1_V_din <= tmp_5_reg_449;
-- img_data_stream_1_V_write assign process. --
img_data_stream_1_V_write_assign_proc : process(exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
img_data_stream_1_V_write <= ap_const_logic_1;
else
img_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_2_V_din <= tmp_6_reg_454;
-- img_data_stream_2_V_write assign process. --
img_data_stream_2_V_write_assign_proc : process(exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
img_data_stream_2_V_write <= ap_const_logic_1;
else
img_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
j_V_fu_335_p2 <= std_logic_vector(unsigned(p_1_reg_206) + unsigned(ap_const_lv12_1));
not_sof_2_fu_350_p2 <= (sof_1_fu_98 xor ap_const_lv1_1);
-- p_Val2_s_phi_fu_245_p4 assign process. --
p_Val2_s_phi_fu_245_p4_assign_proc : process(INPUT_STREAM_TDATA, brmerge_fu_344_p2, axi_data_V_1_phi_fu_198_p4, ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0, ap_sig_bdd_229)
begin
if (ap_sig_bdd_229) then
if (not((ap_const_lv1_0 = brmerge_fu_344_p2))) then
p_Val2_s_phi_fu_245_p4 <= axi_data_V_1_phi_fu_198_p4;
elsif ((ap_const_lv1_0 = brmerge_fu_344_p2)) then
p_Val2_s_phi_fu_245_p4 <= INPUT_STREAM_TDATA;
else
p_Val2_s_phi_fu_245_p4 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end if;
else
p_Val2_s_phi_fu_245_p4 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end if;
end process;
tmp_10_fu_363_p1 <= p_Val2_s_phi_fu_245_p4(8 - 1 downto 0);
tmp_user_V_fu_310_p1 <= INPUT_STREAM_TUSER;
end behav;
| gpl-3.0 | a8910b15489202371db80970f8053059 | 0.581919 | 2.702105 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/jtag/jtagcom.vhd | 1 | 7,731 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: jtagcom
-- File: jtagcom.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Modified: J. Gaisler, K. Glembo, J. Andersson - Aeroflex Gaisler
-- Description: JTAG Debug Interface with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libjtagcom.all;
use gaisler.misc.all;
entity jtagcom is
generic (
isel : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
reread : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tck : in std_ulogic;
trst : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of jtagcom is
constant ADDBITS : integer := 10;
constant NOCMP : boolean := (isel /= 0);
type state_type is (shft, ahb, nxt_shft);
type reg_type is record
addr : std_logic_vector(34 downto 0);
data : std_logic_vector(32 downto 0);
state : state_type;
tcktog: std_logic_vector(nsync-1 downto 0);
tcktog2: std_ulogic;
tdishft: std_ulogic;
trst : std_logic_vector(nsync-1 downto 0);
tdi : std_logic_vector(nsync-1 downto 0);
shift : std_logic_vector(nsync-1 downto 0);
shift2: std_ulogic;
upd : std_logic_vector(nsync-1 downto 0);
upd2 : std_ulogic;
asel : std_logic_vector(nsync-1 downto 0);
dsel : std_logic_vector(nsync-1 downto 0);
seq : std_ulogic;
holdn : std_ulogic;
end record;
type tckreg_type is record
tcktog: std_ulogic;
tdi: std_ulogic;
tdor: std_ulogic;
end record;
signal nexttdo: std_ulogic;
signal r, rin : reg_type;
signal tr: tckreg_type;
begin
comb : process (rst, r, tapo, dmao, tr)
variable v : reg_type;
variable redge0 : std_ulogic;
variable vdmai : ahb_dma_in_type;
variable asel, dsel : std_ulogic;
variable vtapi : tap_in_type;
variable write, seq : std_ulogic;
variable vnexttdo: std_ulogic;
begin
v := r;
if NOCMP then
asel := tapo.asel; dsel := tapo.dsel;
else
if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if;
if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if;
end if;
vtapi.en := asel or dsel;
vnexttdo := '0';
if asel='1' then
if tapo.shift='1' then
vnexttdo := r.addr(1);
else
vnexttdo := r.addr(0);
end if;
else
if tapo.shift='1' then
vnexttdo := r.data(1);
else
vnexttdo := r.data(0);
end if;
if reread /= 0 then vnexttdo := vnexttdo and r.holdn; end if;
end if;
nexttdo <= vnexttdo;
vtapi.tdo := tr.tdor;
write := r.addr(34); seq := r.seq;
v.tcktog(0) := r.tcktog(nsync-1); v.tcktog(nsync-1) := tr.tcktog;
v.tcktog2 := r.tcktog(0); v.shift2 := r.shift(0);
v.trst(0) := r.trst(nsync-1); v.trst(nsync-1) := tapo.reset;
v.tdi(0) := r.tdi(nsync-1); v.tdi(nsync-1) := tr.tdi;
v.shift(0) := r.shift(nsync-1); v.shift(nsync-1) := tapo.shift;
v.upd(0) := r.upd(nsync-1); v.upd(nsync-1) := tapo.upd;
v.upd2 := r.upd(0);
v.asel(0) := r.asel(nsync-1); v.asel(nsync-1) := asel;
v.dsel(0) := r.dsel(nsync-1); v.dsel(nsync-1) := dsel;
redge0 := r.tcktog2 xor r.tcktog(0);
v.tdishft := '0';
vdmai.address := r.addr(31 downto 0); vdmai.wdata := ahbdrivedata(r.data(31 downto 0));
vdmai.start := '0'; vdmai.burst := '0'; vdmai.write := write;
vdmai.busy := '0'; vdmai.irq := '0'; vdmai.size := '0' & r.addr(33 downto 32);
case r.state is
when shft =>
if (r.asel(0) or r.dsel(0)) = '1' then
if r.shift2 = '1' then
if redge0 = '1' then
if r.asel(0) = '1' then v.addr(33 downto 0) := r.addr(34 downto 1); end if;
if r.dsel(0) = '1' then v.data(31 downto 0) := r.data(32 downto 1); end if;
v.tdishft := '1'; -- Shift in TDI next AHB cycle
end if;
elsif r.upd2 = '1' then
if reread /= 0 then
v.data(32) := '0'; -- Transfer not done
end if;
if (r.asel(0) and not write) = '1' then v.state := ahb; end if;
if (r.dsel(0) and (write or (not write and seq))) = '1' then -- data register
v.state := ahb;
if (seq and not write) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
end if;
end if;
if r.tdishft='1' then
if r.asel(0)='1' then v.addr(34):=r.tdi(0); end if;
if r.dsel(0)='1' then v.data(32):=r.tdi(0); v.seq:=r.tdi(0); end if;
end if;
if reread /= 0 then v.holdn := '1'; end if;
vdmai.size := "000";
when ahb =>
if reread /= 0 and r.shift2 = '1' then v.holdn := '0'; end if;
if dmao.active = '1' then
if dmao.ready = '1' then
v.data(31 downto 0) := ahbreadword(dmao.rdata);
v.state := nxt_shft;
if reread /= 0 then
v.data(32) := '1'; -- Transfer done
end if;
if (write and seq) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
else
vdmai.start := '1';
end if;
when nxt_shft =>
if reread /= 0 then
v.holdn := (r.holdn or r.upd2) and not r.shift2;
if r.upd2 = '0' and r.shift2 = '0' and r.holdn = '1' then v.state := shft; end if;
else
if r.upd2 = '0' then v.state := shft; end if;
end if;
end case;
if (rst = '0') or (r.trst(0) = '1') then
v.state := shft; v.addr := (others => '0'); v.seq := '0';
end if;
if reread = 0 then v.holdn := '0'; end if;
rin <= v; dmai <= vdmai; tapi <= vtapi;
end process;
reg : process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
tckreg: process (tck,trst)
begin
if rising_edge(tck) then
tr.tcktog <= not tr.tcktog;
tr.tdi <= tapo.tdi;
tr.tdor <= nexttdo;
end if;
if trst='0' then
tr.tcktog <= '0';
tr.tdi <= '0';
tr.tdor <= '0';
end if;
end process;
end;
| gpl-2.0 | 3ca9bc9c4c54b46459ab60e7512d4734 | 0.546889 | 3.284197 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/FIFO_image_filter_img_1_cols_V.vhd | 4 | 4,564 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_cols_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_img_1_cols_V_shiftReg;
architecture rtl of FIFO_image_filter_img_1_cols_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_img_1_cols_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_img_1_cols_V is
component FIFO_image_filter_img_1_cols_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_img_1_cols_V_shiftReg : FIFO_image_filter_img_1_cols_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | e9e8cc120de13dd5a0cda18b9ff1a64a | 0.534619 | 3.483969 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-asic/spw_lvttl_pads.vhd | 1 | 4,432 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (C) 2009-2013, Aeroflex Gaisler AB
-------------------------------------------------------------------------------
-- Entity: spw_2x_lvttl_pads
-- File: spw_2x_lvttl_pads.vhd
-- Author: Marko Isomaki, Aeroflex Gaisler
-- Contact: [email protected]
-- Description: pads for SpW signals in router ASIC LVTTL ports
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.config.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.conv_std_logic;
entity spw_lvttl_pads is
generic (
padtech : integer := 0;
oepol : integer := 0;
level : integer := 0;
voltage : integer := 0;
filter : integer := 0;
strength : integer := 4;
slew : integer := 0;
input_type : integer := 0
);
port (
---------------------------------------------------------------------------
-- Signals going off-chip
---------------------------------------------------------------------------
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
---------------------------------------------------------------------------
-- Signals to core
---------------------------------------------------------------------------
lspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1)
);
end entity;
architecture rtl of spw_lvttl_pads is
begin
------------------------------------------------------------------------------
-- SpW port pads
------------------------------------------------------------------------------
spw_pads : for i in 0 to CFG_SPW_NUM-1 generate
spw_pad_input: if input_type <= 3 generate
spw_rxd_pad : inpad
generic map (
tech => padtech,
level => level,
voltage => voltage,
filter => filter,
strength => strength)
port map (
pad => spw_rxd(i),
o => lspw_rxd(i));
spw_rxs_pad : inpad
generic map (
tech => padtech,
level => level,
voltage => voltage,
filter => filter,
strength => strength)
port map (
pad => spw_rxs(i),
o => lspw_rxs(i));
end generate;
spw_no_pad_input: if input_type >= 4 generate
lspw_rxd(i) <= spw_rxd(i);
lspw_rxs(i) <= spw_rxs(i);
end generate;
spw_txd_pad : outpad
generic map (
tech => padtech,
level => level,
slew => slew,
voltage => voltage,
strength => strength)
port map (
pad => spw_txd(i),
i => lspw_txd(i));
spw_txs_pad : outpad
generic map (
tech => padtech,
level => level,
slew => slew,
voltage => voltage,
strength => strength)
port map (
pad => spw_txs(i),
i => lspw_txs(i));
end generate;
end;
| gpl-2.0 | a17bcbfcbedeac2ea8c13ccb3f6a7533 | 0.471345 | 4.286267 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep1c20/config.vhd | 1 | 5,576 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := altera;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1;
constant CFG_ATBSZ : integer := 1;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#000F#;
constant CFG_GRGPIO_WIDTH : integer := (2);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 452467e5173242732244fb506462ea86 | 0.644548 | 3.670836 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml50x/testbench.vhd | 1 | 11,356 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
library hynix;
use hynix.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal bus_error : std_logic_vector (1 downto 0);
signal sram_flash_addr : std_logic_vector(23 downto 0);
signal address : std_logic_vector(24 downto 0);
signal sram_flash_data, data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_oen : std_ulogic;
signal flash_oen : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_cen : std_logic;
signal flash_adv_n : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic_vector(1 downto 0);
signal ddr_clkb : std_logic_vector(1 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqsp : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1+CFG_DDR2SP downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
signal ddr_dq2 : std_logic_vector (63 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal txd2 : std_ulogic; -- UART2 tx data
signal rxd2 : std_ulogic; -- UART2 rx data
signal gpio : std_logic_vector(12 downto 0); -- I/O port
signal led : std_logic_vector(12 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_int : std_ulogic := '0';
signal phy_gtx_clk : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal usb_csn, usb_rstn : std_logic;
signal iic_scl_main, iic_sda_main : std_logic;
signal iic_scl_video, iic_sda_video : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_logic;
signal tft_lcd_clk_n : std_logic;
signal tft_lcd_hsync : std_logic;
signal tft_lcd_vsync : std_logic;
signal tft_lcd_de : std_logic;
signal tft_lcd_reset_b : std_logic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(15 downto 0);
--pcie--
signal cor_sys_reset_n : std_logic := '1';
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
signal rp_sys_clk : std_logic;
signal cor_pci_exp_txn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0');
signal cor_pci_exp_txp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0');
signal cor_pci_exp_rxn : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0');
signal cor_pci_exp_rxp : std_logic_vector(CFG_NO_OF_LANES-1 downto 0) := (others => '0');
--pcie end--
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk_200_p : std_ulogic := '0';
signal clk_200_n : std_ulogic := '1';
signal clk_33 : std_ulogic := '0';
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
clk_200_p <= not clk_200_p after 2.5 ns;
clk_200_n <= not clk_200_n after 2.5 ns;
clk_33 <= not clk_33 after 15 ns;
rxd1 <= 'H'; gpio(11) <= 'L';
sram_clk_fb <= sram_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl_main <= 'H'; iic_sda_main <= 'H';
iic_scl_video <= 'H'; iic_sda_video <= 'H';
sysace_d <= (others => 'H'); sysace_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, clk_200_p, clk_200_n, clk_33, sram_flash_addr,
sram_flash_data, sram_cen, sram_bw, sram_oen, sram_flash_we_n,
flash_cen, flash_oen, flash_adv_n,sram_clk, sram_clk_fb, sram_mode,
sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, txd2, rxd2, gpio, led, bus_error,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_int,
ps2_keyb_clk, ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data,
usb_csn, usb_rstn,
iic_scl_main, iic_sda_main,
iic_scl_video, iic_sda_video,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_d, cor_pci_exp_txp, cor_pci_exp_txn, cor_pci_exp_rxp,
cor_pci_exp_rxn, ep_sys_clk_p, ep_sys_clk_n, cor_sys_reset_n
);
ddr2mem: for i in 0 to 3 generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => true, PUSCheckFlag => false,
index => 3-i, fname => sdramfile, fdelay => 100*CFG_MIG_DDR2)
port map (DQ => ddr_dq2(i*16+15 downto i*16), LDQS => ddr_dqsp(i*2),
LDQSB => ddr_dqsn(i*2), UDQS => ddr_dqsp(i*2+1),
UDQSB => ddr_dqsn(i*2+1), LDM => ddr_dm(i*2),
WEB => ddr_web, CASB => ddr_casb, RASB => ddr_rasb, CSB => ddr_csb(0),
BA => ddr_ba(1 downto 0), ADDR => ddr_ad(12 downto 0), CKE => ddr_cke(0),
CLK => ddr_clk(0), CLKB => ddr_clkb(0), UDM => ddr_dm(i*2+1));
end generate;
nodqdel : if (CFG_MIG_DDR2 = 1) generate
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 0.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
dqdel : if (CFG_MIG_DDR2 = 0) generate
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 2.5)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
sram01 : for i in 0 to 1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(15-i*8 downto 8-i*8),
sram_cen, sram_bw(i+2), sram_oen);
end generate;
sram23 : for i in 2 to 3 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(47-i*8 downto 40-i*8),
sram_cen, sram_bw(i-2), sram_oen);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(15 downto 0),
gnd, gnd, flash_cen, sram_flash_we_n, flash_oen);
phy_mii_data <= 'H';
p0: phy
generic map (address => 7)
port map(phy_rst_n, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl_main, iic_sda_main);
iuerr : process
begin
wait for 5000 ns;
if to_x01(bus_error(0)) = '0' then wait on bus_error; end if;
assert (to_x01(bus_error(0)) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= sram_flash_data(15 downto 0) & sram_flash_data(31 downto 16);
address <= sram_flash_addr & '0';
test0 : grtestmod
port map ( sys_rst_in, sys_clk, bus_error(0), sram_flash_addr(20 downto 1), data,
iosn, flash_oen, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
-- ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
data <= buskeep(data), (others => 'H') after 250 ns;
end ;
| gpl-2.0 | 02d5af8827eee6ff1f07b1821890ddf6 | 0.62522 | 2.965787 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/gr1553b/gr1553b_pkg.vhd | 1 | 15,843 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: gr1553b_pkg
-- File: gr1553b_pkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Package for GR1553B top-level component and user-visible types
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.ahb_mst_in_type;
use grlib.amba.ahb_mst_out_type;
use grlib.amba.apb_slv_in_type;
use grlib.amba.apb_slv_out_type;
library techmap;
use techmap.gencomp.all;
package gr1553b_pkg is
constant gr1553b_version: integer := 0;
constant gr1553b_cfgver: integer := 0;
-----------------------------------------------------------------------------
-- Types and top level component
type gr1553b_txout_type is record
busA_txP: std_logic;
busA_txN: std_logic;
busA_txen: std_logic;
busA_rxen: std_logic;
busB_txP: std_logic;
busB_txN: std_logic;
busB_txen: std_logic;
busB_rxen: std_logic;
-- For convenience, inverted versions of txen
busA_txin: std_logic;
busB_txin: std_logic;
end record;
type gr1553b_rxin_type is record
busA_rxP: std_logic;
busA_rxN: std_logic;
busB_rxP: std_logic;
busB_rxN: std_logic;
end record;
type gr1553b_auxin_type is record
extsync: std_logic;
rtaddr: std_logic_vector(4 downto 0);
rtpar: std_logic;
end record;
type gr1553b_auxout_type is record
rtsync: std_logic;
busreset: std_logic;
validcmdA: std_logic;
validcmdB: std_logic;
timedoutA: std_logic;
timedoutB: std_logic;
badreg: std_logic;
irqvec: std_logic_vector(7 downto 0);
end record;
constant gr1553b_rxin_zero: gr1553b_rxin_type :=
(busA_rxP=>'0', busA_rxN=>'0', busB_rxP=>'0', busB_rxN=>'0');
constant gr1553b_txout_zero: gr1553b_txout_type :=
('0','0','0','0','0','0','0','0','1','1');
constant gr1553b_auxin_zero: gr1553b_auxin_type :=
(extsync => '0', rtaddr => "00000", rtpar => '0');
constant gr1553b_auxout_zero: gr1553b_auxout_type :=
('0','0','0','0','0','0','0',x"00");
constant gr1553b_rxin_none: gr1553b_rxin_type := gr1553b_rxin_zero;
constant gr1553b_txout_none: gr1553b_txout_type := gr1553b_txout_zero;
constant gr1553b_auxin_none: gr1553b_auxin_type := gr1553b_auxin_zero;
constant gr1553b_auxout_none: gr1553b_auxout_type := gr1553b_auxout_zero;
component gr1553b is
generic(
hindex: integer := 0;
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer range 0 to 1 := 0;
bm_filters: integer range 0 to 1 := 1;
codecfreq: integer := 20;
sameclk: integer range 0 to 1 := 0
);
port(
clk: in std_logic;
rst: in std_logic;
ahbmi: in ahb_mst_in_type;
ahbmo: out ahb_mst_out_type;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
auxin: in gr1553b_auxin_type;
auxout: out gr1553b_auxout_type;
codec_clk: in std_logic;
codec_rst: in std_logic;
txout: out gr1553b_txout_type;
txout_fb: in gr1553b_txout_type;
rxin: in gr1553b_rxin_type
);
end component;
-----------------------------------------------------------------------------
-- Pads convenience component
component gr1553b_pads is
generic (
padtech: integer;
outen_pol: integer range 0 to 1;
level: integer := ttl;
slew: integer := 0;
voltage: integer := x33v;
strength: integer := 12;
filter: integer := 0
);
port (
txout: in gr1553b_txout_type;
rxin: out gr1553b_rxin_type;
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaoutenin : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busboutenin : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Wrappers for netlists etc.
component gr1553b_stdlogic is
generic (
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer range 0 to 1 := 0
);
port (
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
-- AHB interface
mi_hgrant : in std_logic; -- bus grant
mi_hready : in std_ulogic; -- transfer done
mi_hresp : in std_logic_vector(1 downto 0); -- response type
mi_hrdata : in std_logic_vector(31 downto 0); -- read data bus
mo_hbusreq: out std_ulogic; -- bus request
mo_htrans : out std_logic_vector(1 downto 0); -- transfer type
mo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
mo_hwrite : out std_ulogic; -- read/write
mo_hsize : out std_logic_vector(2 downto 0); -- transfer size
mo_hburst : out std_logic_vector(2 downto 0); -- burst type
mo_hwdata : out std_logic_vector(31 downto 0); -- write data bus
-- APB interface
si_psel : in std_logic; -- slave select
si_penable: in std_ulogic; -- strobe
si_paddr : in std_logic_vector(7 downto 0); -- address bus (byte addr)
si_pwrite : in std_ulogic; -- write
si_pwdata : in std_logic_vector(31 downto 0); -- write data bus
so_prdata : out std_logic_vector(31 downto 0); -- read data bus
so_pirq : out std_logic; -- interrupt bus
-- Aux signals
bcsync : in std_logic;
rtsync : out std_logic;
busreset : out std_logic;
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_logic;
-- 1553 transceiver interface
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaouten : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busbouten : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end component;
component gr1553b_nlw is
generic(
tech: integer := 0;
hindex: integer := 0;
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1
);
port(
clk: in std_logic;
rst: in std_logic;
ahbmi: in ahb_mst_in_type;
ahbmo: out ahb_mst_out_type;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
auxin: in gr1553b_auxin_type;
auxout: out gr1553b_auxout_type;
codec_clk: in std_logic;
codec_rst: in std_logic;
txout: out gr1553b_txout_type;
txout_fb: in gr1553b_txout_type;
rxin: in gr1553b_rxin_type
);
end component;
-----------------------------------------------------------------------------
-- APB Register definitions
constant REG_IRQSTATUS: std_logic_vector := x"00";
constant REG_IRQENABLE: std_logic_vector := x"04";
constant REG_BCSTATUS: std_logic_vector := x"40";
constant REG_BCACTION: std_logic_vector := x"44";
constant REG_BCSCHEMADDR: std_logic_vector := x"48";
constant REG_BCASYNCADDR: std_logic_vector := x"4C";
constant REG_BCTIME: std_logic_vector := x"50";
constant REG_BCWAKEUP: std_logic_vector := x"54";
constant REG_BCIRQSRC: std_logic_vector := x"58";
constant REG_BCRTBUSMASK: std_logic_vector := x"5C";
constant REG_BCSCHEMSLOT: std_logic_vector := x"68";
constant REG_BCASYNCSLOT: std_logic_vector := x"6C";
constant REG_RTSTATUS: std_logic_vector := x"80";
constant REG_RTCONFIG: std_logic_vector := x"84";
constant REG_RTBUSSTAT: std_logic_vector := x"88";
constant REG_RTBUSWORDS: std_logic_vector := x"8C";
constant REG_RTSYNC: std_logic_vector := x"90";
constant REG_RTTABLEADDR: std_logic_vector := x"94";
constant REG_RTMODECONFIG: std_logic_vector := x"98";
constant REG_RTTIMETAG: std_logic_vector := x"A4";
constant REG_RTLOGMASK: std_logic_vector := x"AC";
constant REG_RTLOGPOS: std_logic_vector := x"B0";
constant REG_RTIRQSRC: std_logic_vector := x"B4";
constant REG_BMSTATUS: std_logic_vector := x"C0";
constant REG_BMCONFIG: std_logic_vector := x"C4";
constant REG_BMADDRFILT: std_logic_vector := x"C8";
constant REG_BMSAFILT: std_logic_vector := x"CC";
constant REG_BMMCFILT: std_logic_vector := x"D0";
constant REG_BMBUFSTART: std_logic_vector := x"D4";
constant REG_BMBUFEND: std_logic_vector := x"D8";
constant REG_BMBUFPOS: std_logic_vector := x"DC";
constant REG_BMTIMETAG: std_logic_vector := x"E0";
-----------------------------------------------------------------------------
-- Embedded RT core
component grrt is
generic (
codecfreq: integer := 20;
sameclk : integer := 1;
syncrst : integer range 0 to 1 := 1
);
port (
-- Clock and reset
clk : in std_ulogic;
rst : in std_ulogic;
clk1553 : in std_ulogic;
rst1553 : in std_ulogic;
-- Control signals
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_ulogic;
rtstat : in std_logic_vector(3 downto 0); -- 3=SR, 2=busy 1=SSF 0=TF
ad31en : in std_ulogic; -- 1=RT31 is normal addr, 0=RT31 is broadcast
rtsync : out std_ulogic;
rtreset : out std_ulogic;
stamp : out std_ulogic;
-- Front-end interface
phase : out std_logic_vector(1 downto 0);
transfer : out std_logic_vector(11 downto 0);
resp : in std_logic_vector(1 downto 0);
tfrerror : out std_ulogic;
txdata : in std_logic_vector(15 downto 0);
rxdata : out std_logic_vector(15 downto 0);
datardy : in std_ulogic;
datarw : out std_ulogic;
-- 1553 transceiver interface
aoutin : out std_ulogic;
aoutp : out std_ulogic;
aoutn : out std_ulogic;
ainen : out std_ulogic;
ainp : in std_ulogic;
ainn : in std_ulogic;
boutin : out std_ulogic;
boutp : out std_ulogic;
boutn : out std_ulogic;
binen : out std_ulogic;
binp : in std_ulogic;
binn : in std_ulogic;
-- Fail-safe timer feedback
aoutp_fb : in std_logic;
aoutn_fb : in std_logic;
boutp_fb : in std_logic;
boutn_fb : in std_logic
);
end component;
-----------------------------------------------------------------------------
-- Test signal generators
component gr1553b_tgapb is
generic(
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
codecfreq: integer := 20;
extmodeen: integer range 0 to 1 := 0;
rawmodeen: integer range 0 to 1 := 0;
rawmemtech: integer := 0
);
port(
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
txout_core: in gr1553b_txout_type;
rxin_core: out gr1553b_rxin_type;
txout_bus: out gr1553b_txout_type;
rxin_bus: in gr1553b_rxin_type;
testing: out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Simulation types and components for test bench
-- U=Undefined, X=Unknown, 0=Zero, +=High, -=Low
type uwire1553 is ('U','X','0','+','-');
type uwire1553_array is array(natural range <>) of uwire1553;
function resolved (a: uwire1553_array) return uwire1553;
subtype wire1553 is resolved uwire1553;
component simtrans1553_single is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
buswire: inout wire1553;
rxen: in std_logic;
txin: in std_logic;
txP: in std_logic;
txN: in std_logic;
rxP: out std_logic;
rxN: out std_logic
);
end component;
component simtrans1553 is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
busA: inout wire1553;
busB: inout wire1553;
rxenA: in std_logic;
txinA: in std_logic;
txAP: in std_logic;
txAN: in std_logic;
rxAP: out std_logic;
rxAN: out std_logic;
rxenB: in std_logic;
txinB: in std_logic;
txBP: in std_logic;
txBN: in std_logic;
rxBP: out std_logic;
rxBN: out std_logic
);
end component;
component combine1553 is
port (
clk: in std_ulogic;
txin1,rxen1: in std_ulogic;
tx1P,tx1N: in std_ulogic;
rx1P,rx1N: out std_ulogic;
txin2,rxen2: in std_ulogic;
tx2P,tx2N: in std_ulogic;
rx2P,rx2N: out std_ulogic;
txin,rxen: out std_ulogic;
txP,txN: out std_ulogic;
rxP,rxN: in std_ulogic
);
end component;
end package;
package body gr1553b_pkg is
function resolved (a: uwire1553_array) return uwire1553 is
variable w,w2: uwire1553;
begin
w := a(a'left);
for q in a'range loop
w2 := a(q);
if w /= w2 then
case w is
when 'U' => w := 'X';
when 'X' => null;
when '0' => w := w2;
when '+' | '-' => if w2 /= '0' then w:='X'; end if;
end case;
end if;
end loop;
return w;
end;
end package body;
| gpl-2.0 | a569aec7ec12ef198d0e0b492ee97b48 | 0.560689 | 3.491186 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_reg_module.vhd | 2 | 86,306 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reg_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 1 ;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 32 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
m_axi_sg_hrdresetn : in std_logic ; --
--
s_axi_lite_aclk : in std_logic ; --
axi_lite_reset_n : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
--
-- MM2S Signals --
mm2s_stop : in std_logic ; --
mm2s_halted_clr : in std_logic ; --
mm2s_halted_set : in std_logic ; --
mm2s_idle_set : in std_logic ; --
mm2s_idle_clr : in std_logic ; --
mm2s_dma_interr_set : in std_logic ; --
mm2s_dma_slverr_set : in std_logic ; --
mm2s_dma_decerr_set : in std_logic ; --
mm2s_ioc_irq_set : in std_logic ; --
mm2s_dly_irq_set : in std_logic ; --
mm2s_irqdelay_status : in std_logic_vector(7 downto 0) ; --
mm2s_irqthresh_status : in std_logic_vector(7 downto 0) ; --
mm2s_ftch_interr_set : in std_logic ; --
mm2s_ftch_slverr_set : in std_logic ; --
mm2s_ftch_decerr_set : in std_logic ; --
mm2s_updt_interr_set : in std_logic ; --
mm2s_updt_slverr_set : in std_logic ; --
mm2s_updt_decerr_set : in std_logic ; --
mm2s_new_curdesc_wren : in std_logic ; --
mm2s_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_dlyirq_dsble : out std_logic ; -- CR605888 --
mm2s_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
mm2s_irqthresh_wren : out std_logic ; --
mm2s_irqdelay_wren : out std_logic ; --
mm2s_tailpntr_updated : out std_logic ; --
mm2s_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_sa : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_length_wren : out std_logic ; --
--
-- S2MM Signals --
tdest_in : in std_logic_vector (6 downto 0) ;
same_tdest_in : in std_logic;
sg_ctl : out std_logic_vector (7 downto 0) ;
s2mm_sof : in std_logic ;
s2mm_eof : in std_logic ;
s2mm_stop : in std_logic ; --
s2mm_halted_clr : in std_logic ; --
s2mm_halted_set : in std_logic ; --
s2mm_idle_set : in std_logic ; --
s2mm_idle_clr : in std_logic ; --
s2mm_dma_interr_set : in std_logic ; --
s2mm_dma_slverr_set : in std_logic ; --
s2mm_dma_decerr_set : in std_logic ; --
s2mm_ioc_irq_set : in std_logic ; --
s2mm_dly_irq_set : in std_logic ; --
s2mm_irqdelay_status : in std_logic_vector(7 downto 0) ; --
s2mm_irqthresh_status : in std_logic_vector(7 downto 0) ; --
s2mm_ftch_interr_set : in std_logic ; --
s2mm_ftch_slverr_set : in std_logic ; --
s2mm_ftch_decerr_set : in std_logic ; --
s2mm_updt_interr_set : in std_logic ; --
s2mm_updt_slverr_set : in std_logic ; --
s2mm_updt_decerr_set : in std_logic ; --
s2mm_new_curdesc_wren : in std_logic ; --
s2mm_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_tvalid : in std_logic;
s2mm_dlyirq_dsble : out std_logic ; -- CR605888 --
s2mm_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
s2mm_irqthresh_wren : out std_logic ; --
s2mm_irqdelay_wren : out std_logic ; --
s2mm_tailpntr_updated : out std_logic ; --
s2mm_tvalid_latch : out std_logic ;
s2mm_tvalid_latch_del : out std_logic ;
s2mm_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_da : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : out std_logic ; --
s2mm_bytes_rcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : in std_logic ; --
--
soft_reset : out std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- Fetch/Update error addresses --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
bd_eq : in std_logic
);
end axi_dma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant LENGTH_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH - C_SG_LENGTH_WIDTH;
constant LENGTH_PAD : std_logic_vector(LENGTH_PAD_WIDTH-1 downto 0) := (others => '0');
constant ZERO_BYTES : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
constant NUM_REG_PER_S2MM_INT : integer := NUM_REG_PER_CHANNEL + (NUM_REG_PER_S2MM*C_ENABLE_MULTI_CHANNEL);
-- Specifies to axi_dma_register which block belongs to S2MM channel
-- so simple dma s2mm_da register offset can be correctly assigned
-- CR603034
--constant NOT_S2MM_CHANNEL : integer := 0;
--constant IS_S2MM_CHANNEL : integer := 1;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi2ip_wrce : std_logic_vector(23+(120*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_rdce : std_logic_vector(23+(120*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_error_in : std_logic := '0';
signal mm2s_error_out : std_logic := '0';
signal s2mm_curdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_curdesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int3 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_error_in : std_logic := '0';
signal s2mm_error_out : std_logic := '0';
signal read_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mm2s_introut_i_cdc_from : std_logic := '0';
signal mm2s_introut_d1_cdc_tig : std_logic := '0';
signal mm2s_introut_to : std_logic := '0';
signal s2mm_introut_i_cdc_from : std_logic := '0';
signal s2mm_introut_d1_cdc_tig : std_logic := '0';
signal s2mm_introut_to : std_logic := '0';
signal mm2s_sgctl : std_logic_vector (7 downto 0);
signal s2mm_sgctl : std_logic_vector (7 downto 0);
signal or_sgctl : std_logic_vector (7 downto 0);
signal open_window, wren : std_logic;
signal s2mm_tailpntr_updated_int : std_logic;
signal s2mm_tailpntr_updated_int1 : std_logic;
signal s2mm_tailpntr_updated_int2 : std_logic;
signal s2mm_tailpntr_updated_int3 : std_logic;
signal tvalid_int : std_logic;
signal tvalid_int1 : std_logic;
signal tvalid_int2 : std_logic;
signal new_tdest : std_logic;
signal tvalid_latch : std_logic;
signal tdest_changed : std_logic;
signal tdest_fix : std_logic_vector (4 downto 0);
signal same_tdest_int1 : std_logic;
signal same_tdest_int2 : std_logic;
signal same_tdest_int3 : std_logic;
signal same_tdest_arrived : std_logic;
--ATTRIBUTE async_reg OF mm2s_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_introut_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_to : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
or_sgctl <= mm2s_sgctl or s2mm_sgctl;
sg_ctl <= mm2s_sgctl or s2mm_sgctl;
mm2s_dmacr <= mm2s_dmacr_i; -- MM2S DMA Control Register
mm2s_dmasr <= mm2s_dmasr_i; -- MM2S DMA Status Register
mm2s_sa <= mm2s_sa_i; -- MM2S Source Address (Simple Only)
mm2s_length <= mm2s_length_i; -- MM2S Length (Simple Only)
s2mm_dmacr <= s2mm_dmacr_i; -- S2MM DMA Control Register
s2mm_dmasr <= s2mm_dmasr_i; -- S2MM DMA Status Register
s2mm_da <= s2mm_da_i; -- S2MM Destination Address (Simple Only)
s2mm_length <= s2mm_length_i; -- S2MM Length (Simple Only)
-- Soft reset set in mm2s DMACR or s2MM DMACR
soft_reset <= mm2s_dmacr_i(DMACR_RESET_BIT)
or s2mm_dmacr_i(DMACR_RESET_BIT);
-- CR572013 - added to match legacy SDMA operation
mm2s_irqthresh_rstdsbl <= not mm2s_dmacr_i(DMACR_DLY_IRQEN_BIT);
s2mm_irqthresh_rstdsbl <= not s2mm_dmacr_i(DMACR_DLY_IRQEN_BIT);
--GEN_S2MM_TDEST : if (C_NUM_S2MM_CHANNELS > 1) generate
GEN_S2MM_TDEST : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
PROC_WREN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_taildesc_int3 <= (others => '0');
s2mm_tailpntr_updated_int <= '0';
s2mm_tailpntr_updated_int2 <= '0';
s2mm_tailpntr_updated <= '0';
else -- (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- s2mm_tailpntr_updated_int <= new_tdest or same_tdest_arrived;
-- s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
-- s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
-- Commenting this code as it is causing SG to start early
s2mm_tailpntr_updated_int <= new_tdest or s2mm_tailpntr_updated_int1 or (same_tdest_arrived and (not bd_eq));
s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
end if;
end if;
end process PROC_WREN;
-- this is always '1' as MCH needs to have all desc reg programmed before hand
--s2mm_tailpntr_updated_int3_i <= s2mm_tailpntr_updated_int2_i and (not s2mm_tailpntr_updated_int_i); -- and tvalid_latch;
tdest_fix <= "11111";
new_tdest <= tvalid_int1 xor tvalid_int2;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
tvalid_int <= '0';
tvalid_int1 <= '0';
tvalid_int2 <= '0';
tvalid_latch <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
tvalid_int <= tdest_in (6); --s2mm_tvalid;
tvalid_int1 <= tvalid_int;
tvalid_int2 <= tvalid_int1;
s2mm_tvalid_latch_del <= tvalid_latch;
if (new_tdest = '1') then
tvalid_latch <= '0';
else
tvalid_latch <= '1';
end if;
end if;
end if;
end process;
-- will trigger tailptrupdtd and it will then get SG out of pause
same_tdest_arrived <= same_tdest_int2 xor same_tdest_int3;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
same_tdest_int1 <= '0';
same_tdest_int2 <= '0';
same_tdest_int3 <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
same_tdest_int1 <= same_tdest_in;
same_tdest_int2 <= same_tdest_int1;
same_tdest_int3 <= same_tdest_int2;
end if;
end if;
end process;
-- process (m_axi_sg_aclk)
-- begin
-- if (m_axi_sg_aresetn = '0') then
-- tvalid_int <= '0';
-- tvalid_int1 <= '0';
-- tvalid_latch <= '0';
-- tdest_in_int <= (others => '0');
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- tvalid_int <= s2mm_tvalid;
-- tvalid_int1 <= tvalid_int;
-- tdest_in_int <= tdest_in;
-- -- if (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- if (tvalid_int1 = '1' and tdest_in_int = "00000" and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- elsif (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- tvalid_latch <= '0';
-- elsif (tvalid_int1 = '1' and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- end if;
-- end if;
-- end process;
s2mm_tvalid_latch <= tvalid_latch;
PROC_TDEST_IN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_curdesc_int2 <= (others => '0');
s2mm_taildesc_int2 <= (others => '0');
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
s2mm_curdesc_int2 <= s2mm_curdesc_int;
s2mm_taildesc_int2 <= s2mm_taildesc_int;
end if;
end if;
end process PROC_TDEST_IN;
s2mm_curdesc <= s2mm_curdesc_int2;
s2mm_taildesc <= s2mm_taildesc_int2;
end generate GEN_S2MM_TDEST;
GEN_S2MM_NO_TDEST : if (C_ENABLE_MULTI_CHANNEL = 0) generate
--GEN_S2MM_NO_TDEST : if (C_NUM_S2MM_CHANNELS = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int1;
s2mm_curdesc <= s2mm_curdesc_int;
s2mm_taildesc <= s2mm_taildesc_int;
s2mm_tvalid_latch <= '1';
s2mm_tvalid_latch_del <= '1';
end generate GEN_S2MM_NO_TDEST;
-- For 32 bit address map only lsb registers out
GEN_DESC_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_curdesc <= mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL32;
-- For 64 bit address map lsb and msb registers out
GEN_DESC_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
mm2s_curdesc <= mm2s_curdesc_msb_i & mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_msb_i & mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_msb_muxed & s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_msb_muxed & s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL64;
-------------------------------------------------------------------------------
-- Generate AXI Lite Inteface
-------------------------------------------------------------------------------
GEN_AXI_LITE_IF : if C_INCLUDE_MM2S = 1 or C_INCLUDE_S2MM = 1 generate
begin
AXI_LITE_IF_I : entity axi_dma_v7_1.axi_dma_lite_if
generic map(
C_NUM_CE => 23+(120*C_ENABLE_MULTI_CHANNEL) ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
ip2axi_aclk => m_axi_sg_aclk ,
ip2axi_aresetn => m_axi_sg_hrdresetn ,
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_aresetn => axi_lite_reset_n ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
axi2ip_wrce => axi2ip_wrce ,
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_rdce => open ,
axi2ip_rdaddr => axi2ip_rdaddr ,
ip2axi_rddata => ip2axi_rddata
);
end generate GEN_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- No channels therefore do not generate an AXI Lite interface
-------------------------------------------------------------------------------
GEN_NO_AXI_LITE_IF : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
s_axi_lite_awready <= '0';
s_axi_lite_wready <= '0';
s_axi_lite_bresp <= (others => '0');
s_axi_lite_bvalid <= '0';
s_axi_lite_arready <= '0';
s_axi_lite_rvalid <= '0';
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rresp <= (others => '0');
end generate GEN_NO_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- Generate MM2S Registers if included
-------------------------------------------------------------------------------
GEN_MM2S_REGISTERS : if C_INCLUDE_MM2S = 1 generate
begin
I_MM2S_DMA_REGISTER : entity axi_dma_v7_1.axi_dma_register
generic map (
C_NUM_REGISTERS => NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
-- C_NUM_S2MM_CHANNELS => 1 --C_S2MM_NUM_CHANNELS
--C_CHANNEL_IS_S2MM => NOT_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
(RESERVED_2C_INDEX
downto MM2S_DMACR_INDEX),
--(MM2S_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => mm2s_stop ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
-- SG Error Control
ftch_interr_set => mm2s_ftch_interr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => mm2s_updt_interr_set ,
updt_slverr_set => mm2s_updt_slverr_set ,
updt_decerr_set => mm2s_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
dma_interr_set => mm2s_dma_interr_set ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
error_in => s2mm_error_out ,
error_out => mm2s_error_out ,
introut => mm2s_introut_i_cdc_from ,
soft_reset_in => s2mm_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => mm2s_tailpntr_updated ,
-- Channel Registers
sg_ctl => mm2s_sgctl ,
dmacr => mm2s_dmacr_i ,
dmasr => mm2s_dmasr_i ,
curdesc_lsb => mm2s_curdesc_lsb_i ,
curdesc_msb => mm2s_curdesc_msb_i ,
taildesc_lsb => mm2s_taildesc_lsb_i ,
taildesc_msb => mm2s_taildesc_msb_i ,
-- curdesc1_lsb => open ,
-- curdesc1_msb => open ,
-- taildesc1_lsb => open ,
-- taildesc1_msb => open ,
-- curdesc2_lsb => open ,
-- curdesc2_msb => open ,
-- taildesc2_lsb => open ,
-- taildesc2_msb => open ,
--
-- curdesc3_lsb => open ,
-- curdesc3_msb => open ,
-- taildesc3_lsb => open ,
-- taildesc3_msb => open ,
--
-- curdesc4_lsb => open ,
-- curdesc4_msb => open ,
-- taildesc4_lsb => open ,
-- taildesc4_msb => open ,
--
-- curdesc5_lsb => open ,
-- curdesc5_msb => open ,
-- taildesc5_lsb => open ,
-- taildesc5_msb => open ,
--
-- curdesc6_lsb => open ,
-- curdesc6_msb => open ,
-- taildesc6_lsb => open ,
-- taildesc6_msb => open ,
--
-- curdesc7_lsb => open ,
-- curdesc7_msb => open ,
-- taildesc7_lsb => open ,
-- taildesc7_msb => open ,
--
-- curdesc8_lsb => open ,
-- curdesc8_msb => open ,
-- taildesc8_lsb => open ,
-- taildesc8_msb => open ,
--
-- curdesc9_lsb => open ,
-- curdesc9_msb => open ,
-- taildesc9_lsb => open ,
-- taildesc9_msb => open ,
--
-- curdesc10_lsb => open ,
-- curdesc10_msb => open ,
-- taildesc10_lsb => open ,
-- taildesc10_msb => open ,
--
-- curdesc11_lsb => open ,
-- curdesc11_msb => open ,
-- taildesc11_lsb => open ,
-- taildesc11_msb => open ,
--
-- curdesc12_lsb => open ,
-- curdesc12_msb => open ,
-- taildesc12_lsb => open ,
-- taildesc12_msb => open ,
--
-- curdesc13_lsb => open ,
-- curdesc13_msb => open ,
-- taildesc13_lsb => open ,
-- taildesc13_msb => open ,
--
-- curdesc14_lsb => open ,
-- curdesc14_msb => open ,
-- taildesc14_lsb => open ,
-- taildesc14_msb => open ,
--
--
-- curdesc15_lsb => open ,
-- curdesc15_msb => open ,
-- taildesc15_lsb => open ,
-- taildesc15_msb => open ,
--
-- tdest_in => "00000" ,
buffer_address => mm2s_sa_i ,
buffer_length => mm2s_length_i ,
buffer_length_wren => mm2s_length_wren ,
bytes_received => ZERO_BYTES , -- Not used on transmit
bytes_received_wren => '0' -- Not used on transmit
);
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
PROC_REG_INTR2LITE : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => mm2s_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- -- if(axi_lite_reset_n = '0')then
-- -- mm2s_introut_d1_cdc_tig <= '0';
-- -- mm2s_introut_to <= '0';
-- -- else
-- mm2s_introut_d1_cdc_tig <= mm2s_introut_i_cdc_from;
-- mm2s_introut_to <= mm2s_introut_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
mm2s_introut <= mm2s_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
mm2s_introut <= mm2s_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Tie MM2S Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_MM2S_REGISTERS : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_dmacr_i <= (others => '0');
mm2s_dmasr_i <= (others => '0');
mm2s_curdesc_lsb_i <= (others => '0');
mm2s_curdesc_msb_i <= (others => '0');
mm2s_taildesc_lsb_i <= (others => '0');
mm2s_taildesc_msb_i <= (others => '0');
mm2s_tailpntr_updated <= '0';
mm2s_sa_i <= (others => '0');
mm2s_length_i <= (others => '0');
mm2s_length_wren <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_introut <= '0';
mm2s_sgctl <= (others => '0');
mm2s_dlyirq_dsble <= '0';
end generate GEN_NO_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Generate S2MM Registers if included
-------------------------------------------------------------------------------
GEN_S2MM_REGISTERS : if C_INCLUDE_S2MM = 1 generate
begin
I_S2MM_DMA_REGISTER : entity axi_dma_v7_1.axi_dma_register_s2mm
generic map (
C_NUM_REGISTERS => NUM_REG_PER_S2MM_INT, --NUM_REG_TOTAL, --NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
--C_CHANNEL_IS_S2MM => IS_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
((23+(120*C_ENABLE_MULTI_CHANNEL)-1)
downto RESERVED_2C_INDEX) ,
-- downto S2MM_DMACR_INDEX),
--S2MM_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => s2mm_stop ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
-- SG Error Control
dma_interr_set => s2mm_dma_interr_set ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_interr_set => s2mm_ftch_interr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => s2mm_updt_interr_set ,
updt_slverr_set => s2mm_updt_slverr_set ,
updt_decerr_set => s2mm_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
error_in => mm2s_error_out ,
error_out => s2mm_error_out ,
introut => s2mm_introut_i_cdc_from ,
soft_reset_in => mm2s_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => s2mm_tailpntr_updated_int1 ,
-- Channel Registers
sg_ctl => s2mm_sgctl ,
dmacr => s2mm_dmacr_i ,
dmasr => s2mm_dmasr_i ,
curdesc_lsb => s2mm_curdesc_lsb_i ,
curdesc_msb => s2mm_curdesc_msb_i ,
taildesc_lsb => s2mm_taildesc_lsb_i ,
taildesc_msb => s2mm_taildesc_msb_i ,
curdesc1_lsb => s2mm_curdesc1_lsb_i ,
curdesc1_msb => s2mm_curdesc1_msb_i ,
taildesc1_lsb => s2mm_taildesc1_lsb_i ,
taildesc1_msb => s2mm_taildesc1_msb_i ,
curdesc2_lsb => s2mm_curdesc2_lsb_i ,
curdesc2_msb => s2mm_curdesc2_msb_i ,
taildesc2_lsb => s2mm_taildesc2_lsb_i ,
taildesc2_msb => s2mm_taildesc2_msb_i ,
curdesc3_lsb => s2mm_curdesc3_lsb_i ,
curdesc3_msb => s2mm_curdesc3_msb_i ,
taildesc3_lsb => s2mm_taildesc3_lsb_i ,
taildesc3_msb => s2mm_taildesc3_msb_i ,
curdesc4_lsb => s2mm_curdesc4_lsb_i ,
curdesc4_msb => s2mm_curdesc4_msb_i ,
taildesc4_lsb => s2mm_taildesc4_lsb_i ,
taildesc4_msb => s2mm_taildesc4_msb_i ,
curdesc5_lsb => s2mm_curdesc5_lsb_i ,
curdesc5_msb => s2mm_curdesc5_msb_i ,
taildesc5_lsb => s2mm_taildesc5_lsb_i ,
taildesc5_msb => s2mm_taildesc5_msb_i ,
curdesc6_lsb => s2mm_curdesc6_lsb_i ,
curdesc6_msb => s2mm_curdesc6_msb_i ,
taildesc6_lsb => s2mm_taildesc6_lsb_i ,
taildesc6_msb => s2mm_taildesc6_msb_i ,
curdesc7_lsb => s2mm_curdesc7_lsb_i ,
curdesc7_msb => s2mm_curdesc7_msb_i ,
taildesc7_lsb => s2mm_taildesc7_lsb_i ,
taildesc7_msb => s2mm_taildesc7_msb_i ,
curdesc8_lsb => s2mm_curdesc8_lsb_i ,
curdesc8_msb => s2mm_curdesc8_msb_i ,
taildesc8_lsb => s2mm_taildesc8_lsb_i ,
taildesc8_msb => s2mm_taildesc8_msb_i ,
curdesc9_lsb => s2mm_curdesc9_lsb_i ,
curdesc9_msb => s2mm_curdesc9_msb_i ,
taildesc9_lsb => s2mm_taildesc9_lsb_i ,
taildesc9_msb => s2mm_taildesc9_msb_i ,
curdesc10_lsb => s2mm_curdesc10_lsb_i ,
curdesc10_msb => s2mm_curdesc10_msb_i ,
taildesc10_lsb => s2mm_taildesc10_lsb_i ,
taildesc10_msb => s2mm_taildesc10_msb_i ,
curdesc11_lsb => s2mm_curdesc11_lsb_i ,
curdesc11_msb => s2mm_curdesc11_msb_i ,
taildesc11_lsb => s2mm_taildesc11_lsb_i ,
taildesc11_msb => s2mm_taildesc11_msb_i ,
curdesc12_lsb => s2mm_curdesc12_lsb_i ,
curdesc12_msb => s2mm_curdesc12_msb_i ,
taildesc12_lsb => s2mm_taildesc12_lsb_i ,
taildesc12_msb => s2mm_taildesc12_msb_i ,
curdesc13_lsb => s2mm_curdesc13_lsb_i ,
curdesc13_msb => s2mm_curdesc13_msb_i ,
taildesc13_lsb => s2mm_taildesc13_lsb_i ,
taildesc13_msb => s2mm_taildesc13_msb_i ,
curdesc14_lsb => s2mm_curdesc14_lsb_i ,
curdesc14_msb => s2mm_curdesc14_msb_i ,
taildesc14_lsb => s2mm_taildesc14_lsb_i ,
taildesc14_msb => s2mm_taildesc14_msb_i ,
curdesc15_lsb => s2mm_curdesc15_lsb_i ,
curdesc15_msb => s2mm_curdesc15_msb_i ,
taildesc15_lsb => s2mm_taildesc15_lsb_i ,
taildesc15_msb => s2mm_taildesc15_msb_i ,
tdest_in => tdest_in (5 downto 0) ,
buffer_address => s2mm_da_i ,
buffer_length => s2mm_length_i ,
buffer_length_wren => s2mm_length_wren ,
bytes_received => s2mm_bytes_rcvd ,
bytes_received_wren => s2mm_bytes_rcvd_wren
);
GEN_DESC_MUX_SINGLE_CH : if C_NUM_S2MM_CHANNELS = 1 generate
begin
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
end generate GEN_DESC_MUX_SINGLE_CH;
GEN_DESC_MUX : if C_NUM_S2MM_CHANNELS > 1 generate
begin
PROC_DESC_SEL : process (tdest_in, s2mm_curdesc_lsb_i,s2mm_curdesc_msb_i, s2mm_taildesc_lsb_i, s2mm_taildesc_msb_i,
s2mm_curdesc1_lsb_i,s2mm_curdesc1_msb_i, s2mm_taildesc1_lsb_i, s2mm_taildesc1_msb_i,
s2mm_curdesc2_lsb_i,s2mm_curdesc2_msb_i, s2mm_taildesc2_lsb_i, s2mm_taildesc2_msb_i,
s2mm_curdesc3_lsb_i,s2mm_curdesc3_msb_i, s2mm_taildesc3_lsb_i, s2mm_taildesc3_msb_i,
s2mm_curdesc4_lsb_i,s2mm_curdesc4_msb_i, s2mm_taildesc4_lsb_i, s2mm_taildesc4_msb_i,
s2mm_curdesc5_lsb_i,s2mm_curdesc5_msb_i, s2mm_taildesc5_lsb_i, s2mm_taildesc5_msb_i,
s2mm_curdesc6_lsb_i,s2mm_curdesc6_msb_i, s2mm_taildesc6_lsb_i, s2mm_taildesc6_msb_i,
s2mm_curdesc7_lsb_i,s2mm_curdesc7_msb_i, s2mm_taildesc7_lsb_i, s2mm_taildesc7_msb_i,
s2mm_curdesc8_lsb_i,s2mm_curdesc8_msb_i, s2mm_taildesc8_lsb_i, s2mm_taildesc8_msb_i,
s2mm_curdesc9_lsb_i,s2mm_curdesc9_msb_i, s2mm_taildesc9_lsb_i, s2mm_taildesc9_msb_i,
s2mm_curdesc10_lsb_i,s2mm_curdesc10_msb_i, s2mm_taildesc10_lsb_i, s2mm_taildesc10_msb_i,
s2mm_curdesc11_lsb_i,s2mm_curdesc11_msb_i, s2mm_taildesc11_lsb_i, s2mm_taildesc11_msb_i,
s2mm_curdesc12_lsb_i,s2mm_curdesc12_msb_i, s2mm_taildesc12_lsb_i, s2mm_taildesc12_msb_i,
s2mm_curdesc13_lsb_i,s2mm_curdesc13_msb_i, s2mm_taildesc13_lsb_i, s2mm_taildesc13_msb_i,
s2mm_curdesc14_lsb_i,s2mm_curdesc14_msb_i, s2mm_taildesc14_lsb_i, s2mm_taildesc14_msb_i,
s2mm_curdesc15_lsb_i,s2mm_curdesc15_msb_i, s2mm_taildesc15_lsb_i, s2mm_taildesc15_msb_i
)
begin
case tdest_in (3 downto 0) is
when "0000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
when "0001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc1_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc1_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc1_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc1_msb_i;
when "0010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc2_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc2_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc2_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc2_msb_i;
when "0011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc3_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc3_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc3_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc3_msb_i;
when "0100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc4_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc4_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc4_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc4_msb_i;
when "0101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc5_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc5_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc5_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc5_msb_i;
when "0110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc6_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc6_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc6_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc6_msb_i;
when "0111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc7_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc7_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc7_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc7_msb_i;
when "1000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc8_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc8_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc8_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc8_msb_i;
when "1001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc9_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc9_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc9_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc9_msb_i;
when "1010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc10_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc10_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc10_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc10_msb_i;
when "1011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc11_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc11_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc11_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc11_msb_i;
when "1100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc12_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc12_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc12_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc12_msb_i;
when "1101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc13_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc13_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc13_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc13_msb_i;
when "1110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc14_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc14_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc14_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc14_msb_i;
when "1111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc15_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc15_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc15_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc15_msb_i;
when others =>
s2mm_curdesc_lsb_muxed <= (others => '0');
s2mm_curdesc_msb_muxed <= (others => '0');
s2mm_taildesc_lsb_muxed <= (others => '0');
s2mm_taildesc_msb_muxed <= (others => '0');
end case;
end process PROC_DESC_SEL;
end generate GEN_DESC_MUX;
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
-- Cross interrupt out to AXI Lite clock domain
PROC_REG_INTR2LITE : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s2mm_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(axi_lite_reset_n = '0')then
-- s2mm_introut_d1_cdc_tig <= '0';
-- s2mm_introut_to <= '0';
-- else
-- s2mm_introut_d1_cdc_tig <= s2mm_introut_i_cdc_from;
-- s2mm_introut_to <= s2mm_introut_d1_cdc_tig;
-- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
s2mm_introut <= s2mm_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
s2mm_introut <= s2mm_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- Tie S2MM Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_S2MM_REGISTERS : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_dmacr_i <= (others => '0');
s2mm_dmasr_i <= (others => '0');
s2mm_curdesc_lsb_i <= (others => '0');
s2mm_curdesc_msb_i <= (others => '0');
s2mm_taildesc_lsb_i <= (others => '0');
s2mm_taildesc_msb_i <= (others => '0');
s2mm_da_i <= (others => '0');
s2mm_length_i <= (others => '0');
s2mm_length_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_introut <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_tailpntr_updated_int1 <= '0';
s2mm_sgctl <= (others => '0');
end generate GEN_NO_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
read_addr <= axi2ip_rdaddr(9 downto 0);
-- Generate read mux for Scatter Gather Mode
GEN_READ_MUX_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_curdesc_lsb_i ,
mm2s_curdesc_msb_i ,
mm2s_taildesc_lsb_i ,
mm2s_taildesc_msb_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_curdesc_lsb_i ,
s2mm_curdesc_msb_i ,
s2mm_taildesc_lsb_i ,
s2mm_taildesc_msb_i ,
s2mm_curdesc1_lsb_i ,
s2mm_curdesc1_msb_i ,
s2mm_taildesc1_lsb_i ,
s2mm_taildesc1_msb_i ,
s2mm_curdesc2_lsb_i ,
s2mm_curdesc2_msb_i ,
s2mm_taildesc2_lsb_i ,
s2mm_taildesc2_msb_i ,
s2mm_curdesc3_lsb_i ,
s2mm_curdesc3_msb_i ,
s2mm_taildesc3_lsb_i ,
s2mm_taildesc3_msb_i ,
s2mm_curdesc4_lsb_i ,
s2mm_curdesc4_msb_i ,
s2mm_taildesc4_lsb_i ,
s2mm_taildesc4_msb_i ,
s2mm_curdesc5_lsb_i ,
s2mm_curdesc5_msb_i ,
s2mm_taildesc5_lsb_i ,
s2mm_taildesc5_msb_i ,
s2mm_curdesc6_lsb_i ,
s2mm_curdesc6_msb_i ,
s2mm_taildesc6_lsb_i ,
s2mm_taildesc6_msb_i ,
s2mm_curdesc7_lsb_i ,
s2mm_curdesc7_msb_i ,
s2mm_taildesc7_lsb_i ,
s2mm_taildesc7_msb_i ,
s2mm_curdesc8_lsb_i ,
s2mm_curdesc8_msb_i ,
s2mm_taildesc8_lsb_i ,
s2mm_taildesc8_msb_i ,
s2mm_curdesc9_lsb_i ,
s2mm_curdesc9_msb_i ,
s2mm_taildesc9_lsb_i ,
s2mm_taildesc9_msb_i ,
s2mm_curdesc10_lsb_i ,
s2mm_curdesc10_msb_i ,
s2mm_taildesc10_lsb_i ,
s2mm_taildesc10_msb_i ,
s2mm_curdesc11_lsb_i ,
s2mm_curdesc11_msb_i ,
s2mm_taildesc11_lsb_i ,
s2mm_taildesc11_msb_i ,
s2mm_curdesc12_lsb_i ,
s2mm_curdesc12_msb_i ,
s2mm_taildesc12_lsb_i ,
s2mm_taildesc12_msb_i ,
s2mm_curdesc13_lsb_i ,
s2mm_curdesc13_msb_i ,
s2mm_taildesc13_lsb_i ,
s2mm_taildesc13_msb_i ,
s2mm_curdesc14_lsb_i ,
s2mm_curdesc14_msb_i ,
s2mm_taildesc14_lsb_i ,
s2mm_taildesc14_msb_i ,
s2mm_curdesc15_lsb_i ,
s2mm_curdesc15_msb_i ,
s2mm_taildesc15_lsb_i ,
s2mm_taildesc15_msb_i ,
or_sgctl
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_lsb_i;
when MM2S_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_msb_i;
when MM2S_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_lsb_i;
when MM2S_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_msb_i;
when SGCTL_OFFSET =>
ip2axi_rddata <= x"00000" & or_sgctl (7 downto 4) & "0000" & or_sgctl (3 downto 0);
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_lsb_i;
when S2MM_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_msb_i;
when S2MM_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_lsb_i;
when S2MM_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_msb_i;
when S2MM_CURDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_lsb_i;
when S2MM_CURDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_msb_i;
when S2MM_TAILDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_lsb_i;
when S2MM_TAILDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_msb_i;
when S2MM_CURDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_lsb_i;
when S2MM_CURDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_msb_i;
when S2MM_TAILDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_lsb_i;
when S2MM_TAILDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_msb_i;
when S2MM_CURDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_lsb_i;
when S2MM_CURDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_msb_i;
when S2MM_TAILDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_lsb_i;
when S2MM_TAILDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_msb_i;
when S2MM_CURDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_lsb_i;
when S2MM_CURDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_msb_i;
when S2MM_TAILDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_lsb_i;
when S2MM_TAILDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_msb_i;
when S2MM_CURDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_lsb_i;
when S2MM_CURDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_msb_i;
when S2MM_TAILDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_lsb_i;
when S2MM_TAILDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_msb_i;
when S2MM_CURDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_lsb_i;
when S2MM_CURDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_msb_i;
when S2MM_TAILDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_lsb_i;
when S2MM_TAILDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_msb_i;
when S2MM_CURDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_lsb_i;
when S2MM_CURDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_msb_i;
when S2MM_TAILDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_lsb_i;
when S2MM_TAILDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_msb_i;
when S2MM_CURDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_lsb_i;
when S2MM_CURDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_msb_i;
when S2MM_TAILDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_lsb_i;
when S2MM_TAILDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_msb_i;
when S2MM_CURDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_lsb_i;
when S2MM_CURDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_msb_i;
when S2MM_TAILDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_lsb_i;
when S2MM_TAILDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_msb_i;
when S2MM_CURDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_lsb_i;
when S2MM_CURDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_msb_i;
when S2MM_TAILDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_lsb_i;
when S2MM_TAILDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_msb_i;
when S2MM_CURDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_lsb_i;
when S2MM_CURDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_msb_i;
when S2MM_TAILDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_lsb_i;
when S2MM_TAILDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_msb_i;
when S2MM_CURDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_lsb_i;
when S2MM_CURDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_msb_i;
when S2MM_TAILDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_lsb_i;
when S2MM_TAILDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_msb_i;
when S2MM_CURDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_lsb_i;
when S2MM_CURDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_msb_i;
when S2MM_TAILDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_lsb_i;
when S2MM_TAILDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_msb_i;
when S2MM_CURDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_lsb_i;
when S2MM_CURDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_msb_i;
when S2MM_TAILDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_lsb_i;
when S2MM_TAILDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_msb_i;
when S2MM_CURDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_lsb_i;
when S2MM_CURDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_msb_i;
when S2MM_TAILDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_lsb_i;
when S2MM_TAILDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_msb_i;
-- coverage off
when others =>
ip2axi_rddata <= (others => '0');
-- coverage on
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SG;
-- Generate read mux for Simple DMA Mode
GEN_READ_MUX_FOR_SMPL_DMA : if C_INCLUDE_SG = 0 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_sa_i ,
mm2s_length_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_da_i ,
s2mm_length_i
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_SA_OFFSET =>
ip2axi_rddata <= mm2s_sa_i;
when MM2S_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & mm2s_length_i;
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_DA_OFFSET =>
ip2axi_rddata <= s2mm_da_i;
when S2MM_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & s2mm_length_i;
when others =>
ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SMPL_DMA;
end implementation;
| gpl-3.0 | 07388d7098330559d68f8dff7a9142b6 | 0.437861 | 3.715922 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-sp601/testbench.vhd | 1 | 10,949 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library hynix;
use hynix.components.all;
use work.debug.all;
use work.config.all;
library hynix;
use hynix.components.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 37 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
constant ct : integer := clkperiod/2;
signal clk : std_logic := '0';
signal clk200p : std_logic := '1';
signal clk200n : std_logic := '0';
signal rst : std_logic := '0';
signal rstn1 : std_logic;
signal rstn2 : std_logic;
signal error : std_logic;
-- PROM flash
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- Debug support unit
signal dsubre : std_ulogic;
-- AHB Uart
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
-- APB Uart
signal urxd : std_ulogic;
signal utxd : std_ulogic;
-- Ethernet signals
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic;
signal erxdt : std_logic_vector(7 downto 0);
signal erx_dv : std_ulogic;
signal erx_er : std_ulogic;
signal erx_col : std_ulogic;
signal erx_crs : std_ulogic;
signal etxdt : std_logic_vector(7 downto 0);
signal etx_en : std_ulogic;
signal etx_er : std_ulogic;
signal emdc : std_ulogic;
signal emdio : std_logic;
-- SVGA signals
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(3 downto 0);
signal vid_g : std_logic_vector(3 downto 0);
signal vid_b : std_logic_vector(3 downto 0);
-- Select signal for SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_logic;
signal spi_mosi : std_logic;
-- Output signals for LEDs
signal led : std_logic_vector(2 downto 0);
signal brdyn : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
rst <= '1', '0' after 100 ns;
dsubre <= '0';
urxd <= 'H';
spi_sel_n <= 'H';
spi_clk <= 'L';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => rst,
reset_o1 => rstn1,
reset_o2 => rstn2,
clk27 => clk,
clk200_p => clk200p,
clk200_n => clk200n,
errorn => error,
-- PROM
address => address(23 downto 0),
data => data(31 downto 24),
romsn => romsn,
oen => oen,
writen => writen,
iosn => iosn,
testdata => data(23 downto 0),
-- DDR2
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_we => ddr_we,
ddr_ras => ddr_ras,
ddr_cas => ddr_cas,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
ddr_odt => ddr_odt,
ddr_rzq => ddr_rzq,
ddr_zio => ddr_zio,
-- Debug Unit
dsubre => dsubre,
-- AHB Uart
dsutx => dsutx,
dsurx => dsurx,
-- PHY
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxdt(7 downto 0),
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxdt(7 downto 0),
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc,
emdio => emdio,
-- SPI flash select
-- spi_sel_n => spi_sel_n,
-- spi_clk => spi_clk,
-- spi_mosi => spi_mosi,
-- Output signals for LEDs
led => led
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr2mem0 : for i in 0 to 0 generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => true, PUSCheckFlag => false,
index => i, bbits => 16, fname => sdramfile,
fdelay => 150)
port map (DQ => ddr_dq(i*16+15 downto i*16),
LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2),
UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1),
LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas,
RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba(1 downto 0),
ADDR => ddr_ad(12 downto 0), CKE => ddr_cke,
CLK => ddr_clk, CLKB => ddr_clkb, UDM => ddr_dm(i*2+1));
end generate;
end generate;
ddr2mem : if (CFG_DDR2SP /= 0) generate
ddr2mem0 : for i in 0 to 0 generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => true, PUSCheckFlag => false,
index => i, bbits => 16, fname => sdramfile)
port map (DQ => ddr_dq2(i*16+15 downto i*16),
LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2),
UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1),
LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas,
RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba(1 downto 0),
ADDR => ddr_ad(12 downto 0), CKE => ddr_cke,
CLK => ddr_clk, CLKB => ddr_clkb, UDM => ddr_dm(i*2+1));
end generate;
ddr2delay0 : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 10.0)
port map(a => ddr_dq, b => ddr_dq2);
end generate;
prom0 : sram
generic map (index => 6, abits => 24, fname => promfile)
port map (address(23 downto 0), data(31 downto 24), romsn, writen, oen);
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map (address => 1)
port map(rstn1, emdio, etx_clk, erx_clk, erxdt, erx_dv, erx_er,
erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, '0');
end generate;
spimem0: if CFG_SPIMCTRL = 1 generate
s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => 0) -- Dual output is not supported in this design
port map (spi_clk, spi_mosi, data(24), spi_sel_n);
end generate spimem0;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data, iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 | d333cf0b0bfabc0a475a131c24ee97e9 | 0.540871 | 3.395039 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/libcache.vhd | 1 | 22,736 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: libcache
-- File: libcache.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: Cache-related types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
package libcache is
constant TAG_HIGH : integer := 31;
constant CTAG_LRRPOS : integer := 9;
constant CTAG_LOCKPOS : integer := 8;
constant MAXSETS : integer := 4;
-- 3-way set permutations
-- s012 => set 0 - least recently used
-- set 2 - most recently used
constant s012 : std_logic_vector(2 downto 0) := "000";
constant s021 : std_logic_vector(2 downto 0) := "001";
constant s102 : std_logic_vector(2 downto 0) := "010";
constant s120 : std_logic_vector(2 downto 0) := "011";
constant s201 : std_logic_vector(2 downto 0) := "100";
constant s210 : std_logic_vector(2 downto 0) := "101";
-- 4-way set permutations
-- s0123 => set 0 - least recently used
-- set 3 - most recently used
-- bits assigned so bits 4:3 is LRU and 1:0 is MRU
-- middle bit is 0 for 01 02 03 12 13 23, 1 for 10 20 30 21 31 32
constant s0123 : std_logic_vector(4 downto 0) := "00011";
constant s0132 : std_logic_vector(4 downto 0) := "00010";
constant s0213 : std_logic_vector(4 downto 0) := "00111";
constant s0231 : std_logic_vector(4 downto 0) := "00001";
constant s0312 : std_logic_vector(4 downto 0) := "00110";
constant s0321 : std_logic_vector(4 downto 0) := "00101";
constant s1023 : std_logic_vector(4 downto 0) := "01011";
constant s1032 : std_logic_vector(4 downto 0) := "01010";
constant s1203 : std_logic_vector(4 downto 0) := "01111";
constant s1230 : std_logic_vector(4 downto 0) := "01000";
constant s1302 : std_logic_vector(4 downto 0) := "01110";
constant s1320 : std_logic_vector(4 downto 0) := "01100";
constant s2013 : std_logic_vector(4 downto 0) := "10011";
constant s2031 : std_logic_vector(4 downto 0) := "10001";
constant s2103 : std_logic_vector(4 downto 0) := "10111";
constant s2130 : std_logic_vector(4 downto 0) := "10000";
constant s2301 : std_logic_vector(4 downto 0) := "10101";
constant s2310 : std_logic_vector(4 downto 0) := "10100";
constant s3012 : std_logic_vector(4 downto 0) := "11010";
constant s3021 : std_logic_vector(4 downto 0) := "11001";
constant s3102 : std_logic_vector(4 downto 0) := "11110";
constant s3120 : std_logic_vector(4 downto 0) := "11000";
constant s3201 : std_logic_vector(4 downto 0) := "11101";
constant s3210 : std_logic_vector(4 downto 0) := "11100";
type lru_3set_table_vector_type is array(0 to 2) of std_logic_vector(2 downto 0);
type lru_3set_table_type is array (0 to 7) of lru_3set_table_vector_type;
constant lru_3set_table : lru_3set_table_type :=
( (s120, s021, s012), -- s012
(s210, s021, s012), -- s021
(s120, s021, s102), -- s102
(s120, s201, s102), -- s120
(s210, s201, s012), -- s201
(s210, s201, s102), -- s210
(s210, s201, s102), -- dummy
(s210, s201, s102) -- dummy
);
type lru_4set_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
type lru_4set_table_type is array(0 to 31) of lru_4set_table_vector_type;
constant lru_4set_table : lru_4set_table_type :=
( (s2310, s0231, s0312, s0213), -- "00000" (s0231/reset)
(s2310, s0231, s0312, s0213), -- "00001" s0231
(s1320, s0321, s0132, s0123), -- "00010" s0132
(s1230, s0231, s0132, s0123), -- "00011" s0123
(s3210, s0321, s0312, s0213), -- "00100" (s0321)
(s3210, s0321, s0312, s0213), -- "00101" s0321
(s3120, s0321, s0312, s0123), -- "00110" s0312
(s2130, s0231, s0132, s0213), -- "00111" s0213
(s1230, s2301, s1302, s1203), -- "01000" s1230
(s1230, s2301, s1302, s1203), -- "01001" (s1230)
(s1320, s0321, s1032, s1023), -- "01010" s1032
(s1230, s0231, s1032, s1023), -- "01011" s1023
(s1320, s3201, s1302, s1203), -- "01100" s1320
(s1320, s3201, s1302, s1203), -- "01101" (s1320)
(s1320, s3021, s1302, s1023), -- "01110" s1302
(s1230, s2031, s1032, s1203), -- "01111" s1203
(s2130, s2301, s1302, s2103), -- "10000" s2130
(s2310, s2031, s0312, s2013), -- "10001" s2031
(s2130, s2031, s0132, s2013), -- "10010" (s2013)
(s2130, s2031, s0132, s2013), -- "10011" s2013
(s2310, s2301, s3102, s2103), -- "10100" s2310
(s2310, s2301, s3012, s2013), -- "10101" s2301
(s2130, s2031, s1032, s2103), -- "10110" (s2103)
(s2130, s2031, s1032, s2103), -- "10111" s2103
(s3120, s3201, s3102, s1203), -- "11000" s3120
(s3210, s3021, s3012, s0213), -- "11001" s3021
(s3120, s3021, s3012, s0123), -- "11010" s3012
(s3120, s3021, s3012, s0123), -- "11011" (s3012)
(s3210, s3201, s3102, s2103), -- "11100" s3210
(s3210, s3201, s3012, s2013), -- "11101" s3201
(s3120, s3021, s3102, s1023), -- "11110" s3102
(s3120, s3021, s3102, s1023) -- "11111" (s3102)
);
type lru3_repl_table_single_type is array(0 to 2) of integer range 0 to 2;
type lru3_repl_table_type is array(0 to 7) of lru3_repl_table_single_type;
constant lru3_repl_table : lru3_repl_table_type :=
( (0, 1, 2), -- s012
(0, 2, 2), -- s021
(1, 1, 2), -- s102
(1, 1, 2), -- s120
(2, 2, 2), -- s201
(2, 2, 2), -- s210
(2, 2, 2), -- dummy
(2, 2, 2) -- dummy
);
type lru4_repl_table_single_type is array(0 to 3) of integer range 0 to 3;
type lru4_repl_table_type is array(0 to 31) of lru4_repl_table_single_type;
constant lru4_repl_table : lru4_repl_table_type :=
( (0, 2, 2, 3), -- (s0231/reset)
(0, 2, 2, 3), -- s0231
(0, 1, 3, 3), -- s0132
(0, 1, 2, 3), -- s0123
(0, 3, 3, 3), -- (s0321)
(0, 3, 3, 3), -- s0321
(0, 3, 3, 3), -- s0312
(0, 2, 2, 3), -- s0213
(1, 1, 2, 3), -- s1230
(1, 1, 2, 3), -- (s1230)
(1, 1, 3, 3), -- s1032
(1, 1, 2, 3), -- s1023
(1, 1, 3, 3), -- s1320
(1, 1, 3, 3), -- (s1320)
(1, 1, 3, 3), -- s1302
(1, 1, 2, 3), -- s1203
(2, 2, 2, 3), -- s2130
(2, 2, 2, 3), -- s2031
(2, 2, 2, 3), -- (s2013)
(2, 2, 2, 3), -- s2013
(2, 2, 2, 3), -- s2310
(2, 2, 2, 3), -- s2301
(2, 2, 2, 3), -- (s2103)
(2, 2, 2, 3), -- s2103
(3, 3, 3, 3), -- s3120
(3, 3, 3, 3), -- s3021
(3, 3, 3, 3), -- s3012
(3, 3, 3, 3), -- (s3012)
(3, 3, 3, 3), -- s3210
(3, 3, 3, 3), -- s3201
(3, 3, 3, 3), -- s3102
(3, 3, 3, 3) -- (s3102)
);
type ildram_in_type is record
enable : std_ulogic;
read : std_ulogic;
write : std_ulogic;
end record;
subtype ctxword is std_logic_vector(M_CTX_SZ-1 downto 0);
type ctxdatatype is array (0 to 3) of ctxword;
type icram_in_type is record
address : std_logic_vector(19 downto 0);
tag : cdatatype;
twrite : std_logic_vector(0 to 3);
tenable : std_ulogic;
flush : std_ulogic;
data : std_logic_vector(31 downto 0);
denable : std_ulogic;
dwrite : std_logic_vector(0 to 3);
ldramin : ildram_in_type;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
end record;
type icram_out_type is record
tag : cdatatype;
data : cdatatype;
ctx : ctxdatatype;
end record;
type ldram_in_type is record
address : std_logic_vector(23 downto 2);
enable : std_ulogic;
read : std_ulogic;
write : std_ulogic;
end record;
type dcram_in_type is record
address : std_logic_vector(19 downto 0);
tag : cdatatype; --std_logic_vector(31 downto 0);
ptag : cdatatype; --std_logic_vector(31 downto 0);
twrite : std_logic_vector(0 to 3);
tpwrite : std_logic_vector(0 to 3);
tenable : std_logic_vector(0 to 3);
flush : std_ulogic;
data : cdatatype;
denable : std_logic_vector(0 to 3);
dwrite : std_logic_vector(0 to 3);
senable : std_logic_vector(0 to 3);
swrite : std_logic_vector(0 to 3);
saddress : std_logic_vector(19 downto 0);
faddress : std_logic_vector(19 downto 0);
ldramin : ldram_in_type;
ctx : ctxdatatype;
tdiag : std_logic_vector(3 downto 0);
ddiag : std_logic_vector(3 downto 0);
sdiag : std_logic_vector(3 downto 0);
end record;
type dcram_out_type is record
tag : cdatatype;
data : cdatatype;
stag : cdatatype;
ctx : ctxdatatype;
end record;
type cram_in_type is record
icramin : icram_in_type;
dcramin : dcram_in_type;
end record;
type cram_out_type is record
icramo : icram_out_type;
dcramo : dcram_out_type;
end record;
type memory_ic_in_type is record
address : std_logic_vector(31 downto 0); -- memory address
burst : std_ulogic; -- burst request
req : std_ulogic; -- memory cycle request
su : std_ulogic; -- supervisor address space
flush : std_ulogic; -- flush in progress
end record;
type memory_ic_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_ulogic; -- cycle ready
grant : std_ulogic; --
retry : std_ulogic; --
mexc : std_ulogic; -- memory exception
cache : std_ulogic; -- cacheable data
scanen : std_ulogic;
end record;
type memory_dc_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
asi : std_logic_vector(3 downto 0); -- ASI for load/store
size : std_logic_vector(1 downto 0);
burst : std_ulogic;
read : std_ulogic;
req : std_ulogic;
lock : std_ulogic;
cache : std_ulogic;
end record;
type memory_dc_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_ulogic; -- cycle ready
grant : std_ulogic;
retry : std_ulogic;
mexc : std_ulogic; -- memory exception
werr : std_ulogic; -- memory write error
cache : std_ulogic; -- cacheable data
ba : std_ulogic; -- bus active (used for snooping)
bg : std_ulogic; -- bus grant (used for snooping)
scanen : std_ulogic;
testen : std_ulogic;
end record;
constant dir : integer := 3;
constant rnd : integer := 2;
constant lrr : integer := 1;
constant lru : integer := 0;
type cache_replalgbits_type is array (0 to 3) of integer;
constant creplalg_tbl : cache_replalgbits_type := (0, 1, 0, 0);
type lru_bits_type is array(1 to 4) of integer;
constant lru_table : lru_bits_type := (1,1,3,5);
component cachemem
generic (
tech : integer range 0 to NTECH := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
mmuen : integer range 0 to 1 := 0;
testen : integer range 0 to 3 := 0
);
port (
clk : in std_ulogic;
crami : in cram_in_type;
cramo : out cram_out_type;
sclk : in std_ulogic
);
end component;
-- mmu versions
component mmu_acache
generic (
hindex : integer range 0 to NAHBMST-1 := 0;
ilinesize : integer range 4 to 8 := 4;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
mcmmi : in memory_mm_in_type;
mcmmo : out memory_mm_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbso : in ahb_slv_out_vector;
hclken : in std_ulogic
);
end component;
component mmu_icache
generic (
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
lram : integer range 0 to 1 := 0;
lramsize : integer range 1 to 512 := 1;
lramstart : integer range 0 to 255 := 16#8e#;
mmuen : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : in dcache_out_type;
mcii : out memory_ic_in_type;
mcio : in memory_ic_out_type;
icrami : out icram_in_type;
icramo : in icram_out_type;
fpuholdn : in std_logic;
mmudci : in mmudc_in_type;
mmuici : out mmuic_in_type;
mmuico : in mmuic_out_type
);
end component;
component mmu_dcache
generic (
dsu : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
ilram : integer range 0 to 1 := 0;
ilramstart : integer range 0 to 255 := 16#8e#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
memtech : integer range 0 to NTECH := 0;
cached : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
ahbsi : in ahb_slv_in_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_logic;
mmudci : out mmudc_in_type;
mmudco : in mmudc_out_type;
sclk : in std_ulogic;
ahbso : in ahb_slv_out_vector
);
end component;
component mmu_cache
generic (
hindex : integer := 0;
memtech : integer range 0 to NTECH := 0;
dsu : integer range 0 to 1 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_ulogic;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end component;
component clk2xqual
port (
rst : in std_ulogic;
clk : in std_ulogic;
clk2 : in std_ulogic;
clken : out std_ulogic);
end component;
component clk2xsync
generic (
hindex : integer := 0;
clk2x : integer := 1);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbi2 : out ahb_mst_in_type;
ahbo : in ahb_mst_out_type;
ahbo2 : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbsi2 : out ahb_slv_in_type;
mcii : in memory_ic_in_type;
mcdi : in memory_dc_in_type;
mcdo : in memory_dc_out_type;
mmreq : in std_ulogic;
mmgrant : in std_ulogic;
hclken : in std_ulogic
);
end component;
function cache_cfg(repl, sets, linesize, setsize, lock, snoop,
lram, lramsize, lramstart, mmuen : integer) return std_logic_vector;
end;
package body libcache is
function cache_cfg(repl, sets, linesize, setsize, lock, snoop,
lram, lramsize, lramstart, mmuen : integer)
return std_logic_vector is
variable cfg : std_logic_vector(31 downto 0);
begin
cfg := (others => '0');
cfg(31 downto 31) := conv_std_logic_vector(lock, 1);
cfg(30 downto 28) := conv_std_logic_vector(repl+1, 3);
if snoop /= 0 then cfg(27) := '1'; end if;
cfg(26 downto 24) := conv_std_logic_vector(sets-1, 3);
cfg(23 downto 20) := conv_std_logic_vector(log2(setsize), 4);
cfg(19 downto 19) := conv_std_logic_vector(lram, 1);
cfg(18 downto 16) := conv_std_logic_vector(log2(linesize), 3);
cfg(15 downto 12) := conv_std_logic_vector(log2(lramsize), 4);
cfg(11 downto 4) := conv_std_logic_vector(lramstart, 8);
cfg(3 downto 3) := conv_std_logic_vector(mmuen, 1);
return(cfg);
end;
end;
| gpl-2.0 | c9423fa45dddf7708c1fd639d7391b84 | 0.501451 | 3.48071 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_s2mm_sts_mngr.vhd | 3 | 11,859 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the S2MM
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- system state --
s2mm_run_stop : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_cmnd_idle : in std_logic ; --
s2mm_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
s2mm_stop : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
--
-- system control --
s2mm_all_idle : out std_logic ; --
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic --
);
end axi_dma_s2mm_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal s2mm_datamover_idle : std_logic := '0';
signal s2mm_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cmpt_cdc_d2 : std_logic := '0';
signal s2mm_halt_cmpt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_cdc_d2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- all is idle when all is idle
all_is_idle <= s2mm_ftch_idle
and s2mm_updt_idle
and s2mm_cmnd_idle
and s2mm_sts_idle;
s2mm_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
---- if(m_axi_sg_aresetn = '0')then
---- s2mm_halt_cmpt_d1_cdc_tig <= '0';
---- s2mm_halt_cmpt_d2 <= '0';
---- else
-- s2mm_halt_cmpt_d1_cdc_tig <= s2mm_halt_cmplt;
-- s2mm_halt_cmpt_cdc_d2 <= s2mm_halt_cmpt_d1_cdc_tig;
---- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_cmpt_d2 <= s2mm_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_cmpt_d2 <= s2mm_halt_cmplt;
end generate GEN_FOR_SYNC;
s2mm_datamover_idle <= '1' when (s2mm_stop = '1' and s2mm_halt_cmpt_d2 = '1')
or (s2mm_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_set <= '0';
elsif(s2mm_run_stop = '0' and all_is_idle = '1' and s2mm_datamover_idle = '1')then
s2mm_halted_set <= '1';
else
s2mm_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_clr <= '0';
elsif(s2mm_run_stop = '1')then
s2mm_halted_clr <= '1';
else
s2mm_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
s2mm_idle_set <= all_is_idle_re and s2mm_run_stop;
s2mm_idle_clr <= all_is_idle_fe;
end implementation;
| gpl-3.0 | 29afe0846bca099a9307c0240a5d277f | 0.44793 | 4.470034 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_wr_status_cntl.vhd | 5 | 57,329 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_sg_wr_status_cntl;
architecture implementation of axi_sg_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_sg_v4_1.axi_sg_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1.axi_sg_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1.axi_sg_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| gpl-3.0 | adccfc7b633f36e213c018b150c12c44 | 0.411973 | 5.093195 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_mm2s_sts_mngr.vhd | 3 | 11,928 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the MM2S
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-- system signals
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- dma control and sg engine status signals --
mm2s_run_stop : in std_logic ; --
--
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_cmnd_idle : in std_logic ; --
mm2s_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
mm2s_stop : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
--
-- system state and control --
mm2s_all_idle : out std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic --
);
end axi_dma_mm2s_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal mm2s_datamover_idle : std_logic := '0';
signal mm2s_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cmpt_cdc_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_cdc_d2 : SIGNAL IS "true";
signal mm2s_halt_cmpt_d2 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Everything is idle when everything is idle
all_is_idle <= mm2s_ftch_idle
and mm2s_updt_idle
and mm2s_cmnd_idle
and mm2s_sts_idle;
-- Pass out for soft reset use
mm2s_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
AWVLD_CDC_TO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_cmpt_d1_cdc_tig <= '0';
-- -- mm2s_halt_cmpt_d2 <= '0';
-- -- else
-- mm2s_halt_cmpt_d1_cdc_tig <= mm2s_halt_cmplt;
-- mm2s_halt_cmpt_cdc_d2 <= mm2s_halt_cmpt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_cmpt_d2 <= mm2s_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_cmpt_d2 <= mm2s_halt_cmplt;
end generate GEN_FOR_SYNC;
mm2s_datamover_idle <= '1' when (mm2s_stop = '1' and mm2s_halt_cmpt_d2 = '1')
or (mm2s_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_set <= '0';
-- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted
elsif(mm2s_run_stop = '0' and all_is_idle = '1' and mm2s_datamover_idle = '1')then
mm2s_halted_set <= '1';
else
mm2s_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_clr <= '0';
elsif(mm2s_run_stop = '1')then
mm2s_halted_clr <= '1';
else
mm2s_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
mm2s_idle_set <= all_is_idle_re and mm2s_run_stop;
mm2s_idle_clr <= all_is_idle_fe;
end implementation;
| gpl-3.0 | 90788cad2a1673ae285932ef20a57b3e | 0.454645 | 4.430906 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-avnet-eval-xc4vlx60/ahb2mig_avnet_eval.vhd | 1 | 18,876 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex5 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package avnet_eval is
constant APPDATA_WIDTH : integer := 32; -- # of usr read/write data bus bits.
constant ADDR_WIDTH : integer := 36; -- # of memory row and # of addr bits.
constant MIGHMASK : integer := 16#FE0#; -- AHB mask for 256 Mbyte memory
-- constant MIGHMASK : integer := 16#E00#; -- AHB mask for 512 Mbyte memory
-- constant MIGHMASK : integer := 16#C00#; -- AHB mask for 1024 Mbyte memory
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_en : std_logic;
mig_rst : std_logic;
end record;
type mig_app_out_type is record
app_af_afull : std_logic;
app_wdf_afull : std_logic;
app_rd_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_rd_data_valid : std_logic;
end record;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.avnet_eval.all;
entity ahb2mig_avnet_eval is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
rst_50 : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clk_50 : in std_ulogic;
init_done : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_avnet_eval is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold1, rhold2, rhold3, rhold4, rhold5, rhold6, rhold7, dread,
whold1, whold2, whold3, whold4, whold5, whold6, whold7);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 7) of std_logic_vector(31 downto 0);
type wrm is array(0 to 7) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(255 downto 0);
sync : std_ulogic;
dstate : ddr_state_type;
addr : std_logic_vector(2 downto 0);
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
signal rdel : std_logic_vector(25 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst_ahb, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(2 downto 2) is
when "0" => rdata := r.hrdata(127 downto 0);
when others => rdata := r.hrdata(255 downto 128);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(127 downto 0);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(127 downto 64);
else va.hrdata(63 downto 0) := rdata(63 downto 0); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "01" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "10" => va.hrdata(31 downto 0) := rdata(95 downto 64);
when others => va.hrdata(31 downto 0) := rdata(127 downto 96);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(4 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst_ahb = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
-- delayed reset for the MIG, will not work otherwise ...
rstp : process(clk_50)
begin
if rising_edge(clk_50) then
if rdel(25) = '0' then rdel <= rdel + 1; end if;
if rst_50 = '0' then
rdel <= (others => '0');
-- pragma translate_off
rdel <= (25 => '0', 2 => '0', others => '1');
-- pragma translate_on
end if;
end if;
end process;
ddr_ctrl : process(rst_ddr, r, ra, migo, init_done, rdel)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
variable app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "100"; app_wdf_wren := '0';
app_wdf_mask := (others => '0');
app_wdf_mask := ra.write(0);
app_wdf_data := (others => '0');
app_wdf_data(31 downto 0) := ra.hwdata(0);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
app_addr := '0' & app_cmd & "00000" & ra.acc.haddr(27 downto 5) & r.addr(0) & "000";
v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
v.addr := "00" & ra.acc.haddr(4); app_addr(3) := ra.acc.haddr(4);
if (startsd = '1') and (migo.app_af_afull = '0') and (init_done = '1') then
if ra.acc.hwrite = '0' then
if ra.acc.haddr(4) = '0' then
v.dstate := dread; v.addr := r.addr + 1;
else v.dstate := rhold4; end if;
app_en := '1';
elsif migo.app_wdf_afull = '0' then
if ra.acc.haddr(4) = '0' then
v.dstate := whold1; v.addr := r.addr + 1;
else
v.dstate := whold5;
app_wdf_mask(3 downto 0) := ra.write(4);
app_wdf_data(31 downto 0) := ra.hwdata(4);
end if;
app_en := '1'; app_wdf_wren := '1';
end if;
end if;
when dread =>
if r.addr(0) = '1' then
v.addr := r.addr + 1; app_en := '1';
end if;
if migo.app_rd_data_valid = '1' then
v.hrdata(31 downto 0) := migo.app_rd_data(31 downto 0);
v.dstate := rhold1;
end if;
when rhold1 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(63 downto 32) := migo.app_rd_data(31 downto 0);
v.dstate := rhold2;
end if;
when rhold2 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(95 downto 64) := migo.app_rd_data(31 downto 0);
v.dstate := rhold3;
end if;
when rhold3 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(127 downto 96) := migo.app_rd_data(31 downto 0);
v.dstate := rhold4;
end if;
when rhold4 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(159 downto 128) := migo.app_rd_data(31 downto 0);
v.dstate := rhold5;
end if;
when rhold5 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(191 downto 160) := migo.app_rd_data(31 downto 0);
v.dstate := rhold6;
end if;
when rhold6 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(223 downto 192) := migo.app_rd_data(31 downto 0);
v.dstate := rhold7;
end if;
when rhold7 =>
if migo.app_rd_data_valid = '1' then
v.hrdata(255 downto 224) := migo.app_rd_data(31 downto 0);
v.dstate := midle;
v.startsd := not r.startsd;
end if;
when whold1 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(1);
app_wdf_data(31 downto 0) := ra.hwdata(1);
v.dstate := whold2;
when whold2 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(2);
app_wdf_data(31 downto 0) := ra.hwdata(2);
v.dstate := whold3;
when whold3 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(3);
app_wdf_data(31 downto 0) := ra.hwdata(3);
if (ra.write(4) = "0000") and (ra.write(5) = "0000") and (ra.write(6) = "0000") and
(ra.write(7) = "0000")
then v.startsd := not r.startsd; v.dstate := midle;
elsif migo.app_wdf_afull = '0' then v.dstate := whold4; app_en := '1'; end if;
when whold4 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(4);
app_wdf_data(31 downto 0) := ra.hwdata(4);
v.dstate := whold5;
when whold5 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(5);
app_wdf_data(31 downto 0) := ra.hwdata(5);
v.dstate := whold6;
when whold6 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(6);
app_wdf_data(31 downto 0) := ra.hwdata(6);
v.dstate := whold7;
when whold7 =>
app_wdf_wren := '1';
app_wdf_mask(3 downto 0) := ra.write(7);
app_wdf_data(31 downto 0) := ra.hwdata(7);
v.startsd := not r.startsd;
v.dstate := midle;
when others =>
end case;
-- reset
if rst_ddr = '0' then
v.startsd := '0';
app_en := '0';
v.dstate := midle;
v.addr := "000";
end if;
ri <= v;
migi.app_addr <= app_addr;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
migi.mig_rst <= rdel(25);
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ahb2mig" & tost(hindex) & ": 32-bit DDR controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
| gpl-2.0 | 7b997ec9ac1db90890420440f9e028d0 | 0.572844 | 3.178848 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_s2mm_cmdsts_if.vhd | 3 | 22,858 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_cmdsts_if is
generic (
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_ENABLE_QUEUE : integer range 0 to 1 := 1
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
((2*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0); --
s2mm_cmnd_pending : out std_logic ; --
--
s2mm_packet_eof : out std_logic ; --
--
s2mm_sts_received_clr : in std_logic ; --
s2mm_sts_received : out std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((2*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8)-1 downto 0); --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
s2mm_brcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_done : out std_logic ; --
s2mm_error : out std_logic ; --
s2mm_interr : out std_logic ; --
s2mm_slverr : out std_logic ; --
s2mm_decerr : out std_logic ; --
s2mm_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_s2mm_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal s2mm_slverr_i : std_logic := '0';
signal s2mm_decerr_i : std_logic := '0';
signal s2mm_interr_i : std_logic := '0';
signal s2mm_error_or : std_logic := '0';
signal s2mm_packet_eof_i : std_logic := '0';
signal smpl_dma_overflow : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
s2mm_slverr <= s2mm_slverr_i;
s2mm_decerr <= s2mm_decerr_i;
s2mm_interr <= s2mm_interr_i or smpl_dma_overflow;
s2mm_packet_eof <= s2mm_packet_eof_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when s2mm_desc_cmplt = '1' and s2mm_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_HOLD_NO_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_s2mm_cmd_tvalid <= '0';
-- s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
-- new command and descriptor not flagged as stale
elsif(s2mm_cmnd_wr = '1' and stale_desc = '0')then
s_axis_s2mm_cmd_tvalid <= '1';
-- s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
s2mm_cmnd_pending <= '1';
-- clear flag on datamover acceptance of command
elsif(s_axis_s2mm_cmd_tready = '1')then
s_axis_s2mm_cmd_tvalid <= '0';
-- s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
end generate GEN_HOLD_NO_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
-- new command and descriptor not flagged as stale
elsif(s2mm_cmnd_wr = '1' and stale_desc = '0')then
s_axis_s2mm_cmd_tvalid <= '1';
s_axis_s2mm_cmd_tdata <= s2mm_cmnd_data;
s2mm_cmnd_pending <= '1';
-- clear flag on datamover acceptance of command
elsif(s_axis_s2mm_cmd_tready = '1')then
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
s2mm_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
elsif(sts_tready = '1' and m_axis_s2mm_sts_tvalid = '1')then
sts_tready <= '0';
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_s2mm_sts_tready <= sts_tready;
log_status <= '1' when m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0'
else '0';
-- Status stream is included, and using the rxlength from the status stream and in Scatter Gather Mode
DETERMINATE_BTT_MODE : if (C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_SG_USE_STSAPP_LENGTH = 1
and C_INCLUDE_SG = 1) or (C_MICRO_DMA = 1) generate
begin
-- Bytes received not available in determinate byte mode
s2mm_brcvd <= (others => '0');
-- Simple DMA overflow not used in Scatter Gather Mode
smpl_dma_overflow <= '0';
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
s2mm_done <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
s2mm_slverr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
s2mm_decerr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_DECERR_BIT);
s2mm_interr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
s2mm_tag <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- End Of Frame (EOF = 1) detected on status received. Used
-- for interrupt delay timer
REG_RX_EOF : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_packet_eof_i <= '0';
elsif(log_status = '1')then
s2mm_packet_eof_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGEOF_BIT)
or m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
else
s2mm_packet_eof_i <= '0';
end if;
end if;
end process REG_RX_EOF;
end generate DETERMINATE_BTT_MODE;
-- No Status Stream or not using rxlength from status stream or in Simple DMA Mode
INDETERMINATE_BTT_MODE : if (C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_SG_USE_STSAPP_LENGTH = 0
or C_INCLUDE_SG = 0) and (C_MICRO_DMA = 0) generate
-- Bytes received MSB index bit
constant BRCVD_MSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - C_SG_LENGTH_WIDTH);
-- Bytes received LSB index bit
constant BRCVD_LSB_BIT : integer := (C_DM_STATUS_WIDTH - 2) - (BUFFER_LENGTH_WIDTH - 1);
begin
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_brcvd <= (others => '0');
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
s2mm_brcvd <= m_axis_s2mm_sts_tdata(BRCVD_MSB_BIT downto BRCVD_LSB_BIT);
s2mm_done <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
s2mm_slverr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
s2mm_decerr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_DECERR_BIT);
s2mm_interr_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
s2mm_tag <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
s2mm_brcvd <= (others => '0');
s2mm_done <= '0';
s2mm_slverr_i <= '0';
s2mm_decerr_i <= '0';
s2mm_interr_i <= '0';
s2mm_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- End Of Frame (EOF = 1) detected on statis received. Used
-- for interrupt delay timer
REG_RX_EOF : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_packet_eof_i <= '0';
elsif(log_status = '1')then
s2mm_packet_eof_i <= m_axis_s2mm_sts_tdata(DATAMOVER_STS_TLAST_BIT)
or m_axis_s2mm_sts_tdata(DATAMOVER_STS_INTERR_BIT);
else
s2mm_packet_eof_i <= '0';
end if;
end if;
end process REG_RX_EOF;
-- If in Simple DMA mode then generate overflow flag
GEN_OVERFLOW_SMPL_DMA : if C_INCLUDE_SG = 0 generate
REG_OVERFLOW : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_dma_overflow <= '0';
-- If status received and TLAST bit is NOT set then packet is bigger than
-- BTT value commanded which is an invalid command
elsif(log_status = '1' and m_axis_s2mm_sts_tdata(DATAMOVER_STS_TLAST_BIT) = '0')then
smpl_dma_overflow <= '1';
end if;
end if;
end process REG_OVERFLOW;
end generate GEN_OVERFLOW_SMPL_DMA;
-- If in Scatter Gather Mode then do NOT generate simple dma mode overflow flag
GEN_NO_OVERFLOW_SMPL_DMA : if C_INCLUDE_SG = 1 generate
begin
smpl_dma_overflow <= '0';
end generate GEN_NO_OVERFLOW_SMPL_DMA;
end generate INDETERMINATE_BTT_MODE;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_s2mm_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
s2mm_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error_or <= s2mm_slverr_i or s2mm_decerr_i or s2mm_interr_i or smpl_dma_overflow;
-- Log errors into a global error output
S2MM_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((s2mm_error_or = '1')
or (stale_desc = '1' and s2mm_cmnd_wr='1'))then
s2mm_error <= '1';
end if;
end if;
end process S2MM_ERROR_PROCESS;
end implementation;
| gpl-3.0 | 72b6b0565aa44ba4b26fc55c7bd06808 | 0.451833 | 4.296617 | false | false | false | false |
medevo/howdoi | VHDL/subtract_unsigned.vhd | 1 | 772 | -- How do I subtract two std_logic_vectors unsigned
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity alu is
Port ( in1 : in std_logic_vector(15 downto 0);
in2 : in std_logic_vector(15 downto 0);
clk : in STD_LOGIC; -- Just in case, this design is async
result : out std_logic_vector(15 downto 0));
end alu;
architecture Behavioral of alu is
begin
process(clk,in1,in2)
variable tmp_s_16 : SIGNED (15 downto 0);
variable tmp_l_16 : std_logic_vector(15 downto 0);
tmp_s_16 := x"0000";
tmp_l_16 := x"0000";
-- Unsigned Subtract
tmp_l_16 := STD_LOGIC_VECTOR(unsigned(in1) - unsigned(in2));
tmp_s_16 := signed(tmp_l_16);
result <= std_logic_vector(tmp_s_16);
end process;
end Behavioral; | unlicense | 0a538371b3fdb2334ae5eb6d13e719b5 | 0.654145 | 2.891386 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep3c25-eek/serializer.vhd | 1 | 2,666 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Entity: serializer
-- File: serializer.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- [email protected]
--
-- Description: Takes in three vectors and serializes them into one
-- output vector. Intended to be used to serialize
-- RGB VGA data.
--
library ieee;
use ieee.std_logic_1164.all;
entity serializer is
generic (
length : integer := 8 -- vector length
);
port (
clk : in std_ulogic;
sync : in std_ulogic;
ivec0 : in std_logic_vector((length-1) downto 0);
ivec1 : in std_logic_vector((length-1) downto 0);
ivec2 : in std_logic_vector((length-1) downto 0);
ovec : out std_logic_vector((length-1) downto 0)
);
end entity serializer;
architecture rtl of serializer is
type state_type is (vec0, vec1, vec2);
type sreg_type is record
state : state_type;
sync : std_logic_vector(1 downto 0);
end record;
signal r, rin : sreg_type;
begin -- rtl
comb: process (r, clk, sync, ivec0, ivec1, ivec2)
variable v : sreg_type;
begin -- process comb
v := r;
v.sync := r.sync(0) & sync;
case r.state is
when vec0 =>
ovec <= ivec0;
v.state := vec1;
when vec1 =>
ovec <= ivec1;
v.state := vec2;
when vec2 =>
ovec <= ivec2;
v.state := vec0;
end case;
if (r.sync(0) xor sync) = '1' then
v.state := vec1;
end if;
rin <= v;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
end rtl;
| gpl-2.0 | b59e70d5ffcbe7f100ea46fd04777995 | 0.587022 | 3.760226 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_smple_sm.vhd | 2 | 16,885 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_smple_sm.vhd
-- Description: This entity contains the DMA Controller State Machine for
-- Simple DMA mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_smple_sm is
generic (
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_MICRO_DMA : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
run_stop : in std_logic ; --
keyhole : in std_logic ;
stop : in std_logic ; --
cmnd_idle : out std_logic ; --
sts_idle : out std_logic ; --
--
-- DataMover Status --
sts_received : in std_logic ; --
sts_received_clr : out std_logic ; --
--
-- DataMover Command --
cmnd_wr : out std_logic ; --
cmnd_data : out std_logic_vector --
((2*C_M_AXI_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0); --
cmnd_pending : in std_logic ; --
--
-- Trasnfer Qualifiers --
xfer_length_wren : in std_logic ; --
xfer_address : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; --
xfer_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) --
);
end axi_dma_smple_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_smple_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Command Destination Stream Offset
constant CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_ADDR_WIDTH)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SMPL_STATE_TYPE is (
IDLE,
EXECUTE_XFER,
WAIT_STATUS
);
signal smpl_cs : SMPL_STATE_TYPE;
signal smpl_ns : SMPL_STATE_TYPE;
-- State Machine Signals
signal write_cmnd_cmb : std_logic := '0';
signal cmnd_wr_i : std_logic := '0';
signal sts_received_clr_cmb : std_logic := '0';
signal cmnds_queued : std_logic := '0';
signal cmd_dumb : std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal zeros : std_logic_vector (45 downto 0) := (others => '0');
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Pass command write control out
cmnd_wr <= cmnd_wr_i;
burst_type <= '1' and (not keyhole);
-- 0 means fixed burst
-- 1 means increment burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(smpl_cs,
run_stop,
xfer_length_wren,
sts_received,
cmnd_pending,
cmnds_queued,
stop
)
begin
-- Default signal assignment
write_cmnd_cmb <= '0';
sts_received_clr_cmb <= '0';
cmnd_idle <= '0';
smpl_ns <= smpl_cs;
case smpl_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running, no errors, and new length written,then execute
-- transfer
if( run_stop = '1' and xfer_length_wren = '1' and stop = '0'
and cmnds_queued = '0') then
smpl_ns <= EXECUTE_XFER;
else
cmnd_idle <= '1';
end if;
-------------------------------------------------------------------
when EXECUTE_XFER =>
-- error detected
if(stop = '1')then
smpl_ns <= IDLE;
-- Write another command if there is not one already pending
elsif(cmnd_pending = '0')then
write_cmnd_cmb <= '1';
smpl_ns <= WAIT_STATUS;
else
smpl_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(sts_received = '1' or stop = '1')then
sts_received_clr_cmb <= '1';
smpl_ns <= IDLE;
else
smpl_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
smpl_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_cs <= IDLE;
else
smpl_cs <= smpl_ns;
end if;
end if;
end process REGISTER_STATE;
-- Register state machine signals
REGISTER_STATE_SIGS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn ='0')then
sts_received_clr <= '0';
else
sts_received_clr <= sts_received_clr_cmb;
end if;
end if;
end process REGISTER_STATE_SIGS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- Key Hole Operation'1' -- Not Used
& PAD_VALUE
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- key Hole Operation '1' -- Not Used
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Flag indicating command being processed by Datamover
-------------------------------------------------------------------------------
-- count number of queued commands to keep track of what datamover is still
-- working on
CMD2STS_COUNTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or stop = '1')then
cmnds_queued <= '0';
elsif(cmnd_wr_i = '1')then
cmnds_queued <= '1';
elsif(sts_received = '1')then
cmnds_queued <= '0';
end if;
end if;
end process CMD2STS_COUNTER;
-- Indicate status is idle when no cmnd/sts queued
sts_idle <= '1' when cmnds_queued = '0'
else '0';
end implementation;
| gpl-3.0 | 80c472406c0034ad4c46764542b069e2 | 0.38247 | 5.45205 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/grlib/stdlib/stdio_tb.vhd | 1 | 4,719 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--------------------------------------------------------------------------------
-- Package: StdIO
-- File: stdio.vhd
-- Author: Gaisler Research
-- Description: Package for common I/O functions
--------------------------------------------------------------------------------
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.StdIO.all;
entity StdIO_TB is
end entity StdIO_TB;
architecture Behavioural of StdIO_TB is
begin
process
variable LW: Line;
variable LR: Line;
file WFile: Text;
file RFile: Text;
constant SUL: Std_ULogic := 'H';
constant SL: Std_Logic := 'L';
constant SULV1: Std_ULogic_Vector := "1";
constant SULV2: Std_ULogic_Vector := "10";
constant SULV3: Std_ULogic_Vector := "011";
constant SULV4: Std_ULogic_Vector := "0100";
constant SULV5: Std_ULogic_Vector := "00101";
constant SULV6: Std_ULogic_Vector := "000110";
constant SULV7: Std_ULogic_Vector := "0000111";
constant SULV8: Std_ULogic_Vector := "00001000";
constant SULV9: Std_ULogic_Vector := "000001001";
constant SULVA: Std_ULogic_Vector := "00000001001000110100010101100111";
constant SULVB: Std_ULogic_Vector := "10001001101010111100110111101111";
variable SULVC: Std_ULogic_Vector(0 to 3);
variable SULVD: Std_ULogic_Vector(0 to 7);
variable SULVE: Std_ULogic_Vector(0 to 15);
variable SULVF: Std_ULogic_Vector(0 to 16);
constant SLVA: Std_Logic_Vector := "00000001001000110100010101100111";
constant SLVB: Std_Logic_Vector := "10001001101010111100110111101111";
variable SLVC: Std_Logic_Vector(0 to 7);
variable SLVD: Std_Logic_Vector(0 to 15);
begin
Write(LW, SUL);
WriteLine(Output, LW);
Write(LW, SL);
WriteLine(Output, LW);
HWrite(LW, SULV1);
WriteLine(Output, LW);
HWrite(LW, SULV2);
WriteLine(Output, LW);
HWrite(LW, SULV3);
WriteLine(Output, LW);
HWrite(LW, SULV4);
WriteLine(Output, LW);
HWrite(LW, SULV5);
WriteLine(Output, LW);
HWrite(LW, SULV6);
WriteLine(Output, LW);
HWrite(LW, SULV7);
WriteLine(Output, LW);
HWrite(LW, SULV8);
WriteLine(Output, LW);
HWrite(LW, SULV9);
WriteLine(Output, LW);
HWrite(LW, SULVA);
WriteLine(Output, LW);
HWrite(LW, SULVB);
WriteLine(Output, LW);
File_Open(WFile, "file.txt", Write_Mode);
HWrite(LW, SULVA);
WriteLine(WFile, LW);
HWrite(LW, SULVB);
WriteLine(WFile, LW);
HWrite(LW, SULVA);
WriteLine(WFile, LW);
HWrite(LW, SULVB);
WriteLine(WFile, LW);
HWrite(LW, SLVA);
WriteLine(WFile, LW);
HWrite(LW, SLVB);
WriteLine(WFile, LW);
File_Close(WFile);
File_Open(RFile, "file.txt", Read_Mode);
ReadLine(RFile, LR);
HRead(LR, SULVC);
HWrite(LW, SULVC);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SULVD);
HWrite(LW, SULVD);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SULVE);
HWrite(LW, SULVE);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SULVF);
HWrite(LW, SULVF);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SLVC);
HWrite(LW, SLVC);
WriteLine(Output, LW);
ReadLine(RFile, LR);
HRead(LR, SLVD);
HWrite(LW, SLVD);
WriteLine(Output, LW);
File_Close(RFile);
wait;
end process;
end architecture Behavioural;
| gpl-2.0 | 5fbca6c55222e0b2f71081d7926efaa6 | 0.581903 | 3.845966 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_p_src_rows_V_channel1.vhd | 2 | 4,636 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_rows_V_channel1_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_src_rows_V_channel1_shiftReg;
architecture rtl of FIFO_image_filter_p_src_rows_V_channel1_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_src_rows_V_channel1 is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_src_rows_V_channel1 is
component FIFO_image_filter_p_src_rows_V_channel1_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_src_rows_V_channel1_shiftReg : FIFO_image_filter_p_src_rows_V_channel1_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | a5af0812f91d48e82c7a89eef2eab25b | 0.540121 | 3.475262 | false | false | false | false |
Luisda199824/ProcesadorMonociclo | TB_Alu.vhd | 1 | 1,401 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TB_Alu IS
END TB_Alu;
ARCHITECTURE behavior OF TB_Alu IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Alu
PORT(
AluOp : IN std_logic_vector(5 downto 0);
rs1 : IN std_logic_vector(31 downto 0);
rs2 : IN std_logic_vector(31 downto 0);
AluResult : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal AluOp : std_logic_vector(5 downto 0) := (others => '0');
signal rs1 : std_logic_vector(31 downto 0) := (others => '0');
signal rs2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal AluResult : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Alu PORT MAP (
AluOp => AluOp,
rs1 => rs1,
rs2 => rs2,
AluResult => AluResult
);
-- Stimulus process
stim_proc: process
begin
rs1 <= x"00000000";
rs2 <= x"0000000A";
AluOp <= "000000";
wait for 20 ns;
AluOp <= "000001";
wait for 20 ns;
AluOp <= "000010";
wait for 20 ns;
AluOp <= "000011";
wait for 20 ns;
AluOp <= "000100";
wait for 20 ns;
AluOp <= "000101";
wait for 20 ns;
AluOp <= "000110";
wait for 20 ns;
AluOp <= "000111";
wait;
end process;
END;
| mit | 518f98349e32146931cb62263b658179 | 0.585296 | 3.288732 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep2s60-ddr/config.vhd | 1 | 5,448 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 8329afea1459d218db3f16ba54749906 | 0.642621 | 3.658831 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/spi/spi2ahbx.vhd | 1 | 17,383 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahbx
-- File: spi2ahbx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- This entity is typically wrapped with spi2ahb or spi2ahb_apb.
-------------------------------------------------------------------------------
--
-- Short core documentation, for additional information see the GRLIB IP
-- Library User's Manual (GRIP):
--
-- The core functions as a SPI memory device. To write to the core, issue the
-- following SPI bus sequence:
--
-- 0. Assert chip select
-- 1. Write instruction
-- 2. Send 32-bit address
-- 3. Send data to be written
-- 4. Deassert chip select
--
-- The core will expect 32-bits of data and write these as a word. This can be
-- changed by writing to the core's control register. See documentation further
-- down. If less than HSIZE bytes are transferred the core will drop the data.
-- After HSIZE bytes has been transferred the core will perform the write to
-- memory. If another byte is received before the core has written its data
-- then the core will discard the current and any following bytes. This
-- condition can be detected by checking the MALFUNCTION bit in the core's
-- status register.
--
-- To read to the core, issue the following SPI bus sequence:
--
-- 0. Assert chip select
-- 1. Send read instruction
-- 2. Send 32-bit address to be used
-- 3. Send dummy byte (depending on read instruction used)
-- 4. Read bytes
-- 5. Deassert chip select
--
-- The core will perform 32-bit data accesses to fill its internal buffer. This
-- can be changed by writing to the core's control register (see documentation
-- further down). If the buffer is empty when the core should return the first
-- byte then the core will return invalid data. This condition can be later
-- detected by checking the MALFUNCTION bit in the core's status register.
-- When the core initiates additional data fetches can be configured via the
-- RAHEAD bit in the control/status register.
--
-- The cores control/status register is read via the RDSR instruction and
-- written via the WRSR instruction.
--
-- +--------+-----------------------------------------------------------------+
-- | Bit(s) | Description |
-- +--------+-----------------------------------------------------------------+
-- | 7 | Reserved, always zero (RO) |
-- | 6 | RAHEAD: Read ahead. When this bit is set the core will make a |
-- | | new access to fetch data as soon as the last current data bit |
-- | | has been moved. Otherwise the core will not attempt the new |
-- | | access until the 'change' transition on SCK. See GRIP doc. for |
-- | | details. Default value is '1'. (RW) |
-- | 5 | PROT: Memory protection triggered. Last access was outside |
-- | | range. Updated after each AMBA access (RO) |
-- | 4 | MEXC: Memory exception. Gets set if core receives AMBA ERROR |
-- | | response. Updated after each AMBA access. (RO) |
-- | 3 | DMAACT: Core is currently performing DMA (RO) |
-- | 2 | MALFUNCTION: Set to 1 if DMA is not finished when new byte |
-- | | starts getting shifted |
-- | 1:0 | HSIZE: Controls the access size core will use for AMBA accesses |
-- | | Default is HSIZE = WORD. HSIZE 11 is illegal (RW) |
-- +--------+-----------------------------------------------------------------+
--
-- Documentation of generics:
--
-- [hindex] AHB master index
--
-- [oepol] Output enable polarity
--
-- [filter] Length of filter used on SCK
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.spi.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity spi2ahbx is
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
--
spi2ahbi : in spi2ahb_in_type;
spi2ahbo : out spi2ahb_out_type
);
end entity spi2ahbx;
architecture rtl of spi2ahbx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OE : std_ulogic := conv_std_logic(oepol = 1);
constant HIZ : std_ulogic := not OE;
-----------------------------------------------------------------------------
-- Instructions
-----------------------------------------------------------------------------
constant RDSR_INST : std_logic_vector(7 downto 0) := X"05";
constant WRSR_INST : std_logic_vector(7 downto 0) := X"01";
constant READ_INST : std_logic_vector(7 downto 0) := X"03";
constant READD_INST : std_logic_vector(7 downto 0) := X"0B"; -- with dummy
constant WRITE_INST : std_logic_vector(7 downto 0) := X"02";
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type state_type is (decode, rdsr, wrsr, addr, dummy, rd, wr, idle, malfunction);
type spi2ahb_reg_type is record
state : state_type;
--
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hsize : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
--
rahead : std_ulogic;
mexc : std_ulogic;
dodma : std_ulogic;
prot : std_ulogic;
malf : std_ulogic;
--
brec : std_ulogic;
rec : std_ulogic;
dummy : std_ulogic;
cnt : std_logic_vector(2 downto 0);
bcnt : std_logic_vector(1 downto 0);
sreg : std_logic_vector(7 downto 0);
miso : std_ulogic;
rdop : std_logic_vector(1 downto 0);
--
misooen : std_ulogic;
sel : std_logic_vector(1 downto 0);
psck : std_ulogic;
sck : std_logic_vector(filter downto 0);
mosi : std_logic_vector(1 downto 0);
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal ami : ahb_dma_in_type;
signal amo : ahb_dma_out_type;
signal r, rin : spi2ahb_reg_type;
begin
-- Generic AHB master interface
ahbmst0 : ahbmst
generic map (hindex => hindex, hirq => 0, venid => VENDOR_GAISLER,
devid => GAISLER_SPI2AHB, version => 0,
chprot => 3, incaddr => 0)
port map (rstn, clk, ami, amo, ahbi, ahbo);
comb: process (r, rstn, spii, amo, spi2ahbi)
variable v : spi2ahb_reg_type;
variable hrdata : std_logic_vector(31 downto 0);
variable ahbreq : std_ulogic;
variable lb : std_ulogic;
variable sample : std_ulogic;
variable change : std_ulogic;
begin
v := r; ahbreq := '0'; lb := '0'; hrdata := (others => '0');
sample := '0'; change := '0'; v.brec := '0';
---------------------------------------------------------------------------
-- Sync input signals
---------------------------------------------------------------------------
v.sel := r.sel(0) & spii.spisel;
v.sck := r.sck(filter-1 downto 0) & spii.sck;
v.mosi := r.mosi(0) & spii.mosi;
---------------------------------------------------------------------------
-- DMA control
---------------------------------------------------------------------------
if r.dodma = '1' then
if amo.active = '1' then
if amo.ready = '1' then
hrdata := ahbreadword(amo.rdata);
case r.hsize is
when "00" =>
v.haddr := r.haddr + 1;
for i in 1 to 3 loop
if i = conv_integer(r.haddr(1 downto 0)) then
hrdata(31 downto 24) := hrdata(31-8*i downto 24-8*i);
end if;
end loop;
when "01" =>
v.haddr := r.haddr + 2;
if r.haddr(1) = '1' then
hrdata(31 downto 16) := hrdata(15 downto 0);
end if;
when others =>
v.haddr := r.haddr + 4;
end case;
v.sreg := hrdata(31 downto 24);
v.hdata(31 downto 8) := hrdata(23 downto 0);
v.mexc := '0';
v.dodma := '0';
end if;
if amo.mexc = '1' then
v.mexc := '1';
v.dodma := '0';
end if;
else
ahbreq := '1';
end if;
end if;
---------------------------------------------------------------------------
-- SPI communication
---------------------------------------------------------------------------
if andv(r.sck(filter downto 1)) = '1' then v.psck := '1'; end if;
if orv(r.sck(filter downto 1)) = '0' then v.psck := '0'; end if;
if (r.psck xor v.psck) = '1' then
if r.psck = conv_std_logic(cpol = 1) then
sample := not conv_std_logic(cpha = 1);
change := conv_std_logic(cpha = 1);
else
sample := conv_std_logic(cpha = 1);
change := not conv_std_logic(cpha = 1);
end if;
end if;
if sample = '1' then
v.cnt := r.cnt + 1;
if r.cnt = "111" then
v.cnt := (others => '0');
v.brec := '1';
end if;
if r.state /= dummy then
v.sreg := r.sreg(6 downto 0) & r.mosi(1);
end if;
end if;
if change = '1' then
v.miso := r.sreg(7);
end if;
---------------------------------------------------------------------------
-- SPI slave control FSM
---------------------------------------------------------------------------
if ((r.hsize = "00") or ((r.hsize(0) and r.bcnt(0)) = '1') or
(r.bcnt = "11")) then
lb := '1';
end if;
case r.state is
when decode =>
if r.brec = '1' then
case r.sreg is
when RDSR_INST =>
v.state := rdsr;
v.sreg := '0' & r.rahead & r.prot & r.mexc &
r.dodma & r.malf & r.hsize;
when WRSR_INST => v.state := wrsr;
when READ_INST | READD_INST=>
v.state := addr; v.rec := '0';
v.dummy := r.sreg(3);
when WRITE_INST => v.state := addr; v.rec := '1';
when others => null;
end case;
end if;
when rdsr =>
if r.brec = '1' then
v.sreg := '0' & r.rahead & r.prot & r.mexc &
r.dodma & r.malf & r.hsize;
end if;
when wrsr =>
if r.brec = '1' then
v.rahead := r.sreg(6);
v.hsize := r.sreg(1 downto 0);
end if;
when addr =>
-- First we need a 4 byte address, then we handle data.
if r.brec = '1' then
if r.dodma = '1' then
v.state := malfunction;
else
v.haddr := r.haddr(23 downto 0) & r.sreg;
end if;
v.bcnt := r.bcnt + 1;
if r.bcnt = "11" then
if r.rec = '1' then
v.state := wr;
else
if r.dummy = '1' then
v.state := dummy;
else
v.state := rd;
end if;
v.malf := '0';
v.dodma := '1';
v.hwrite := '0';
end if;
end if;
end if;
when dummy =>
if r.brec = '1' then
v.state := rd;
end if;
when rd =>
if r.brec = '1' then
v.bcnt := r.bcnt + 1;
v.hdata(31 downto 8) := r.hdata(23 downto 0);
v.sreg := r.hdata(31 downto 24);
if (lb and r.rahead) = '1' then
v.dodma := '1';
v.bcnt := "00";
end if;
v.rdop(0) := lb and not r.rahead;
end if;
if (change and v.dodma) = '1' then
v.state := malfunction;
end if;
-- Without readahead
if orv(r.rdop) = '1' then
if (sample and v.dodma) = '1' then
-- Case is a little tricky. Master may have sampled bad
-- data but we detect the DMA operation as completed.
v.state := malfunction;
end if;
if (r.rdop(0) and change) = '1' then
v.dodma := '1';
v.rdop := "10";
end if;
if (r.dodma and not v.dodma) = '1' then
v.miso := hrdata(31);
v.rdop := (others => '0');
end if;
end if;
when wr =>
if r.brec = '1' then
v.bcnt := r.bcnt + 1;
if v.dodma = '0' then
if r.bcnt = "00" then v.hdata(31 downto 24) := r.sreg; end if;
if r.bcnt(1) = '0' then v.hdata(23 downto 16) := r.sreg; end if;
if r.bcnt(0) = '0' then v.hdata(15 downto 8) := r.sreg; end if;
v.hdata(7 downto 0) := r.sreg;
if lb = '1' then v.dodma := '1'; v.hwrite := '1'; v.malf := '0'; end if;
else
v.state := malfunction;
end if;
end if;
when idle =>
if r.sel(1) = '0' then
v.state := decode;
v.misooen := OE;
v.cnt := (others => '0');
v.bcnt := (others => '0');
end if;
when malfunction =>
v.malf := '1';
end case;
if r.state /= rd then v.rdop := (others => '0'); end if;
if spi2ahbi.hmask /= zero32 then
if v.dodma = '1' then
if ((spi2ahbi.haddr xor r.haddr) and spi2ahbi.hmask) /= zero32 then
v.dodma := '0';
v.prot := '1';
v.state := idle;
else
v.prot := '0';
end if;
end if;
else
v.prot := '0';
end if;
if spi2ahbi.en = '1' then
if r.sel(1) = '1' then
v.state := idle;
v.misooen := HIZ;
end if;
else
v.state := idle;
v.misooen := HIZ;
end if;
----------------------------------------------------------------------------
-- Reset
----------------------------------------------------------------------------
if rstn = '0' then
v.state := idle;
v.haddr := (others => '0');
v.hdata := (others => '0');
v.hsize := HSIZE_WORD(1 downto 0);
v.rahead := '1';
v.mexc := '0';
v.dodma := '0';
v.prot := '0';
v.malf := '0';
v.psck := conv_std_logic(cpol = 1);
v.miso := '1';
v.misooen := HIZ;
end if;
if spi2ahbi.hmask = zero32 then v.prot := '0'; end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB master control
ami.address <= r.haddr;
ami.wdata <= ahbdrivedata(r.hdata);
ami.start <= ahbreq;
ami.burst <= '0';
ami.write <= r.hwrite;
ami.busy <= '0';
ami.irq <= '0';
ami.size <= '0' & r.hsize;
-- Update outputs
spi2ahbo.dma <= r.dodma;
spi2ahbo.wr <= r.hwrite;
spi2ahbo.prot <= r.prot;
-- Several unused here..
spio.miso <= r.miso;
spio.misooen <= r.misooen;
spio.mosi <= '0';
spio.mosioen <= HIZ;
spio.sck <= '0';
spio.sckoen <= HIZ;
spio.ssn <= (others => '0');
spio.enable <= spi2ahbi.en;
spio.astart <= '0';
end process comb;
reg: process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map ("spi2ahb" & tost(hindex) & ": SPI to AHB bridge");
-- pragma translate_on
end architecture rtl;
| gpl-2.0 | 741f57dc7689893eba0215e4b5e6bdac | 0.46511 | 3.953377 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/vga_main/ctrl_8x16_rom.vhd | 1 | 47,189 | --------------------------------------------------------------------------------
--
-- Title : ctrl_8x16_rom
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Description : ROM generator for VGA characters
--
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ctrl_8x16_rom is
port(
clk : in std_logic; --! clock
addr : in std_logic_vector(10 downto 0); --! ROM address 2^11
data : out std_logic_vector(7 downto 0) --! ROM data 1 byte
);
end ctrl_8x16_rom;
architecture ctrl_8x16_rom of ctrl_8x16_rom is
constant addr_width : integer:= 11;
constant data_width : integer:= 8;
signal addr_reg : std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition
constant ROM: rom_type:=(
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000001", -- 8 *
"00000001", -- 9 *
"00000001", -- a *
"00000001", -- b *
"00000011", -- c **
"00000111", -- d ***
"00001111", -- e ****
"11111111", -- f ********
-- code x09
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3 **
"00011000", -- 4 **
"01011010", -- 5 ** ** **
"00111100", -- 6 ****
"01111110", -- 7 *** ***
"00111100", -- 8 ****
"01011010", -- 9 ** ** **
"00011000", -- a **
"00000000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x510
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f
"00000000", -- 0
"11111110", -- 1
"11111110", -- 2
"11111110", -- 3
"11111110", -- 4 *
"11111110", -- 5 ***
"11111110", -- 6 ** **
"11111110", -- 7 ** **
"11111110", -- 8 ** **
"11111110", -- 9 ** **
"11111110", -- a *******
"11111110", -- b
"11111110", -- c
"11111110", -- d
"11111110", -- e
"00000000" -- f
);
begin
addr_reg <= addr when rising_edge(clk);
data <= ROM(to_integer(unsigned(addr_reg)));
end ctrl_8x16_rom;
| mit | fdb98f6193c5c420c486b976f1bc4d52 | 0.422026 | 2.617539 | false | false | false | false |
freecores/usb_fpga_1_11 | examples/usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.vhd | 7 | 636 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= pb_buf;
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if ( pd >= 97 ) and ( pd <= 122)
then
pb_buf <= pd - 32;
else
pb_buf <= pd;
end if;
end if;
end process dpUCECHO;
end RTL;
| gpl-3.0 | d82498dfcd5bec6bde6790a09bf70c8e | 0.589623 | 3.148515 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/allpads.vhd | 1 | 30,983 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Package: allpads
-- File: allpads.vhd
-- Author: Jiri Gaisler et al. - Aeroflex Gaisler
-- Description: All tech pads
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allpads is
component apa3_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component apa3_clkpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component apa3_inpad
generic (level : integer := 0; voltage : integer := 0;
filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component apa3_inpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component apa3_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0;
filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component apa3_iopad_ds
generic (level : integer := lvds);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component apa3_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component apa3_outpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component apa3_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3_toutpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3e_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component apa3e_clkpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component apa3e_inpad
generic (level : integer := 0; voltage : integer := 0;
filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component apa3e_inpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component apa3e_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0;
filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component apa3e_iopad_ds
generic (level : integer := lvds);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component apa3e_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3e_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component apa3e_outpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component apa3e_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3e_toutpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3l_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component apa3l_clkpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component apa3l_inpad
generic (level : integer := 0; voltage : integer := 0;
filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component apa3l_inpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component apa3l_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0;
filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component apa3l_iopad_ds
generic (level : integer := lvds);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component apa3l_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3l_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component apa3l_outpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component apa3l_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component apa3l_toutpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component fusion_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component fusion_clkpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component fusion_inpad
generic (level : integer := 0; voltage : integer := 0;
filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component fusion_inpad_ds
generic (level : integer := lvds);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component fusion_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0;
filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component fusion_iopad_ds
generic (level : integer := lvds);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component fusion_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component fusion_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component fusion_outpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component fusion_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component fusion_toutpad_ds
generic (level : integer := lvds);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component axcel_inpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component axcel_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component axcel_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component axcel_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component axcel_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component axcel_clkpad
generic (level : integer := 0; voltage : integer := 0; arch : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component axcel_inpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component axcel_outpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component atc18_inpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component atc18_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component atc18_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component atc18_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component atc18_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component atc18_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ihp25_inpad
generic(level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ihp25rh_inpad
generic(level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ihp25_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component ihp25rh_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component ihp25_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component ihp25rh_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component ihp25_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_logic);
end component;
component ihp25rh_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_logic);
end component;
component ihp25_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component ihp25rh_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component rhumc_inpad
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component rhumc_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component rhumc_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component rhumc_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component saed32_inpad
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component saed32_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component saed32_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component saed32_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component dare_inpad
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component dare_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component dare_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component dare_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component umc_inpad
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component umc_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component umc_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component umc_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component unisim_inpad
generic (level : integer := 0; voltage : integer := x33v);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component unisim_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component unisim_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component unisim_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component unisim_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component unisim_skew_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end component;
component unisim_clkpad
generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0;
tech : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1'; lock : out std_ulogic);
end component;
component unisim_inpad_ds
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component unisim_iopad_ds
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component unisim_outpad_ds
generic (level : integer := lvds; slew : integer := 0; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component unisim_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component virtex4_inpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component virtex4_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component rh_lib18t_inpad
generic ( voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component rh_lib18t_iopad
generic ( strength : integer := 4);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component rh_lib18t_inpad_ds is
port (padp, padn : in std_ulogic; o : out std_ulogic; en : in std_ulogic);
end component;
component rh_lib18t_outpad_ds is
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component ut025crh_inpad
generic ( level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ut025crh_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component ut025crh_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component ut025crh_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component ut025crh_lvds_combo
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1));
end component;
component ut130hbd_inpad
generic ( level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component ut130hbd_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0;
filter : integer :=0 );
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component ut130hbd_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic);
end component;
component ut130hbd_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component ut130hbd_lvds_combo
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1));
end component;
component ut90nhbd_inpad is
generic (
level : integer := 0;
voltage : integer := 0;
filter : integer := 0);
port (
pad : in std_ulogic;
o : out std_ulogic);
end component;
component ut90nhbd_iopad is
generic(
level : integer := 0;
slew : integer := 0;
voltage : integer := 0;
strength : integer := 0);
port(
pad : inout std_ulogic;
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
slewctrl : in std_ulogic);
end component;
component ut90nhbd_outpad is
generic (
level : integer := 0;
slew : integer := 0;
voltage : integer := 0;
strength : integer := 0);
port(
pad : out std_ulogic;
i : in std_ulogic;
slewctrl : in std_ulogic);
end component;
component ut90nhbd_toutpad is
generic (
level : integer := 0;
slew : integer := 0;
voltage : integer := 0;
strength : integer := 0);
port (
pad : out std_ulogic;
i : in std_ulogic;
en : in std_ulogic;
slewctrl : in std_ulogic);
end component;
component rhumc_lvds_combo
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end component;
component umc_lvds_combo
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end component;
component peregrine_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component peregrine_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component peregrine_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic);
end component;
component nextreme_inpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component nextreme_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component nextreme_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component atc18rha_inpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
component atc18rha_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end component;
component atc18rha_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component atc18rha_odpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end component;
component atc18rha_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end component;
component atc18rha_clkpad
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end component;
constant n2x_padcontrol_bits: integer := 22;
constant n2x_padcontrol_none: std_logic_vector(n2x_padcontrol_bits-1 downto 0) := (others => '0');
component n2x_inpad
generic (level : integer := 0; voltage : integer := x33v; reg : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic;
clk : in std_ulogic := '0'; rstn : in std_ulogic := '0');
end component;
component n2x_iopad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
reg : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic;
compen, compupd: in std_ulogic;
pcomp, ncomp: in std_logic_vector(4 downto 0);
pslew, nslew: in std_logic_vector(3 downto 0);
clk : in std_ulogic := '0'; rstn : in std_ulogic := '0');
end component;
component n2x_outpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12;
reg : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic;
compen, compupd: in std_ulogic;
pcomp, ncomp: in std_logic_vector(4 downto 0);
pslew, nslew: in std_logic_vector(3 downto 0);
clk : in std_ulogic := '0'; rstn : in std_ulogic := '0');
end component;
component n2x_toutpad
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12;
reg : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
compen, compupd: in std_ulogic;
pcomp, ncomp: in std_logic_vector(4 downto 0);
pslew, nslew: in std_logic_vector(3 downto 0);
clk : in std_ulogic := '0'; rstn : in std_ulogic := '0');
end component;
component n2x_inpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component n2x_iopad_ds
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component n2x_outpad_ds
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end component;
component n2x_inpad_ddr
generic (level : integer := 0; voltage : integer := x33v);
port (pad : in std_ulogic; o1, o2 : out std_ulogic; c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component n2x_inpad_ddrv
generic (level : integer := 0; voltage : integer := x33v; width : integer := 1);
port (
pad : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic; ce : in std_ulogic;
r : in std_ulogic; s : in std_ulogic);
end component;
component n2x_sdram_phy
generic (
level : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
aw : integer := 15; -- # address bits
dw : integer := 32; -- # data bits
ncs : integer := 2;
reg : integer := 0); -- 1: include registers on all signals
port (
-- SDRAM interface
addr : out std_logic_vector(aw-1 downto 0);
dq : inout std_logic_vector(dw-1 downto 0);
cke : out std_logic_vector(ncs-1 downto 0);
sn : out std_logic_vector(ncs-1 downto 0);
wen : out std_ulogic;
rasn : out std_ulogic;
casn : out std_ulogic;
dqm : out std_logic_vector(dw/8-1 downto 0);
-- Interface toward memory controller
laddr : in std_logic_vector(aw-1 downto 0);
ldq_din : out std_logic_vector(dw-1 downto 0);
ldq_dout : in std_logic_vector(dw-1 downto 0);
ldq_oen : in std_logic_vector(dw-1 downto 0);
lcke : in std_logic_vector(ncs-1 downto 0);
lsn : in std_logic_vector(ncs-1 downto 0);
lwen : in std_ulogic;
lrasn : in std_ulogic;
lcasn : in std_ulogic;
ldqm : in std_logic_vector(dw/8-1 downto 0);
-- Only used when reg generic is non-zero
rstn : in std_ulogic; -- Registered pads reset
clk : in std_ulogic; -- SDRAM clock for registered pads
-- Optional pad configuration inputs
cfgi_cmd : in std_logic_vector(19 downto 0) := "00000000000000000000"; -- CMD pads
cfgi_dq : in std_logic_vector(19 downto 0) := "00000000000000000000" -- DQ pads
);
end component;
end;
| gpl-2.0 | 4ffa161360ba74a2f8d35fa91c944a6b | 0.632024 | 3.434542 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-terasic-de0-nano/config.vhd | 1 | 6,253 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- SDRAM controller
constant CFG_SDCTRL : integer := 1;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0B#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 1;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (2);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#50000#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- Second GPIO port
constant CFG_GRGPIO2_ENABLE : integer := 1;
constant CFG_GRGPIO2_IMASK : integer := 16#fe#;
constant CFG_GRGPIO2_WIDTH : integer := (32);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | d52e97ab8fb1d8b4ce7c3b994419ddcc | 0.649448 | 3.693444 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/road/simulation/bmg_stim_gen.vhd | 1 | 12,582 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (11 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0):= hex_to_std_logic_vector("0",12);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (99199 downto 0) of std_logic_vector(11 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"road.mif",
DEFAULT_DATA,
12,
99200);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>99200 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(16 DOWNTO 0) <= READ_ADDR(16 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 99200 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit | 854bb8e4f0b2e4d00712b19dc871c6ff | 0.547846 | 3.684334 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/eth/core/greth_pkg.vhd | 1 | 20,055 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
package grethpkg is
--gigabit sync types
type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0);
type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0);
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1500, 16);
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
type ahb_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(4 downto 0);
write : std_ulogic;
data : std_logic_vector(31 downto 0);
waddress : std_logic_vector(4 downto 0);
end record;
type ahb_fifo_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type nchar_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(5 downto 0);
write : std_ulogic;
data : std_logic_vector(8 downto 0);
waddress : std_logic_vector(5 downto 0);
end record;
type nchar_fifo_out_type is record
data : std_logic_vector(8 downto 0);
end record;
type rmapbuf_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(7 downto 0);
write : std_ulogic;
data : std_logic_vector(7 downto 0);
waddress : std_logic_vector(7 downto 0);
end record;
type rmapbuf_out_type is record
data : std_logic_vector(7 downto 0);
end record;
type ahbc_mst_in_type is record
hgrant : std_ulogic; -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type ahbc_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_in_type is record
psel : std_ulogic; -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type gbit_host_tx_type is record
full_duplex : std_ulogic;
start : std_ulogic;
read_ack : std_ulogic;
data : std_logic_vector(31 downto 0);
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type gbit_rx_host_type is record
sync_start : std_ulogic;
done : std_ulogic;
write : std_logic_vector(3 downto 0);
dataout : data_sync_type;
byte_count : std_logic_vector(10 downto 0);
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
end record;
type gbit_host_rx_type is record
full_duplex : std_ulogic;
gbit : std_ulogic;
doneack : std_ulogic;
writeack : std_logic_vector(3 downto 0);
speed : std_ulogic;
writeok : std_logic_vector(3 downto 0);
rxenable : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_gtx_host_type is record
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
read : std_logic_vector(3 downto 0);
status : std_logic_vector(2 downto 0);
end record;
type gbit_host_gtx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
burstmode : std_ulogic;
txen : std_ulogic;
start_sync : std_ulogic;
readack : std_logic_vector(3 downto 0);
valid : std_logic_vector(3 downto 0);
data : data_sync_type;
len : std_logic_vector(10 downto 0);
end record;
type host_tx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
start : std_ulogic;
readack : std_ulogic;
speed : std_ulogic;
data : std_logic_vector(31 downto 0);
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
end record;
type tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type rx_host_type is record
dataout : std_logic_vector(31 downto 0);
start : std_ulogic;
done : std_ulogic;
write : std_ulogic;
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
lentype : std_logic_vector(15 downto 0);
mcasthash : std_logic_vector(5 downto 0);
end record;
type host_rx_type is record
writeack : std_ulogic;
doneack : std_ulogic;
speed : std_ulogic;
writeok : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_crs : std_ulogic;
rx_er : std_ulogic;
enable : std_ulogic;
end record;
component greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end component;
component greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end component;
component eth_rstgen is
generic(acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end component;
component greth_gbit_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in gbit_host_tx_type;
txo : out gbit_tx_host_type);
end component;
component greth_gbit_gtx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
gtxi : in gbit_host_gtx_type;
gtxo : out gbit_gtx_host_type
);
end component;
component greth_gbit_rx is
generic(
multicast : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in gbit_host_rx_type;
rxo : out gbit_rx_host_type);
end component;
component eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type);
end component;
component eth_edcl_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type
);
end component;
function mirror(din : in std_logic_vector) return std_logic_vector;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector;
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer;
function setburstlength(fifosize : in integer) return integer;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector;
end package;
package body grethpkg is
function mirror(din : in std_logic_vector)
return std_logic_vector is
variable do : std_logic_vector(din'range);
begin
for i in 0 to din'length-1 loop
do(din'high-i) := din(i+din'low);
end loop;
return do;
end function;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(16 downto 0);
variable vd2 : std_logic_vector(16 downto 0);
variable sum : std_logic_vector(16 downto 0);
begin
vd1 := '0' & d1; vd2 := '0' & d2;
sum := vd1 + vd2;
sum(15 downto 0) := sum(15 downto 0) + sum(16);
return sum(15 downto 0);
end function;
--16-bit one's complement adder for ip/tcp checksum detection
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(25 downto 0);
variable vd2 : std_logic_vector(25 downto 0);
variable sum : std_logic_vector(25 downto 0);
begin
vd1 := "0000000000" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic is
variable valid : std_ulogic;
begin
valid := '1';
if usesz = '1' then
if len > minpload then
if bcnt /= len then
valid := '0';
end if;
else
if bcnt /= minpload then
valid := '0';
end if;
end if;
end if;
return valid;
end function;
function setburstlength(fifosize : in integer) return integer is
begin
if fifosize <= 64 then
return fifosize/2;
else
return 32;
end if;
end function;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(17 downto 0);
variable vd2 : std_logic_vector(17 downto 0);
variable sum : std_logic_vector(17 downto 0);
begin
vd1 := "00" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
end package body;
| gpl-2.0 | 2b0eec26ae8419887e4c3eadb445da50 | 0.549539 | 3.283399 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-cpci-xc2v6000/leon3mp.vhd | 1 | 31,965 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to 1);
can_rxd : in std_logic_vector(0 to 1);
can_stb : out std_logic_vector(0 to 1);
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal can_lrx, can_ltx : std_logic;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 40000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_SDCTRL+CFG_CAN+CFG_PCI;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ, CFG_SPW_EN)
port map (lclk, pci_lclk, clkm, open, spw_lclk, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg1 : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0,
ramws => CFG_SRCTRL_RAMWS, romws => CFG_SRCTRL_PROMWS,
ramaddr => 16#400#, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sd1 : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data(31 downto 0), sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data(63 downto 32), sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm(7 downto 0));
end generate;
-- sdsn : if (CFG_SDEN = 0) or (CFG_MEMC = 2) generate ahbso(3) <= ahbs_none; end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, sden => CFG_MCTRL_SDEN,
invclk => CFG_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mg0 : if (CFG_SRCTRL + CFG_MCTRL_LEON2) = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, vcc);
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, vcc(1 downto 0));
end generate;
mgpads : if (CFG_SRCTRL + CFG_MCTRL_LEON2) /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
j2u : if CFG_AHB_UART = 0 generate
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, u1i.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, u1o.txd);
end generate;
j1u : if CFG_AHB_UART = 1 generate
rxd_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
rxd_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
txd_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
-- nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
-- nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
-- nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
-- notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
-- ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb(0) <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(0), can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(0), can_lrx);
end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => fabtech,
hindex => maxahbmsp+i, pindex => 10+i, paddr => 10+i, pirq => 10+i,
sysfreq => cpu_freq, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT,
netlist => CFG_SPW_NETLIST, ports => 1, dmachan => CFG_SPW_DMACHAN,
memtech => memtech, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME, rxunaligned => CFG_SPW_RXUNAL)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ*2/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-CPCI-XC2V6000 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | d62db2d90df3109c66471d1d97cbad18 | 0.56346 | 3.415429 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/grfpwx.vhd | 1 | 4,312 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwx
-- File: grfpwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity grfpwx is
generic (fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 3 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end;
architecture rtl of grfpwx is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
signal rf1rd1, rf1rd2, rf2rd1, rf2rd2, rf1wd, rf2wd : std_logic_vector(38 downto 0);
begin
x1 : if true generate
grfpw0 : grfpw_net generic map (fabtech, pclow, dsu, disas)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
rf1 : regfile_3p_l3 generic map (memtech, 4, 32, 1, 16
)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr,
rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2
);
rf2 : regfile_3p_l3 generic map (memtech, 4, 32, 1, 16
)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr,
rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2
);
end;
| gpl-2.0 | bce0e409cb177b8013dd7102a757dc5f | 0.507885 | 3.350427 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/score/simulation/score_synth.vhd | 1 | 6,814 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: score_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY score_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE score_synth_ARCH OF score_synth IS
COMPONENT score_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: score_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | 1ddef06626fca1766aec702418d3774c | 0.579689 | 3.810962 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_mm2s_basic_wrap.vhd | 5 | 43,235 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_reset;
use axi_sg_v4_1.axi_sg_cmd_status;
use axi_sg_v4_1.axi_sg_scc;
use axi_sg_v4_1.axi_sg_addr_cntl;
use axi_sg_v4_1.axi_sg_rddata_cntl;
use axi_sg_v4_1.axi_sg_rd_status_cntl;
use axi_sg_v4_1.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
| gpl-3.0 | 3f82d95b3a7d4eaf60bad2fcf3d0de91 | 0.443553 | 4.121151 | false | false | false | false |
mistryalok/Zedboard | learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/coregen_comp_defs.vhd | 4 | 13,824 | -------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: coregen_comp_defs.vhd
-- Version: initial
-- Description:
-- Component declarations for all black box netlists generated by
-- running COREGEN and AXI BRAM CTRL when XST elaborated the client core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- coregen_comp_defs.vhd
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE coregen_comp_defs IS
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v8_2
-- Component declaration for blk_mem_gen_v8_2 pulled from the blk_mem_gen_v8_2.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v8_2
generic (
----------------------------------------------------------------------------
-- Generic Declarations
----------------------------------------------------------------------------
--Device Family & Elaboration Directory Parameters:
C_FAMILY : STRING := "virtex4";
C_XDEVICEFAMILY : STRING := "virtex4";
-- C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_AXI_TYPE : INTEGER := 1;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
--General Memory Parameters:
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 9;
C_ALGORITHM : INTEGER := 0;
C_PRIM_TYPE : INTEGER := 3;
--Memory Initialization Parameters:
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "111111111";
C_RST_TYPE : STRING := "SYNC";
--Port A Parameters:
--Reset Parameters:
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_A : INTEGER := 4;
C_READ_WIDTH_A : INTEGER := 4;
C_WRITE_DEPTH_A : INTEGER := 4096;
C_READ_DEPTH_A : INTEGER := 4096;
C_ADDRA_WIDTH : INTEGER := 12;
--Port B Parameters:
--Reset Parameters:
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_B : INTEGER := 4;
C_READ_WIDTH_B : INTEGER := 4;
C_WRITE_DEPTH_B : INTEGER := 4096;
C_READ_DEPTH_B : INTEGER := 4096;
C_ADDRB_WIDTH : INTEGER := 12;
--Output Registers/ Pipelining Parameters:
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
--Input/Output Registers for SoftECC :
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
--ECC Parameters
C_USE_ECC : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
--Simulation Model Parameters:
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 0;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
----------------------------------------------------------------------------
-- Input and Output Declarations
----------------------------------------------------------------------------
-- Native BMG Input and Output Port Declarations
--Port A:
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '0';
REGCEA : IN STD_LOGIC := '0';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
--Port B:
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '0';
REGCEB : IN STD_LOGIC := '0';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
--ECC:
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT; --blk_mem_gen_v8_2
END coregen_comp_defs;
| gpl-3.0 | 0d682b195773db490e1ef6715d1bdbbd | 0.42947 | 4.494148 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/misc/grgpio.vhd | 1 | 11,578 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grgpio
-- File: grgpio.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Scalable general-purpose I/O port
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity grgpio is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0; -- Only synchronous reset
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#;
pirq : integer := 0;
irqgen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end;
architecture rtl of grgpio is
constant REVISION : integer := 2;
constant PIMASK : std_logic_vector(31 downto 0) := '0' & conv_std_logic_vector(imask, 31);
constant BPMASK : std_logic_vector(31 downto 0) := conv_std_logic_vector(bypass, 32);
constant BPDIRM : std_logic_vector(31 downto 0) := conv_std_logic_vector(bpdir, 32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GPIO, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
-- Prevent tools from issuing index errors for unused code
function calc_nirqmux return integer is
begin
if irqgen = 0 then return 1; end if;
return irqgen;
end;
constant NIRQMUX : integer := calc_nirqmux;
subtype irqmap_type is std_logic_vector(log2x(NIRQMUX)-1 downto 0);
type irqmap_array_type is array (natural range <>) of irqmap_type;
type registers is record
din1 : std_logic_vector(nbits-1 downto 0);
din2 : std_logic_vector(nbits-1 downto 0);
dout : std_logic_vector(nbits-1 downto 0);
imask : std_logic_vector(nbits-1 downto 0);
level : std_logic_vector(nbits-1 downto 0);
edge : std_logic_vector(nbits-1 downto 0);
ilat : std_logic_vector(nbits-1 downto 0);
dir : std_logic_vector(nbits-1 downto 0);
bypass : std_logic_vector(nbits-1 downto 0);
irqmap : irqmap_array_type(nbits-1 downto 0);
end record;
constant nbitszero : std_logic_vector(nbits-1 downto 0) := (others => '0');
constant irqmapzero : irqmap_array_type(nbits-1 downto 0) := (others => (others => '0'));
function dirzero_func return std_logic_vector is
variable vres : std_logic_vector(nbits-1 downto 0);
begin
vres := (others => '0');
if oepol = 0 then vres := (others => '1'); end if;
return vres;
end function dirzero_func;
constant dirzero : std_logic_vector(nbits-1 downto 0) := dirzero_func;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : registers := (
din1 => nbitszero, din2 => nbitszero, -- Sync. regs, not reset
dout => nbitszero,imask => nbitszero, level => nbitszero, edge => nbitszero,
ilat => nbitszero, dir => dirzero, bypass => nbitszero, irqmap => irqmapzero);
signal r, rin : registers;
signal arst : std_ulogic;
begin
arst <= apbi.testrst when (scantest = 1) and (apbi.testen = '1') else rst;
comb : process(rst, r, apbi, gpioi)
variable readdata, tmp2, dout, dir, pval, din : std_logic_vector(31 downto 0);
variable v : registers;
variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
din := (others => '0');
din(nbits-1 downto 0) := gpioi.din(nbits-1 downto 0);
v := r; v.din2 := r.din1; v.din1 := din(nbits-1 downto 0);
v.ilat := r.din2; dout := (others => '0'); dir := (others => '0');
dir(nbits-1 downto 0) := r.dir(nbits-1 downto 0);
if (syncrst = 1) and (rst = '0') then
if oepol = 0 then dir(nbits-1 downto 0) := (others => '1');
else dir(nbits-1 downto 0) := (others => '0'); end if;
end if;
dout(nbits-1 downto 0) := r.dout(nbits-1 downto 0);
-- read registers
readdata := (others => '0');
case apbi.paddr(5 downto 2) is
when "0000" => readdata(nbits-1 downto 0) := r.din2;
when "0001" => readdata(nbits-1 downto 0) := r.dout;
when "0010" =>
if oepol = 0 then readdata(nbits-1 downto 0) := not r.dir;
else readdata(nbits-1 downto 0) := r.dir; end if;
when "0011" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.imask(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0100" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.level(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0101" =>
if (imask /= 0) then
readdata(nbits-1 downto 0) :=
r.edge(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0110" =>
if (bypass /= 0) then
readdata(nbits-1 downto 0) :=
r.bypass(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when "0111" =>
readdata(12 downto 8) := conv_std_logic_vector(irqgen, 5);
readdata(4 downto 0) := conv_std_logic_vector(nbits-1, 5);
when others =>
if irqgen > 1 then
for i in 0 to (nbits+3)/4-1 loop
if i = conv_integer(apbi.paddr(4 downto 2)) then
for j in 0 to 3 loop
if (j+i*4) > (nbits-1) then
exit;
end if;
readdata((24+log2x(NIRQMUX)-1-j*8) downto (24-j*8)) := r.irqmap(i*4+j);
end loop;
end if;
end loop;
end if;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" => null;
when "0001" => v.dout := apbi.pwdata(nbits-1 downto 0);
when "0010" =>
if oepol = 0 then v.dir := not apbi.pwdata(nbits-1 downto 0);
else v.dir := apbi.pwdata(nbits-1 downto 0); end if;
when "0011" =>
if (imask /= 0) then
v.imask := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0100" =>
if (imask /= 0) then
v.level := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0101" =>
if (imask /= 0) then
v.edge := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
end if;
when "0110" =>
if (bypass /= 0) then
v.bypass := apbi.pwdata(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
end if;
when "0111" =>
null;
when others =>
if irqgen > 1 then
for i in 0 to (nbits+3)/4-1 loop
if i = conv_integer(apbi.paddr(4 downto 2)) then
for j in 0 to 3 loop
if (j+i*4) > (nbits-1) then
exit;
end if;
v.irqmap(i*4+j) := apbi.pwdata((24+log2x(NIRQMUX)-1-j*8) downto (24-j*8));
end loop;
end if;
end loop;
end if;
end case;
end if;
-- interrupt filtering and routing
xirq := (others => '0'); tmp2 := (others => '0');
if (imask /= 0) then
tmp2(nbits-1 downto 0) := r.din2;
for i in 0 to nbits-1 loop
if (PIMASK(i) and r.imask(i)) = '1' then
if r.edge(i) = '1' then
if r.level(i) = '1' then tmp2(i) := r.din2(i) and not r.ilat(i);
else tmp2(i) := not r.din2(i) and r.ilat(i); end if;
else tmp2(i) := r.din2(i) xor not r.level(i); end if;
else
tmp2(i) := '0';
end if;
end loop;
for i in 0 to nbits-1 loop
if irqgen = 0 then
-- IRQ for line i = i + pirq
if (i+pirq) > NAHBIRQ-1 then
exit;
end if;
xirq(i+pirq) := tmp2(i);
else
-- IRQ for line i determined by irq select register i
for j in 0 to NIRQMUX-1 loop
if (j+pirq) > NAHBIRQ-1 then
exit;
end if;
if (irqgen = 1) or (j = conv_integer(r.irqmap(i))) then
xirq(j+pirq) := xirq(j+pirq) or tmp2(i);
end if;
end loop;
end if;
end loop;
end if;
-- drive filtered inputs on the output record
pval := (others => '0');
pval(nbits-1 downto 0) := r.din2;
-- Drive output with gpioi.sig_in for bypassed registers
if bypass /= 0 then
for i in 0 to nbits-1 loop
if r.bypass(i) = '1' then
dout(i) := gpioi.sig_in(i);
end if;
end loop;
end if;
-- Drive output with gpioi.sig_in for bypassed registers
if bpdir /= 0 then
for i in 0 to nbits-1 loop
if (BPDIRM(i) and gpioi.sig_en(i)) = '1' then
dout(i) := gpioi.sig_in(i);
if oepol = 0 then dir(i) := '0'; else dir(i) := '1'; end if;
end if;
end loop;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.imask := RES.imask; v.bypass := RES.bypass;
v.dir := RES.dir; v.dout := RES.dout;
v.irqmap := RES.irqmap;
end if;
if irqgen < 2 then v.irqmap := (others => (others => '0')); end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= xirq;
if (scantest = 1) and (apbi.testen = '1') then
dir := (others => apbi.testoen);
elsif (syncrst = 1 ) and (rst = '0') then
if oepol = 1 then dir := (others => '0');
else dir := (others => '1'); end if;
end if;
gpioo.dout <= dout;
gpioo.oen <= dir;
gpioo.val <= pval;
-- non filtered input
gpioo.sig_out <= din;
end process;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk, arst)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers din1 and din2 not reset
r.din1 <= rin.din1;
r.din2 <= rin.din2;
end if;
end if;
if (syncrst = 0 ) and (arst = '0') then
if oepol = 1 then r.dir <= (others => '0');
else r.dir <= (others => '1'); end if;
end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("grgpio" & tost(pindex) &
": " & tost(nbits) & "-bit GPIO Unit rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 | 92acd87f143ed9bd7162a86f2faf96f9 | 0.567369 | 3.329882 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_ftch_mngr.vhd | 4 | 25,954 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_mngr.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_nxtdesc_wren : in std_logic ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_nxtdesc_wren : in std_logic ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_eof_detected : in std_logic ;
tail_updt : in std_logic ;
tail_updt_latch : out std_logic ;
ch2_sg_idle : out std_logic ;
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
--
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
bd_eq : out std_logic
);
end axi_sg_ftch_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_cmnd_wr_i : std_logic := '0';
signal ftch_cmnd_data_i : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal ch1_sg_idle : std_logic := '0';
signal ch1_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_sg_idle_int : std_logic := '0';
signal ch2_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ftch_done : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal ftch_interr : std_logic := '0';
signal ftch_slverr : std_logic := '0';
signal ftch_decerr : std_logic := '0';
signal ftch_error_early : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_cmnd_wr <= ftch_cmnd_wr_i;
ftch_cmnd_data <= ftch_cmnd_data_i;
ftch_error <= ftch_error_i;
ch2_sg_idle <= ch2_sg_idle_int;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_FTCH_SG : entity axi_sg_v4_1.axi_sg_ftch_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
updt_error => updt_error ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_updt_done => ch1_updt_done ,
ch1_desc_flush => ch1_desc_flush ,
ch1_sg_idle => ch1_sg_idle ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_fetch_address => ch1_fetch_address ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_updt_done => ch2_updt_done ,
ch2_desc_flush => ch2_desc_flush ,
ch2_sg_idle => ch2_sg_idle_int ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_fetch_address => ch2_fetch_address ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_ftch_pause => ch2_ftch_pause ,
-- Transfer Request
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Transfer Status
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_stale_desc => ftch_stale_desc ,
ftch_error_addr => ftch_error_addr ,
ftch_error_early => ftch_error_early
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Pointer Manager
-------------------------------------------------------------------------------
I_FTCH_PNTR_MNGR : entity axi_sg_v4_1.axi_sg_ftch_pntr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
nxtdesc => nxtdesc ,
-------------------------------
-- CHANNEL 1
-------------------------------
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch1_curdesc => ch1_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch1_fetch_address => ch1_fetch_address ,
ch1_sg_idle => ch1_sg_idle ,
-------------------------------
-- CHANNEL 2
-------------------------------
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,--CR568950
ch2_eof_detected => ch2_eof_detected ,
-- CURDESC update on run/stop assertion (from ftch_sm)
ch2_curdesc => ch2_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
tail_updt_latch => tail_updt_latch ,
tail_updt => tail_updt ,
ch2_updt_done => ch2_updt_done ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch2_fetch_address => ch2_fetch_address ,
ch2_sg_idle => ch2_sg_idle_int ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_FTCH_CMDSTS_IF : entity axi_sg_v4_1.axi_sg_ftch_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Scatter Gather Fetch Status
mm2s_err => mm2s_err ,
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_error_early => ftch_error_early
);
end implementation;
| gpl-3.0 | 2c02963c444af31b925d3b8dba4c83d7 | 0.357324 | 5.124186 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-pci-xc2v3000/leon3mp.vhd | 1 | 26,983 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
spw_rxd : in std_logic_vector(0 to 1);
spw_rxs : in std_logic_vector(0 to 1);
spw_txd : out std_logic_vector(0 to 1);
spw_txs : out std_logic_vector(0 to 1)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal resetnl, clk2x, spw_clkl : std_logic;
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
constant IOAEN : integer := 0;
constant sysfreq : integer := (CFG_CLKMUL*40000/CFG_CLKDIV);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, sysfreq)
port map (lclk, pci_lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech)
port map (sdclk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, resetnl);
rst0 : rstgen -- reset generator
port map (resetnl, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mctrl2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 8, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(8));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(8) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 8)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#, irq => 4,
ioaddr => 16#400#, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, irq => 4)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 0)-- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => sysfreq/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw_clkl <= clk2x;
spw : if CFG_SPW_EN > 0 generate
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, rmap => CFG_SPW_RMAP,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT,
netlist => CFG_SPW_NETLIST, ports => 1, dmachan => CFG_SPW_DMACHAN,
spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME, rxunaligned => CFG_SPW_RXUNAL)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(2*sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad generic map (padtech)
port map (spw_rxd(i), dtmp(i));
spw_rxs_pad : inpad generic map (padtech)
port map (spw_rxs(i), stmp(i));
spw_txd_pad : outpad generic map (padtech)
port map (spw_txd(i), spwo(i).d(0));
spw_txs_pad : outpad generic map (padtech)
port map (spw_txs(i), spwo(i).s(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-PCI-XC2V3000 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 758631d1df4b7a28ac872aaf9fbfaa54 | 0.557129 | 3.482127 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/explosion/example_design/explosion_exdes.vhd | 1 | 4,342 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: explosion_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY explosion_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END explosion_exdes;
ARCHITECTURE xilinx OF explosion_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT explosion IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : explosion
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | 3f4170f34e80f21ffc9cc907e56d095a | 0.576232 | 4.862262 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_timer_0_0/sim/design_1_axi_timer_0_0.vhd | 1 | 8,492 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_timer_v2_0;
USE axi_timer_v2_0.axi_timer;
ENTITY design_1_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END design_1_axi_timer_0_0;
ARCHITECTURE design_1_axi_timer_0_0_arch OF design_1_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "zynq",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END design_1_axi_timer_0_0_arch;
| gpl-3.0 | d851560294d2e2631956b4dbf18fc53c | 0.68488 | 3.344624 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/grlib/sparc/cpu_disas.vhd | 1 | 4,306 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: cpu_disas
-- File: cpu_disas.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
entity cpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of cpu_disas is
begin
dummy <= '1';
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1'); --and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') then
print_insn (iindex, pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
entity fpu_disas is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
wr2inst : in std_logic_vector(31 downto 0);
wr2pc : in std_logic_vector(31 downto 2);
divinst : in std_logic_vector(31 downto 0);
divpc : in std_logic_vector(31 downto 2);
dbg_wrdata: in std_logic_vector(63 downto 0);
index : in std_logic_vector(3 downto 0);
dbg_wren : in std_logic_vector(1 downto 0);
resv : in std_ulogic;
ld : in std_ulogic;
rdwr : in std_ulogic;
ccwr : in std_ulogic;
rdd : in std_ulogic;
div_valid : in std_ulogic;
holdn : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of fpu_disas is
begin
dummy <= '1';
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
if rising_edge(clk) and (rstn = '1') then
valid := ((((rdwr and not ld) or ccwr or (ld and resv)) and holdn) = '1');
print_fpinsn(0, wr2pc(31 downto 2) & "00", wr2inst, dbg_wrdata,
(rdd = '1'), valid, false, (dbg_wren /= "00"));
print_fpinsn(0, divpc(31 downto 2) & "00", divinst, dbg_wrdata,
(rdd = '1'), (div_valid and holdn) = '1', false, (dbg_wren /= "00"));
end if;
end process;
end;
-- pragma translate_on
| gpl-2.0 | 7a7e60d3cc991660debfe28ee36c909d | 0.603344 | 3.4448 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/srmmu/mmutw.vhd | 1 | 10,326 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutw
-- File: mmutw.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU table-walk logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutw is
generic (
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end mmutw;
architecture rtl of mmutw is
type write_buffer_type is record -- write buffer
addr, data : std_logic_vector(31 downto 0);
read : std_logic;
end record;
constant write_buffer_none : write_buffer_type := (
addr => (others => '0'), data => (others => '0'), read => '0');
type states is (idle, waitm, pte, lv1, lv2, lv3, lv4);
type tw_rtype is record
state : states;
wb : write_buffer_type;
req : std_logic;
walk_op : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : tw_rtype := (
state => idle,
wb => write_buffer_none,
req => '0',
walk_op => '0');
signal c,r : tw_rtype;
begin
p0: process (rst, r, twi, mcmmo, mmctrl1)
variable v : tw_rtype;
variable finish : std_logic;
variable index : std_logic_vector(31-2 downto 0);
variable lvl : std_logic_vector(1 downto 0);
variable fault_mexc : std_logic;
variable fault_trans : std_logic;
variable fault_inv : std_logic;
variable fault_lvl : std_logic_vector(1 downto 0);
variable pte,ptd,inv,rvd : std_logic;
variable goon, found : std_logic;
variable base : std_logic_vector(31 downto 0);
variable pagesize : integer range 0 to 3;
begin
v := r;
--#init
finish := '0';
index := (others => '0');
lvl := (others => '0');
fault_mexc := '0';
fault_trans := '0';
fault_inv := '0';
fault_lvl := (others => '0');
pte := '0';ptd := '0';inv := '0';rvd := '0';
goon := '0'; found := '0';
base := (others => '0');
base(PADDR_PTD_U downto PADDR_PTD_D) := mcmmo.data(PTD_PTP32_U downto PTD_PTP32_D);
if mcmmo.grant = '1' then
v.req := '0';
end if;
if mcmmo.retry = '1' then v.req := '1'; end if;
-- # pte/ptd
if ((mcmmo.ready and not r.req)= '1') then -- context
case mcmmo.data(PT_ET_U downto PT_ET_D) is
when ET_INV => inv := '1';
when ET_PTD => ptd := '1'; goon := '1';
when ET_PTE => pte := '1'; found := '1';
when ET_RVD => rvd := '1'; null;
when others => null;
end case;
end if;
fault_trans := (rvd);
fault_inv := inv;
pagesize := MMU_getpagesize(mmupgsz,mmctrl1);
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
when others => -- standard 4k tag comparision [ 8 6 6 ]
end case;
-- # state machine
case r.state is
when idle =>
if (twi.walk_op_ur) = '1' then
v.walk_op := '1';
index(M_CTX_SZ-1 downto 0) := mmctrl1.ctx;
base := (others => '0');
base(PADDR_PTD_U downto PADDR_PTD_D) := mmctrl1.ctxp(MMCTRL_PTP32_U downto MMCTRL_PTP32_D);
v.wb.addr := base or (index&"00");
v.wb.read := '1';
v.req := '1';
v.state := lv1;
elsif (twi.areq_ur) = '1' then
index := (others => '0');
v.wb.addr := twi.aaddr;
v.wb.data := twi.adata;
v.wb.read := '0';
v.req := '1';
v.state := waitm;
end if;
when waitm =>
if ((mcmmo.ready and not r.req)= '1') then -- amba: result ready current cycle
fault_mexc := mcmmo.mexc;
v.state := idle;
finish := '1';
end if;
when lv1 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_CTX; fault_lvl := FS_L_CTX;
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
index(P8K_VA_I1_SZ-1 downto 0) := twi.data(P8K_VA_I1_U downto P8K_VA_I1_D);
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
index(P16K_VA_I1_SZ-1 downto 0) := twi.data(P16K_VA_I1_U downto P16K_VA_I1_D);
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
index(P32K_VA_I1_SZ-1 downto 0) := twi.data(P32K_VA_I1_U downto P32K_VA_I1_D);
when others =>
-- standard 4k tag comparision [ 8 6 6 ]
index(VA_I1_SZ-1 downto 0) := twi.data(VA_I1_U downto VA_I1_D);
end case;
v.state := lv2;
end if;
when lv2 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_REGION; fault_lvl := FS_L_L1;
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
index(P8K_VA_I2_SZ-1 downto 0) := twi.data(P8K_VA_I2_U downto P8K_VA_I2_D);
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
index(P16K_VA_I2_SZ-1 downto 0) := twi.data(P16K_VA_I2_U downto P16K_VA_I2_D);
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
index(P32K_VA_I2_SZ-1 downto 0) := twi.data(P32K_VA_I2_U downto P32K_VA_I2_D);
when others =>
-- standard 4k tag comparision [ 8 6 6 ]
index(VA_I2_SZ-1 downto 0) := twi.data(VA_I2_U downto VA_I2_D);
end case;
v.state := lv3;
end if;
when lv3 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_SEGMENT; fault_lvl := FS_L_L2;
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
index(P8K_VA_I3_SZ-1 downto 0) := twi.data(P8K_VA_I3_U downto P8K_VA_I3_D);
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
index(P16K_VA_I3_SZ-1 downto 0) := twi.data(P16K_VA_I3_U downto P16K_VA_I3_D);
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
index(P32K_VA_I3_SZ-1 downto 0) := twi.data(P32K_VA_I3_U downto P32K_VA_I3_D);
when others =>
-- standard 4k tag comparision [ 8 6 6 ]
index(VA_I3_SZ-1 downto 0) := twi.data(VA_I3_U downto VA_I3_D);
end case;
v.state := lv4;
end if;
when lv4 =>
if ((mcmmo.ready and not r.req)= '1') then
lvl := LVL_PAGE; fault_lvl := FS_L_L3;
fault_trans := fault_trans or ptd;
v.state := idle;
finish := '1';
end if;
when others =>
v.state := idle;
finish := '0';
end case;
base := base or (index&"00");
if r.walk_op = '1' then
if (mcmmo.ready and (not r.req)) = '1' then
fault_mexc := mcmmo.mexc;
if (( ptd and
(not fault_mexc ) and
(not fault_trans) and
(not fault_inv )) = '1') then -- tw : break table walk?
v.wb.addr := base;
v.req := '1';
else
v.walk_op := '0';
finish := '1';
v.state := idle;
end if;
end if;
end if;
-- # reset
if (not RESET_ALL) and ( rst = '0' ) then
v.state := RRES.state;
v.req := RRES.req;
v.walk_op := RRES.walk_op;
v.wb.read := RRES.wb.read;
end if;
--# drive signals
two.finish <= finish;
two.data <= mcmmo.data;
two.addr <= r.wb.addr(31 downto 0);
two.lvl <= lvl;
two.fault_mexc <= fault_mexc;
two.fault_trans <= fault_trans;
two.fault_inv <= fault_inv;
two.fault_lvl <= fault_lvl;
mcmmi.address <= r.wb.addr;
mcmmi.data <= r.wb.data;
mcmmi.burst <= '0';
mcmmi.size <= "10";
mcmmi.read <= r.wb.read;
mcmmi.lock <= '0';
mcmmi.req <= r.req;
c <= v;
end process p0;
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end rtl;
| gpl-2.0 | e3fa08c2a0e8aa1514c9d2b5177324bb | 0.476758 | 3.490872 | false | false | false | false |
capitanov/Stupid_watch | src/rtl/pwm_test/ctrl_pwm.vhd | 1 | 3,817 | --------------------------------------------------------------------------------
--
-- Title : ctrl_pwm.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Pulse-width modulation
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ctrl_pwm is
port (
clk : in std_logic; --! clock
rst : in std_logic; --! reset
rst_reg : in std_logic; --! count reset
zoom_reg : in std_logic; --! switch change
zoom_cnt : in std_logic; --! switch counter
log_led : out std_logic --! pulsed LED enable
);
end ctrl_pwm;
architecture ctrl_pwm of ctrl_pwm is
constant Nmax : integer:=19;
constant Ncnt : integer:=13;
signal cnt_dec : std_logic_vector(Ncnt downto 0);
signal thrsh : std_logic_vector(Ncnt downto 0);
signal cnt_big : std_logic_vector(Nmax downto 0);
signal zoom_regz : std_logic;
signal front_reg : std_logic;
signal zoom_cntz : std_logic;
signal front_cnt : std_logic;
signal switch_reg : std_logic_vector(2 downto 0);
signal switch_cnt : std_logic_vector(2 downto 0);
begin
zoom_cntz <= zoom_cnt when rising_edge(clk);
zoom_regz <= zoom_reg when rising_edge(clk);
front_reg <= zoom_reg and not zoom_regz after 1 ns when rising_edge(clk);
front_cnt <= zoom_cnt and not zoom_cntz after 1 ns when rising_edge(clk);
pr_switch: process(clk, rst) is
begin
if rst = '0' then
switch_reg <= (others => '0');
switch_cnt <= (others => '0');
elsif rising_edge(clk) then
-- if rst_reg = '0' then
-- switch_reg <= (others => '0');
-- switch_cnt <= (others => '0');
-- else
if front_reg = '1' then
switch_reg <= switch_reg + '1';
else
null;
end if;
if front_cnt = '1' then
switch_cnt <= switch_cnt + '1';
else
null;
end if;
-- end if;
end if;
end process;
pr_case_cnt: process(clk, rst) is
begin
if rst = '0' then
cnt_dec <= (others => '0');
elsif rising_edge(clk) then
-- if rst_reg = '0' then
-- cnt_dec <= (others => '0') after 1 ns;
-- else
if cnt_dec(Ncnt) = '0' then
cnt_dec <= cnt_dec + '1' after 1 ns;
else
cnt_dec <= (others => '0') after 1 ns;
-- end if;
end if;
end if;
end process;
pr_thrs: process(clk, rst) is
begin
if rst = '0' then
thrsh <= (others => '0');
elsif rising_edge(clk) then
-- if rst_reg = '0' then
-- thrsh <= (others => '0') after 1 ns;
-- else
if cnt_big(Nmax) = '1' then
if thrsh(Ncnt) = '1' then
thrsh <= (others => '0') after 1 ns;
else
thrsh <= thrsh + '1' after 1 ns;
end if;
else
null;
end if;
-- end if;
end if;
end process;
pr_case_reg: process(clk, rst) is
begin
if rst = '0' then
cnt_big <= (others => '0');
elsif rising_edge(clk) then
-- if rst_reg = '0' then
-- cnt_big <= (others => '0') after 1 ns;
-- else
if cnt_big(Nmax) = '0' then
case switch_cnt is
when "000" => cnt_big <= cnt_big + '1' after 1 ns;
when "001" => cnt_big <= cnt_big + "10" after 1 ns;
when "010" => cnt_big <= cnt_big + "100" after 1 ns;
when "011" => cnt_big <= cnt_big + "1000" after 1 ns;
when "100" => cnt_big <= cnt_big + "1100" after 1 ns;
when "101" => cnt_big <= cnt_big + "10000" after 1 ns;
when "110" => cnt_big <= cnt_big + "10100" after 1 ns;
when others => cnt_big <= cnt_big + "11100" after 1 ns;
end case;
else
cnt_big <= (others => '0') after 1 ns;
end if;
-- end if;
end if;
end process;
log_led <= '0' when unsigned(cnt_dec) < unsigned(thrsh) else '1';
end ctrl_pwm; | mit | cdfef379c072ef8db129f4b475ebfa64 | 0.539167 | 2.78207 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/spi/spi2ahb.vhd | 1 | 2,940 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb
-- File: spi2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.spi.all;
entity spi2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb;
architecture rtl of spi2ahb is
signal spi2ahbi : spi2ahb_in_type;
begin
bridge : spi2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter,
cpol => cpol,
cpha => cpha)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
spii => spii,
spio => spio,
spi2ahbi => spi2ahbi,
spi2ahbo => open);
spi2ahbi.en <= '1';
spi2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
spi2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
end architecture rtl;
| gpl-2.0 | 8512731343275582416064bb8b6a0e1c | 0.567687 | 3.89404 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_afifo_autord.vhd | 4 | 15,519 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0;
use lib_fifo_v1_0.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read : std_logic := '0';
Signal first_read1 : std_logic := '0';
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
process (AFIFO_Rd_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_read <= '0';
first_read1 <= '0';
elsif (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (sig_afifo_empty = '0') then
first_read <= first_write;
first_read1 <= first_read;
end if;
end if;
end process;
autoread <= first_read xor first_read1;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
| gpl-3.0 | e24158109f6af06d7144646060b7cc52 | 0.475546 | 4.209113 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/grpci1/pcidma.vhd | 1 | 4,065 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_dma
-- File: pci_dma.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: PCI master and target interface with DMA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use gaisler.pcilib.all;
entity pcidma is
generic (
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
dapbirq : integer := 0;
blength : integer := 16;
mstndx : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0; -- 0 little, 1 big
class_code: integer := 16#0B4000#;
rev : integer := 0;
irq : integer := 0;
irqmask : integer := 0;
scanen : integer := 0;
hostrst : integer := 0;
syncrst : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of pcidma is
signal ahbsi2 : ahb_slv_in_type;
signal ahbso2 : ahb_slv_out_type;
begin
dma : dmactrl generic map (hindex => dmstndx, slvindex => slvndx, pindex => dapbndx,
paddr => dapbaddr, pirq => dapbirq, blength => blength)
port map (rst, clk, apbi, dapbo, ahbmi, dahbmo, ahbsi, ahbso, ahbsi2, ahbso2);
pci : pci_mtf generic map (memtech => memtech, hmstndx => mstndx, dmamst => dmstndx,
fifodepth => fifodepth, device_id => device_id, vendor_id => vendor_id,
hslvndx => slvndx, pindex => apbndx, paddr => apbaddr, irq => irq, irqmask => irqmask,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, abits => abits, syncrst => syncrst,
dmaabits => dmaabits, nsync => nsync, oepol => oepol, endian => endian,
class_code => class_code, rev => rev, scanen => scanen, hostrst => hostrst)
port map (rst, clk, pciclk, pcii, pcio, apbi, apbo, ahbmi, ahbmo, ahbsi2, ahbso2);
end;
| gpl-2.0 | 69690d621896affa93767c7a0caacebc | 0.585732 | 3.722527 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_wrdata_cntl.vhd | 5 | 91,465 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_sg_wrdata_cntl;
architecture implementation of axi_sg_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
-- coverage off
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-- coverage on
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_s2mm_strm_wready_del : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
-- sig_s2mm_strm_wready_del;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
sig_s2mm_strm_wready_del <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
sig_s2mm_strm_wready_del <= sig_s2mm_strm_wready;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= (others => '1') when mmap_reset = '0' else (others => '0'); --sig_strt_strb_reg
-- data2skid_wstrb <= sig_strt_strb_reg
-- When (sig_first_dbeat = '1')
-- Else sig_last_strb_reg
-- When (sig_last_dbeat = '1')
-- Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
-- coverage off
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
-- coverage on
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
-- coverage off
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
-- coverage on
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
-- GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
--
-- -- local constants
-- Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
-- Constant NUM_ZEROS_WIDTH : integer := 8;
-- Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
-- Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
-- funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
--
-- Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
--
--
--
-- -- local signals
-- signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
-- signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
-- signal lsig_ld_byte_cntr : std_logic := '0';
-- signal lsig_incr_byte_cntr : std_logic := '0';
-- signal lsig_clr_byte_cntr : std_logic := '0';
-- signal lsig_end_of_cmd_reg : std_logic := '0';
-- signal lsig_eop_s_h_reg : std_logic := '0';
-- signal lsig_eop_reg : std_logic := '0';
-- signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
--
--
--
--
-- begin
--
--
-- -- Assign the outputs to the Write Status Controller
-- data2wsc_eop <= lsig_eop_reg and
-- not(sig_next_calc_error_reg);
--
-- data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
--
--
--
-- -- WRSTRB logic ------------------------------
--
--
--
-- --sig_strbgen_bytes <= (others => '1'); -- set to the max value
--
--
-- -- set the length to the max number of bytes per databeat
-- sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
--
--
--
--
--
--
-- sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
-- STRBGEN_ADDR_SLICE_WIDTH)) ;
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_STRT_STRB_GEN
-- --
-- -- Description:
-- -- Strobe generator used to generate the starting databeat
-- -- strobe value for soft shutdown case where the S2MM has to
-- -- flush out all of the transfers that have been committed
-- -- to the AXI Write address channel. Starting Strobes must
-- -- match the committed address offest for each transfer.
-- --
-- ------------------------------------------------------------
-- I_STRT_STRB_GEN : entity axi_sg_v4_1.axi_sg_strb_gen2
-- generic map (
--
-- C_OP_MODE => 0 , -- 0 = Offset/Length mode
-- C_STRB_WIDTH => BYTES_PER_DBEAT ,
-- C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
-- C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
--
-- )
-- port map (
--
-- start_addr_offset => sig_strbgen_addr ,
-- end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
-- num_valid_bytes => sig_strbgen_bytes ,
-- strb_out => sig_sfhalt_next_strt_strb
--
-- );
--
--
--
--
--
--
--
-- -- Generate the WSTRB to use during soft shutdown
-- sig_halt_strb <= sig_strt_strb_reg
-- When (sig_first_dbeat = '1' or
-- sig_single_dbeat = '1')
-- Else (others => '1');
--
--
--
-- -- Generate the Write Strobes for the MMap Write Data Channel
-- -- for the Indeterminate BTT case. Strobes come from the Stream
-- -- input from the Indeterminate BTT module during normal operation.
-- -- However, during soft shutdown, those strobes become unpredictable
-- -- so generated strobes have to be used.
-- data2skid_wstrb <= sig_halt_strb
-- When (sig_halt_reg = '1')
--
-- Else s2mm_strm_wstrb;
--
--
--
-- -- Generate the Stream Ready for the Stream input side
-- sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
-- (sig_mmap2data_ready and -- MMap is accepting the xfers
-- sig_addr_chan_rdy and -- xfers are commited on the address channel and
-- sig_dqual_rdy and -- there are commands in the command fifo
-- not(sig_calc_error_reg) and -- No internal error
-- not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- -- or when the soft shutdown has completed
--
--
-- -- MMap Write Data Channel Valid Handshaking
-- sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
-- sig_halt_reg ) and -- force valid if halt requested
-- sig_addr_chan_rdy and -- xfers are commited on the address channel and
-- sig_dqual_rdy and -- there are commands in the command fifo
-- not(sig_calc_error_reg) and -- No internal error
-- not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- -- or when the soft shutdown has completed
--
--
--
-- -- TLAST Error housekeeping for Indeterminate BTT Mode
-- -- There is no Underrun/overrun in Stroe and Forward mode
--
-- sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
-- sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_EOP_REG_FLOP
-- --
-- -- Process Description:
-- -- Register the End of Packet marker.
-- --
-- -------------------------------------------------------------
-- IMP_EOP_REG_FLOP : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_end_of_cmd_reg <= '0';
-- lsig_eop_reg <= '0';
--
--
-- Elsif (sig_good_strm_dbeat = '1') Then
--
--
-- lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
-- s2mm_strm_wlast;
--
-- lsig_eop_reg <= s2mm_strm_eop;
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_EOP_REG_FLOP;
--
--
--
--
--
-- ----- Byte Counter Logic -----------------------------------------------
-- -- The Byte counter reflects the actual byte count received on the
-- -- Stream input for each parent command loaded into the S2MM command
-- -- FIFO. Thus it counts input bytes until the command complete qualifier
-- -- is set and the TLAST input from the Stream input.
--
--
-- lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
-- not(sig_good_strm_dbeat); -- immediately after the previous one finished.
--
--
-- lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
-- sig_good_strm_dbeat; -- immediately after the previous one finished.
--
-- lsig_incr_byte_cntr <= sig_good_strm_dbeat;
--
--
-- lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
-- BYTE_CNTR_WIDTH);
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_BYTE_CMTR
-- --
-- -- Process Description:
-- -- Keeps a running byte count per burst packet loaded into the
-- -- xfer FIFO. It is based on the strobes set on the incoming
-- -- Stream dbeat.
-- --
-- -------------------------------------------------------------
-- IMP_BYTE_CMTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- lsig_clr_byte_cntr = '1') then
--
-- lsig_byte_cntr <= (others => '0');
--
-- elsif (lsig_ld_byte_cntr = '1') then
--
-- lsig_byte_cntr <= lsig_byte_cntr_incr_value;
--
-- elsif (lsig_incr_byte_cntr = '1') then
--
-- lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
--
-- else
-- null; -- hold current value
-- end if;
-- end if;
-- end process IMP_BYTE_CMTR;
--
--
--
--
--
-- end generate GEN_INDET_BTT;
--
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_sg_v4_1.axi_sg_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| gpl-3.0 | 334a9ade5c3b330300ecfd27ea992689 | 0.417537 | 4.926479 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/misc/gracectrl.vhd | 1 | 14,024 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: gracectrl
-- File: gracectrl.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- Contact: [email protected]
-- Description: Provides a GRLIB AMBA AHB slave interface to Xilinx System ACE
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, gaisler;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use gaisler.misc.all;
entity gracectrl is
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
haddr : integer := 16#000#; -- Base address
hmask : integer := 16#fff#; -- Area mask
split : integer range 0 to 1 := 0; -- Enable AMBA SPLIT support
swap : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0; -- Output enable polarity
mode : integer range 0 to 2 := 0 -- 0: 16-bit mode only
-- 1: 8-bit mode only
-- 2: 8-bit, emulate 16-bit
);
port (
rstn : in std_ulogic;
clk : in std_ulogic; -- System (AMBA) clock
clkace : in std_ulogic; -- System ACE clock
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
acei : in gracectrl_in_type;
aceo : out gracectrl_out_type
);
end gracectrl;
architecture rtl of gracectrl is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant REVISION : amba_version_type := 0;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_GRACECTRL, 0, REVISION, hirq),
-- 1 => conv_std_logic_vector(swap*4 + mode, 32),
4 => ahb_iobar(haddr, hmask), others => zero32);
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1);
constant INPUT : std_ulogic := not conv_std_logic(oepol = 1);
constant ACEDW : integer := 16-8*(mode mod 2);
-----------------------------------------------------------------------------
-- Functions
-----------------------------------------------------------------------------
-- purpose: swaps a hword if 'swap' is non-zero and mode is zero,
-- otherwise just propagate data
function condhswap (d : std_logic_vector)
return std_logic_vector is
variable dx : std_logic_vector(15 downto 0);
begin -- hswap
dx(ACEDW-1 downto 0) := d;
if swap /= 0 and mode = 0 then
return dx(7 downto 0) & dx(15 downto 8);
end if;
return dx;
end condhswap;
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type sys_sync_type is record
accdone : std_logic_vector(1 downto 0);
irq : std_logic_vector(2 downto 0);
end record;
type sys_reg_type is record
acc : std_ulogic; -- Perform access
active : std_ulogic; -- Access active
sync : sys_sync_type;
-- AHB
insplit : std_ulogic; -- SPLIT response issued
unsplit : std_ulogic; -- SPLIT complete not issued
irq : std_ulogic; -- Interrupt request
hwrite : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 1);
haddr : std_logic_vector(6 downto 0);
hready : std_ulogic;
wdata : std_logic_vector(ACEDW-1 downto 0);
hresp : std_logic_vector(1 downto 0);
splmst : std_logic_vector(log2(NAHBMST)-1 downto 0); -- SPLIT:ed master
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- Other SPLIT:ed masters
ahbcancel : std_ulogic; -- Locked access cancels ongoing SPLIT
-- response
end record;
type ace_state_type is (idle, en, rd, done);
type ace_sync_type is record
acc : std_logic_vector(1 downto 0);
rstn : std_logic_vector(1 downto 0);
hwrite : std_logic_vector(1 downto 0);
dummy : std_logic_vector(1 downto 0);
end record;
type ace_reg_type is record
state : ace_state_type;
sync : ace_sync_type;
accdone : std_ulogic;
rdata : std_logic_vector(ACEDW-1 downto 0);
edone : std_ulogic;
aceo : gracectrl_out_type;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : sys_reg_type;
signal s, sin : ace_reg_type;
begin -- rtl
-----------------------------------------------------------------------------
-- System clock domain
-----------------------------------------------------------------------------
combsys: process (r, s, rstn, ahbsi, acei.irq)
variable v : sys_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable hsplit : std_logic_vector(NAHBMST-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin -- process comb
v := r; v.irq := '0'; irq := (others => '0'); irq(hirq) := r.irq;
v.hresp := HRESP_OKAY; v.hready := '1'; hsplit := (others => '0');
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
-- Sync
v.sync.accdone := r.sync.accdone(0) & s.accdone;
v.sync.irq := r.sync.irq(1 downto 0) & acei.irq;
-- AHB communication
if ahbsi.hready = '1' then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hmbsel := ahbsi.hmbsel(r.hmbsel'range);
if split = 0 or (not (r.active or r.acc) or ahbsi.hmastlock) = '1' then
v.hready := '0';
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr(6 downto 0);
v.hsel := '1';
if r.insplit = '0' then
v.acc := '1';
end if;
if split /= 0 then
if ahbsi.hmastlock = '0' then
v.hresp := HRESP_SPLIT;
v.splmst := ahbsi.hmaster;
v.unsplit := '1';
else
v.ahbcancel := r.insplit;
end if;
v.insplit := not ahbsi.hmastlock;
end if;
else
-- Core is busy, transfer is not locked respond with SPLIT
v.hready := '0';
if split /= 0 then
v.hresp := HRESP_SPLIT;
v.hsplit(conv_integer(ahbsi.hmaster)) := '1';
end if;
end if;
else
v.hsel := '0';
end if;
end if;
if (r.hready = '0') then
if (r.hresp = HRESP_OKAY) then v.hready := '0';
else v.hresp := r.hresp; end if;
end if;
if r.acc = '1' then
-- Propagate data
if r.active = '0' then
if mode /= 1 then
if r.haddr(1) = '0' then v.wdata := hwdata(ACEDW+15 downto 16);
else v.wdata := hwdata(ACEDW-1 downto 0); end if;
else
case r.haddr(1 downto 0) is
when "00" => v.wdata(7 downto 0) := hwdata(31 downto 24);
when "01" => v.wdata(7 downto 0) := hwdata(23 downto 16);
when "10" => v.wdata(7 downto 0) := hwdata(15 downto 8);
when others => v.wdata(7 downto 0) := hwdata(7 downto 0);
end case;
end if;
if mode = 2 then
-- Override writes to busmode register
if r.haddr(6 downto 1) = zero32(6 downto 1) then
v.wdata := (others => '0'); -- Byte
end if;
end if;
end if;
-- Remove access signal when access is done
if r.sync.accdone(1) = '1' then
v.acc := '0';
end if;
v.active := '1';
end if;
-- AMBA response when access is complete
if r.acc = '0' and r.sync.accdone(1) = '0' and r.active = '1' then
if split /= 0 and r.unsplit = '1' then
hsplit(conv_integer(r.splmst)) := '1';
v.unsplit := '0';
end if;
if ((split = 0 or v.ahbcancel = '0') and
(split = 0 or ahbsi.hmaster = r.splmst or r.insplit = '0') and
(((ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1') or
((split = 0 or r.insplit = '0') and r.hready = '0' and r.hresp = HRESP_OKAY))) then
v.hresp := HRESP_OKAY;
if split /= 0 then
v.insplit := '0';
v.hsplit := r.hsplit;
end if;
v.hready := '1';
v.hsel := '0';
v.active := '0';
elsif split /= 0 and v.ahbcancel = '1' then
v.acc := '1';
v.ahbcancel := '0';
end if;
end if;
-- Interrupt request, not filtered, pulsed
if (not r.sync.irq(2) and r.sync.irq(1)) = '1' then
v.irq := '1';
end if;
-- Reset
if rstn = '0' then
v.acc := '0';
v.active := '0';
--
v.insplit := '0';
v.unsplit := '0';
v.hready := '1';
v.hwrite := '0';
v.hsel := '0';
v.hmbsel := (others => '0');
v.ahbcancel := '0';
end if;
if split = 0 then
v.insplit := '0';
v.unsplit := '0';
v.splmst := (others => '0');
v.hsplit := (others => '0');
v.ahbcancel := '0';
end if;
-- Update registers
rin <= v;
-- AHB slave output
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(s.rdata); -- Bad, but does not toggle much
ahbso.hconfig <= HCONFIG;
ahbso.hirq <= irq;
ahbso.hindex <= hindex;
ahbso.hsplit <= hsplit;
end process combsys;
regsys: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process regsys;
-----------------------------------------------------------------------------
-- System ACE clock domain
-----------------------------------------------------------------------------
combace: process (r, s, rstn, acei)
variable v : ace_reg_type;
begin -- process comb
v := s;
-- Synchronize inputs
v.sync.acc := s.sync.acc(0) & r.acc;
v.sync.rstn := s.sync.rstn(0) & rstn;
v.sync.hwrite := s.sync.hwrite(0) & r.hwrite;
if mode = 2 then
-- Fake reads from BUSMODE register?
v.sync.dummy := s.sync.dummy(0) & not orv(r.haddr(6 downto 1));
else
v.sync.dummy := (others => '0');
end if;
case s.state is
when idle =>
v.aceo.addr := r.haddr(6 downto 0);
if mode = 2 then v.aceo.do(7 downto 0) := r.wdata(7 downto 0);
else v.aceo.do(r.wdata'range) := condhswap(r.wdata); end if;
if s.sync.acc(1) = '1' then
v.aceo.cen := '0';
v.aceo.doen := INPUT xor r.hwrite;
v.state := en;
end if;
if mode = 2 then v.edone := '0'; end if;
when en =>
v.aceo.wen := not r.hwrite;
if s.sync.hwrite(1) = '1' then
v.state := done;
else
v.state := rd;
end if;
when rd =>
v.aceo.oen := '0';
v.state := done;
when done =>
v.aceo.oen := '1';
v.aceo.wen := '1';
if mode = 2 and s.edone = '0' then
-- Keep 16-bit address map
v.aceo.addr(0) := '1';
v.aceo.do(7 downto 0) := r.wdata(ACEDW-1 downto ACEDW-8);
v.rdata(7 downto 0) := acei.di(7 downto 0);
v.edone := '1';
v.state := en;
else
v.aceo.cen := '1';
if s.accdone = '0' then
if mode = 2 then
v.rdata(ACEDW-1 downto ACEDW-8) := acei.di(7 downto 0);
if s.sync.dummy(1) = '1' then -- Fake read
v.rdata := (others => '0'); v.rdata(0) := '1';
end if;
else
v.rdata := condhswap(acei.di)(s.rdata'range);
end if;
v.accdone := '1';
else
v.aceo.doen := INPUT;
end if;
if s.sync.acc(1) = '0' then
v.state := idle;
v.accdone := '0';
end if;
end if;
end case;
-- Reset
if s.sync.rstn(1) = '0' then
v.state := idle;
v.accdone := '0';
v.aceo.cen := '1';
v.aceo.wen := '1';
v.aceo.oen := '1';
v.aceo.doen := INPUT;
end if;
if mode = 1 then v.aceo.do(15 downto 8) := (others => '0'); end if;
if mode /= 2 then v.edone := '0'; end if;
-- Update registers
sin <= v;
-- Assign outputs to System ACE
aceo <= s.aceo;
end process combace;
regace: process (clkace)
begin -- process reg
if rising_edge(clkace) then
s <= sin;
end if;
end process regace;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"gracectrl" & tost(hindex) & ": System ACE I/F Controller, rev " &
tost(REVISION) & ", irq " & tost(hirq));
-- pragma translate_on
end rtl;
| gpl-2.0 | 3da5292c96e764a754d83b257ae53360 | 0.484883 | 3.760794 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/outpad.vhd | 1 | 5,685 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad
-- File: outpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else i;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
um : if (tech = umc) generate
x0 : umc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
saed : if (tech = saed32) generate
x0 : saed32_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
dar : if (tech = dare) generate
x0 : dare_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ihprh : if (tech = ihp25rh) generate
x0 : ihp25rh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength) port map (padx, i, gnd, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_outpad generic map (level, slew, voltage, strength) port map (pad, i);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
nex : if (tech = easic90) generate
x0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, vcc);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_outpad generic map (level, slew, voltage, strength)
port map(pad, i, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
x0 : ut90nhbd_outpad generic map (level, slew, voltage, strength)
port map(pad, i, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity outpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of outpadv is
begin
v : for j in width-1 downto 0 generate
x0 : outpad generic map (tech, level, slew, voltage, strength)
port map (pad(j), i(j), cfgi);
end generate;
end;
| gpl-2.0 | baf6f6c465aa4194c3a55bd0c981a1cf | 0.643096 | 3.548689 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/grlib/amba/dma2ahb_pkg.vhd | 1 | 6,000 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB_Package (package declaration)
--
-- File name : dma2ahb_pkg.vhd
--
-- Purpose : Interface package for AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : See DMA2AHB VHDL core
--
-- Library : gaisler
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts
-- Support for record types
-- 1.5 SH 1 Sep 2005 New library gaisler
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.7 SH 6 Dec 2007 Added syncrst generic
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package DMA2AHB_Package is
-----------------------------------------------------------------------------
-- Direct Memory Access to AMBA AHB Master Interface Types
-----------------------------------------------------------------------------
type DMA_In_Type is record
Reset: Std_Logic;
Address: Std_Logic_Vector(32-1 downto 0);
Data: Std_Logic_Vector(32-1 downto 0);
Request: Std_Logic; -- access requested
Burst: Std_Logic; -- burst requested
Beat: Std_Logic_Vector(1 downto 0); -- incrementing beat
Size: Std_Logic_Vector(1 downto 0); -- size
Store: Std_Logic; -- data write requested
Lock: Std_Logic; -- locked Transfer
end record;
type DMA_Out_Type is record
Grant: Std_Logic; -- access accepted
OKAY: Std_Logic; -- write access ready
Ready: Std_Logic; -- read data ready
Retry: Std_Logic; -- retry
Fault: Std_Logic; -- error occured
Data: Std_Logic_Vector(32-1 downto 0);
end record;
-- constants for HBURST definition (used with dma_in_type.Beat)
constant HINCR: Std_Logic_Vector(1 downto 0) := "00";
constant HINCR4: Std_Logic_Vector(1 downto 0) := "01";
constant HINCR8: Std_Logic_Vector(1 downto 0) := "10";
constant HINCR16: Std_Logic_Vector(1 downto 0) := "11";
-- constants for HSIZE definition (used with dma_in_type.Size)
constant HSIZE8: Std_Logic_Vector(1 downto 0) := "00";
constant HSIZE16: Std_Logic_Vector(1 downto 0) := "01";
constant HSIZE32: Std_Logic_Vector(1 downto 0) := "10";
-----------------------------------------------------------------------------
-- Direct Memory Access to AMBA AHB Master Interface
-----------------------------------------------------------------------------
component DMA2AHB is
generic(
hindex: in Integer := 0;
vendorid: in Integer := 0;
deviceid: in Integer := 0;
version: in Integer := 0;
syncrst: in Integer := 1;
boundary: in Integer := 1);
port(
-- AMBA AHB system signals
HCLK: in Std_ULogic;
HRESETn: in Std_ULogic;
-- Direct Memory Access Interface
DMAIn: in DMA_In_Type;
DMAOut: out DMA_OUt_Type;
-- AMBA AHB Master Interface
AHBIn: in AHB_Mst_In_Type;
AHBOut: out AHB_Mst_Out_Type);
end component DMA2AHB;
end package DMA2AHB_Package; --===============================================--
| gpl-2.0 | 4f5db5653870f8692f4be742984d2187 | 0.501833 | 4.716981 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/pcipads.vhd | 1 | 10,803 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcipads
-- File: pcipads.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI pads module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.pci.all;
library grlib;
use grlib.stdlib.all;
entity pcipads is
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0;
no66 : integer := 0;
onchipreqgnt : integer := 0; -- Internal req and gnt signals
drivereset : integer := 0; -- Drive PCI rst with outpad
constidsel : integer := 0; -- pci_idsel is tied to local constant
level : integer := pci33; -- input/output level
voltage : integer := x33v -- input/output voltage
);
port (
pci_rst : inout std_logic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0) --:= conv_std_logic_vector(16#F#, 4) -- Disable int by default
--pci_int : inout std_logic_vector(3 downto 0) :=
-- conv_std_logic_vector(16#F# - (16#F# * oepol), 4) -- Disable int by default
);
end;
architecture rtl of pcipads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- Reset
rstpad : if noreset = 0 generate
nodrive: if drivereset = 0 generate
pci_rst_pad : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => 0)
port map (pci_rst, pcio.rst, pcii.rst);
end generate nodrive;
drive: if drivereset /= 0 generate
pci_rst_pad : outpad generic map (tech => padtech, level => level,
voltage => voltage)
port map (pci_rst, pcio.rst);
pcii.rst <= pcio.rst;
end generate drive;
end generate;
norstpad : if noreset = 1 generate
pcii.rst <= pci_rst;
end generate;
localgnt: if onchipreqgnt = 1 generate
pcii.gnt <= pci_gnt;
pci_req <= pcio.req when pcio.reqen = conv_std_logic(oepol=1) else '1';
end generate localgnt;
extgnt: if onchipreqgnt = 0 generate
pad_pci_gnt : inpad generic map (padtech, level, voltage) port map (pci_gnt, pcii.gnt);
pad_pci_req : toutpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_req, pcio.req, pcio.reqen);
end generate extgnt;
idsel_pad: if constidsel = 0 generate
pad_pci_idsel : inpad generic map (padtech, level, voltage) port map (pci_idsel, pcii.idsel);
end generate idsel_pad;
idsel_local: if constidsel /= 0 generate
pcii.idsel <= pci_idsel;
end generate idsel_local;
onlyhost : if host = 2 generate
pcii.host <= '0'; -- Always host
end generate;
dohost : if host = 1 generate
pad_pci_host : inpad generic map (padtech, level, voltage) port map (pci_host, pcii.host);
end generate;
nohost : if host = 0 generate
pcii.host <= '1'; -- disable pci host functionality
end generate;
do66 : if no66 = 0 generate
pad_pci_66 : inpad generic map (padtech, level, voltage) port map (pci_66, pcii.pci66);
end generate;
dono66 : if no66 = 1 generate
pcii.pci66 <= '0';
end generate;
pad_pci_lock : iopad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_lock, pcio.lock, pcio.locken, pcii.lock);
pad_pci_ad : iopadvv generic map (tech => padtech, level => level,
voltage => voltage, width => 32,
oepol => oepol)
port map (pci_ad, pcio.ad, pcio.vaden, pcii.ad);
pad_pci_cbe0 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(0), pcio.cbe(0), pcio.cbeen(0), pcii.cbe(0));
pad_pci_cbe1 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(1), pcio.cbe(1), pcio.cbeen(1), pcii.cbe(1));
pad_pci_cbe2 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(2), pcio.cbe(2), pcio.cbeen(2), pcii.cbe(2));
pad_pci_cbe3 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(3), pcio.cbe(3), pcio.cbeen(3), pcii.cbe(3));
pad_pci_frame : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_frame, pcio.frame, pcio.frameen, pcii.frame);
pad_pci_trdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_trdy, pcio.trdy, pcio.trdyen, pcii.trdy);
pad_pci_irdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_irdy, pcio.irdy, pcio.irdyen, pcii.irdy);
pad_pci_devsel: iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_devsel, pcio.devsel, pcio.devselen, pcii.devsel);
pad_pci_stop : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_stop, pcio.stop, pcio.stopen, pcii.stop);
pad_pci_perr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_perr, pcio.perr, pcio.perren, pcii.perr);
pad_pci_par : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_par, pcio.par, pcio.paren, pcii.par);
pad_pci_serr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_serr, pcio.serr, pcio.serren, pcii.serr);
-- PCI interrupt pads
-- int = 0 => no interrupt
-- int = 1 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 2 => PCI_INT[B] = out, PCI_INT[A,C,D] = Not connected
-- int = 3 => PCI_INT[C] = out, PCI_INT[A,B,D] = Not connected
-- int = 4 => PCI_INT[D] = out, PCI_INT[A,B,C] = Not connected
-- int = 10 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 11 => PCI_INT[B] = inout, PCI_INT[A,C,D] = in
-- int = 12 => PCI_INT[C] = inout, PCI_INT[A,B,D] = in
-- int = 13 => PCI_INT[D] = inout, PCI_INT[A,B,C] = in
-- int = 14 => PCI_INT[A,B,C,D] = in
-- int = 100 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 101 => PCI_INT[A,B] = out, PCI_INT[C,D] = Not connected
-- int = 102 => PCI_INT[A,B,C] = out, PCI_INT[D] = Not connected
-- int = 103 => PCI_INT[A,B,C,D] = out
-- int = 110 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 111 => PCI_INT[A,B] = inout, PCI_INT[C,D] = in
-- int = 112 => PCI_INT[A,B,C] = inout, PCI_INT[D] = in
-- int = 113 => PCI_INT[A,B,C,D] = inout
interrupt : if int /= 0 generate
x : for i in 0 to 3 generate
xo : if i = int - 1 and int < 10 generate
pad_pci_int : odpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.inten);
end generate;
xonon : if i /= int - 1 and int < 10 and int < 100 generate
pci_int(i) <= '1';
end generate;
xio : if i = (int - 10) and int >= 10 and int < 100 generate
pad_pci_int : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.inten, pcii.int(i));
end generate;
xi : if i /= (int - 10) and int >= 10 and int < 100 generate
pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
port map (pci_int(i), pcii.int(i));
end generate;
x2o : if i <= (int - 100) and int < 110 and int >= 100 generate
pad_pci_int : odpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.vinten(i));
end generate;
x2onon : if i > (int - 100) and int < 110 and int >= 100 generate
pci_int(i) <= '1';
end generate;
x2oi : if i <= (int - 110) and int >= 110 generate
pad_pci_int : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.vinten(i), pcii.int(i));
end generate;
x2i : if i > (int - 110) and int >= 110 generate
pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
port map (pci_int(i), pcii.int(i));
end generate;
end generate;
end generate;
nointerrupt : if int = 0 generate
pcii.int <= (others => '0');
end generate;
pcii.pme_status <= '0';
end;
| gpl-2.0 | 37b197edbb053a03d61d0250087a4c33 | 0.569934 | 3.517747 | false | false | false | false |
mistryalok/Zedboard | learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/ua_narrow.vhd | 6 | 18,144 | -------------------------------------------------------------------------------
-- ua_narrow.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: ua_narrow.vhd
--
-- Description: Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/8/2011 v1.03a
-- ~~~~~~
-- Update bit vector usage of address LSB for calculating ua_narrow_load.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 3/1/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/2/2011 v1.03a
-- ~~~~~~
-- Update range of integer signals.
-- ^^^^^^
-- JLJ 3/4/2011 v1.03a
-- ~~~~~~
-- Remove use of local function, Create_Size_Max.
-- ^^^^^^
-- JLJ 3/11/2011 v1.03a
-- ~~~~~~
-- Remove C_AXI_DATA_WIDTH generate statments.
-- ^^^^^^
-- JLJ 3/14/2011 v1.03a
-- ~~~~~~
-- Update ua_narrow_load signal assignment to pass simulations & XST.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, ua_narrow_wrap_gt_width,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity ua_narrow is
generic (
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_NARROW_BURST_CNT_LEN : integer := 4
-- Size of narrow burst counter
);
port (
curr_wrap_burst : in std_logic;
curr_incr_burst : in std_logic;
bram_addr_ld_en : in std_logic;
curr_axlen : in std_logic_vector (7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector (2 downto 0) := (others => '0');
curr_axaddr_lsb : in std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
curr_ua_narrow_wrap : out std_logic;
curr_ua_narrow_incr : out std_logic;
ua_narrow_load : out std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0)
:= (others => '0')
);
end entity ua_narrow;
-------------------------------------------------------------------------------
architecture implementation of ua_narrow is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- Use constant to compare when LSB of ADDR is equal to zero.
constant axaddr_lsb_zero : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Convert # of data bytes for AXI data bus into an unsigned vector (C_MAX_LSHIFT_SIZE:0).
constant C_AXI_DATA_WIDTH_BYTES_UNSIGNED : unsigned (C_MAX_LSHIFT_SIZE downto 0) :=
to_unsigned (C_AXI_DATA_WIDTH_BYTES, C_MAX_LSHIFT_SIZE+1);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal ua_narrow_wrap_gt_width : std_logic := '0';
signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal curr_axsize_int : integer := 0;
signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
signal curr_axlen_unsigned_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
signal bytes_per_addr : integer := 1; -- range 1 to 128 := 1;
signal size_plus_lsb : integer range 1 to 256 := 1;
signal narrow_addr_offset : integer := 1;
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
-- v1.03a
-- Added for narrow INCR bursts with UA addresses
-- Check if burst is a) INCR type,
-- b) a narrow burst (SIZE = full width of bus)
-- c) LSB of address is non zero
curr_ua_narrow_incr <= '1' when (curr_incr_burst = '1') and
(curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and
(curr_axaddr_lsb /= axaddr_lsb_zero) and
(bram_addr_ld_en = '1')
else '0';
-- v1.03a
-- Detect narrow WRAP bursts
-- Detect if the operation is a) WRAP type,
-- b) a narrow burst (SIZE = full width of bus)
-- c) LSB of address is non zero
-- d) complete size of WRAP is larger than width of BRAM
curr_ua_narrow_wrap <= '1' when (curr_wrap_burst = '1') and
(curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and
(curr_axaddr_lsb /= axaddr_lsb_zero) and
(bram_addr_ld_en = '1') and
(ua_narrow_wrap_gt_width = '1')
else '0';
---------------------------------------------------------------------------
-- v1.03a
-- Check condition if narrow burst wraps within the size of the BRAM width.
-- Check if size * length > BRAM width in bytes.
--
-- When asserted = '1', means that narrow burst counter is not preloaded early,
-- the BRAM burst will be contained within the BRAM data width.
curr_axsize_unsigned <= unsigned (curr_axsize);
curr_axsize_int <= to_integer (curr_axsize_unsigned);
curr_axlen_unsigned <= unsigned (curr_axlen);
-- Original logic with multiply function.
--
-- ua_narrow_wrap_gt_width <= '0' when (((2**(to_integer (curr_axsize_unsigned))) *
-- unsigned (curr_axlen (7 downto 0)))
-- < C_AXI_DATA_WIDTH_BYTES)
-- else '1';
-- Replace with left shift operation of AxLEN.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
LEN_LSHIFT: process (curr_axlen_unsigned, curr_axsize_int)
begin
for i in C_MAX_LSHIFT_SIZE downto 0 loop
if (i >= curr_axsize_int + 8) then
curr_axlen_unsigned_lshift (i) <= '0';
elsif (i >= curr_axsize_int) then
curr_axlen_unsigned_lshift (i) <= curr_axlen_unsigned (i - curr_axsize_int);
else
curr_axlen_unsigned_lshift (i) <= '0';
end if;
end loop;
end process LEN_LSHIFT;
-- Final result.
ua_narrow_wrap_gt_width <= '0' when (curr_axlen_unsigned_lshift < C_AXI_DATA_WIDTH_BYTES_UNSIGNED)
else '1';
---------------------------------------------------------------------------
-- v1.03a
-- For narrow burst transfer, provides the number of bytes per address
-- XST does not support divisors that are not constants AND powers of two.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_axsize_unsigned)));
-- With this new process:
-- Replace case statement with unsigned signal comparator.
DIV_AXSIZE: process (curr_axsize)
begin
case (curr_axsize) is
when "000" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 128; -- Max SIZE for 1024-bit AXI bus
when others => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES;
end case;
end process DIV_AXSIZE;
-- Original statement.
-- XST does not support divisors that are not constants AND powers of two.
-- Insert process to perform (size_plus_lsb / size_bytes_int) function in generation of ua_narrow_load.
--
-- size_bytes_int <= (2**(to_integer (curr_axsize_unsigned)));
--
-- ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr -
-- (size_plus_lsb / size_bytes_int), C_NARROW_BURST_CNT_LEN));
-- AxSIZE + LSB of address
-- Use all LSB address bit lanes for the narrow transfer based on C_S_AXI_DATA_WIDTH
size_plus_lsb <= (2**(to_integer (curr_axsize_unsigned))) +
to_integer (unsigned (curr_axaddr_lsb (C_AXI_DATA_WIDTH_BYTES_LOG2-1 downto 0)));
-- Process to keep synthesis with divide by constants that are a power of 2.
DIV_SIZE_BYTES: process (size_plus_lsb,
curr_axsize)
begin
-- Use unsigned w/ curr_axsize signal
case (curr_axsize) is
when "000" => narrow_addr_offset <= size_plus_lsb / 1;
when "001" => narrow_addr_offset <= size_plus_lsb / 2;
when "010" => narrow_addr_offset <= size_plus_lsb / 4;
when "011" => narrow_addr_offset <= size_plus_lsb / 8;
when "100" => narrow_addr_offset <= size_plus_lsb / 16;
when "101" => narrow_addr_offset <= size_plus_lsb / 32;
when "110" => narrow_addr_offset <= size_plus_lsb / 64;
when "111" => narrow_addr_offset <= size_plus_lsb / 128; -- Max SIZE for 1024-bit AXI bus
when others => narrow_addr_offset <= size_plus_lsb;
end case;
end process DIV_SIZE_BYTES;
-- Final new statement.
-- Passing in simulation and XST.
ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr -
narrow_addr_offset, C_NARROW_BURST_CNT_LEN))
when (bytes_per_addr >= narrow_addr_offset)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
end architecture implementation;
| gpl-3.0 | ad25754520939794ab03dcd85aa3fb12 | 0.495922 | 4.175834 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-minimal/leon3mp.vhd | 1 | 10,486 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH
);
port (
clk : in std_ulogic; -- FPGA main clock input
-- Buttons & LEDs
btnCpuResetn : in std_ulogic; -- Reset button
Led : out std_logic_vector(15 downto 0);
-- Onboard Cellular RAM
RamOE : out std_ulogic;
RamWE : out std_ulogic;
RamAdv : out std_ulogic;
RamCE : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
address : out std_logic_vector(22 downto 0);
data : inout std_logic_vector(15 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
-- Memory controler signals
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
-- AMBA bus signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to 0);
signal irqo : irq_out_vector(0 to 0);
signal dbgi : l3_debug_in_vector(0 to 0);
signal dbgo : l3_debug_out_vector(0 to 0);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ndsuact : std_ulogic;
signal gpti : gptimer_in_type;
signal clkm, rstn : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart (unconnected)
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkm : signal is true;
constant clock_mult : integer := 10; -- Clock multiplier
constant clock_div : integer := 20; -- Clock divider
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * clock_mult / clock_div; -- CPU freq in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 0)
port map (btnCpuResetn, clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, clock_mult, clock_div, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (ioen => 1, nahbm => 4, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
u0 : leon3s
generic map (hindex=>0, fabtech=>fabtech, memtech=>memtech, dsu=>1, fpu=>0, v8=>2,
mac=>0, isetsize=>8, dsetsize=>8,icen=>1, dcen=>1,tbuf=>2)
port map (clkm, rstn, ahbmi, ahbmo(0), ahbsi, ahbso, irqi(0), irqo(0), dbgi(0), dbgo(0));
-- LEON3 Debug Support Unit
dsu0 : dsu3
generic map (hindex => 2, ncpu => 1, tech => memtech, irq => 0, kbytes => 2)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
-- Debug UART
dcom0 : ahbuart
generic map (hindex => 1, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(1));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => 3)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(3),
open, open, open, open, open, open, open, gnd);
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, rommask => 0,
iomask => 0, ram8 => 0, ram16 => 1,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01"; -- Sets data bus width for PROM accesses.
-- Bidirectional data bus
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
-- Out signals to memory
addr_pad : outpadv generic map (tech => padtech, width => 23) -- Address bus
port map (address, memo.address(23 downto 1));
oen_pad : outpad generic map (tech => padtech) -- Output Enable
port map (RamOE, memo.oen);
cs_pad : outpad generic map (tech => padtech) -- SRAM Chip select
port map (RamCE, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech) -- Write enable
port map (RamWE, memo.writen);
RamCRE <= '0'; -- Special SRAM signals specific
RamClk <= '0'; -- to Nexys4 board
RamAdv <= '0';
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- APB Bridge
generic map (hindex => 1, haddr => 16#800#)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
irqctrl0 : irqmp -- Interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => 1)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
timer0 : gptimer -- Time Unit
generic map (pindex => 3, paddr => 3, pirq => 8,
sepirq => 1, ntimers => 2)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => 1)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent NEXYS 3 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 | 2b741f48f9d263a614614406ce9d4c06 | 0.515163 | 4.053344 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_timer_v2_0/3147922d/hdl/src/vhdl/timer_control.vhd | 7 | 27,927 | -------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :timer_control.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Control logic for Peripheral Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
-- timer_control.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- system clock
-- Reset -- system reset
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- Interrupt -- Interrupt
-- Counter_TC -- Carry out signal of counter
-- Bus2ip_data -- bus2ip data bus
-- BE -- te enab les
-- Load_Counter_Reg -- Load counter register control
-- Load_Load_Reg -- Load load register control
-- Write_Load_Reg -- write control of TLR reg
-- CaptGen_Mux_Sel -- mux select for capture and generate
-- Counter_En -- counter enable signal
-- Count_Down -- count down signal
-- Bus2ip_rdce -- read select
-- Bus2ip_wrce -- write select
-- Freeze -- freeze
-- TCSR0_Reg -- Control/Status register 0
-- TCSR1_Reg -- Control/Status register 1
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_lite_ipif_v3_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRSE;
library axi_timer_v2_0;
use axi_timer_v2_0.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0.TC_Types.TWELVE_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ELEVEN_BIT_TYPE;
use axi_timer_v2_0.TC_Types.ARHT0_POS;
use axi_timer_v2_0.TC_Types.ARHT1_POS;
use axi_timer_v2_0.TC_Types.CAPT0_POS;
use axi_timer_v2_0.TC_Types.CAPT1_POS;
use axi_timer_v2_0.TC_Types.CMPT0_POS;
use axi_timer_v2_0.TC_Types.CMPT1_POS;
use axi_timer_v2_0.TC_Types.ENALL_POS;
use axi_timer_v2_0.TC_Types.ENIT0_POS;
use axi_timer_v2_0.TC_Types.ENIT1_POS;
use axi_timer_v2_0.TC_Types.ENT0_POS;
use axi_timer_v2_0.TC_Types.ENT1_POS;
use axi_timer_v2_0.TC_Types.LOAD0_POS;
use axi_timer_v2_0.TC_Types.LOAD1_POS;
use axi_timer_v2_0.TC_Types.MDT0_POS;
use axi_timer_v2_0.TC_Types.MDT1_POS;
use axi_timer_v2_0.TC_Types.PWMA0_POS;
use axi_timer_v2_0.TC_Types.PWMB0_POS;
use axi_timer_v2_0.TC_Types.T0INT_POS;
use axi_timer_v2_0.TC_Types.T1INT_POS;
use axi_timer_v2_0.TC_Types.UDT0_POS;
use axi_timer_v2_0.TC_Types.UDT1_POS;
use axi_timer_v2_0.TC_Types.CASC_POS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity timer_control is
generic (
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Reset : in std_logic;
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
Interrupt : out std_logic;
Counter_TC : in std_logic_vector(0 to 1);
Bus2ip_data : in std_logic_vector(0 to 31);
BE : in std_logic_vector(0 to 3);
Load_Counter_Reg : out std_logic_vector(0 to 1);
Load_Load_Reg : out std_logic_vector(0 to 1);
Write_Load_Reg : out std_logic_vector(0 to 1);
CaptGen_Mux_Sel : out std_logic_vector(0 to 1);
Counter_En : out std_logic_vector(0 to 1);
Count_Down : out std_logic_vector(0 to 1);
Bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Freeze : in std_logic;
TCSR0_Reg : out TWELVE_BIT_TYPE;
TCSR1_Reg : out ELEVEN_BIT_TYPE
);
end entity timer_control;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of timer_control is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal declaration
-------------------------------------------------------------------------------
signal TCSR0_In : TWELVE_BIT_TYPE;
signal TCSR0_Reset : TWELVE_BIT_TYPE;
signal TCSR0_Set : TWELVE_BIT_TYPE;
signal TCSR0_CE : TWELVE_BIT_TYPE;
signal TCSR0 : TWELVE_BIT_TYPE;
signal TCSR1_In : ELEVEN_BIT_TYPE;
signal TCSR1_Reset : ELEVEN_BIT_TYPE;
signal TCSR1_Set : ELEVEN_BIT_TYPE;
signal TCSR1_CE : ELEVEN_BIT_TYPE;
signal TCSR1 : ELEVEN_BIT_TYPE;
signal captureTrig0_d : std_logic;
signal captureTrig1_d : std_logic;
signal captureTrig0_d2 : std_logic;
signal captureTrig1_d2 : std_logic;
signal captureTrig0_Edge : std_logic;
signal captureTrig1_Edge : std_logic;
signal captureTrig0_pulse: std_logic;
signal captureTrig0_pulse_d1: std_logic;
signal captureTrig0_pulse_d2: std_logic;
signal captureTrig1_pulse: std_logic;
signal read_done0 : std_logic;
signal read_done1 : std_logic;
signal generateOutPre0 : std_logic;
signal generateOutPre1 : std_logic;
signal pair0_Select : std_logic;
signal counter_TC_Reg : std_logic_vector(0 to 1);
signal counter_TC_Reg2 : std_logic;
signal tccr0_select : std_logic;
signal tccr1_select : std_logic;
signal interrupt_reg : std_logic;
signal CaptureTrig0_int : std_logic := '0';
signal CaptureTrig1_int : std_logic := '0';
signal Freeze_int : std_logic := '0';
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 0 (TCSR0)
-------------------------------------------------------------------------------
alias CASC : std_logic is TCSR0(CASC_POS);
alias T0INT : std_logic is TCSR0(T0INT_POS);
alias ENT0 : std_logic is TCSR0(ENT0_POS);
alias ENIT0 : std_logic is TCSR0(ENIT0_POS);
alias LOAD0 : std_logic is TCSR0(LOAD0_POS);
alias ARHT0 : std_logic is TCSR0(ARHT0_POS);
alias CAPT0 : std_logic is TCSR0(CAPT0_POS);
alias CMPT0 : std_logic is TCSR0(CMPT0_POS);
alias UDT0 : std_logic is TCSR0(UDT0_POS);
alias MDT0 : std_logic is TCSR0(MDT0_POS);
alias PWMA0 : std_logic is TCSR0(PWMA0_POS);
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 1 (TCSR1)
-------------------------------------------------------------------------------
alias T1INT : std_logic is TCSR1(T1INT_POS);
alias ENT1 : std_logic is TCSR1(ENT1_POS);
alias ENIT1 : std_logic is TCSR1(ENIT1_POS);
alias LOAD1 : std_logic is TCSR1(LOAD1_POS);
alias ARHT1 : std_logic is TCSR1(ARHT1_POS);
alias CAPT1 : std_logic is TCSR1(CAPT1_POS);
alias CMPT1 : std_logic is TCSR1(CMPT1_POS);
alias UDT1 : std_logic is TCSR1(UDT1_POS);
alias MDT1 : std_logic is TCSR1(MDT1_POS);
alias PWMB0 : std_logic is TCSR1(PWMB0_POS);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
pair0_Select <= (Bus2ip_wrce(0) or Bus2ip_wrce(4));
---------------------------------------------------
--Creating TCSR0 Register
---------------------------------------------------
TCSR0_GENERATE: for i in TWELVE_BIT_TYPE'range generate
TCSR0_FF_I: component FDRSE
port map (
Q => TCSR0(i), -- [out]
C => Clk, -- [in]
CE => TCSR0_CE(i), -- [in]
D => TCSR0_In(i), -- [in]
R => TCSR0_Reset(i), -- [in]
S => TCSR0_Set(i) -- [in]
);
end generate TCSR0_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR0 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR0_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"000100000000"
when Bus2ip_data(T0INT_POS)='1' and Bus2ip_wrce(0)='1' else
(others => '0') ;
----------------------------------------------------
--TCSR0 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR0 REGISTER
----------------------------------------------------
TCSR0_PROCESS: process (Bus2ip_wrce,Bus2ip_data,MDT0,
captureTrig0_Edge,generateOutPre0,TCSR0,
pair0_select,Reset,BE,ENT0,CASC,generateOutPre1) is
begin
TCSR0_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR0 register
---------------------------------------------
TCSR0_CE(31) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(30) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(29) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(28) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(27) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(26) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(25) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(24) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(23) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(22) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(21) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(20) <= Bus2ip_wrce(0) and BE(2);
TCSR0_In <= Bus2ip_data(20 to 31);
TCSR0_In(T0INT_POS) <= TCSR0(T0INT_POS);
----------------------------------------------------
---interrupt bit (23-bit) of TCSR1 register is set to 1
----------------------------------------------------
if (CASC = '0') then
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre0='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
else
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre1='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
end if;
TCSR0_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR0_CE(ENT0_POS) <= pair0_Select;
TCSR0_In(ENT0_POS) <= (Bus2ip_data(ENT0_POS) and Bus2ip_wrce(0) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR0(ENT0_POS) and (not Bus2ip_wrce(0)));
end process TCSR0_PROCESS;
---------------------------------------------------
--Creating TCSR1 Register
---------------------------------------------------
TCSR1_GENERATE: for i in ELEVEN_BIT_TYPE'range generate
TCSR1_FF_I: component FDRSE
port map (
Q => TCSR1(i), -- [out]
C => Clk, -- [in]
CE => TCSR1_CE(i), -- [in]
D => TCSR1_In(i), -- [in]
R => TCSR1_Reset(i), -- [in]
S => TCSR1_Set(i) -- [in]
);
end generate TCSR1_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR1 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR1_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"00100000000"
when Bus2ip_data(T1INT_POS)='1' and Bus2ip_wrce(4)='1' else
(others => '0') ;
------------------------------------------------------------------------
----------------------------------------------------
--TCSR1 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR1 REGISTER
----------------------------------------------------
TCSR1_PROCESS: process (Bus2ip_data,Bus2ip_wrce,MDT1,
captureTrig1_Edge,generateOutPre1,TCSR1,
pair0_Select,Reset,BE,ENT1,CASC,
MDT0,captureTrig0_Edge,ENT0) is
begin
TCSR1_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR1 register
---------------------------------------------
TCSR1_CE(31) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(30) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(29) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(28) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(27) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(26) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(25) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(24) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(23) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(22) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(21) <= Bus2ip_wrce(4) and BE(2);
TCSR1_In <= Bus2ip_data(21 to 31);
TCSR1_In(T1INT_POS) <= TCSR1(T1INT_POS);
----------------------------------------------------------------
---interrupt bit of TCSR1 register is set to 1
----------------------------------------------------------------
if (((MDT1='1' and captureTrig1_Edge='1' and ENT1='1') or
(MDT1='0' and generateOutPre1='1')) and CASC='0') then
TCSR1_Set(T1INT_POS) <= '1';
else
TCSR1_Set(T1INT_POS) <= '0';
end if;
TCSR1_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR1_CE(ENT1_POS) <= pair0_Select;
TCSR1_In(ENT1_POS) <= (Bus2ip_data(ENT1_POS) and Bus2ip_wrce(4) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR1(ENT1_POS) and (not Bus2ip_wrce(4)));
end process TCSR1_PROCESS;
-------------------------------------------------------------------------------
-- Counter Controls
-------------------------------------------------------------------------------
READ_DONE0_I: component FDRSE
port map (
Q => read_done0, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done0, -- [in]
R => captureTrig0_Edge, -- [in]
S => tccr0_select -- [in]
);
READ_DONE1_I: component FDRSE
port map (
Q => read_done1, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done1, -- [in]
R => captureTrig1_Edge, -- [in]
S => tccr1_select -- [in]
);
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Freeze,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => Freeze_int,
scndry_vect_out => open
);
-------------------------------------------------------
---Generating count enable and count down for counter 0
-------------------------------------------------------
Counter_En(0) <= (not Freeze_int and ENT0 and (MDT0 or (not Counter_TC(0)
or (ARHT0 or PWMA0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(0) <= UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Generating count enable and count down for counter 1
-------------------------------------------------------
Counter_En(1) <= (not Freeze_int and ENT1 and (MDT1 or (not Counter_TC(1)
or (ARHT1 or PWMB0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and generateOutPre0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(1) <= UDT1 when (CASC = '0') else
UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Load counter0 and counter1 with TLR register value
-------------------------------------------------------
Load_Counter_Reg(0) <= ((Counter_TC(0) and (ARHT0 or PWMA0) and (not MDT0)) or LOAD0) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD0) ;
Load_Counter_Reg(1) <= ((Counter_TC(1) and ARHT1 and not PWMB0 and (not MDT1)) or
LOAD1 or (Counter_TC(0) and PWMB0)) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD1) ;
-------------------------------------------------------
Load_Load_Reg(0) <= (MDT0 and captureTrig0_Edge and ARHT0) or
(MDT0 and captureTrig0_Edge and not ARHT0 and read_done0);
Load_Load_Reg(1) <= ((MDT1 and captureTrig1_Edge and ARHT1) or
(MDT1 and captureTrig1_Edge and not ARHT1 and read_done1)) when (CASC = '0') else
((MDT0 and captureTrig1_Edge and ARHT0) or
(MDT0 and captureTrig1_Edge and not ARHT0 and read_done1));
-------------------------------------------------------
Write_Load_Reg(0) <= Bus2ip_wrce(1);
Write_Load_Reg(1) <= Bus2ip_wrce(5);
CaptGen_Mux_Sel(0)<= Bus2ip_wrce(1);
CaptGen_Mux_Sel(1)<= Bus2ip_wrce(5);
tccr0_select <= (Bus2ip_wrce(1) or Bus2ip_rdce(1));
tccr1_select <= (Bus2ip_wrce(5) or Bus2ip_rdce(5));
-------------------------------------------------------
---CAPTGEN_SYNC_PROCESS:
-- Process to register the signals
-------------------------------------------------------
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig0,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig0_int,
scndry_vect_out => open
);
INPUT_DOUBLE_REGS2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig1,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig1_int,
scndry_vect_out => open
);
CAPTGEN_SYNC_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_d <= not C_TRIG0_ASSERT;
captureTrig1_d <= not C_TRIG1_ASSERT;
captureTrig0_d2 <= '0';
captureTrig1_d2 <= '0';
counter_TC_Reg(0) <= '0';
counter_TC_Reg(1) <= '0';
counter_TC_Reg2 <= '0';
-- counter_TC_Reg2(1) <= '0';
generateOutPre0 <= '0';
generateOutPre1 <= '0';
GenerateOut0 <= not C_GEN0_ASSERT;
GenerateOut1 <= not C_GEN1_ASSERT;
Interrupt <= '0';
else
captureTrig0_d <= (CaptureTrig0_int xor not(C_TRIG0_ASSERT)) and CAPT0;
captureTrig1_d <= (CaptureTrig1_int xor not(C_TRIG1_ASSERT)) and CAPT1;
captureTrig0_d2 <= captureTrig0_d;
captureTrig1_d2 <= captureTrig1_d;
counter_TC_Reg(0) <= Counter_TC(0);
counter_TC_Reg(1) <= Counter_TC(1);
counter_TC_Reg2 <= counter_TC_Reg(0);
-- counter_TC_Reg2(1) <= counter_TC_Reg(1);
generateOutPre0 <= Counter_TC(0) and (not counter_TC_Reg(0));
generateOutPre1 <= Counter_TC(1) and (not counter_TC_Reg(1));
GenerateOut0 <= ((((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and (not CASC)) or
(((generateOutPre1 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
GenerateOut1 <= ((((generateOutPre1 and CMPT1) xor not(C_GEN1_ASSERT)) and (not CASC)) or
(((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
Interrupt <= (ENIT0 and T0INT) or (ENIT1 and T1INT);
-- for edge-sensitive interrupt
--interrupt_reg<= (ENIT0 and T0INT) or (ENIT1 and T1INT);
--Interrupt <= ((ENIT0 and T0INT) or (ENIT1 and T1INT))
-- and (not interrupt_reg);
end if;
end if;
end process CAPTGEN_SYNC_PROCESS;
captureTrig0_pulse <= captureTrig0_d and not captureTrig0_d2;
captureTrig1_pulse <= captureTrig1_d and not captureTrig1_d2;
captureTrig0_Edge <= captureTrig0_pulse when (CASC = '0') else
(((not Counter_TC(0)) and (not counter_TC_Reg(0)) and captureTrig0_pulse) or
(captureTrig0_pulse_d2 and counter_TC_Reg2) or
(captureTrig0_pulse_d1 and counter_TC_Reg2));
captureTrig1_Edge <= captureTrig1_pulse when (CASC = '0') else
captureTrig0_Edge;
DELAY_CAPT_TRIG_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_pulse_d1 <= '0';
captureTrig0_pulse_d2 <= '0';
else
captureTrig0_pulse_d1 <= captureTrig0_pulse;
captureTrig0_pulse_d2 <= captureTrig0_pulse_d1;
end if;
end if;
end process DELAY_CAPT_TRIG_PROCESS;
TCSR0_Reg <= TCSR0;
TCSR1_Reg <= TCSR1;
end architecture imp;
| gpl-3.0 | dbcdb69da5de4623c3b25f1abb8e55a5 | 0.465464 | 3.909155 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-xc3s1600e/leon3mp.vhd | 1 | 23,247 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
ddrfreq : integer := 100000 -- frequency of ddr clock in kHz
);
port (
reset : in std_ulogic;
-- resoutn : out std_logic;
clk_50mhz : in std_ulogic;
errorn : out std_ulogic;
-- prom interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(15 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
byten : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(15 downto 0);
-- pragma translate_on
-- ddr memory
ddr_clk0 : out std_logic;
ddr_clk0b : out std_logic;
-- ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke0 : out std_logic;
ddr_cs0b : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsuen : in std_ulogic;
dsubre : in std_ulogic;
-- dsuact : out std_ulogic;
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART for serial console I/O
urxd1 : in std_ulogic;
utxd1 : out std_ulogic;
-- ethernet signals
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
spi : out std_ulogic;
led : out std_logic_vector(5 downto 0);
ps2clk : inout std_logic;
ps2data : inout std_logic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic;
vid_g : out std_logic;
vid_b : out std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal lclk : std_ulogic;
signal ddrclk, ddrrst, ddrclkfb : std_ulogic;
signal clkm, rstn, clkml, clk2x : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal vgao : apbvga_out_type;
signal ldsubre : std_logic;
signal duart, ldsuen : std_logic;
signal rsertx, rserrx, rdsuen : std_logic;
signal rstraw : std_logic;
signal rstneg : std_logic;
signal rxd1, rxd2 : std_logic;
signal txd1 : std_logic;
signal lock : std_logic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
rstneg <= not reset; spi <= '1';
rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
led(5) <= lock;
clk_pad : clkpad generic map (tech => padtech) port map (clk_50mhz, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
-- cgo.clklock <= '1';
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, ldsubre);
dsui.break <= ldsubre;
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
led(4) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd2);
dui.rxd <= rxd2;
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(2) <= not rxd2; led(3) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0,
paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 )
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
byten <= '1'; -- 16-bit flash
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (width => 24, tech => padtech)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8),
memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8));
end generate;
-- pragma translate_on
bdr : for i in 0 to 1 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- DDR memory controller -------------------------------------------
----------------------------------------------------------------------
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc : ddrspa generic map ( fabtech => spartan3e, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => 2*BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/10, clkdiv => 2*5, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16)
port map (
cgo.clklock, rstn, clk2x, clkm, lock, clkml, clkml, ahbsi, ahbso(4),
ddr_clk, ddr_clkb, open, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0);
ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0);
ddr_ad <= ddr_adl(12 downto 0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (urxd1, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (utxd1, txd1);
led(0) <= not rxd1; led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => 12 --CFG_GRGPIO_WIDTH
)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
-- vga : if CFG_VGA_ENABLE /= 0 generate
-- vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
-- port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
-- video_clock_pad : outpad generic map ( tech => padtech)
-- port map (vid_clock, dac_clk);
-- dac_clk <= not clkm;
-- end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk1 => 0, clk2 => 0, burstlen => 5)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
end generate;
-- blank_pad : outpad generic map (tech => padtech)
-- port map (vid_blankn, vgao.blank);
-- comp_sync_pad : outpad generic map (tech => padtech)
-- port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpad generic map (tech => padtech)
port map (vid_r, vgao.video_out_r(7));
video_out_g_pad : outpad generic map (tech => padtech)
port map (vid_g, vgao.video_out_g(7));
video_out_b_pad : outpad generic map (tech => padtech)
port map (vid_b, vgao.video_out_b(7));
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
phyrstadr => 31, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB DMA ----------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH,
-- pindex => 12, paddr => 12, dbuf => 32)
-- port map (rstn, clkm, apbi, apbo(12), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH));
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- resoutn <= rstn;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent Spartan3E Eval board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 | 788690296e08cead81cc49ea3ea13520 | 0.541231 | 3.659792 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_AXIvideo2Mat.vhd | 2 | 38,254 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_AXIvideo2Mat is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of image_filter_AXIvideo2Mat is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_ST_pp1_stg0_fsm_4 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_ST_st7_fsm_5 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_ST_st8_fsm_6 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_true : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_26 : BOOLEAN;
signal eol_1_reg_184 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_reg_195 : STD_LOGIC_VECTOR (31 downto 0);
signal p_1_reg_206 : STD_LOGIC_VECTOR (11 downto 0);
signal eol_reg_217 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V_2_reg_229 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_s_reg_241 : STD_LOGIC_VECTOR (31 downto 0);
signal eol_2_reg_253 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_75 : BOOLEAN;
signal tmp_data_V_reg_402 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_87 : BOOLEAN;
signal tmp_last_V_reg_410 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond1_fu_319_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_101 : BOOLEAN;
signal i_V_fu_324_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal i_V_reg_426 : STD_LOGIC_VECTOR (11 downto 0);
signal exitcond2_fu_330_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_reg_431 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp1_stg0_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_112 : BOOLEAN;
signal brmerge_fu_344_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_120 : BOOLEAN;
signal ap_reg_ppiten_pp1_it0 : STD_LOGIC := '0';
signal ap_sig_bdd_133 : BOOLEAN;
signal ap_reg_ppiten_pp1_it1 : STD_LOGIC := '0';
signal j_V_fu_335_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_13_fu_363_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_13_reg_444 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_14_reg_449 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_4_reg_454 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st7_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_158 : BOOLEAN;
signal ap_sig_bdd_163 : BOOLEAN;
signal axi_last_V_3_reg_264 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V1_reg_153 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st8_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_181 : BOOLEAN;
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_188 : BOOLEAN;
signal axi_data_V_3_reg_276 : STD_LOGIC_VECTOR (31 downto 0);
signal axi_data_V1_reg_163 : STD_LOGIC_VECTOR (31 downto 0);
signal p_s_reg_173 : STD_LOGIC_VECTOR (11 downto 0);
signal eol_1_phi_fu_187_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_phi_fu_198_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal eol_phi_fu_221_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_s_phi_fu_245_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_eol_2_reg_253pp1_it0 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V_1_mux_fu_356_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal eol_3_reg_288 : STD_LOGIC_VECTOR (0 downto 0);
signal sof_1_fu_98 : STD_LOGIC_VECTOR (0 downto 0);
signal not_sof_2_fu_350_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_user_V_fu_310_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (6 downto 0);
signal ap_sig_bdd_119 : BOOLEAN;
signal ap_sig_bdd_211 : BOOLEAN;
signal ap_sig_bdd_144 : BOOLEAN;
signal ap_sig_bdd_229 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((exitcond1_fu_319_p2 = ap_const_lv1_0)))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp1_it0 assign process. --
ap_reg_ppiten_pp1_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp1_it1 assign process. --
ap_reg_ppiten_pp1_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- axi_data_V1_reg_163 assign process. --
axi_data_V1_reg_163_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
axi_data_V1_reg_163 <= tmp_data_V_reg_402;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_6)) then
axi_data_V1_reg_163 <= axi_data_V_3_reg_276;
end if;
end if;
end process;
-- axi_data_V_1_reg_195 assign process. --
axi_data_V_1_reg_195_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
axi_data_V_1_reg_195 <= p_Val2_s_reg_241;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
axi_data_V_1_reg_195 <= axi_data_V1_reg_163;
end if;
end if;
end process;
-- axi_data_V_3_reg_276 assign process. --
axi_data_V_3_reg_276_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
axi_data_V_3_reg_276 <= axi_data_V_1_phi_fu_198_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
axi_data_V_3_reg_276 <= INPUT_STREAM_TDATA;
end if;
end if;
end process;
-- axi_last_V1_reg_153 assign process. --
axi_last_V1_reg_153_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
axi_last_V1_reg_153 <= tmp_last_V_reg_410;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_6)) then
axi_last_V1_reg_153 <= axi_last_V_3_reg_264;
end if;
end if;
end process;
-- axi_last_V_2_reg_229 assign process. --
axi_last_V_2_reg_229_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_144) then
if (ap_sig_bdd_211) then
axi_last_V_2_reg_229 <= eol_1_phi_fu_187_p4;
elsif (ap_sig_bdd_119) then
axi_last_V_2_reg_229 <= INPUT_STREAM_TLAST;
elsif ((ap_true = ap_true)) then
axi_last_V_2_reg_229 <= ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0;
end if;
end if;
end if;
end process;
-- axi_last_V_3_reg_264 assign process. --
axi_last_V_3_reg_264_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
axi_last_V_3_reg_264 <= eol_1_phi_fu_187_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
axi_last_V_3_reg_264 <= INPUT_STREAM_TLAST;
end if;
end if;
end process;
-- eol_1_reg_184 assign process. --
eol_1_reg_184_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
eol_1_reg_184 <= axi_last_V_2_reg_229;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
eol_1_reg_184 <= axi_last_V1_reg_153;
end if;
end if;
end process;
-- eol_2_reg_253 assign process. --
eol_2_reg_253_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_144) then
if (ap_sig_bdd_211) then
eol_2_reg_253 <= axi_last_V_1_mux_fu_356_p2;
elsif (ap_sig_bdd_119) then
eol_2_reg_253 <= INPUT_STREAM_TLAST;
elsif ((ap_true = ap_true)) then
eol_2_reg_253 <= ap_reg_phiprechg_eol_2_reg_253pp1_it0;
end if;
end if;
end if;
end process;
-- eol_3_reg_288 assign process. --
eol_3_reg_288_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
eol_3_reg_288 <= eol_phi_fu_221_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
eol_3_reg_288 <= INPUT_STREAM_TLAST;
end if;
end if;
end process;
-- eol_reg_217 assign process. --
eol_reg_217_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
eol_reg_217 <= eol_2_reg_253;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
eol_reg_217 <= ap_const_lv1_0;
end if;
end if;
end process;
-- p_1_reg_206 assign process. --
p_1_reg_206_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
p_1_reg_206 <= j_V_fu_335_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
p_1_reg_206 <= ap_const_lv12_0;
end if;
end if;
end process;
-- p_Val2_s_reg_241 assign process. --
p_Val2_s_reg_241_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_144) then
if (ap_sig_bdd_211) then
p_Val2_s_reg_241 <= axi_data_V_1_phi_fu_198_p4;
elsif (ap_sig_bdd_119) then
p_Val2_s_reg_241 <= INPUT_STREAM_TDATA;
elsif ((ap_true = ap_true)) then
p_Val2_s_reg_241 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end if;
end if;
end if;
end process;
-- p_s_reg_173 assign process. --
p_s_reg_173_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
p_s_reg_173 <= ap_const_lv12_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_6)) then
p_s_reg_173 <= i_V_reg_426;
end if;
end if;
end process;
-- sof_1_fu_98 assign process. --
sof_1_fu_98_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
sof_1_fu_98 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
sof_1_fu_98 <= ap_const_lv1_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
exitcond2_reg_431 <= exitcond2_fu_330_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
i_V_reg_426 <= i_V_fu_324_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
tmp_13_reg_444 <= tmp_13_fu_363_p1;
tmp_14_reg_449 <= p_Val2_s_phi_fu_245_p4(15 downto 8);
tmp_4_reg_454 <= p_Val2_s_phi_fu_245_p4(23 downto 16);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((INPUT_STREAM_TVALID = ap_const_logic_0)))) then
tmp_data_V_reg_402 <= INPUT_STREAM_TDATA;
tmp_last_V_reg_410 <= INPUT_STREAM_TLAST;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, INPUT_STREAM_TVALID, ap_sig_bdd_75, exitcond1_fu_319_p2, exitcond2_fu_330_p2, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1, ap_sig_bdd_163, eol_3_reg_288, tmp_user_V_fu_310_p1)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_75)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((not((INPUT_STREAM_TVALID = ap_const_logic_0)) and (ap_const_lv1_0 = tmp_user_V_fu_310_p1))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not((INPUT_STREAM_TVALID = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_user_V_fu_310_p1)))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
if (not((exitcond1_fu_319_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_4;
end if;
when ap_ST_pp1_stg0_fsm_4 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0))))) then
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_4;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st7_fsm_5;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_4;
end if;
when ap_ST_st7_fsm_5 =>
if (((ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
ap_NS_fsm <= ap_ST_st7_fsm_5;
elsif ((not(ap_sig_bdd_163) and not((ap_const_lv1_0 = eol_3_reg_288)))) then
ap_NS_fsm <= ap_ST_st8_fsm_6;
else
ap_NS_fsm <= ap_ST_st7_fsm_5;
end if;
when ap_ST_st8_fsm_6 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when others =>
ap_NS_fsm <= "XXXXXXX";
end case;
end process;
-- INPUT_STREAM_TREADY assign process. --
INPUT_STREAM_TREADY_assign_proc : process(INPUT_STREAM_TVALID, ap_sig_cseq_ST_st2_fsm_1, exitcond2_fu_330_p2, ap_sig_cseq_ST_pp1_stg0_fsm_4, brmerge_fu_344_p2, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1, ap_sig_cseq_ST_st7_fsm_5, ap_sig_bdd_163, eol_3_reg_288)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((INPUT_STREAM_TVALID = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = brmerge_fu_344_p2) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))))))) then
INPUT_STREAM_TREADY <= ap_const_logic_1;
else
INPUT_STREAM_TREADY <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, exitcond1_fu_319_p2, ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((exitcond1_fu_319_p2 = ap_const_lv1_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(exitcond1_fu_319_p2, ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((exitcond1_fu_319_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0 <= "X";
ap_reg_phiprechg_eol_2_reg_253pp1_it0 <= "X";
ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
-- ap_sig_bdd_101 assign process. --
ap_sig_bdd_101_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_101 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_112 assign process. --
ap_sig_bdd_112_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_112 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_119 assign process. --
ap_sig_bdd_119_assign_proc : process(exitcond2_fu_330_p2, brmerge_fu_344_p2)
begin
ap_sig_bdd_119 <= ((exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = brmerge_fu_344_p2));
end process;
-- ap_sig_bdd_120 assign process. --
ap_sig_bdd_120_assign_proc : process(INPUT_STREAM_TVALID, exitcond2_fu_330_p2, brmerge_fu_344_p2)
begin
ap_sig_bdd_120 <= ((INPUT_STREAM_TVALID = ap_const_logic_0) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = brmerge_fu_344_p2));
end process;
-- ap_sig_bdd_133 assign process. --
ap_sig_bdd_133_assign_proc : process(img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, exitcond2_reg_431)
begin
ap_sig_bdd_133 <= (((img_data_stream_0_V_full_n = ap_const_logic_0) and (exitcond2_reg_431 = ap_const_lv1_0)) or ((exitcond2_reg_431 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond2_reg_431 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)));
end process;
-- ap_sig_bdd_144 assign process. --
ap_sig_bdd_144_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
ap_sig_bdd_144 <= ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))));
end process;
-- ap_sig_bdd_158 assign process. --
ap_sig_bdd_158_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_158 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_163 assign process. --
ap_sig_bdd_163_assign_proc : process(INPUT_STREAM_TVALID, eol_3_reg_288)
begin
ap_sig_bdd_163 <= ((INPUT_STREAM_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = eol_3_reg_288));
end process;
-- ap_sig_bdd_181 assign process. --
ap_sig_bdd_181_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_181 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_188 assign process. --
ap_sig_bdd_188_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_188 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_211 assign process. --
ap_sig_bdd_211_assign_proc : process(exitcond2_fu_330_p2, brmerge_fu_344_p2)
begin
ap_sig_bdd_211 <= ((exitcond2_fu_330_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = brmerge_fu_344_p2)));
end process;
-- ap_sig_bdd_229 assign process. --
ap_sig_bdd_229_assign_proc : process(exitcond2_fu_330_p2, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it0)
begin
ap_sig_bdd_229 <= ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0));
end process;
-- ap_sig_bdd_26 assign process. --
ap_sig_bdd_26_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_26 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_75 assign process. --
ap_sig_bdd_75_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_75 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_87 assign process. --
ap_sig_bdd_87_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_87 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_pp1_stg0_fsm_4 assign process. --
ap_sig_cseq_ST_pp1_stg0_fsm_4_assign_proc : process(ap_sig_bdd_112)
begin
if (ap_sig_bdd_112) then
ap_sig_cseq_ST_pp1_stg0_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp1_stg0_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_26)
begin
if (ap_sig_bdd_26) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_87)
begin
if (ap_sig_bdd_87) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_188)
begin
if (ap_sig_bdd_188) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_101)
begin
if (ap_sig_bdd_101) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_5 assign process. --
ap_sig_cseq_ST_st7_fsm_5_assign_proc : process(ap_sig_bdd_158)
begin
if (ap_sig_bdd_158) then
ap_sig_cseq_ST_st7_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_6 assign process. --
ap_sig_cseq_ST_st8_fsm_6_assign_proc : process(ap_sig_bdd_181)
begin
if (ap_sig_bdd_181) then
ap_sig_cseq_ST_st8_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- axi_data_V_1_phi_fu_198_p4 assign process. --
axi_data_V_1_phi_fu_198_p4_assign_proc : process(axi_data_V_1_reg_195, p_Val2_s_reg_241, exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))) then
axi_data_V_1_phi_fu_198_p4 <= p_Val2_s_reg_241;
else
axi_data_V_1_phi_fu_198_p4 <= axi_data_V_1_reg_195;
end if;
end process;
axi_last_V_1_mux_fu_356_p2 <= (eol_1_phi_fu_187_p4 or not_sof_2_fu_350_p2);
brmerge_fu_344_p2 <= (sof_1_fu_98 or eol_phi_fu_221_p4);
-- eol_1_phi_fu_187_p4 assign process. --
eol_1_phi_fu_187_p4_assign_proc : process(eol_1_reg_184, axi_last_V_2_reg_229, exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))) then
eol_1_phi_fu_187_p4 <= axi_last_V_2_reg_229;
else
eol_1_phi_fu_187_p4 <= eol_1_reg_184;
end if;
end process;
-- eol_phi_fu_221_p4 assign process. --
eol_phi_fu_221_p4_assign_proc : process(eol_reg_217, eol_2_reg_253, exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))) then
eol_phi_fu_221_p4 <= eol_2_reg_253;
else
eol_phi_fu_221_p4 <= eol_reg_217;
end if;
end process;
exitcond1_fu_319_p2 <= "1" when (p_s_reg_173 = img_rows_V_read) else "0";
exitcond2_fu_330_p2 <= "1" when (p_1_reg_206 = img_cols_V_read) else "0";
i_V_fu_324_p2 <= std_logic_vector(unsigned(p_s_reg_173) + unsigned(ap_const_lv12_1));
img_data_stream_0_V_din <= tmp_13_reg_444;
-- img_data_stream_0_V_write assign process. --
img_data_stream_0_V_write_assign_proc : process(exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
img_data_stream_0_V_write <= ap_const_logic_1;
else
img_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_1_V_din <= tmp_14_reg_449;
-- img_data_stream_1_V_write assign process. --
img_data_stream_1_V_write_assign_proc : process(exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
img_data_stream_1_V_write <= ap_const_logic_1;
else
img_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_2_V_din <= tmp_4_reg_454;
-- img_data_stream_2_V_write assign process. --
img_data_stream_2_V_write_assign_proc : process(exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
img_data_stream_2_V_write <= ap_const_logic_1;
else
img_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
j_V_fu_335_p2 <= std_logic_vector(unsigned(p_1_reg_206) + unsigned(ap_const_lv12_1));
not_sof_2_fu_350_p2 <= (sof_1_fu_98 xor ap_const_lv1_1);
-- p_Val2_s_phi_fu_245_p4 assign process. --
p_Val2_s_phi_fu_245_p4_assign_proc : process(INPUT_STREAM_TDATA, brmerge_fu_344_p2, axi_data_V_1_phi_fu_198_p4, ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0, ap_sig_bdd_229)
begin
if (ap_sig_bdd_229) then
if (not((ap_const_lv1_0 = brmerge_fu_344_p2))) then
p_Val2_s_phi_fu_245_p4 <= axi_data_V_1_phi_fu_198_p4;
elsif ((ap_const_lv1_0 = brmerge_fu_344_p2)) then
p_Val2_s_phi_fu_245_p4 <= INPUT_STREAM_TDATA;
else
p_Val2_s_phi_fu_245_p4 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end if;
else
p_Val2_s_phi_fu_245_p4 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end if;
end process;
tmp_13_fu_363_p1 <= p_Val2_s_phi_fu_245_p4(8 - 1 downto 0);
tmp_user_V_fu_310_p1 <= INPUT_STREAM_TUSER;
end behav;
| gpl-3.0 | 429fe8ef3a35002af2667b92ad41018d | 0.581952 | 2.702317 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/altera_mf/memory_altera_mf.vhd | 1 | 8,340 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_altera_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Altera altsynram
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of altera_syncram_dp is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
address_b : in std_logic_vector(widthad_b-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
data_b : in std_logic_vector(width_b-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
q_b : out std_logic_vector(width_b-1 downto 0);
rden_b : in std_logic;
wren_a : in std_logic;
wren_b : in std_logic
);
end component;
begin
u0 : altsyncram
generic map (
WIDTH_A => dbits, WIDTHAD_A => abits,
WIDTH_B => dbits, WIDTHAD_B => abits)
port map (
address_a => address1, address_b => address2, clock0 => clk1,
clock1 => clk2, data_a => datain1, data_b => datain2,
q_a => dataout1, q_b => dataout2, rden_b => enable2,
wren_a => write1, wren_b => write2);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
entity altera_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of altera_syncram is
component altera_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(dbits-1 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
u0: altera_syncram_dp
generic map (abits, dbits)
port map (
clk1 => clk, address1 => address, datain1 => datain,
dataout1 => dataout, enable1 => enable, write1 => write,
clk2 => clk, address2 => agnd, datain2 => dgnd,
dataout2 => open, enable2 => agnd(0), write2 => agnd(0));
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram128bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end;
architecture behav of altera_syncram128bw is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1;
byte_size : integer := 0;
width_byteena_a : integer := 1
);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
wren_a : in std_logic;
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1')
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(127 downto 0);
signal write1 : std_logic;
signal enablex : std_logic_vector (15 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
write1 <= orv(write and enable);
enablex <= write when write1 = '1' else enable;
u0 : altsyncram
generic map (
WIDTH_A => 128, WIDTHAD_A => abits,
WIDTH_B => 128, WIDTHAD_B => abits, byte_size => 8,
width_byteena_a => 16 )
port map (
address_a => address, clock0 => clk, clock1 => clk,
data_a => datain, q_a => dataout, wren_a => write1,
byteena_a => enablex );
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altsyncram;
-- pragma translate_on
entity altera_syncram256bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0)
);
end;
architecture behav of altera_syncram256bw is
component altsyncram
generic (
width_a : natural;
width_b : natural := 1;
widthad_a : natural;
widthad_b : natural := 1;
byte_size : integer := 0;
width_byteena_a : integer := 1
);
port(
address_a : in std_logic_vector(widthad_a-1 downto 0);
clock0 : in std_logic;
clock1 : in std_logic;
data_a : in std_logic_vector(width_a-1 downto 0);
q_a : out std_logic_vector(width_a-1 downto 0);
wren_a : in std_logic;
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1')
);
end component;
signal agnd : std_logic_vector(abits-1 downto 0);
signal dgnd : std_logic_vector(255 downto 0);
signal write1 : std_logic;
signal enablex : std_logic_vector (31 downto 0);
begin
agnd <= (others => '0'); dgnd <= (others => '0');
write1 <= orv(write and enable);
enablex <= write when write1 = '1' else enable;
u0 : altsyncram
generic map (
WIDTH_A => 256, WIDTHAD_A => abits,
WIDTH_B => 256, WIDTHAD_B => abits, byte_size => 8,
width_byteena_a => 32 )
port map (
address_a => address, clock0 => clk, clock1 => clk,
data_a => datain, q_a => dataout, wren_a => write1,
byteena_a => enablex );
end;
| gpl-2.0 | e59094600925c7e9b408088acc6bcf4c | 0.619185 | 3.296443 | false | false | false | false |
laurocruz/snakes_vhdl | src/snake_lib/snake_dir.vhd | 1 | 831 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY snake_lib;
USE snake_lib.snake_pack.all;
ENTITY snake_dir IS
PORT (reset : IN STD_LOGIC;
snake_turn : IN STD_LOGIC_VECTOR(1 downto 0);
dir : BUFFER STD_LOGIC_VECTOR(0 to 1));
END snake_dir;
ARCHITECTURE Behavior OF snake_dir IS
BEGIN
PROCESS(snake_turn(0), snake_turn(1), reset)
BEGIN
IF (reset = '1') THEN
dir <= "11";
ELSIF (snake_turn(0) = '1') THEN
IF (dir = "00") THEN
dir <= "01";
ELSIF (dir = "01") THEN
dir <= "11";
ElSIF (dir = "11") THEN
dir <= "10";
ELSE
dir <= "00";
END IF;
ELSIF (snake_turn(1) = '1') THEN
IF (dir = "00") THEN
dir <= "10";
ELSIF (dir = "10") THEN
dir <= "11";
ELSIF (dir = "11") THEN
dir <= "01";
ELSE
dir <= "00";
END IF;
END IF;
END PROCESS;
END Behavior;
| mit | f1779f8629bee585a8c58b5704473cfc | 0.565584 | 2.541284 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ddr/ddr2spax_ddr.vhd | 1 | 52,333 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spax
-- File: ddr2spax.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: DDR2 memory controller with asynch AHB interface
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr2spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
-- dqsgating : integer := 0;
nosync : integer := 0;
dqsgating : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
phytech : integer := 0;
hasdqvalid : integer := 0;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
hwidth : in std_ulogic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end ddr2spax_ddr;
architecture rtl of ddr2spax_ddr is
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
function tosl(x: integer) return std_logic is
begin
if x /= 0 then return '1'; else return '0'; end if;
end tosl;
function zerov(w: integer) return std_logic_vector is
constant r: std_logic_vector(w-1 downto 0) := (others => '0');
begin
return r;
end zerov;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
constant oepols: std_logic := tosl(oepol);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_rabits: integer := 1+l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant wbuf_rdbits: integer := 2*ddrbits;
-- Read buffer dimensions
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := 2*(ddrbits+chkbits);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(3 downto 0);
trcd : std_logic_vector(2 downto 0); -- tRCD : 2-9 clock cycles
trfc : std_logic_vector(7 downto 0);
trp : std_logic_vector(2 downto 0); -- precharge to activate: 2-9 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
cal_en : std_logic_vector(7 downto 0);
cal_inc : std_logic_vector(7 downto 0);
cbcal_en : std_logic_vector(3 downto 0);
cbcal_inc : std_logic_vector(3 downto 0);
cal_pll : std_logic_vector(1 downto 0); -- *** ??? pll_reconf
cal_rst : std_logic;
readdly : std_logic_vector(3 downto 0);
twr : std_logic_vector(4 downto 0);
emr : std_logic_vector(1 downto 0); -- selects EM register
ocd : std_ulogic; -- enable/disable ocd
dqsctrl : std_logic_vector(7 downto 0);
eightbanks : std_ulogic;
caslat : std_logic_vector(1 downto 0); -- CAS latency 3-6
odten : std_logic_vector(1 downto 0);
tras : std_logic_vector(4 downto 0); -- RAS-to-Precharge minimum
trtp : std_ulogic;
regmem : std_ulogic; -- Registered memory (1 cycle extra latency)
strength : std_ulogic; -- Drive strength 1=reduced, 0=normal
end record;
constant ddr_burstlen: integer := (burstlen*32)/(2*ddrbits);
constant l2ddr_burstlen: integer := l2blen-l2ddrw;
type ddrstate is (dsidle,dsrascas,dscaslat,dsreaddly,dsdata,dsdone,dsagain,dsreg,dsrefresh,dspreall);
type ddrcmdstate is (dcrstdel,dcoff,dcinit1,dcinit2,dcinit3,dcinit4,dcinit5,dcinit6,dcinit7,dcinit8,dcon);
type ddr_reg_type is record
s : ddrstate;
cmds : ddrcmdstate;
response : ddr_response_type;
response1 : ddr_response_type;
response2 : ddr_response_type;
response_prev : ddr_response_type;
cfg : sdram_cfg_type;
rowsel : std_logic_vector(2 downto 0);
endaddr : std_logic_vector(l2blen-4 downto 2);
addrlo : std_logic_vector(l2ddrw-4 downto 0);
col : std_logic_vector(13 downto 0);
hwrite : std_logic;
hsize : std_logic_vector(2 downto 0);
ctr : std_logic_vector(7 downto 0);
casctr : std_logic_vector(l2ddr_burstlen-1 downto 0);
datacas : std_logic;
prectr : std_logic_vector(5 downto 0);
rastimer : std_logic_vector(4 downto 0);
tras_met : std_logic;
pchpend : std_logic;
refctr : std_logic_vector(16 downto 0);
refpend : std_logic;
pastlast : std_logic;
sdo_csn : std_logic_vector(1 downto 0);
sdo_wen : std_ulogic;
wen_prev : std_ulogic;
sdo_rasn : std_ulogic;
rasn_pre : std_ulogic;
sdo_casn : std_ulogic;
sdo_dqm : std_logic_vector(15 downto 0);
dqm_prev : std_logic_vector(15 downto 0);
twr_plus_cl : std_logic_vector(5 downto 0);
request_row : std_logic_vector(14 downto 0);
request_bank : std_logic_vector(2 downto 0);
request_cs : std_logic_vector(0 downto 0);
row : std_logic_vector(14 downto 0);
setrow : std_logic;
samerow : std_logic;
start_tog_prev: std_logic;
sdo_bdrive : std_ulogic;
sdo_qdrive : std_ulogic;
sdo_nbdrive : std_ulogic;
sdo_address : std_logic_vector(14 downto 0);
sdo_address_prev: std_logic_vector(14 downto 0);
sdo_ba : std_logic_vector(2 downto 0);
sdo_data : std_logic_vector(sdo.data'length-1 downto 0);
sdo_cb : std_logic_vector(sdo.cb'length-1 downto 0);
sdo_odt : std_logic;
sdo_oct : std_logic;
rbwrite : std_logic;
rbwdata : std_logic_vector(rbuf_wdbits-1 downto 0);
ramaddr : std_logic_vector(rbuf_wabits-1 downto 0);
ramaddr_prev : std_logic_vector(rbuf_wabits-1 downto 0);
mr_twr : std_logic_vector(2 downto 0);
mr_tcl : std_logic_vector(2 downto 0);
read_pend : std_logic_vector(15 downto 0);
req1,req2 : ddr_request_type;
start1,start2 : std_logic;
hwidth1 : std_logic;
hwidth : std_logic;
hwcas : std_logic;
hwctr : std_logic;
end record;
signal dr,ndr : ddr_reg_type;
signal muxsel2,muxsel1,muxsel0: std_ulogic;
signal muxin4: std_logic_vector(31 downto 0);
signal muxout4: std_logic_vector(3 downto 0);
signal start_tog_delta1,start_tog_delta2: std_logic;
signal arst: std_ulogic;
attribute syn_keep: boolean;
attribute syn_keep of muxsel2:signal is true;
attribute syn_keep of muxsel1:signal is true;
attribute syn_keep of muxsel0:signal is true;
begin
arst <= testrst when (scantest/=0 and ddr_syncrst=0) and testen='1' else ddr_rst;
start_tog_delta1 <= start_tog;
start_tog_delta2 <= start_tog_delta1;
muxsel2 <= dr.rowsel(2);
muxsel1 <= dr.rowsel(1);
muxsel0 <= dr.rowsel(0);
muxproc : process(muxin4,muxsel2,muxsel1,muxsel0)
begin
muxout4(3) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(31 downto 24));
muxout4(2) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(23 downto 16));
muxout4(1) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(15 downto 8));
muxout4(0) <= genmux((muxsel2 & muxsel1 & muxsel0),muxin4(7 downto 0));
end process;
ddrcomb : process(ddr_rst,sdi,request,frequest,start_tog_delta2,dr,wbrdata,muxout4,hwidth,reqsel,testen,testoen)
constant plmemwrite: boolean := false;
constant plmemread: boolean := false;
variable dv: ddr_reg_type;
variable o: ddrctrl_out_type;
variable bdrive,qdrive: std_logic;
variable vreq,vreqf: ddr_request_type;
variable resp,resp2: ddr_response_type;
variable vstart: std_logic;
variable acsn: std_logic_vector(1 downto 0);
variable arow: std_logic_vector(14 downto 0);
variable acol: std_logic_vector(13 downto 0);
variable abank: std_logic_vector(2 downto 0);
variable aendaddr: std_logic_vector(l2blen-4 downto 2);
variable aloa: std_logic_vector(l2ddrw-4 downto 0);
variable rbw: std_logic;
variable rbwd: std_logic_vector(rbuf_wdbits-1 downto 0);
variable rbwa: std_logic_vector(rbuf_wabits-1 downto 0);
variable wbra: std_logic_vector(wbuf_rabits-1 downto 0);
variable regdata: std_logic_vector(31 downto 0);
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
variable regsd3 : std_logic_vector(31 downto 0); -- data from registers
variable regsd4 : std_logic_vector(31 downto 0); -- data from registers
variable regsd5 : std_logic_vector(31 downto 0); -- data from registers
variable mr : std_logic_vector(14 downto 0); -- DDR2 Mode register
variable mask: std_logic_vector(15 downto 0);
variable hio1: std_logic;
variable w5: std_logic;
variable precharge_next: std_logic;
variable precharge_notras: std_logic;
variable goto_caslat: std_logic;
variable block_precharge: std_logic;
variable regt0,regt1: std_logic_vector(ddrbits-1 downto 0);
variable addrtemp3,addrtemp2,addrtemp1,addrtemp0: std_logic_vector(7 downto 0);
variable expcsize: std_logic_vector(2 downto 0);
variable caslat_reg: std_logic_vector(2 downto 0);
variable addrlo32, endaddr32: std_logic_vector(3 downto 2);
variable endaddr43: std_logic_vector(4 downto 3);
variable endaddr42: std_logic_vector(4 downto 2);
variable inc_rctr: std_logic;
begin
dv := dr;
o := ddrctrl_out_none;
o.sdcke := (others => dr.cfg.cke);
o.sdcsn := dr.sdo_csn;
o.sdwen := dr.wen_prev;
o.rasn := dr.sdo_rasn and dr.rasn_pre;
o.casn := dr.sdo_casn and dr.datacas;
o.dqm := dr.dqm_prev;
o.bdrive := dr.sdo_bdrive;
o.qdrive := dr.sdo_qdrive;
o.nbdrive := dr.sdo_nbdrive;
o.address := dr.sdo_address;
o.data := dr.sdo_data;
o.ba := dr.sdo_ba;
o.cal_en := dr.cfg.cal_en;
o.cal_inc := dr.cfg.cal_inc;
o.cal_pll := dr.cfg.cal_pll;
o.cal_rst := dr.cfg.cal_rst;
o.odt := (others => dr.sdo_odt);
o.oct := dr.sdo_oct;
o.cb := dr.sdo_cb;
o.cbcal_en := dr.cfg.cbcal_en;
o.cbcal_inc := dr.cfg.cbcal_inc;
resp := ddr_response_none;
resp2 := ddr_response_none;
rbw := dr.rbwrite;
rbwd := dr.rbwdata;
rbwa := (others => '0');
w5 := '0';
wbra := dr.response.done_tog & dr.ramaddr;
dv.ramaddr_prev := dr.ramaddr;
dv.dqm_prev := dr.sdo_dqm;
dv.wen_prev := dr.sdo_wen;
dv.response_prev := dr.response;
dv.sdo_address_prev := dr.sdo_address;
dv.cfg.cal_en := (others => '0');
dv.cfg.cal_inc := (others => '0');
dv.cfg.cal_pll := (others => '0');
dv.cfg.cal_rst := '0';
dv.cfg.cbcal_en := (others => '0');
dv.cfg.cbcal_inc := (others => '0');
dv.sdo_data := (others => '0');
dv.sdo_data(2*ddrbits-1 downto ddrbits) := wbrdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits);
dv.sdo_data(ddrbits-1 downto 0) := wbrdata(ddrbits-1 downto 0);
dv.sdo_cb := (others => '0');
if chkbits > 0 then
dv.sdo_cb(2*chkbits-1 downto chkbits) := wbrdata(2*ddrbits+2*chkbits-1 downto 2*ddrbits+chkbits);
dv.sdo_cb(chkbits-1 downto 0) := wbrdata(ddrbits+chkbits-1 downto ddrbits);
end if;
if hwidthen/=0 and dr.hwidth='1' and dr.hwctr='1' then
dv.sdo_data(ddrbits-1 downto 0) := dr.sdo_data(2*ddrbits-1 downto ddrbits);
if chkbits > 0 then
dv.sdo_cb(chkbits-1 downto 0) := dr.sdo_cb(2*chkbits-1 downto chkbits);
end if;
end if;
if not (hwidthen/=0 and hasdqvalid/=0 and sdi.datavalid='0') then
dv.rbwdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits) := sdi.data(2*ddrbits-1 downto ddrbits);
dv.rbwdata(ddrbits-1 downto 0) := sdi.data(ddrbits-1 downto 0);
if chkbits > 0 then
dv.rbwdata(2*ddrbits+2*chkbits-1 downto 2*ddrbits+chkbits) := sdi.cb(2*chkbits-1 downto chkbits);
dv.rbwdata(ddrbits+chkbits-1 downto ddrbits) := sdi.cb(chkbits-1 downto 0);
end if;
-- Half-width input data muxing
if hwidthen/=0 and dr.hwidth='1' and dr.hwctr='1' then
dv.rbwdata(2*ddrbits+chkbits-1 downto 2*ddrbits+chkbits-ddrbits/2) :=
dr.rbwdata(2*ddrbits+chkbits-ddrbits/2-1 downto ddrbits+chkbits);
dv.rbwdata(2*ddrbits+chkbits-ddrbits/2-1 downto ddrbits+chkbits) :=
dr.rbwdata(ddrbits/2-1 downto 0);
dv.rbwdata(ddrbits-1 downto ddrbits/2) :=
sdi.data(ddrbits+ddrbits/2-1 downto ddrbits);
if chkbits > 0 then
dv.rbwdata(2*ddrbits+2*chkbits-1 downto 2*ddrbits+2*chkbits-chkbits/2) :=
dr.rbwdata(2*ddrbits+2*chkbits-chkbits/2-1 downto 2*ddrbits+chkbits);
dv.rbwdata(2*ddrbits+2*chkbits-chkbits/2-1 downto 2*ddrbits+chkbits) :=
dr.rbwdata(ddrbits+chkbits/2-1 downto ddrbits);
dv.rbwdata(ddrbits+chkbits-1 downto ddrbits+chkbits/2) :=
sdi.cb(chkbits+chkbits/2-1 downto chkbits);
end if;
end if;
end if;
-- hwidth input should be constant but sample it for robustness
-- then sample in one more stage to allow replication if necessary
dv.hwidth1 := hwidth;
dv.hwidth := dr.hwidth1;
if hwidthen=0 then dv.hwidth:='0'; end if;
-- Synchronize 1/2 stages
dv.req1 := request; dv.req2 := dr.req1;
dv.start1 := start_tog_delta2; dv.start2 := dr.start1;
vstart := dr.start2;
vreq := dr.req2;
vreqf := dr.req1;
if nosync /= 0 then vstart:=start_tog_delta2; vreq:=request; vreqf:=request; end if;
if nosync > 1 then vreqf:=frequest; end if;
dv.start_tog_prev := vstart;
regsd1 := (others => '0');
regsd1(31 downto 15) := dr.cfg.refon & dr.cfg.ocd & dr.cfg.emr & dr.cfg.bsize(3) & dr.cfg.trcd(0) &
dr.cfg.bsize(2 downto 0) & dr.cfg.csize & dr.cfg.command &
dr.cfg.dllrst & dr.cfg.renable & dr.cfg.cke;
regsd1(11 downto 0) := dr.cfg.refresh;
regsd2 := (others => '0');
regsd2(25 downto 18) := std_logic_vector(to_unsigned(phytech,8));
if bigmem /= 0 then regsd2(17):='1'; end if;
if chkbits > 0 then regsd2(16):='1'; end if;
regsd2(15 downto 0) := "1" &
std_logic_vector(to_unsigned(log2(ddrbits/8),3)) &
std_logic_vector(to_unsigned(MHz,12));
if dr.hwidth='1' then
regsd2(14 downto 12) := std_logic_vector(to_unsigned(log2((ddrbits/2)/8),3));
end if;
regsd3 := (others => '0');
regsd3(17 downto 16) := dr.cfg.readdly(1 downto 0);
regsd3(22 downto 18) := dr.cfg.trfc(4 downto 0);
regsd3(27 downto 23) := dr.cfg.twr;
regsd3(28) := dr.cfg.trp(0);
regsd4 := (others => '0');
regsd4(23 downto 22) := dr.cfg.readdly(3 downto 2);
regsd4(21) := dr.cfg.regmem;
regsd4(13 downto 0) := dr.cfg.trtp & "00" & dr.cfg.caslat &
dr.cfg.eightbanks & dr.cfg.dqsctrl;
regsd5 := (others => '0');
regsd5(30 downto 28) := dr.cfg.trp;
regsd5(25 downto 18) := dr.cfg.trfc;
regsd5(17 downto 16) := dr.cfg.odten;
regsd5(15) := dr.cfg.strength;
regsd5(10 downto 8) := dr.cfg.trcd;
regsd5(4 downto 0) := dr.cfg.tras;
case ddrbits is
when 16 => o.regwdata := dr.sdo_data(31 downto 0) & dr.sdo_data(31 downto 0);
when 32 => o.regwdata := dr.sdo_data(31 downto 0) & dr.sdo_data(63 downto 32);
when 64 => o.regwdata := dr.sdo_data(31 downto 0) & dr.sdo_data(63 downto 32);
when others => o.regwdata := dr.sdo_data(2*ddrbits-7*32-1 downto 2*ddrbits-8*32) &
dr.sdo_data(2*ddrbits-6*32-1 downto 2*ddrbits-7*32);
end case;
if dr.cfg.regmem='1' then
caslat_reg := std_logic_vector(unsigned('0' & dr.cfg.caslat)+1);
else
caslat_reg := '0' & dr.cfg.caslat;
end if;
-- Mode register
dv.mr_twr := std_logic_vector(unsigned(dr.cfg.twr(2 downto 0))-3);
if dv.mr_twr="110" or dv.mr_twr="111" or dv.mr_twr="000" then
dv.mr_twr := "101";
end if;
dv.mr_tcl := std_logic_vector(unsigned('0' & dr.cfg.caslat)+3);
mr := (others => '0');
mr(12) := '0'; -- Power down exit time
mr(11 downto 9) := dr.mr_twr; -- WR-1
mr(8) := dr.cfg.dllrst; -- DLL Reset
mr(7) := '0'; -- Test mode
mr(6 downto 4) := dr.mr_tcl; -- CL
mr(3) := '0'; -- Burst type, 0=seq 1=interl
mr(2 downto 0) := "010"; -- Burst len 010=4, 011=8
-- Calculate address parts from a2ds.haddr and a2ds.startword
expcsize := dr.hwidth & dr.cfg.csize;
case expcsize is
when "011" => arow := vreqf.startaddr(l2ddrw+22 downto l2ddrw+8);
when "111" | "010" => arow := vreqf.startaddr(l2ddrw+21 downto l2ddrw+7);
when "110" | "001" => arow := vreqf.startaddr(l2ddrw+20 downto l2ddrw+6);
when "101" | "000" => arow := vreqf.startaddr(l2ddrw+19 downto l2ddrw+5);
when others => arow := vreqf.startaddr(l2ddrw+18 downto l2ddrw+4);
end case;
dv.rowsel := dr.cfg.bsize(2 downto 0);
if bigmem /= 0 and dr.cfg.bsize(3 downto 1)="000" then
dv.rowsel := "010";
end if;
if bigmem = 0 and dr.cfg.bsize(3)='1' then
dv.rowsel := "111";
end if;
addrtemp3 := vreqf.startaddr(30 downto 23); --CS
addrtemp2 := vreqf.startaddr(29 downto 22); --BA2/1
addrtemp1 := vreqf.startaddr(28 downto 21); --BA1/0
addrtemp0 := vreqf.startaddr(27 downto 20); --BA0/-
if bigmem=1 then
addrtemp3(1 downto 0) := "0" & vreqf.startaddr(31);
addrtemp2(1 downto 0) := vreqf.startaddr(31 downto 30);
addrtemp1(1 downto 0) := vreqf.startaddr(30 downto 29);
addrtemp0(1 downto 0) := vreqf.startaddr(29 downto 28);
end if;
muxin4 <= addrtemp3 & addrtemp2 & addrtemp1 & addrtemp0;
abank := muxout4(2 downto 0);
if dr.cfg.eightbanks='0' then
abank := '0' & abank(2) & abank(1);
end if;
acol := vreqf.startaddr(log2(ddrbits/8)+13 downto log2(ddrbits/8));
if ddrbits=16 then acol(0):='0'; end if; -- Always align to at least 32 bits
acsn(0) := muxout4(3);
acsn(1) := not acsn(0);
dv.setrow := '0';
if dr.setrow='1' then
dv.row := dr.sdo_address_prev;
end if;
dv.samerow := '0';
if abank=dr.sdo_ba and acsn=dr.sdo_csn and arow=dr.row then
dv.samerow := '1';
end if;
dv.request_row := arow;
dv.request_cs := acsn(0 downto 0);
dv.request_bank := abank;
hio1 := vreqf.hio;
if raspipe /= 0 then
vstart := dr.start_tog_prev;
arow := dr.request_row;
acsn := (not dr.request_cs) & dr.request_cs;
abank := dr.request_bank;
hio1 := vreq.hio;
end if;
aendaddr := vreq.endaddr(log2(4*burstlen)-1 downto 2);
if vreq.hsize(1 downto 0)="11" and vreq.hio='0' then
aendaddr(2):='1';
end if;
if ahbdw > 64 and vreqf.hsize(2)='1' then
aendaddr(3 downto 2) := "11";
if ahbdw > 128 and vreqf.hsize(0)='1' then
aendaddr(4) := '1';
end if;
end if;
aloa(l2ddrw-4 downto 0) := vreq.startaddr(l2ddrw-4 downto 0);
if ddrbits > 32 then addrlo32 := dr.addrlo(3 downto 2);
elsif ddrbits > 16 then addrlo32 := '0' & dr.addrlo(2);
else addrlo32 := "00";
end if;
endaddr32 := dr.endaddr(3 downto 2);
endaddr43 := dr.endaddr(4 downto 3);
endaddr42 := dr.endaddr(4 downto 2);
-- Calculate data mask
mask := (others => dr.pastlast);
-- Set mask bits for <word access
if dr.hsize="000" then
if dr.addrlo(0)='1' then
mask := mask or "1010101010101010";
else
mask := mask or "0101010101010101";
end if;
end if;
if dr.hsize(2 downto 1)="00" then
if dr.addrlo(1)='1' then
mask := mask or "1100110011001100";
else
mask := mask or "0011001100110011";
end if;
end if;
-- First access
-- (this could be written in generic code instead)
if dr.ctr=zerov(dr.ctr'length) then
case ddrbits is
when 16 =>
null;
when 32 =>
if dr.addrlo(2)='1' then
mask(7 downto 0) := mask(7 downto 0) or x"F0";
end if;
when 64 =>
case addrlo32 is
when "00" => null;
when "01" => mask := mask or x"F000";
when "10" => mask := mask or x"FF00";
when others => mask := mask or x"FFF0";
end case;
when others => null;
end case;
end if;
-- Last access
if dr.ramaddr = dr.endaddr(log2(4*burstlen)-1 downto log2(2*ddrbits/8)) then
if hwidthen=0 or dr.hwidth='0' or dr.hwctr='1' then
dv.pastlast := '1';
end if;
case ddrbits is
when 16 => null;
when 32 =>
if dr.endaddr(2)='0' then
mask(7 downto 0) := mask(7 downto 0) or x"0F";
end if;
when 64 =>
case endaddr32 is
when "00" => mask := mask or x"0FFF";
when "01" => mask := mask or x"00FF";
when "10" => mask := mask or x"000F";
when others => null;
end case;
when others => null;
end case;
end if;
-- Before first
if dr.col(1)='1' and dr.ctr(0)='1' and dr.ctr(dr.ctr'high downto 1)=zerov(dr.ctr'length-1) then
mask := mask or x"FFFF";
end if;
dv.sdo_rasn := '1'; dv.sdo_casn := '1'; dv.sdo_wen := '1';
dv.sdo_odt := '0'; dv.sdo_oct := '0';
dv.rbwrite := '0';
dv.ctr := std_logic_vector(unsigned(dr.ctr)+1);
if hwidthen/=0 and dr.hwidth='1' and dr.s=dsdata then
dv.hwctr := not dr.hwctr;
if dr.hwctr='0' then dv.ctr := dr.ctr; end if;
end if;
dv.rastimer := std_logic_vector(unsigned(dr.rastimer)+1);
if dr.rastimer=dr.cfg.tras then dv.tras_met := '1'; end if;
-- Calculate whether we would precharge the next cycle if Tras=0
precharge_notras := '0';
if dr.casctr=zerov(dr.casctr'length) and dr.prectr="000000" and dr.pchpend='1' then
precharge_notras := '1';
end if;
-- Calculate whether we should precharge the next cycle
precharge_next := precharge_notras and dr.tras_met;
block_precharge := '0';
inc_rctr := '0';
goto_caslat := '0';
case dr.s is
when dsidle =>
dv.ctr := (others => '0');
dv.hwctr := '0';
dv.sdo_bdrive := not oepols;
dv.sdo_qdrive := not oepols;
dv.sdo_nbdrive := not oepols;
dv.col := acol;
dv.sdo_csn := (others => '1');
dv.rastimer := (others => '0');
dv.tras_met := '0';
dv.response.rctr_gray := "0000";
if dr.refpend='1' and dr.cfg.refon='1' then
-- Periodic refresh
dv.sdo_csn := (others => '0');
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.refpend := '0';
dv.s := dsrefresh;
elsif vstart /= dr.response.done_tog and (dr.cmds=dcon or (dr.cmds=dcoff and dr.cfg.renable='0')) then
-- R/W data
dv.sdo_rasn := '0' or hio1;
dv.sdo_csn := acsn;
dv.sdo_address := arow;
dv.sdo_ba := abank;
dv.s := dsrascas;
elsif dr.cfg.command /= "000" then
-- Command
dv.sdo_csn := (others => '0');
if dr.cfg.command(2 downto 1)="11" then
dv.sdo_wen:='0'; dv.sdo_casn:='0'; dv.sdo_rasn:='0';
dv.sdo_ba := "00" & dr.cfg.command(0);
if dr.cfg.command(0)='0' or dr.cfg.emr="00" then
dv.sdo_ba := "000";
dv.sdo_address := mr;
else
dv.sdo_ba := "0" & dr.cfg.emr;
if dr.cfg.emr="01" then
dv.sdo_address := "0000"&conv_std_logic(dqsse=1)&dr.cfg.ocd&dr.cfg.ocd&dr.cfg.ocd
& dr.cfg.odten(1)&"000"& dr.cfg.odten(0) & dr.cfg.strength & "0";
else
dv.sdo_address := (others => '0');
end if;
end if;
else
dv.sdo_wen := dr.cfg.command(2);
dv.sdo_casn := dr.cfg.command(1);
dv.sdo_rasn := dr.cfg.command(0);
dv.sdo_address(10) := '1';
-- print("X Command: " & tost(dr.cfg.command) & " -> casn:" & tost(dv.sdo_casn) & ",rasn:" & tost(dv.sdo_rasn) & ",wen:" & tost(dv.sdo_wen));
end if;
dv.cfg.command := "000";
if dr.cfg.command=CMD_REF then
dv.s := dsrefresh;
end if;
if dr.cfg.command=CMD_PRE then
dv.s := dspreall;
end if;
end if;
when dsrascas =>
if dr.ctr(2 downto 0)="000" then
-- pragma translate_off
assert dr.ctr="00000000" severity failure;
-- pragma translate_on
-- dv.row := dr.sdo_address;
dv.setrow := '1';
end if;
dv.hwrite := vreq.hwrite;
dv.hsize := vreq.hsize;
dv.endaddr := aendaddr;
dv.addrlo := aloa;
dv.sdo_address := dr.col(13 downto 10) & '0' & dr.col(9 downto 1) & '0';
if dr.hwidth='1' then
dv.sdo_address := dr.col(12 downto 9) & '0' & dr.col(8 downto 1) & "00";
end if;
if vreq.hio='1' and dr.ctr(0)='1' then
dv.s := dsreg;
dv.ctr := (others => '0');
dv.hwctr := '0';
elsif vreq.hio='0' and dr.ctr(2 downto 0)=dr.cfg.trcd then
goto_caslat := '1';
end if;
when dscaslat =>
dv.sdo_odt := dr.hwrite;
dv.sdo_oct := not dr.hwrite;
dv.pastlast := '0';
if dr.ctr(2 downto 0)=caslat_reg then
if dr.hwrite='1' then
dv.s := dsdata;
else
dv.s := dsreaddly;
end if;
dv.ctr := (others => '0');
dv.hwctr := '0';
dv.sdo_qdrive := not (dr.hwrite xor oepols);
dv.sdo_nbdrive := not (dr.hwrite xor oepols);
end if;
when dsreaddly =>
dv.sdo_odt := dr.hwrite;
dv.sdo_oct := not dr.hwrite;
dv.pastlast := '0';
if dr.ctr(3 downto 0)=dr.cfg.readdly then
dv.s := dsdata;
dv.ctr := (others => '0');
dv.hwctr := '0';
end if;
when dsdata =>
inc_rctr := '0';
dv.sdo_odt := dr.hwrite;
dv.sdo_oct := not dr.hwrite;
dv.rbwrite := '1';
dv.sdo_dqm := mask;
dv.sdo_bdrive := not (dr.hwrite xor oepols);
dv.sdo_qdrive := not (dr.hwrite xor oepols);
dv.sdo_nbdrive := not (dr.hwrite xor oepols);
-- If-case to handle pausing for half-width mode
if hwidthen=0 or dr.hwidth='0' or dr.hwctr='1' then
inc_rctr := '1';
-- The first request may be on a 2-odd column to get the first data first
-- Make sure following requests are on even mult of 4xcolumns
if dr.ctr(0)='1' then
dv.col(1) := '0';
end if;
-- Make sure we don't advance read counter for the unwanted 3:rd/4:th
-- word in the burst in this case
if dr.ctr(0)='1' and dr.col(1)='1' then
inc_rctr := '0';
end if;
-- Toggle done and change state after completed burst
if dr.ctr(log2(ddr_burstlen)-1 downto 0)=(not zerov(l2ddr_burstlen)) then
dv.sdo_nbdrive := not oepols;
dv.s := dsdone;
dv.response.done_tog := not dr.response.done_tog;
end if;
end if;
-- Stall if not ready yet
if hasdqvalid/=0 and sdi.datavalid='0' and dr.hwrite='0' then
dv.ctr := dr.ctr;
dv.hwctr := dr.hwctr;
dv.response := dr.response;
dv.s := dsdata;
dv.col(1) := dr.col(1);
dv.rbwrite := '0';
inc_rctr := '0';
end if;
if inc_rctr='1' and dr.hwrite='0' then
dv.response.rctr_gray(l2ddr_burstlen-1 downto 0) :=
nextgray(dr.response.rctr_gray(l2ddr_burstlen-1 downto 0));
end if;
when dsdone =>
dv.response.rctr_gray := "0000";
dv.sdo_bdrive := not oepols;
if dr.ctr(0)='1' then
dv.sdo_qdrive := not oepols;
end if;
if dr.pchpend='0' and dr.prectr=zerov(dr.prectr'length) then
dv.s := dsidle;
end if;
-- Short circuit if request on same row and waiting for Tras to expire
if precharge_notras='1' and precharge_next='0' and
dr.start_tog_prev /= dr.response.done_tog and dr.samerow='1' and vreq.hio='0' then
dv.col := acol;
dv.endaddr := aendaddr;
dv.addrlo := aloa;
dv.hwrite := vreq.hwrite;
dv.hsize := vreq.hsize;
dv.s := dsagain;
dv.sdo_qdrive := not oepols;
end if;
when dsagain =>
block_precharge := '1';
dv.sdo_address := dr.col(13 downto 10) & '0' & dr.col(9 downto 1) & '0';
goto_caslat := '1';
when dsreg =>
-- This code assumes ddrbits>=16, needs to be changed slightly to support
-- smaller widths
dv.rbwrite := '1';
-- DDR2CFG1-5,PHYCFG read
regt0 := (others => '0'); regt1 := (others => '0');
case ddrbits is
when 16 =>
case endaddr42 is
when "000" => regt0 := regsd1(31 downto 16); regt1 := regsd1(15 downto 0);
when "001" => regt0 := regsd2(31 downto 16); regt1 := regsd2(15 downto 0);
when "010" => regt0 := regsd3(31 downto 16); regt1 := regsd3(15 downto 0);
when "011" => regt0 := regsd4(31 downto 16); regt1 := regsd4(15 downto 0);
when "100" | "101" => regt0 := regsd5(31 downto 16); regt1 := regsd5(15 downto 0);
when "110" => regt0 := sdi.regrdata(31 downto 16); regt1 := sdi.regrdata(15 downto 0);
when others => regt0 := sdi.regrdata(63 downto 48); regt1 := sdi.regrdata(47 downto 32);
end case;
when 32 =>
case endaddr43 is
when "00" => regt0 := regsd1; regt1 := regsd2;
when "01" => regt0 := regsd3; regt1 := regsd4;
when "10" => regt0 := regsd5; regt1 := regsd2;
when others => regt0 := sdi.regrdata(31 downto 0); regt1 := sdi.regrdata(63 downto 32);
end case;
when 64 =>
case dr.endaddr(4) is
when '0' => regt0 := regsd1 & regsd2; regt1 := regsd3 & regsd4;
when others => regt0 := regsd5 & regsd2; regt1 := sdi.regrdata(31 downto 0) & sdi.regrdata(63 downto 32);
end case;
when 128 =>
regt0 := regsd1 & regsd2 & regsd3 & regsd4;
regt1 := regsd5 & regsd2 & sdi.regrdata(31 downto 0) & sdi.regrdata(63 downto 32);
when others =>
regt0(ddrbits-1 downto ddrbits-255) := regsd1 & regsd2 & regsd3 & regsd4 &
regsd5 & x"00000000" & sdi.regrdata(31 downto 0) & sdi.regrdata(63 downto 32);
end case;
dv.rbwdata(ddrbits*2+chkbits-1 downto ddrbits+chkbits) := regt0;
dv.rbwdata(ddrbits-1 downto 0) := regt1;
-- Note write data is two cycles behind
regt0 := dr.sdo_data(ddrbits*2-1 downto ddrbits);
regt1 := dr.sdo_data(ddrbits-1 downto 0);
if dr.hwrite='1' and dr.ctr(2 downto 0)="010" then
w5 := '0';
case ddrbits is
when 16 =>
case endaddr42 is
when "000" => regsd1 := regt0 & regt1;
when "001" => regsd2 := regt0 & regt1;
when "010" => regsd3 := regt0 & regt1;
when "011" => regsd4 := regt0 & regt1;
when "100" => regsd5 := regt0 & regt1;
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when 32 =>
case endaddr42 is
when "000" => regsd1 := regt0;
when "001" => regsd2 := regt1;
when "010" => regsd3 := regt0;
when "011" => regsd4 := regt1;
when "100" => regsd5 := regt0;
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when 64 =>
case endaddr42 is
when "000" => regsd1 := regt0(63 downto 32);
when "001" => regsd2 := regt0(31 downto 0);
when "010" => regsd3 := regt1(63 downto 32);
when "011" => regsd4 := regt1(31 downto 0);
when "100" => regsd5 := regt0(63 downto 32);
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when 128 =>
case endaddr42 is
when "000" => regsd1 := regt0(127 downto 96);
when "001" => regsd2 := regt0(95 downto 64);
when "010" => regsd3 := regt0(63 downto 32);
when "011" => regsd4 := regt0(31 downto 0);
when "100" => regsd5 := regt1(127 downto 96);
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
when others =>
case endaddr42 is
when "000" => regsd1 := regt0(ddrbits-1 downto ddrbits-32);
when "001" => regsd2 := regt0(ddrbits-33 downto ddrbits-64);
when "010" => regsd3 := regt0(ddrbits-65 downto ddrbits-96);
when "011" => regsd4 := regt0(ddrbits-97 downto ddrbits-128);
when "100" => regsd5 := regt0(ddrbits-129 downto ddrbits-160);
w5 := '1';
when "110" => o.regwrite(0) := '1';
when "111" => o.regwrite(1) := '1';
when others => null;
end case;
end case;
-- Update lsb aliases for expanded fields in ddr2cfg5
if w5='1' then
regsd3(28) := regsd5(28); -- TRP
regsd3(22 downto 18) := regsd5(22 downto 18); -- TRFC
regsd1(26) := regsd5(8); -- TRCD
end if;
end if;
if (dr.hwrite='1' and dr.ctr(2 downto 1)="11") or dr.hwrite='0' then
dv.s := dsidle;
dv.response.done_tog := not dr.response.done_tog;
end if;
dv.cfg := (refon => regsd1(31), ocd => regsd1(30), emr => regsd1(29 downto 28),
trcd => regsd5(10 downto 9) & regsd1(26),
bsize => regsd1(27) & regsd1(25 downto 23), csize => regsd1(22 downto 21),
command => regsd1(20 downto 18), dllrst => regsd1(17), renable => regsd1(16),
cke => regsd1(15), refresh => regsd1(11 downto 0),
cal_pll => regsd3(30 downto 29), cal_rst => regsd3(31),
trp => regsd5(30 downto 29) & regsd3(28),
twr => regsd3(27 downto 23),
trfc => regsd5(25 downto 23) & regsd3(22 downto 18),
readdly => regsd4(23 downto 22) & regsd3(17 downto 16), cal_inc => regsd3(15 downto 8),
cal_en => regsd3(7 downto 0),
eightbanks => regsd4(8), dqsctrl => regsd4(7 downto 0),
caslat => regsd4(10 downto 9),
odten => regsd5(17 downto 16), tras => regsd5(4 downto 0), strength => regsd5(15),
trtp => regsd4(13), cbcal_inc => regsd4(31 downto 28), cbcal_en => regsd4(27 downto 24),
regmem => regsd4(21)
);
when dsrefresh =>
if dr.ctr(7 downto 0)=dr.cfg.trfc then
dv.s := dsidle;
end if;
when dspreall =>
-- Wait for tRP (eightbanks=0) or tRP+1 (eightbanks=1)
if dr.ctr(3 downto 0)=std_logic_vector(("0" & unsigned(dr.cfg.trp)) + (2+eightbanks)) then
dv.s := dsidle;
end if;
end case;
if goto_caslat='1' then
dv.s := dscaslat;
-- Set counter to -4 for read and -1 for write to compensate
-- write-read diff and pipelining.
-- Only need lowest three bits so set highest 3 to '0' as usual
dv.ctr(5 downto 3) := "000";
dv.ctr(2 downto 0) := "100";
if vreq.hwrite='1' then
dv.ctr(2 downto 0) := "111";
end if;
dv.casctr := std_logic_vector(to_unsigned(ddr_burstlen/2, dv.casctr'length));
dv.hwcas := '0';
dv.pchpend := '1';
end if;
-- CAS and precharge handling
-- FSM above sets up casctr and pchpend
dv.twr_plus_cl := std_logic_vector(("0" & unsigned(dr.cfg.twr)) + ("0000" & unsigned(dr.cfg.caslat)));
if dr.prectr /= zerov(dr.prectr'length) then
dv.prectr := std_logic_vector(unsigned(dr.prectr)-1);
end if;
dv.read_pend := '0' & dr.read_pend(dr.read_pend'high downto 1);
dv.datacas := '1';
if dr.casctr /= zerov(dr.casctr'length) then
if dr.datacas='1' then
dv.datacas := '0';
-- dv.sdo_casn := '0';
dv.sdo_wen := not dr.hwrite;
if dr.hwrite='0' then
case dr.cfg.caslat is
when "00" => dv.read_pend(4 downto 3) := "11";
when "01" => dv.read_pend(5 downto 4) := "11";
when "10" => dv.read_pend(6 downto 5) := "11";
when others => dv.read_pend(7 downto 6) := "11";
end case;
end if;
elsif dr.hwidth='1' then
dv.hwcas := not dr.hwcas;
if dr.hwcas='1' then
dv.casctr := std_logic_vector(unsigned(dr.casctr)-1);
if l2blen-l2ddrw > 1 then
dv.sdo_address(l2blen-l2ddrw+1 downto 3) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw+1 downto 3)+1));
end if;
dv.sdo_address(2) := '0';
else
dv.sdo_address(2) := not dr.sdo_address(2);
end if;
else
dv.casctr := std_logic_vector(unsigned(dr.casctr)-1);
if l2blen-l2ddrw > 1 then
dv.sdo_address(l2blen-l2ddrw downto 2) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw downto 2)+1));
end if;
dv.sdo_address(1) := '0';
end if;
-- Set up precharge counter (will not run until casctr=0)
if dr.hwrite='0' then
dv.prectr := "00000" & dr.cfg.trtp;
else
dv.prectr := dr.twr_plus_cl;
end if;
end if;
o.read_pend := dv.read_pend(7 downto 0);
dv.rasn_pre := '1';
if precharge_next='1' and block_precharge='0' then
dv.pchpend := '0';
dv.sdo_wen := '0';
-- dv.sdo_rasn := '0';
dv.rasn_pre := '0';
dv.prectr := "000" & dr.cfg.trp;
end if;
-- Refresh and init handling
dv.refctr := std_logic_vector(unsigned(dr.refctr)+1);
case dr.cmds is
when dcrstdel =>
if dr.refctr=std_logic_vector(to_unsigned(MHz*rstdel, dr.refctr'length)) then
dv.cmds := dcoff;
end if;
-- Bypass reset delay by writing anything to regsd2
if dr.start_tog_prev='1' and
vreq.hio='1' and vreq.hwrite='1' and vreq.endaddr(4 downto 2)="001" then
dv.cmds := dcoff;
end if;
when dcoff =>
-- Wait for renable to be set high and phy to be locked
dv.refctr := (others => '0');
if dr.cfg.renable='1' then
dv.cfg.cke := '1';
dv.cfg.dllrst := '1';
dv.cfg.ocd := '0';
dv.cmds := dcinit1;
end if;
when dcinit1 =>
-- Wait >=400 ns
if dr.refctr=std_logic_vector(to_unsigned((MHz*4+9)/10, dr.refctr'length)) then
dv.cmds := dcinit2;
dv.cfg.command := CMD_PRE;
dv.cfg.emr := "00";
end if;
when dcinit2 =>
-- MR order 2,3,1,0
-- 2xcycles per command
if dr.cfg.command="000" then
dv.cfg.command := CMD_EMR;
dv.cfg.emr := (not dr.cfg.emr(0)) & dr.cfg.emr(1); -- 00->10->11->01->00
if dr.cfg.emr="01" then
dv.cmds := dcinit3;
dv.refctr := (others => '0');
end if;
end if;
when dcinit3 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_PRE;
dv.cmds := dcinit4;
end if;
when dcinit4 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_REF;
dv.cmds := dcinit5;
end if;
when dcinit5 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_REF;
dv.cmds := dcinit6;
end if;
when dcinit6 =>
if dr.cfg.command="000" then
dv.cfg.command := CMD_EMR;
dv.cfg.emr := "00";
dv.cfg.dllrst := '0';
dv.cmds := dcinit7;
dv.refctr := (others => '0');
end if;
when dcinit7 =>
if dr.refctr(7 downto 0)=std_logic_vector(to_unsigned(200,8)) then
dv.cfg.command := CMD_EMR;
dv.cfg.emr := "01";
dv.cfg.ocd := '1';
dv.cmds := dcinit8;
end if;
when dcinit8 =>
if dr.cfg.command="000" then
if dr.cfg.ocd='1' then
dv.cfg.ocd := '0';
dv.cfg.command := CMD_EMR;
else
dv.cmds := dcon;
dv.cfg.renable := '0';
end if;
end if;
dv.refctr := (others => '0');
when dcon =>
if dr.cfg.cke='0' then
dv.cmds := dcoff;
elsif dr.cfg.renable='1' then
dv.cmds := dcinit2;
dv.refctr := (others => '0');
elsif dr.refctr(11 downto 0)=dr.cfg.refresh then
dv.refpend := '1';
dv.refctr := (others => '0');
end if;
end case;
-- Calculate next address
dv.ramaddr(0) := dv.ctr(0) xor dv.col(1);
if rbuf_wabits > 1 then
dv.ramaddr(rbuf_wabits-1 downto 1) :=
std_logic_vector(unsigned(dr.col(rbuf_wabits downto 2)) +
unsigned(dv.ctr(rbuf_wabits-1 downto 1)));
end if;
-- print("col: " & tost(dr.col) & ", dv.ctr: " & tost(dv.ctr) & ", res: " & tost(dv.ramaddr));
if eightbanks=0 then dv.cfg.eightbanks:='0'; end if;
rbwd := dv.rbwdata;
rbwa := dr.ramaddr;
rbw := dv.rbwrite;
if plmemwrite then
rbwd := dr.rbwdata;
rbwa := dr.ramaddr_prev;
rbw := dr.rbwrite;
end if;
if not plmemread then
o.dqm := dr.sdo_dqm;
o.sdwen := dr.sdo_wen;
o.data := dv.sdo_data;
o.cb := dv.sdo_cb;
end if;
-- half-width output data muxing, placed after (potential) pipeline regs.
if hwidthen/=0 and dr.hwidth='1' then
if dr.hwctr='1' then
o.data(ddrbits/2-1 downto 0) := o.data(2*ddrbits-ddrbits/2-1 downto ddrbits);
o.data(2*ddrbits-ddrbits/2-1 downto ddrbits) := o.data(2*ddrbits-1 downto 2*ddrbits-ddrbits/2);
if chkbits > 0 then
o.cb(chkbits/2-1 downto 0) := o.cb(2*chkbits-chkbits/2-1 downto chkbits);
o.cb(2*chkbits-chkbits/2-1 downto chkbits) := o.cb(2*chkbits-1 downto 2*chkbits-chkbits/2);
end if;
o.dqm(ddrbits/16-1 downto 0) := o.dqm(ddrbits/4-ddrbits/16-1 downto ddrbits/8);
o.dqm(ddrbits/4-ddrbits/16-1 downto ddrbits/8) := o.dqm(ddrbits/4-1 downto ddrbits/4-ddrbits/16);
else
o.data(2*ddrbits-ddrbits/2-1 downto ddrbits) := o.data(ddrbits-1 downto ddrbits/2);
if chkbits > 0 then
o.cb(2*chkbits-chkbits/2-1 downto chkbits) := o.cb(chkbits-1 downto chkbits/2);
end if;
o.dqm(ddrbits/4-ddrbits/16-1 downto ddrbits/8) := o.dqm(ddrbits/8-1 downto ddrbits/16);
end if;
end if;
if ddr_rst='0' then
dv.s := dsidle;
dv.cmds := dcrstdel;
dv.response := ddr_response_none;
dv.casctr := (others => '0');
dv.refctr := (others => '0');
dv.pchpend := '0';
dv.refpend := '0';
dv.rbwrite := '0';
dv.ctr := (others => '0');
dv.hwctr := '0';
dv.sdo_nbdrive := not oepols;
dv.sdo_csn := (others => '1');
dv.rastimer := (others => '0');
dv.tras_met := '0';
dv.cfg.command := "000";
dv.cfg.emr := "00";
dv.cfg.csize := conv_std_logic_vector(col-9, 2);
dv.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 4);
dv.cfg.refon := '0';
dv.cfg.trfc := conv_std_logic_vector(TRFC*MHz/1000-2, 8);
dv.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
dv.cfg.twr := conv_std_logic_vector((15)*MHz/1000+3, 5);
dv.sdo_dqm := (others => '1');
dv.cfg.dllrst := '0';
dv.cfg.cke := '0';
dv.cfg.ocd := '0';
dv.cfg.readdly := conv_std_logic_vector(readdly, 4);
dv.cfg.eightbanks := conv_std_logic_vector(eightbanks, 1)(0);
dv.cfg.odten := std_logic_vector(to_unsigned(odten,2));
dv.cfg.dqsctrl := (others => '0');
dv.cfg.strength := '0';
if pwron = 1 then dv.cfg.renable := '1'; else dv.cfg.renable:='0'; end if;
-- Default to min 15 ns tRCD, 15 ns tRP, min(7.5 ns,2*tCK) tRTP
-- Use CL=3 for DDR2-400/533, 4 for DDR2-667, 5 for DDR2-800
dv.cfg.trcd := "000";
dv.cfg.trp := "000";
dv.cfg.trtp := '0';
dv.cfg.caslat := "00";
dv.cfg.regmem := '0';
if MHz > 130 then
dv.cfg.trcd := "001";
dv.cfg.trp := "001";
end if;
if MHz > 200 then
-- Will work up to 600 MHz, then trcd/trp needs to be expanded
dv.cfg.trcd := std_logic_vector(to_unsigned((15 * MHz + 999) / 1000 - 2, 3));
dv.cfg.trp := std_logic_vector(to_unsigned((15 * MHz + 999) / 1000 - 2, 3));
end if;
if MHz > 267 then
-- Works up to 400 MHz, then trtp will need to be expanded
dv.cfg.trtp := '1';
dv.cfg.caslat := "01";
end if;
if MHz > 334 then
dv.cfg.caslat := "10";
end if;
dv.cfg.cal_rst := '1'; -- Reset input delays
dv.sdo_ba := (others => '0');
dv.sdo_address := (others => '0');
-- Default to min 45 ns tRAS
dv.cfg.tras := std_logic_vector(to_unsigned((45*MHz+999)/1000 - 2, 5));
dv.read_pend := (others => '0');
if ddr_syncrst /= 0 then
dv.cfg.cke := '0';
dv.sdo_bdrive := not oepols;
dv.sdo_qdrive := not oepols;
dv.sdo_odt := '0';
if phyptctrl /= 0 then
o.sdcke := "00";
o.bdrive := not oepols;
o.qdrive := not oepols;
o.odt := (others => '0');
end if;
end if;
end if;
if dr.cfg.odten="00" then
dv.sdo_odt := '0';
end if;
if octen=0 then
dv.sdo_oct := '0';
end if;
for x in 0 to chkbits/4-1 loop
o.cbdqm(x) := o.dqm(x*ddrbits/chkbits);
end loop;
if vreq.maskdata='1' then
o.dqm := (others => '1');
end if;
if vreq.maskcb='1' then
o.cbdqm := (others => '1');
end if;
if dr.cfg.command /= "000" then
-- print("Command: " & tost(dr.cfg.command) & " -> casn:" & tost(dv.sdo_casn) & ",rasn:" & tost(dv.sdo_rasn) & ",wen:" & tost(dv.sdo_wen));
end if;
-- Dynamic nosync handling (nosync=2)
if plmemwrite then
dv.response1 := dr.response;
dv.response2 := dr.response;
else
dv.response1 := dv.response;
dv.response2 := dv.response;
end if;
if reqsel='1' then dv.response1 := ddr_response_none; end if;
if reqsel='0' then dv.response2 := ddr_response_none; end if;
if nosync > 1 then
resp := dr.response1;
elsif plmemwrite then
resp := dr.response_prev;
else
resp := dr.response;
end if;
resp2 := dr.response2;
if scantest/=0 and phyptctrl/=0 then
if testen='1' then
o.bdrive := testoen;
o.qdrive := testoen;
end if;
end if;
rbwdata <= rbwd;
rbwaddr <= rbwa;
rbwrite <= rbw;
wbraddr <= wbra;
sdo <= o;
response <= resp;
response2 <= resp2;
ndr <= dv;
end process;
ddrregs: process(clk_ddr,arst)
begin
if rising_edge(clk_ddr) then
dr <= ndr;
end if;
if ddr_syncrst=0 and arst='0' then
dr.cfg.cke <= '0';
dr.sdo_bdrive <= not oepols;
dr.sdo_qdrive <= not oepols;
dr.sdo_odt <= '0';
end if;
end process;
end;
| gpl-2.0 | f07809a5cb274c015afe38c9311e70e0 | 0.535742 | 3.38003 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_src0_cols_V.vhd | 2 | 4,556 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_src0_cols_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_src0_cols_V_shiftReg;
architecture rtl of FIFO_image_filter_src0_cols_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_src0_cols_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_src0_cols_V is
component FIFO_image_filter_src0_cols_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_src0_cols_V_shiftReg : FIFO_image_filter_src0_cols_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | a56eaf4afea40d585071720e220c7906 | 0.535558 | 3.499232 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_src1_data_stream_2_V.vhd | 2 | 6,292 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FIFO_image_filter_src1_data_stream_2_V is
generic (
MEM_STYLE : string := "block";
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 15;
DEPTH : natural := 20000
);
port (
clk : in std_logic;
reset : in std_logic;
if_full_n : out std_logic;
if_write_ce : in std_logic;
if_write : in std_logic;
if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
if_empty_n : out std_logic;
if_read_ce : in std_logic;
if_read : in std_logic;
if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity;
architecture arch of FIFO_image_filter_src1_data_stream_2_V is
type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal q_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal waddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal raddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal wnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal rnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal push : std_logic;
signal pop : std_logic;
signal usedw : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal full_n : std_logic := '1';
signal empty_n : std_logic := '0';
signal q_tmp : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal show_ahead : std_logic := '0';
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal dout_valid : std_logic := '0';
attribute ram_style: string;
attribute ram_style of mem: signal is MEM_STYLE;
begin
if_full_n <= full_n;
if_empty_n <= dout_valid;
if_dout <= dout_buf;
push <= full_n and if_write_ce and if_write;
pop <= empty_n and if_read_ce and (not dout_valid or if_read);
wnext <= waddr when push = '0' else
(others => '0') when waddr = DEPTH - 1 else
waddr + 1;
rnext <= raddr when pop = '0' else
(others => '0') when raddr = DEPTH - 1 else
raddr + 1;
-- waddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
waddr <= (others => '0');
else
waddr <= wnext;
end if;
end if;
end process;
-- raddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
raddr <= (others => '0');
else
raddr <= rnext;
end if;
end if;
end process;
-- usedw
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
usedw <= (others => '0');
elsif push = '1' and pop = '0' then
usedw <= usedw + 1;
elsif push = '0' and pop = '1' then
usedw <= usedw - 1;
end if;
end if;
end process;
-- full_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
full_n <= '1';
elsif push = '1' and pop = '0' then
if usedw = DEPTH - 1 then
full_n <= '0';
else
full_n <= '1';
end if;
elsif push = '0' and pop = '1' then
full_n <= '1';
end if;
end if;
end process;
-- empty_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
empty_n <= '0';
elsif push = '1' and pop = '0' then
empty_n <= '1';
elsif push = '0' and pop = '1' then
if usedw = 1 then
empty_n <= '0';
else
empty_n <= '1';
end if;
end if;
end if;
end process;
-- mem
process (clk) begin
if clk'event and clk = '1' then
if push = '1' then
mem(to_integer(waddr)) <= if_din;
end if;
end if;
end process;
-- q_buf
process (clk) begin
if clk'event and clk = '1' then
q_buf <= mem(to_integer(rnext));
end if;
end process;
-- q_tmp
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
q_tmp <= (others => '0');
elsif push = '1' then
q_tmp <= if_din;
end if;
end if;
end process;
-- show_ahead
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
show_ahead <= '0';
elsif push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
show_ahead <= '1';
else
show_ahead <= '0';
end if;
end if;
end process;
-- dout_buf
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_buf <= (others => '0');
elsif pop = '1' then
if show_ahead = '1' then
dout_buf <= q_tmp;
else
dout_buf <= q_buf;
end if;
end if;
end if;
end process;
-- dout_valid
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_valid <= '0';
elsif pop = '1' then
dout_valid <= '1';
elsif if_read_ce = '1' and if_read = '1' then
dout_valid <= '0';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | ac38d43fadbdf348f277a89bc3b057c4 | 0.446599 | 3.799517 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_intrpt.vhd | 4 | 28,207 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
| gpl-3.0 | e614ce0a34faeda0222fa3be556ead19 | 0.465558 | 4.045754 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/side/simulation/side_tb.vhd | 1 | 4,331 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: side_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY side_tb IS
END ENTITY;
ARCHITECTURE side_tb_ARCH OF side_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
side_synth_inst:ENTITY work.side_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | d457d76bf4dc11ca0b1f1ff859e64574 | 0.618333 | 4.656989 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-avnet-eval-xc4vlx25/testbench.vhd | 1 | 9,117 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- modified by Thomas Ameseder, Gleichmann Electronics 2004, 2005 to
-- support the use of an external AHB slave and different HPE board versions
------------------------------------------------------------------------------
-- further adapted from Hpe_compact to Hpe_mini (Feb. 2005)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd1, rxd1 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 1000 ns;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
resetn => rst,
resoutn => resoutn,
clk_100mhz => clk,
errorn => error,
address => address(22 downto 1),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
sertx => dsutx,
serrx => dsurx,
rtsn => rtsn,
ctsn => ctsn,
dsuen => dsuen,
dsubre => dsubre,
dsuact => dsuactn,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
u1 : mt46v16m16
generic map (index => -1, fname => sdramfile)
port map(
Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
Dm => ddr_dm(1 downto 0));
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
-- phy0 : if CFG_GRETH > 0 generate
-- p0 : phy
-- port map(rst, led_cfg, open, etx_clk, erx_clk, erxd, erx_dv,
-- erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc);
-- end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 | dfbe0ccb191e64af4091023ef81908e0 | 0.529889 | 3.536462 | false | false | false | false |
lynnieana/autosub_new_task_timingDemo | timingDemo/templates/testbench_template.vhdl | 1 | 4,601 |
ENTITY timingDemo_tb IS END timingDemo_tb;
ARCHITECTURE tb OF timingDemo_tb IS
signal N,O,P,E : integer;
BEGIN
UUT: entity work.timingDemo PORT MAP(N=>N,O=>O,P=>P,E=>E);
process
type result_array is array (natural range <>) of integer;
constant expected_result : result_array:=( --w;x;y;z
%%TESTPATTERN
);
--Check the timing behavior
begin
wait for 0 ns;
if N /= 0 OR O /= 0 OR P /= 0 OR E /= 0 then
report "§{Error for current time = " & time'image(now) & " (N, O, P, E)= (" & integer'image(N) & ", " & integer'image(O) & ", "
& integer'image(P) & ", " & integer'image(E) & ")" &
" expected = (0, 0, 0, 0)§"
severity failure;
end if;
wait for 1 ns;
for i in 0 to 2 loop
wait for %%time_o1 ns;
if N /= expected_result(12*i+0) OR O /= expected_result(12*i+1) OR P /= expected_result(12*i+2) OR E /= expected_result(12*i+3) then
report "§{Error for current time = " & time'image(now) & " (N, O, P, E)= (" & integer'image(N) & ", " & integer'image(O) & ", "
& integer'image(P) & ", " & integer'image(E) & ")" &
" expected = (" & integer'image(expected_result(12*i+0)) & ", " & integer'image(expected_result(12*i+1)) & ", "
& integer'image(expected_result(12*i+2)) & ", " & integer'image(expected_result(12*i+3)) & ")§"
severity failure;
end if;
wait for 1 ns;
if N /= expected_result(12*i+4) OR O /= expected_result(12*i+5) OR P /= expected_result(12*i+6) OR E /= expected_result(12*i+7) then
report "§{Error for current time = " & time'image(now) & " (N, O, P, E)= (" & integer'image(N) & ", " & integer'image(O) & ", "
& integer'image(P) & ", " & integer'image(E) & ")" &
" expected = (" & integer'image(expected_result(12*i+4)) & ", " & integer'image(expected_result(12*i+5)) & ", "
& integer'image(expected_result(12*i+6)) & ", " & integer'image(expected_result(12*i+7)) & ")§"
severity failure;
end if;
wait for %%time_p1 ns;
if N /= expected_result(12*i+4) OR O /= expected_result(12*i+5) OR P /= expected_result(12*i+6) OR E /= expected_result(12*i+7) then
report "§{Error for current time = " & time'image(now) & " (N, O, P, E)= (" & integer'image(N) & ", " & integer'image(O) & ", "
& integer'image(P) & ", " & integer'image(E) & ")" &
" expected = (" & integer'image(expected_result(12*i+4)) & ", " & integer'image(expected_result(12*i+5)) & ", "
& integer'image(expected_result(12*i+6)) & ", " & integer'image(expected_result(12*i+7)) & ")§"
severity failure;
end if;
wait for 1 ns;
if N /= expected_result(12*i+8) OR O /= expected_result(12*i+9) OR P /= expected_result(12*i+10) OR E /= expected_result(12*i+11) then
report "§{Error for current time = " & time'image(now) & " (N, O, P, E)= (" & integer'image(N) & ", " & integer'image(O) & ", "
& integer'image(P) & ", " & integer'image(E) & ")" &
" expected = (" & integer'image(expected_result(12*i+8)) & ", " & integer'image(expected_result(12*i+9)) & ", "
& integer'image(expected_result(12*i+10)) & ", " & integer'image(expected_result(12*i+11)) & ")§"
severity failure;
end if;
wait for %%time_e1 ns;
if N /= expected_result(12*i+8) OR O /= expected_result(12*i+9) OR P /= expected_result(12*i+10) OR E /= expected_result(12*i+11) then
report "§{Error for current time = " & time'image(now) & " (N, O, P, E)= (" & integer'image(N) & ", " & integer'image(O) & ", "
& integer'image(P) & ", " & integer'image(E) & ")" &
" expected = (" & integer'image(expected_result(12*i+8)) & ", " & integer'image(expected_result(12*i+9)) & ", "
& integer'image(expected_result(12*i+10)) & ", " & integer'image(expected_result(12*i+11)) & ")§"
severity failure;
end if;
wait for 1 ns;
if N /= expected_result(12*i+12) OR O /= expected_result(12*i+13) OR P /= expected_result(12*i+14) OR E /= expected_result(12*i+15) then
report "§{Error for current time = " & time'image(now) & " (N, O, P, E)= (" & integer'image(N) & ", " & integer'image(O) & ", "
& integer'image(P) & ", " & integer'image(E) & ")" &
" expected = (" & integer'image(expected_result(12*i+12)) & ", " & integer'image(expected_result(12*i+13)) & ", "
& integer'image(expected_result(12*i+14)) & ", " & integer'image(expected_result(12*i+15)) & ")§"
severity failure;
end if;
end loop;
report "Success" severity failure;
wait;
END PROCESS;
END tb;
| gpl-2.0 | ed5254334223e83ca9d9ae233d87a1f8 | 0.555483 | 2.795247 | false | false | false | false |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_dmask_data_stream_0_V.vhd | 2 | 4,629 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_dmask_data_stream_0_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_dmask_data_stream_0_V_shiftReg;
architecture rtl of FIFO_image_filter_dmask_data_stream_0_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_dmask_data_stream_0_V is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_dmask_data_stream_0_V is
component FIFO_image_filter_dmask_data_stream_0_V_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_dmask_data_stream_0_V_shiftReg : FIFO_image_filter_dmask_data_stream_0_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
| gpl-3.0 | 371cfe5418b295940b9217821b25a2cf | 0.539425 | 3.470015 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/digit/example_design/digit_prod.vhd | 1 | 9,898 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: digit_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : digit.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 12
-- C_READ_WIDTH_A : 12
-- C_WRITE_DEPTH_A : 10240
-- C_READ_DEPTH_A : 10240
-- C_ADDRA_WIDTH : 14
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 12
-- C_READ_WIDTH_B : 12
-- C_WRITE_DEPTH_B : 10240
-- C_READ_DEPTH_B : 10240
-- C_ADDRB_WIDTH : 14
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY digit_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END digit_prod;
ARCHITECTURE xilinx OF digit_prod IS
COMPONENT digit_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : digit_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | dd7448221a401c60716e8501a4c4ccbe | 0.494342 | 3.837922 | false | false | false | false |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_skid_buf.vhd | 13 | 18,142 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- Clock and Reset Inputs ---------------------------------------------
aclk : In std_logic ; --
arst : In std_logic ; --
-----------------------------------------------------------------------
-- Shutdown control (assert for 1 clk pulse) --------------------------
--
skid_stop : In std_logic ; --
-----------------------------------------------------------------------
-- Slave Side (Stream Data Input) -------------------------------------
s_valid : In std_logic ; --
s_ready : Out std_logic ; --
s_data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
s_strb : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
s_last : In std_logic ; --
-----------------------------------------------------------------------
-- Master Side (Stream Data Output ------------------------------------
m_valid : Out std_logic ; --
m_ready : In std_logic ; --
m_data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
m_strb : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
m_last : Out std_logic --
-----------------------------------------------------------------------
);
end entity axi_sg_skid_buf;
architecture implementation of axi_sg_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_early_stop : std_logic := '0';
signal sig_sready_stop_set : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_mvalid_early_stop : std_logic := '0';
signal sig_mvalid_stop_set : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
m_valid <= sig_m_valid_out;
s_ready <= sig_s_ready_out;
m_strb <= sig_strb_reg_out;
m_last <= sig_last_reg_out;
m_data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special s_ready FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else s_data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= s_valid or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(m_ready)));
-- s_ready combinational logic
sig_s_ready_comb <= m_ready or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(s_valid)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers s_ready handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1' or
sig_sready_early_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers m_valid handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1' or
sig_mvalid_stop_set = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= s_data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
sig_data_reg_out <= (others => '0');
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_sready_stop <= sig_sready_stop_reg;
sig_sready_early_stop <= skid_stop; -- deassert S_READY immediately
sig_sready_stop_set <= sig_sready_early_stop;
sig_mvalid_stop <= sig_mvalid_stop_reg;
sig_mvalid_early_stop <= sig_m_valid_dup and
m_ready and
skid_stop;
sig_mvalid_stop_set <= sig_mvalid_early_stop or
(sig_stop_request and
not(sig_m_valid_dup)) or
(sig_m_valid_dup and
m_ready and
sig_stop_request);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_sready_stop_set = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MVALID_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_valid
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_mvalid_stop_set = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
| gpl-3.0 | c828fe9e2a428c2f3953a3ee69fca5b3 | 0.462132 | 4.455305 | false | false | false | false |
Fairyland0902/BlockyRoads | src/BlockyRoads/ipcore_dir/game_over/simulation/game_over_synth.vhd | 1 | 6,838 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: game_over_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY game_over_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE game_over_synth_ARCH OF game_over_synth IS
COMPONENT game_over_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: game_over_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | 980441dc412ee0fb7e6032138a311544 | 0.580287 | 3.798889 | false | false | false | false |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/ambatest/ahbtbs.vhd | 1 | 5,433 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbs
-- File: ahbtbs.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AMBA testbench slave
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use work.ahbtbp.all;
entity ahbtbs is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbtbs is
constant abits : integer := log2(kbytes) + 8;
constant ws : std_logic_vector(7 downto 0) :="00000000";
constant retry : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, 0, 0, abits+2, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits+1 downto 0);
size : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
ws : std_logic_vector(7 downto 0);
rty : std_logic_vector(3 downto 0);
retry : std_logic;
end record;
signal r, c : reg_type;
signal ramsel : std_ulogic;
signal write : std_logic_vector(3 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(31 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(3 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
begin
v := r; v.hready := '1'; bs := (others => '0');
v.hresp := HRESP_OKAY;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.hwrite := ahbsi.hwrite and v.hsel;
v.addr := ahbsi.haddr(abits+1 downto 0);
v.size := ahbsi.hsize(1 downto 0);
v.ws := ws;
--v.retry := retry;
if retry = 1 then
if v.hsel = '1' then
v.rty := r.rty - 1;
if r.rty = "0000" then
v.retry := '0';
v.rty := "0010";
else
v.retry := '1';
end if;
end if;
else
v.retry := '0';
end if;
end if;
if r.ws /= "00000000" and r.hsel = '1' then
v.ws := r.ws - 1;
end if;
if v.ws /= "00000000" and v.hsel = '1' then
v.hready := '0';
elsif v.hsel = '1' and v.retry = '1' then
if r.hresp = HRESP_OKAY then
v.hready := '0';
v.hresp := HRESP_RETRY;
else
v.hready := '1';
v.hresp := HRESP_RETRY;
v.retry := '0';
end if;
end if;
if (r.hwrite or not r.hready) = '1' then
haddr := r.addr(abits+1 downto 2);
else
haddr := ahbsi.haddr(abits+1 downto 2); bs := (others => '0');
end if;
if r.hwrite = '1' and r.hready = '1' then
case r.size(1 downto 0) is
when "00" => bs (conv_integer(r.addr(1 downto 0))) := '1';
when "01" => bs := r.addr(1) & r.addr(1) & not (r.addr(1) & r.addr(1));
when others => bs := (others => '1');
end case;
--v.hready := not (v.hsel and not ahbsi.hwrite);
--v.hwrite := v.hwrite and v.hready;
end if;
if rst = '0' then
v.hwrite := '0'; v.hready := '1'; v.ws := ws;
v.rty := "0010";
end if;
write <= bs; ramsel <= v.hsel or r.hwrite; ahbso.hready <= r.hready;
ramaddr <= haddr; c <= v; ahbso.hrdata <= ramdata;
end process;
ahbso.hresp <= r.hresp; --"00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
ra : for i in 0 to 3 generate
aram : syncram generic map (tech, abits, 8) port map (
clk, ramaddr, ahbsi.hwdata(i*8+7 downto i*8),
ramdata(i*8+7 downto i*8), ramsel, write(3-i));
end generate;
reg : process (clk)
begin
if rising_edge(clk ) then r <= c; end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| gpl-2.0 | a86da9db5b74c44aca2521da1341d812 | 0.565433 | 3.368258 | false | false | false | false |
Subsets and Splits