repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
takeshineshiro/utrasound_fpga_modelsim | fpga_sim/model_trans/work/butterfly_radix4_2nd/_primary.vhd | 2 | 5,250 | library verilog;
use verilog.vl_types.all;
entity butterfly_radix4_2nd is
generic(
cos0 : integer := 32767;
cos1 : integer := 32767;
cos2 : integer := 32767;
cos3 : integer := 30273;
cos4 : integer := 23170;
cos5 : integer := 12540;
cos6 : integer := 23170;
cos7 : integer := 0;
cos8 : integer := 42366;
cos9 : integer := 12540;
cos10 : integer := 42366;
cos11 : integer := 35263;
sin0 : integer := 0;
sin1 : integer := 0;
sin2 : integer := 0;
sin3 : integer := 52996;
sin4 : integer := 42366;
sin5 : integer := 35263;
sin6 : integer := 42366;
sin7 : integer := 32769;
sin8 : integer := 42366;
sin9 : integer := 35263;
sin10 : integer := 42366;
sin11 : integer := 12540
);
port(
clk : in vl_logic;
re_0 : in vl_logic_vector(15 downto 0);
re_1 : in vl_logic_vector(15 downto 0);
re_2 : in vl_logic_vector(15 downto 0);
re_3 : in vl_logic_vector(15 downto 0);
re_4 : in vl_logic_vector(15 downto 0);
re_5 : in vl_logic_vector(15 downto 0);
re_6 : in vl_logic_vector(15 downto 0);
re_7 : in vl_logic_vector(15 downto 0);
re_8 : in vl_logic_vector(15 downto 0);
re_9 : in vl_logic_vector(15 downto 0);
re_10 : in vl_logic_vector(15 downto 0);
re_11 : in vl_logic_vector(15 downto 0);
re_12 : in vl_logic_vector(15 downto 0);
re_13 : in vl_logic_vector(15 downto 0);
re_14 : in vl_logic_vector(15 downto 0);
re_15 : in vl_logic_vector(15 downto 0);
im_0 : in vl_logic_vector(15 downto 0);
im_1 : in vl_logic_vector(15 downto 0);
im_2 : in vl_logic_vector(15 downto 0);
im_3 : in vl_logic_vector(15 downto 0);
im_4 : in vl_logic_vector(15 downto 0);
im_5 : in vl_logic_vector(15 downto 0);
im_6 : in vl_logic_vector(15 downto 0);
im_7 : in vl_logic_vector(15 downto 0);
im_8 : in vl_logic_vector(15 downto 0);
im_9 : in vl_logic_vector(15 downto 0);
im_10 : in vl_logic_vector(15 downto 0);
im_11 : in vl_logic_vector(15 downto 0);
im_12 : in vl_logic_vector(15 downto 0);
im_13 : in vl_logic_vector(15 downto 0);
im_14 : in vl_logic_vector(15 downto 0);
im_15 : in vl_logic_vector(15 downto 0);
butterfly_re0 : out vl_logic_vector(15 downto 0);
butterfly_re1 : out vl_logic_vector(15 downto 0);
butterfly_re2 : out vl_logic_vector(15 downto 0);
butterfly_re3 : out vl_logic_vector(15 downto 0);
butterfly_re4 : out vl_logic_vector(15 downto 0);
butterfly_re5 : out vl_logic_vector(15 downto 0);
butterfly_re6 : out vl_logic_vector(15 downto 0);
butterfly_re7 : out vl_logic_vector(15 downto 0);
butterfly_re8 : out vl_logic_vector(15 downto 0);
butterfly_re9 : out vl_logic_vector(15 downto 0);
butterfly_re10 : out vl_logic_vector(15 downto 0);
butterfly_re11 : out vl_logic_vector(15 downto 0);
butterfly_re12 : out vl_logic_vector(15 downto 0);
butterfly_re13 : out vl_logic_vector(15 downto 0);
butterfly_re14 : out vl_logic_vector(15 downto 0);
butterfly_re15 : out vl_logic_vector(15 downto 0);
butterfly_im0 : out vl_logic_vector(15 downto 0);
butterfly_im1 : out vl_logic_vector(15 downto 0);
butterfly_im2 : out vl_logic_vector(15 downto 0);
butterfly_im3 : out vl_logic_vector(15 downto 0);
butterfly_im4 : out vl_logic_vector(15 downto 0);
butterfly_im5 : out vl_logic_vector(15 downto 0);
butterfly_im6 : out vl_logic_vector(15 downto 0);
butterfly_im7 : out vl_logic_vector(15 downto 0);
butterfly_im8 : out vl_logic_vector(15 downto 0);
butterfly_im9 : out vl_logic_vector(15 downto 0);
butterfly_im10 : out vl_logic_vector(15 downto 0);
butterfly_im11 : out vl_logic_vector(15 downto 0);
butterfly_im12 : out vl_logic_vector(15 downto 0);
butterfly_im13 : out vl_logic_vector(15 downto 0);
butterfly_im14 : out vl_logic_vector(15 downto 0);
butterfly_im15 : out vl_logic_vector(15 downto 0)
);
end butterfly_radix4_2nd;
| apache-2.0 | 850513792afcbfe99c899ba33a43d65a | 0.485333 | 3.571429 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/niosii/synthesis/niosii_rst_controller_003.vhd | 1 | 9,084 | -- niosii_rst_controller_003.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_rst_controller_003 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity niosii_rst_controller_003;
architecture rtl of niosii_rst_controller_003 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_003 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of niosii_rst_controller_003
| mit | fa2564332a97accc74410acfa8801e91 | 0.546786 | 2.726291 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_timer/niosii/synthesis/niosii_rst_controller_001.vhd | 6 | 9,084 | -- niosii_rst_controller_001.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity niosii_rst_controller_001;
architecture rtl of niosii_rst_controller_001 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of niosii_rst_controller_001
| mit | e1380f5eeb9e4f35ec310d41ad810d88 | 0.546786 | 2.726291 | false | false | false | false |
jotego/jt12 | doc/other/operator.vhd | 2 | 17,163 | --------======== operator.vhd ========--------
-- YM2203 / YM2612 (OPN / OPN2) Operator Unit
-- Reverse engineered from YM2203 (and YM2612) die shots
-- Copyright (C) 2015 Sauraen
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- NOTICE:
-- This is an UNTESTED implementation!
--
-- I attempted to get the overall architecture of this unit correct,
-- especially the position and number of registers in the pipeline. I
-- am confident that this is correct at a large-scale level. I am not,
-- however, confident that this description is free from errors. In
-- particular, it is very likely that one or more bits are wrong in the
-- sine or exponential tables. Also, since the chip uses both positive
-- and negative logic throughout, it is easy to miss an inverter, and
-- so there may be an error where a particular signal or variable should
-- be inverted from how it is written here. I tried my best to trace
-- adders, etc. completely, but this is not error-proof.
--
-- The benefit of this situation is that if anyone does test an
-- implementation based on this code, the errors that may exist here are
-- likely to produce obviously wrong results. In previous implementations,
-- authors tried to get the right sound 99% of the time, but had no idea
-- of the pipelined architecture or certain other details here which became
-- important in the other cases. Thus it is much harder to make a perfect
-- implementation.
--------======== EXTERNALLY DEFINED ENTITIES ========--------
-- circular_buffer
-- A simple circular buffer, used for most of the YM2612's registers.
library ieee;
use ieee.std_logic_1164.all;
entity circular_buffer is
generic (
DATA_WIDTH: positive := 8; --arbitrary default value
BUFFER_DEPTH: positive := 3; --arbitrary default value
CLEAR_ON_RESET: boolean := false
);
port (
clk, rst_bar: in std_logic;
din: in std_logic_vector(DATA_WIDTH-1 downto 0);
dout: out std_logic_vector(DATA_WIDTH-1 downto 0);
load: in std_logic
);
end entity;
--------======== FILE BODY ========--------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity opn_operator is
generic (
NUM_VOICES : positive := 6
);
port (
-- Global control
clk, rst_bar: in std_logic;
-- Operator inputs, not all applying to the same operator at the same time
pg_phase: in unsigned(9 downto 0);
eg_atten: in unsigned(9 downto 0);
voice_fb: in unsigned(2 downto 0);
op_fb_enable: in std_logic;
op_algorithm_ctl: in std_logic_vector(5 downto 0);
test_214: in std_logic;
-- Operator output
op_result: out unsigned(13 downto 0)
);
end entity;
architecture arch of opn_operator is
type pipeline_delayer_t is array(natural range <>) of unsigned(9 downto 0);
signal prev1, prevprev1, prev2: unsigned(13 downto 0);
signal fm_preshift: unsigned(14 downto 0);
signal pipeline_delayer : pipeline_delayer_t(2*NUM_VOICES - 7 downto 0);
signal phaselo: unsigned(7 downto 0);
signal signbit, signbit_1, signbit_2: std_logic;
signal totalatten: unsigned(11 downto 0);
signal mantissa: unsigned(9 downto 0);
signal exponent: unsigned(3 downto 0);
signal op_result_pre: unsigned(13 downto 0);
signal op_result_internal: unsigned(13 downto 0);
begin
-- REGISTER/CYCLE 1
-- Creation of phase modulation (FM) feedback signal, before shifting
make_fm_preshift: process(clk) is
variable x, y: unsigned(13 downto 0);
variable xs, ys: unsigned(14 downto 0);
begin
if rising_edge(clk) then
x := (prevprev1 and op_algorithm_ctl(0))
or (prev2 and op_algorithm_ctl(1))
or (op_result_internal and op_algorithm_ctl(2));
y := (op_result_internal and op_algorithm_ctl(3))
or (prev1 and op_algorithm_ctl(4));
xs := x(13) & x(13 downto 0); -- sign-extend
ys := y(13) & y(13 downto 0); -- sign-extend
fm_preshift <= xs + ys; -- carry is discarded
end if;
end process;
-- REGISTER/CYCLE 2 (also YM2612 extra cycles 1-6)
-- Shifting of FM feedback signal, adding phase from PG to FM phase
-- In YM2203, fm_feedback is not registered at all, it is latched on the first edge
-- in add_pg_phase and the second edge is the output of add_pg_phase. In the YM2612, there
-- are 6 cycles worth of registers between the generated (non-registered) fm_feedback signal
-- and the input to add_pg_phase.
shift_fb_and_add_pg_phase: process(clk) is
variable fm_feedback: unsigned(9 downto 0);
variable fm_feedback_delayed: unsigned(9 downto 0);
variable phase: unsigned(9 downto 0);
begin
if rising_edge(clk) then
-- Shift FM feedback signal
if op_fb_enable = '1' then
fm_feedback := fm_preshift(10 downto 1); -- Bit 0 of fm_preshift is never used
else
case to_integer(voice_fb) is
when 1 => fm_feedback :=
(9 downto 6 => fm_preshift(14), 5 downto 0 => fm_preshift(14 downto 9));
when 2 => fm_feedback :=
(9 downto 7 => fm_preshift(14), 6 downto 0 => fm_preshift(14 downto 8));
when 3 => fm_feedback :=
(9 downto 8 => fm_preshift(14), 7 downto 0 => fm_preshift(14 downto 7));
when 4 => fm_feedback :=
(9 => fm_preshift(14), 8 downto 0 => fm_preshift(14 downto 6));
when 5 => fm_feedback := fm_preshift(14 downto 5);
when 6 => fm_feedback := fm_preshift(13 downto 4);
when 7 => fm_feedback := fm_preshift(12 downto 3);
when others => fm_feedback := (others => '0');
end case;
end if;
-- Delay pipeline by 6 cycles if this is a YM2612
if NUM_VOICES <= 3 then
fm_feedback_delayed := fm_feedback; -- Don't delay, don't register at all
else
pipeline_delayer((2*NUM_VOICES)-7) <= fm_feedback;
for i in (2*NUM_VOICES-8) downto 0 loop
pipeline_delayer(i) <= pipeline_delayer(i+1);
end loop;
fm_feedback_delayed := pipeline_delayer(0);
end if;
-- Add in PG phase
add_pg_phase:
phase := fm_feedback_delayed + pg_phase;
phaselo <= phase(7 downto 0) xor phase(8);
signbit <= phase(9);
end if;
end process;
-- REGISTER/CYCLE 3
-- Sine table
sine_table: process(clk) is
type sinetable_t is array(31 downto 0) of std_logic_vector(45 downto 0);
constant sinetable: sinetable_t := (
"0001100000100100010001000010101010101001010010",
"0001100000110100000100000010010001001101000001",
"0001100000110100000100110010001011001101100000",
"0001110000010000000000110010110001001101110010",
"0001110000010000001100000010111010001101101001",
"0001110000010100001001100010000000101101111010",
"0001110000010100001101100010010011001101011010",
"0001110000011100000101010010111000101111111100",
"0001110000111000000001110010101110001101110111",
"0001110000111000010100111000011101011010100110",
"0001110000111100011000011000111100001001111010",
"0001110000111100011100111001101011001001110111",
"0100100001010000010001011001001000111010110111",
"0100100001010100010001001001110001111100101010",
"0100100001010100010101101101111110100101000110",
"0100100011100000001000011001010110101101111001",
"0100100011100100001000101011100101001011101111",
"0100100011101100000111011010000001011010110001",
"0100110011001000000111101010000010111010111111",
"0100110011001100001011011110101110110110000001",
"0100110011101000011010111011001010001101110001",
"0100110011101101011010110101111001010100001111",
"0111000010000001010111000101010101010110010111",
"0111000010000101010111110111110101010010111011",
"0111000010110101101000101100001000010000011001",
"0111010010011001100100011110100100010010010010",
"0111010010111010100101100101000000110100100011",
"1010000010011010101101011101100001110010011010",
"1010000010111111111100100111010100010000111001",
"1010010111110100110010001100111001010110100000",
"1011010111010011111011011110000100110010100001",
"1110011011110001111011100111100001110110100111"
);
variable sta : std_logic_vector(45 downto 0);
variable stb : std_logic_vector(18 downto 0);
variable stf, stg : std_logic_vector(10 downto 0);
variable logsin : unsigned(11 downto 0);
variable subtresult : unsigned(10 downto 0);
variable atten_internal : unsigned(11 downto 0);
begin
if rising_edge(clk) then
-- Main sine table body
sta := sinetable(to_integer(phaselo(5 downto 1)));
-- 2-bit row chooser
case std_logic_vector(phaselo(7 downto 6)) is
when "00" => stb :=
"0000000000" & sta(29) & sta(25)
& "00" & sta(18) & sta(14)
& "0" & sta(7) & sta(3);
when "01" => stb :=
"000000" & sta(37) & sta(34)
& "00" & sta(28) & sta(24)
& "00" & sta(17) & sta(13)
& sta(10) & sta(6) & sta(2);
when "10" => stb :=
"00" & sta(43) & sta(41)
& "00" & sta(36) & sta(33)
& "00" & sta(27) & sta(23)
& "0" & sta(20) & sta(16)
& sta(12) & sta(9) & sta(5) & sta(1);
when others => stb :=
sta(45) & sta(44) & sta(42) & sta(40)
& sta(39) & sta(38) & sta(35) & sta(32)
& sta(31) & sta(30) & sta(26) & sta(22)
& sta(21) & sta(19) & sta(15) & sta(11)
& sta(8) & sta(4) & sta(0);
end case;
-- Fixed value to sum
stf := stb(18 downto 15) & stb(12 downto 11) & stb(8 downto 7) & stb(4 downto 3) & stb(0);
-- Gated value to sum; bit 14 is indeed used twice
stg := "00" & stb(14) & stb(14 downto 13) & stb(10 downto 9) & stb(6 downto 5) & stb(2 downto 1);
stg := stg and phaselo(0);
-- Sum to produce final logsin value
logsin := unsigned('0' & stf) + unsigned('0' & stg); -- Carry-out of 11-bit addition becomes 12th bit
-- Invert-subtract logsin value from EG attenuation value, with inverted carry
-- In the actual chip, the output of the above logsin sum is already inverted.
-- The two LSBs go through inverters (so they're non-inverted); the eg_atten signal goes through inverters.
-- The adder is normal except the carry-in is 1. It's a 10-bit adder.
-- The outputs are inverted outputs, including the carry bit.
--subtresult := not (('0' & not eg_atten) - ('1' & logsin(11 downto 2)));
-- After a little pencil-and-paper, turns out this is equivalent to a regular adder!
subtresult := ('0' & eg_atten) + ('0' & logsin(11 downto 2));
-- Place all but carry bit into result; also two LSBs of logsin
atten_internal := subtresult(9 downto 0) & logsin(1 downto 0);
-- If addition overflowed, make it the largest value (saturate)
atten_internal := atten_internal or subtresult(10);
totalatten <= atten_internal;
signbit_1 <= signbit;
end if;
end process;
-- REGISTER/CYCLE 4
-- Exponential table
exp_table: process(clk) is
type exptable_t is array(31 downto 0) of std_logic_vector(44 downto 0);
constant exptable: exptable_t := (
"101110011001000000110100010111111000111111011",
"110011011100001100000011111001011000111111011",
"010110111001011101110101101111000000111111011",
"011010101010000001110110000111000000111111011",
"110110101010000001010001100001000000111111011",
"101110111001111000110110111010101010010111011",
"000000110000110100111001011110111011010011011",
"011110111001100100010110100100111011010011011",
"010110111000101000110101100010110011010011011",
"001010111001010011110011001110000011010011011",
"101010011001011011010100111101000111000011011",
"110110011000011111110011110011001111100001011",
"101111011101100111100100000011001111100001011",
"100010101010101011010111101101111100100001011",
"110010011001100011010000001101111100100001011",
"101010111000011100110101011010110100100001011",
"111011011101010100100010110000110100100001011",
"100011011100111000000001010100100100100001011",
"110011011101110000000110101110001100000001011",
"101011111100001110100001101000001100000001011",
"101010011001000110110110010001001000000001011",
"101011011100101010000101110111010001000101110",
"110011111101100010000010011111110011001100110",
"100011011100001100100111001001110011001100110",
"010101011100000000100100101011111011101110100",
"000111011101101000000011000111101011101110100",
"010110011000100100010100110100101011101110100",
"000010011001000110010011011000001011101110100",
"100011011100101010100000011010000011101110100",
"110111011101100010100111100100010010101110100",
"000000001001000100110000000100010010101110100",
"000011011100101000000001100010011010001110100"
);
variable eta : std_logic_vector(44 downto 0);
variable etb : std_logic_vector(12 downto 0);
variable etf, etg : std_logic_vector(9 downto 0);
begin
if rising_edge(clk) then
-- Main sine table body
eta := exptable(to_integer(totalatten(5 downto 1)));
-- 2-bit row chooser
case std_logic_vector(totalatten(7 downto 6)) is
when "00" => etb := "1" & eta(43) & eta(40) & eta(36) & eta(32) & eta(28)
& eta(24) & "1" & eta(18) & eta(14) & eta(10) & eta(7) & eta(3);
when "01" => etb := eta(44) & eta(42) & eta(39) & eta(35) & eta(31) & eta(27)
& eta(23) & "1" & eta(17) & eta(13) & "0" & eta(6) & eta(2);
when "10" => etb := "0" & eta(41) & eta(38) & eta(34) & eta(30) & eta(26)
& eta(22) & eta(19) & eta(16) & eta(12) & eta(9) & eta(5) & eta(1);
when others => etb := "00" & eta(37) & eta(33) & eta(29) & eta(25)
& eta(21) & eta(20) & eta(15) & eta(11) & eta(8) & eta(4) & eta(0);
end case;
-- Fixed value to sum
etf := etb(12 downto 6) & etb(4) & etb(3) & etb(0);
-- Gated value to sum
etg := "0000000" & etb(5) & etb(2) & etb(1);
etg := etg and not totalatten(0);
--RESULT
mantissa <= unsigned(etf) + unsigned(etg); --carry-out discarded
exponent <= totalatten(11 downto 8);
signbit_2 <= signbit_1;
end if;
end process;
-- REGISTER/CYCLE 5
-- Floating-point to integer, and incorporating sign bit
shift_and_flip: process(clk) is
variable shifter : unsigned(12 downto 0);
variable result : unsigned(13 downto 0);
begin
if rising_edge(clk) then
-- Two-stage shifting of mantissa by exponent
shifter := "001" & mantissa;
case std_logic_vector(exponent(1 downto 0)) is
when "00" => shifter := '0' & shifter(12 downto 1); -- LSB discarded
-- when "01" => shifter := shifter; -- no change
when "10" => shifter := shifter(11 downto 0) & '0';
when "11" => shifter := shifter(10 downto 0) & "00";
when others => null;
end case;
case std_logic_vector(exponent(3 downto 2)) is
when "00" => shifter := "000000000000" & shifter(12);
when "01" => shifter := "00000000" & shifter(12 downto 8);
when "10" => shifter := "0000" & shifter(12 downto 4);
-- when "11" => shifter := shifter; -- no change
when others => null;
end case;
result := test_214 & shifter; -- Introduce test bit as MSB
-- 2's complement
result := result xor signbit_2;
result := result + signbit_2; -- Carry-out discarded
op_result_pre <= result;
end if;
end process;
-- REGISTER/CYCLE 6
-- Extra register, take output after here
register_output: process(clk) is begin
if rising_edge(clk) then
op_result_internal <= op_result_pre;
end if;
end process;
op_result <= op_result_internal;
-- Circular buffers for old operator output values
-- These latch op_result_internal on the clock after
-- it is generated in register_output, and they provide
-- their output (prev1, etc.) on the same cycle as
-- op_result_internal is available.
prev1_buffer: entity circular_buffer
generic map(
DATA_WIDTH => 14,
BUFFER_DEPTH => NUM_VOICES,
CLEAR_ON_RESET => false)
port map(
clk => clk,
rst_bar => rst_bar,
din => std_logic_vector(op_result_internal),
std_logic_vector(dout) => prev1,
load => op_algorithm_ctl(5)
);
prevprev1_buffer: entity circular_buffer
generic map(
DATA_WIDTH => 14,
BUFFER_DEPTH => NUM_VOICES,
CLEAR_ON_RESET => false)
port map(
clk => clk,
rst_bar => rst_bar,
din => std_logic_vector(prev1),
std_logic_vector(dout) => prevprev1,
load => op_algorithm_ctl(5)
);
prev2_buffer: entity circular_buffer
generic map(
DATA_WIDTH => 14,
BUFFER_DEPTH => NUM_VOICES,
CLEAR_ON_RESET => false)
port map(
clk => clk,
rst_bar => rst_bar,
din => std_logic_vector(op_result_internal),
std_logic_vector(dout) => prev2,
load => op_algorithm_ctl(0)
);
end architecture;
| gpl-3.0 | 615981035c259104327f63d5f40db706 | 0.678203 | 3.376549 | false | false | false | false |
pkerling/ethernet_mac | reset_generator.vhd | 1 | 1,697 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Monitor the speed and issue a core-wide reset if it changes
library ieee;
use ieee.std_logic_1164.all;
use work.ethernet_types.all;
entity reset_generator is
generic(
-- Number of clock_i ticks reset should get asserted for
RESET_TICKS : positive := 1000
);
port(
clock_i : in std_ulogic;
-- Speed signal synchronous to clock_i
speed_i : in t_ethernet_speed;
-- Asynchronous reset input for this logic
-- Do NOT connect reset_i and reset_o anywhere in the design
reset_i : in std_ulogic;
-- Reset output
-- Is also asserted whenever reset_i is asserted
reset_o : out std_ulogic
);
end entity;
architecture rtl of reset_generator is
type t_state is (
WATCH,
RESET
);
signal state : t_state := WATCH;
signal reset_counter : integer range 0 to RESET_TICKS;
signal last_speed : t_ethernet_speed;
begin
speed_watch : process(reset_i, clock_i)
begin
if reset_i = '1' then
last_speed <= SPEED_UNSPECIFIED;
state <= WATCH;
reset_o <= '1';
elsif rising_edge(clock_i) then
reset_o <= '0';
case state is
when WATCH =>
null;
when RESET =>
reset_o <= '1';
if reset_counter = RESET_TICKS then
state <= WATCH;
else
reset_counter <= reset_counter + 1;
end if;
end case;
if speed_i /= last_speed then
-- Speed was changed
state <= RESET;
-- Always reset counter
reset_counter <= 0;
end if;
last_speed <= speed_i;
end if;
end process;
end architecture;
| bsd-3-clause | ce32783378b52be31f839750ed163883 | 0.651149 | 3.244742 | false | false | false | false |
DSP-Crowd/software | _install/de0_nano/src/tbd_rr_base.vhd | 1 | 5,561 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tbd_rr_base is
generic
(
use_sdram_pll : std_ulogic := '1'
);
port
(
clock_50mhz : in std_ulogic;
keys : in std_ulogic_vector(1 downto 0);
switches : in std_ulogic_vector(3 downto 0);
leds : out std_ulogic_vector(7 downto 0);
uart_rx : in std_ulogic;
uart_tx : out std_ulogic;
spi_cs : in std_ulogic_vector(1 downto 0);
spi_clk : in std_ulogic;
spi_mosi : in std_ulogic;
spi_miso : out std_ulogic;
spi_epcs_cs : out std_ulogic;
spi_epcs_clk : out std_ulogic;
spi_epcs_mosi : out std_ulogic;
spi_epcs_miso : in std_ulogic;
arReconf : in std_ulogic;
sdram_addr : out std_logic_vector(12 downto 0);
sdram_ba : out std_logic_vector(1 downto 0);
sdram_cke : out std_logic;
sdram_clk : out std_logic;
sdram_cs_n : out std_logic;
--sdram_dq : inout std_logic_vector(15 downto 0);
sdram_dq : in std_logic_vector(15 downto 0);
sdram_dqm : out std_logic_vector(1 downto 0);
sdram_cas_n : out std_logic;
sdram_ras_n : out std_logic;
sdram_we_n : out std_logic
);
end tbd_rr_base;
architecture rtl of tbd_rr_base is
signal reset_done : std_ulogic := '0';
signal n_reset_async : std_logic;
signal inputs_unsynced : std_ulogic_vector(switches'length downto 0);
signal inputs_synced : std_ulogic_vector(inputs_unsynced'range);
signal inputs_synced_debounced : std_ulogic_vector(inputs_synced'range);
signal key_0_synced_debounced : std_ulogic;
signal switches_synced_debounced : std_ulogic_vector(switches'range);
begin
-- Reconfiguration unit
reconfUnit: entity work.altremotePulsed(rtl)
port map
(
clock => clock_50mhz,
nResetAsync => n_reset_async,
reconf => arReconf
);
-- Give epcs64 signals to external user
-- No need to synchronize. Signals are not used within system clock
spi_epcs_cs <= spi_cs(0);
spi_epcs_clk <= spi_clk;
spi_epcs_mosi <= spi_mosi;
-- Important: MISO must not drive signal if epcs64 is not selected
spi_miso <= spi_epcs_miso when spi_cs(0) = '0' else 'Z';
-- Synchronize inputs
inputs_unsynced <= switches & keys(0);
key_sync: entity work.input_sync(rtl)
generic map
(
num_inputs => inputs_unsynced'length,
num_sync_stages => 2
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
unsynced_inputs => inputs_unsynced,
synced_outputs => inputs_synced
);
-- Debounce inputs
key_debounce: entity work.input_debounce(rtl)
generic map
(
num_inputs => inputs_synced'length
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
synced_inputs => inputs_synced,
debounced_outputs => inputs_synced_debounced
);
key_0_synced_debounced <= inputs_synced_debounced(0);
switches_synced_debounced <= inputs_synced_debounced(inputs_synced_debounced'high downto 1);
-- Hardware-is-alive-LED
hardware_is_alive_led: entity work.frequencyDivider(rtl)
generic map
(
divideBy => 25E7
)
port map
(
clock => clock_50mhz,
nResetAsync => n_reset_async,
output => leds(0)
);
-- Reset
proc_reset: process(clock_50mhz)
begin
if clock_50mhz'event and clock_50mhz = '1' then
reset_done <= '1';
end if;
end process;
n_reset_async <= reset_done and keys(1);
end architecture rtl;
| gpl-2.0 | ccd4090e6a54886f32cef61ab025fc82 | 0.511239 | 3.668206 | false | false | false | false |
insop/hyos | hyos_plb_v1_00_e/hdl/vhdl/TaggedSorter.vhd | 1 | 4,092 | --
-- Title TaggedSorter
--
-- Note: has 2 (1 * 2) queue capacities
-- basic block of tagged sorter
-- C-C Wang's style implementation
--
-- Author: Insop Song
-- Begin Date : 2007 04 23
-- Ver : 0.3b
-- Ver : 0.3c
--
-- Revision History
-- ---------------------------------------------------------------
-- Date Author Comments
-- 2007 05 01 Insop Song
-- 2007 05 01 Insop Song FSM way, not stable yet
-- 2007 05 01 Insop Song
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- width_key, width_data definitions
use work.tagged_pak.all;
ENTITY TaggedSorter IS
-- GENERIC (WIDTH_KEY: integer :=16;
-- WIDTH_DATA: integer :=16);
PORT
(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
insert : IN STD_LOGIC;
extract : IN STD_LOGIC;
LItag : IN STD_LOGIC;
LIkey : IN STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
LIdata : IN STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
ROtag : BUFFER STD_LOGIC;
ROkey : BUFFER STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
ROdata : BUFFER STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
LOtag : BUFFER STD_LOGIC;
LOkey : BUFFER STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
LOdata : BUFFER STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
RItag : IN STD_LOGIC;
RIkey : IN STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
RIdata : IN STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 )
);
END TaggedSorter;
ARCHITECTURE RTL_FSM OF TaggedSorter IS
-- state definition
type cntl_state is (s_compare, s_swap);
signal cs: cntl_state;
SIGNAL Akey, Bkey : STD_LOGIC_VECTOR ( 0 TO WIDTH_KEY-1 );
SIGNAL Adata, Bdata : STD_LOGIC_VECTOR ( 0 TO WIDTH_DATA-1 );
SIGNAL Atag, Btag : STD_LOGIC;
SIGNAL swap : STD_LOGIC;
BEGIN
--sync: PROCESS(clk, reset)
--BEGIN
--IF reset = '1' THEN
--cs <= s_init;
--
--ELSIF (rising_edge(clk)) THEN
--cs <= ns;
--END IF;
--END PROCESS sync;
--comb: PROCESS(cs, insert, extract, swap)
PROCESS(clk, reset)
BEGIN
IF reset ='1' THEN
--cs < = s_init;
Akey <= (others=>'1');
Adata <= (others=>'1');
Atag <= '0';
Bkey <= (others=>'1');
Bdata <= (others=>'1');
Btag <= '0';
LOkey <= (others=>'1');
LOdata <= (others=>'1');
LOtag <= '0';
ROkey <= (others=>'1');
ROdata <= (others=>'1');
ROtag <= '0';
cs <= s_compare;
ELSIF (rising_edge(clk)) THEN
case (cs) is
--when s_init =>
--
--ns <= s_compare;
when s_compare =>
IF (insert ='1' AND extract ='0') THEN
Akey <= LIkey;
Adata <= LIdata;
Atag <= LItag;
Bkey <= ROkey;
Bdata <= ROdata;
Btag <= ROtag;
cs <= s_swap;
ELSIF (insert = '0' AND extract ='1') THEN
Akey <= LOkey;
Adata <= LOdata;
Atag <= LOtag;
Bkey <= RIkey;
Bdata <= RIdata;
Btag <= RItag;
cs <= s_swap;
ELSE
cs <= s_compare;
END IF;
when s_swap =>
if swap = '1' then
LOkey <= Bkey;
LOdata<= Bdata;
LOtag <= Btag;
ROkey <= Akey;
ROdata<= Adata;
ROtag <= '1';
cs <= s_compare;
else
LOkey <= Akey;
LOdata<= Adata;
LOtag <= Atag;
ROkey <= Bkey;
ROdata<= Bdata;
ROtag <= Btag;
cs <= s_compare;
end if;
when others => null;
end case;
--cs <= ns;
end if;
END PROCESS;
--p_swap: PROCESS(Akey, Bkey, Atag)
--BEGIN
--IF ( (Akey < Bkey) OR (Atag ='1')) THEN
--swap <= '1';
--ELSE
--swap <= '0';
--END IF;
--END PROCESS p_swap;
--
swap <= '1' when (Akey < Bkey) OR (Atag ='1') else
'0';
END RTL_FSM;
| gpl-3.0 | c13c4014d015c04d90bf612793696690 | 0.466276 | 3.216981 | false | false | false | false |
ju994lo/syko_proj | cu.vhd | 1 | 1,042 | library ieee;
use ieee.std_logic_1164.all;
----xD
entity cu is
generic
(
);
port
(
clk: in std_logic;
reset: in std_logic;
data1: in std_logic_vector(7 downto 0);
data2: in std_logic_vector(7 downto 0);
ctrl: in std_logic;
flags: out std_logic_vector(3 downto 0);
data3: out std_logic_vector(7 downto 0)
);
end cu;
architecture bhv of cu is
signal reg: std_logic_vector(7 downto 0);
type state_type is (s0, s1, s2, s3);
signal state: state_type;
begin
process (clk, reset)
begin
if reset = '1' then
state <= s0;
elsif (rising_edge(clk)) then
case state is
when s0=>
if input = '1' then
state <= s1;
else
state <= s0;
end if;
when s1=>
if input = '1' then
state <= s2;
else
state <= s1;
end if;
when s2=>
if input = '1' then
state <= s3;
else
state <= s2;
end if;
when s3=>
if input = '1' then
state <= s3;
else
state <= s1;
end if;
end case;
end if;
end process;
end bhv;
| gpl-2.0 | 6b3b6e9c8ced81cfa04d1e7f5e43bd15 | 0.56142 | 2.529126 | false | false | false | false |
pkerling/ethernet_mac | framing_common.vhd | 1 | 2,022 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Common definitions pertaining to the structure of Ethernet frames
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_types.all;
use work.crc32.all;
use work.utility.all;
package framing_common is
-- Preamble/SFD data in IEEE 802.3 clauses 4.2.5 and 4.2.6 is denoted LSB first, so they appear reversed here
constant PREAMBLE_DATA : t_ethernet_data := "01010101";
--constant PREAMBLE_LENGTH : positive := 7;
constant START_FRAME_DELIMITER_DATA : t_ethernet_data := "11010101";
constant PADDING_DATA : t_ethernet_data := "00000000";
-- Data is counted from the end of the SFD to the beginning of the frame check sequence, exclusive
constant MIN_FRAME_DATA_BYTES : positive := 46 + 2 + 6 + 6; -- bytes
constant MAX_FRAME_DATA_BYTES : positive := 1500 + 2 + 6 + 6; -- bytes
constant INTERPACKET_GAP_BYTES : positive := 12; -- bytes
-- 11 bits are sufficient for 2048 bytes, Ethernet can only have 1518
constant PACKET_LENGTH_BITS : positive := 11;
constant MAX_PACKET_LENGTH : positive := (2 ** PACKET_LENGTH_BITS) - 1;
subtype t_packet_length is unsigned((PACKET_LENGTH_BITS - 1) downto 0);
-- Get a specific byte out of the given CRC32 suitable for transmission as Ethernet FCS
function fcs_output_byte(fcs : t_crc32; byte : integer) return t_ethernet_data;
end package;
package body framing_common is
function fcs_output_byte(fcs : t_crc32; byte : integer) return t_ethernet_data is
variable reversed : t_crc32;
variable out_byte : t_ethernet_data;
variable inverted : t_ethernet_data;
begin
-- Reverse and invert the whole CRC32, then get the needed byte out
reversed := reverse_vector(fcs);
out_byte := reversed((((byte + 1) * 8) - 1) downto byte * 8);
inverted := not out_byte;
return inverted;
end function;
end package body;
| bsd-3-clause | 6b032788052e6314733ff43a5ff2d29e | 0.716123 | 3.528796 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_test/niosii_top.vhd | 1 | 6,035 | ----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
----------------------------------------------------------------------------------
--The MIT License (MIT)
--
--Copyright (c) 2015
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
----------------------------------------------------------------------------------
-- Library Define
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity niosii_top is
Port (
p_clk_50Mhz : in std_logic;
p_button : in std_logic_vector( 1 downto 0 );
p_led_out : out std_logic_vector( 7 downto 0 );
sdram_addr : out std_logic_vector(12 downto 0); -- addr
sdram_ba : out std_logic_vector(1 downto 0); -- ba
sdram_cas_n : out std_logic; -- cas_n
sdram_cke : out std_logic; -- cke
sdram_cs_n : out std_logic; -- cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_ras_n : out std_logic; -- ras_n
sdram_we_n : out std_logic; -- we_n
sdram_clk_clk : out std_logic -- clk
);
end niosii_top;
architecture Behavioral of niosii_top is
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_addr : out std_logic_vector(12 downto 0); -- addr
sdram_ba : out std_logic_vector(1 downto 0); -- ba
sdram_cas_n : out std_logic; -- cas_n
sdram_cke : out std_logic; -- cke
sdram_cs_n : out std_logic; -- cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_ras_n : out std_logic; -- ras_n
sdram_we_n : out std_logic; -- we_n
sdram_clk_clk : out std_logic -- clk
);
end component niosii;
signal s_reset_n : std_logic;
begin
s_reset_n <= p_button(0);
u0 : component niosii
port map (
clk_clk => p_clk_50Mhz,
pio_0_external_connection_export => p_led_out,
reset_reset_n => s_reset_n,
sdram_addr => sdram_addr, -- sdram.addr
sdram_ba => sdram_ba, -- .ba
sdram_cas_n => sdram_cas_n, -- .cas_n
sdram_cke => sdram_cke, -- .cke
sdram_cs_n => sdram_cs_n, -- .cs_n
sdram_dq => sdram_dq, -- .dq
sdram_dqm => sdram_dqm, -- .dqm
sdram_ras_n => sdram_ras_n, -- .ras_n
sdram_we_n => sdram_we_n, -- .we_n
sdram_clk_clk => sdram_clk_clk -- sdram_clk.clk
);
end Behavioral;
| mit | 4a36a4b5889c8fdb163de4bfa4422b30 | 0.385418 | 4.967078 | false | false | false | false |
pkerling/ethernet_mac | crc.vhd | 1 | 2,151 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Utility functions for CRC calculation
-- Inspired by "Automatic Generation of Parallel CRC Circuits" by Michael Sprachmann
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utility.all;
package crc is
-- Update CRC old_crc by one bit (input) using a given polynomial
function update_crc(old_crc : std_ulogic_vector; input : std_ulogic; polynomial : std_ulogic_vector) return std_ulogic_vector;
-- Update CRC old_crc by an arbitrary number of bits (input) using a given polynomial
function update_crc(old_crc : std_ulogic_vector; input : std_ulogic_vector; polynomial : std_ulogic_vector) return std_ulogic_vector;
end package;
package body crc is
function update_crc(old_crc : std_ulogic_vector; input : std_ulogic; polynomial : std_ulogic_vector) return std_ulogic_vector is
variable new_crc : std_ulogic_vector(old_crc'range);
variable feedback : std_ulogic;
begin
assert not old_crc'ascending report "CRC argument must have descending range";
-- Simple calculation with LFSR
new_crc := old_crc;
feedback := new_crc(new_crc'high) xor input;
new_crc := std_ulogic_vector(unsigned(new_crc) sll 1);
if (feedback = '1') then
new_crc := new_crc xor polynomial(polynomial'high - 1 downto 0);
end if;
return new_crc;
end function;
-- Let the synthesizer figure out how to compute the checksum in parallel
-- for any number of bits
function update_crc(old_crc : std_ulogic_vector; input : std_ulogic_vector; polynomial : std_ulogic_vector) return std_ulogic_vector is
variable new_crc : std_ulogic_vector(old_crc'range);
begin
assert not old_crc'ascending report "CRC argument must have descending range";
assert not input'ascending report "Input argument must have descending range";
new_crc := old_crc;
-- Start with LSB
for i in input'low to input'high loop
new_crc := update_crc(new_crc, input(i), polynomial);
end loop;
return new_crc;
end function;
end package body;
| bsd-3-clause | 57f3996497dead1fcfb5d28cb802d331 | 0.738726 | 3.463768 | false | false | false | false |
FrankBuss/YaGraphCon | spartan3e/src/rs232_receiver.vhd | 1 | 2,756 | -- Copyright (c) 2009 Frank Buss ([email protected])
-- See license.txt for license
--
-- Simple RS232 receiver with generic, baudrate and 8N1 mode.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE work.all;
entity rs232_receiver is
generic(
-- clock frequency, in hz
SYSTEM_SPEED,
-- baudrate, in bps
BAUDRATE: integer
);
port(
clock: in std_logic;
reset: in std_logic;
-- received RS232 data
data: out unsigned(7 downto 0);
-- RS232 RX pin
rx: in std_logic;
-- this is set for one clock pulse to 1, when the data was received
dataReceived: out std_logic
);
end entity rs232_receiver;
architecture rtl of rs232_receiver is
constant MAX_COUNTER: natural := SYSTEM_SPEED / BAUDRATE;
signal baudrateCounter: natural range 0 to MAX_COUNTER := 0;
type stateType is (
WAIT_FOR_RX_START,
WAIT_HALF_BIT,
RECEIVE_BITS,
WAIT_FOR_STOP_BIT
);
signal state: stateType := WAIT_FOR_RX_START;
signal bitCounter: natural range 0 to 7 := 0;
signal shiftRegister: unsigned(7 downto 0) := (others => '0');
signal rxLatch: std_logic;
begin
update: process(clock, reset)
begin
if rising_edge(clock) then
dataReceived <= '0';
rxLatch <= rx;
if reset = '1' then
state <= WAIT_FOR_RX_START;
data <= (others => '0');
else
case state is
when WAIT_FOR_RX_START =>
if rxLatch = '0' then
-- start bit received, wait for a half bit time
-- to sample bits in the middle of the signal
state <= WAIT_HALF_BIT;
baudrateCounter <= MAX_COUNTER / 2 - 1;
end if;
when WAIT_HALF_BIT =>
if baudrateCounter = 0 then
-- now we are in the middle of the start bit,
-- wait a full bit for the middle of the first bit
state <= RECEIVE_BITS;
bitCounter <= 7;
baudrateCounter <= MAX_COUNTER - 1;
else
baudrateCounter <= baudrateCounter - 1;
end if;
when RECEIVE_BITS =>
-- sample a bit
if baudrateCounter = 0 then
shiftRegister <= rxLatch & shiftRegister(7 downto 1);
if bitCounter = 0 then
state <= WAIT_FOR_STOP_BIT;
else
bitCounter <= bitCounter - 1;
end if;
baudrateCounter <= MAX_COUNTER - 1;
else
baudrateCounter <= baudrateCounter - 1;
end if;
when WAIT_FOR_STOP_BIT =>
-- wait for the middle of the stop bit
if baudrateCounter = 0 then
state <= WAIT_FOR_RX_START;
if rxLatch = '1' then
data <= shiftRegister;
dataReceived <= '1';
-- else: missing stop bit, ignore
end if;
else
baudrateCounter <= baudrateCounter - 1;
end if;
end case;
end if;
end if;
end process;
end architecture rtl;
| mit | 0867be2dfc3fa4718258da783a6454ef | 0.620464 | 3.34466 | false | false | false | false |
pkerling/ethernet_mac | ethernet_types.vhd | 1 | 1,184 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
library ieee;
use ieee.std_logic_1164.all;
package ethernet_types is
-- One Ethernet interface byte
subtype t_ethernet_data is std_ulogic_vector(7 downto 0);
-- Ethernet speed, values defined below
subtype t_ethernet_speed is std_ulogic_vector(1 downto 0);
-- Ethernet MAC layer address
constant MAC_ADDRESS_BYTES : positive := 6;
subtype t_mac_address is std_ulogic_vector((MAC_ADDRESS_BYTES * 8 - 1) downto 0);
-- Use utility.reverse_bytes to convert from the canoncial form to the internal representation
-- Example: signal m : t_mac_address := reverse_bytes(x"04AA19BCDE10");
-- m then represents the canoncial address 04-AA-19-BC-DE-10
-- Broadcast address
constant BROADCAST_MAC_ADDRESS : t_mac_address := x"FFFFFFFFFFFF";
-- Speed constants
constant SPEED_1000MBPS : t_ethernet_speed := "10";
constant SPEED_100MBPS : t_ethernet_speed := "01";
constant SPEED_10MBPS : t_ethernet_speed := "00";
constant SPEED_UNSPECIFIED : t_ethernet_speed := "11";
end package; | bsd-3-clause | edb0a646aa28b25a23ce41b885044836 | 0.732264 | 3.431884 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/niosii_top.vhd | 1 | 4,372 | ----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
----------------------------------------------------------------------------------
--The MIT License (MIT)
--
--Copyright (c) 2015
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
----------------------------------------------------------------------------------
-- Library Define
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity niosii_top is
Port (
p_clk_50Mhz : in std_logic;
p_button : in std_logic_vector( 1 downto 0 );
p_led_out : out std_logic_vector( 7 downto 0 );
p_pwm_dir : out std_logic_vector(1 downto 0);
p_pwm_out : out std_logic_vector(1 downto 0);
p_uart_0_rxd : in std_logic;
p_uart_0_txd : out std_logic;
p_epcs_flash_dclk : out std_logic;
p_epcs_flash_sce : out std_logic;
p_epcs_flash_sdo : out std_logic;
p_epcs_flash_data0 : in std_logic
);
end niosii_top;
architecture Behavioral of niosii_top is
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_rxd : in std_logic := 'X'; -- rxd
uart_0_txd : out std_logic; -- txd
ip_pwm_dir : out std_logic_vector(1 downto 0); -- dir
ip_pwm_out : out std_logic_vector(1 downto 0); -- out
epcs_flash_dclk : out std_logic; -- dclk
epcs_flash_sce : out std_logic; -- sce
epcs_flash_sdo : out std_logic; -- sdo
epcs_flash_data0 : in std_logic := 'X' -- data0
);
end component niosii;
signal s_reset_n : std_logic;
begin
s_reset_n <= p_button(0);
u0 : component niosii
port map (
clk_clk => p_clk_50Mhz,
pio_0_external_connection_export => p_led_out,
reset_reset_n => s_reset_n,
uart_0_rxd => p_uart_0_rxd,
uart_0_txd => p_uart_0_txd,
ip_pwm_dir => p_pwm_dir,
ip_pwm_out => p_pwm_out,
epcs_flash_dclk => p_epcs_flash_dclk,
epcs_flash_sce => p_epcs_flash_sce,
epcs_flash_sdo => p_epcs_flash_sdo,
epcs_flash_data0 => p_epcs_flash_data0
);
end Behavioral;
| mit | 80c4c4810fd53bea2e4339a6a6ee5c58 | 0.486505 | 4.120641 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pwm/niosii/synthesis/submodules/ip_pwm_out.vhd | 6 | 3,223 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2015/01/14 00:19:02
-- Design Name:
-- Module Name: pwm_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ip_pwm_out is
Port (
reset_n : in STD_LOGIC;
clk : in STD_LOGIC;
pwm_hz : in STD_LOGIC_VECTOR (7 downto 0);
pwm_dir : in STD_LOGIC;
pwm_duty : in STD_LOGIC_VECTOR (7 downto 0);
pwm_pin_duty : out STD_LOGIC;
pwm_pin_dir : out STD_LOGIC
);
end ip_pwm_out;
architecture Behavioral of ip_pwm_out is
signal pwm_cnt_div : std_logic_vector( 7 downto 0 );
signal pwm_cnt_div_p : std_logic;
signal pwm_cnt_div_pp : std_logic;
signal pwm_cnt : std_logic_vector( 7 downto 0 );
signal pwm_cnt_p : std_logic;
signal pwm_pin_duty_p : std_logic;
begin
pwm_pin_duty <= pwm_pin_duty_p;
pwm_pin_dir <= pwm_dir;
-- PWM 분주 타이머
--
process( clk ) is
begin
if rising_edge( clk ) then
if reset_n = '0' then
pwm_cnt_div <= ( others => '0' );
else
pwm_cnt_div <= pwm_cnt_div + 1;
end if;
end if;
end process;
process( clk ) is
begin
if rising_edge( clk ) then
case pwm_hz is
when x"00" => pwm_cnt_div_p <= pwm_cnt_div(0);
when x"01" => pwm_cnt_div_p <= pwm_cnt_div(1);
when x"02" => pwm_cnt_div_p <= pwm_cnt_div(2);
when x"03" => pwm_cnt_div_p <= pwm_cnt_div(3);
when x"04" => pwm_cnt_div_p <= pwm_cnt_div(4);
when x"05" => pwm_cnt_div_p <= pwm_cnt_div(5);
when x"06" => pwm_cnt_div_p <= pwm_cnt_div(6);
when x"07" => pwm_cnt_div_p <= pwm_cnt_div(7);
when others => pwm_cnt_div_p <= pwm_cnt_div(0);
end case;
pwm_cnt_div_pp <= pwm_cnt_div_p;
if pwm_cnt_div_pp = '0' and pwm_cnt_div_p = '1' then
pwm_cnt_p <= '1';
else
pwm_cnt_p <= '0';
end if;
end if;
end process;
-- PWM 기본 타이머
--
process( clk ) is
begin
if rising_edge( clk ) then
if reset_n = '0' then
pwm_cnt <= ( others => '0' );
else
if pwm_cnt_p = '1' then
pwm_cnt <= pwm_cnt + 1;
end if;
end if;
end if;
end process;
-- PWM 출력
--
process( clk ) is
begin
if rising_edge( clk ) then
if reset_n = '0' then
pwm_pin_duty_p <= '0';
else
if pwm_cnt < pwm_duty then
if pwm_duty = x"00" then
pwm_pin_duty_p <= '0';
else
pwm_pin_duty_p <= '1';
end if;
else
if pwm_duty = x"FF" then
pwm_pin_duty_p <= '1';
else
pwm_pin_duty_p <= '0';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 674ae8efdef4750607415e828537a7ce | 0.554861 | 2.615699 | false | false | false | false |
DSP-Crowd/software | apps/mobile_rgb-led/de0_nano/src/tbd_rr_base_tb.vhd | 1 | 9,426 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_rr_base is
end tb_rr_base;
architecture bhv of tb_rr_base is
----------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------
-- System
constant c_spi_rate : natural := 99E5; -- Should be something weird => Detect more errors
constant c_bit_with_half_t : time := 1E9 ns / c_spi_rate;
constant c_byte_pad_t : time := 5 * c_bit_with_half_t;
constant SPI_USER_CS_IDX : natural := 1;
-- User
constant c_clk_frequency : natural := 50E6;
constant c_use_issi_sdram : std_ulogic := '1';
constant c_use_sdram_pll : std_ulogic := '1';
-- Derived
----------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------
signal clk : std_ulogic := '1';
signal keys : std_ulogic_vector(1 downto 0);
signal switches : std_ulogic_vector(3 downto 0);
signal leds : std_ulogic_vector(7 downto 0);
signal gdb_tx : std_ulogic := '1';
signal gdb_rx : std_ulogic;
signal spi_cs : std_ulogic_vector(1 downto 0) := (others => '1');
signal spi_clk : std_ulogic := '0';
signal spi_mosi : std_ulogic := '0';
signal spi_miso : std_ulogic := '0';
signal spi_epcs_cs : std_ulogic;
signal spi_epcs_clk : std_ulogic;
signal spi_epcs_mosi : std_ulogic;
signal spi_epcs_miso : std_ulogic;
signal arReconf : std_ulogic;
signal sdram_addr : std_logic_vector(12 downto 0);
signal sdram_ba : std_logic_vector(1 downto 0);
signal sdram_cke : std_logic;
signal sdram_clk : std_logic;
signal sdram_cs_n : std_logic;
signal sdram_dq : std_logic_vector(15 downto 0);
signal sdram_dqm : std_logic_vector(1 downto 0);
signal sdram_cas_n : std_logic;
signal sdram_ras_n : std_logic;
signal sdram_we_n : std_logic;
signal sdram_ctrl_str : string(1 to 5);
begin
clk <= not clk after 1E9 ns / (2 * c_clk_frequency);
keys <= (others => '1');
switches <= (others => '0');
testbed: entity work.tbd_rr_base(rtl)
generic map
(
use_sdram_pll => c_use_sdram_pll
)
port map
(
clock_50mhz => clk,
keys => keys,
switches => switches,
leds => leds,
uart_rx => gdb_tx,
uart_tx => gdb_rx,
spi_cs => spi_cs,
spi_clk => spi_clk,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
spi_epcs_cs => spi_epcs_cs,
spi_epcs_clk => spi_epcs_clk,
spi_epcs_mosi => spi_epcs_mosi,
spi_epcs_miso => spi_epcs_miso,
arReconf => arReconf,
sdram_addr => sdram_addr,
sdram_ba => sdram_ba,
sdram_cke => sdram_cke,
sdram_clk => sdram_clk,
sdram_cs_n => sdram_cs_n,
sdram_dq => sdram_dq,
sdram_dqm => sdram_dqm,
sdram_cas_n => sdram_cas_n,
sdram_ras_n => sdram_ras_n,
sdram_we_n => sdram_we_n
);
altera_sdram : if (c_use_issi_sdram = '0') generate
eSDRAM : entity work.sdram_0_test_component(europa)
port map
(
-- inputs:
clk => sdram_clk,
ZS_ADDR => sdram_addr,
zs_ba => sdram_ba,
zs_cas_n => sdram_cas_n,
zs_cke => sdram_cke,
zs_cs_n => sdram_cs_n,
zs_dqm => sdram_dqm,
zs_ras_n => sdram_ras_n,
zs_we_n => sdram_we_n,
-- outputs:
zs_dq => sdram_dq
);
end generate;
issi_sdram : if (c_use_issi_sdram = '1') generate
eSDRAM_issi : entity work.IS42S16160
port map
(
Dq => sdram_dq,
Addr => sdram_addr,
Ba => sdram_ba,
Clk => sdram_clk,
Cke => sdram_cke,
Cs_n => sdram_cs_n,
Ras_n => sdram_ras_n,
Cas_n => sdram_cas_n,
We_n => sdram_we_n,
Dqm => sdram_dqm
);
end generate;
sdram_ctrl_debug: process(sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n)
variable ctrl_vect : std_logic_vector(2 downto 0);
begin
ctrl_vect := sdram_ras_n & sdram_cas_n & sdram_we_n;
if(sdram_cs_n = '1')then
sdram_ctrl_str <= "DESL ";
else
case ctrl_vect is
when "111" =>
sdram_ctrl_str <= "NOP ";
when "101" =>
sdram_ctrl_str <= "READ ";
when "100" =>
sdram_ctrl_str <= "WRITE";
when "011" =>
sdram_ctrl_str <= "ACT ";
when "010" =>
sdram_ctrl_str <= "PALL ";
when "001" =>
sdram_ctrl_str <= "REF ";
when "000" =>
sdram_ctrl_str <= "MRS ";
when others =>
sdram_ctrl_str <= "??? ";
end case;
end if;
end process;
----------------------------------------------------------------------------------------------------------------------------
-- Testing process
Stimu : process
procedure spi_send_byte(dat : in std_ulogic_vector(7 downto 0)) is
begin
for i in 7 downto 0 loop
spi_mosi <= dat(i);
wait for c_bit_with_half_t;
spi_clk <= '1';
wait for c_bit_with_half_t;
spi_clk <= '0';
end loop;
spi_mosi <= '0';
end procedure;
procedure spi_send_rgb(red : in std_ulogic_vector(7 downto 0); green : in std_ulogic_vector(7 downto 0); blue : in std_ulogic_vector(7 downto 0)) is
begin
wait for c_byte_pad_t;
wait for c_byte_pad_t;
spi_cs(SPI_USER_CS_IDX) <= '0';
wait for c_byte_pad_t;
spi_send_byte(X"00"); -- Dummy address
wait for c_byte_pad_t;
spi_send_byte(X"00");
wait for c_byte_pad_t;
spi_send_byte(red);
wait for c_byte_pad_t;
spi_send_byte(green);
wait for c_byte_pad_t;
spi_send_byte(blue);
wait for c_byte_pad_t;
-- spi_send_byte(X"11"); -- Test byte
spi_cs(SPI_USER_CS_IDX) <= '1';
wait for c_byte_pad_t;
wait for c_byte_pad_t;
end procedure;
begin
-- ########################################################################################################
-----------------------------------------------------------------------------------------------------------
-- Testing Code
wait for 200 ns;
spi_send_rgb(X"AB", X"CD", X"EF");
spi_send_rgb(X"00", X"01", X"FE");
spi_send_rgb(X"00", X"FF", X"FE");
wait for 20 us;
spi_send_rgb(X"01", X"FE", X"FF");
-----------------------------------------------------------------------------------------------------------
-- ########################################################################################################
assert false report "SIMULATION ENDED SUCCESSFULLY" severity note;
wait;
end process;
----------------------------------------------------------------------------------------------------------------------------
end bhv;
| gpl-2.0 | 3095f8841c2a30bb32573c88682046c2 | 0.408445 | 3.869458 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_uart/niosii/synthesis/niosii.vhd | 1 | 48,239 | -- niosii.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii is
port (
clk_clk : in std_logic := '0'; -- clk.clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- pio_0_external_connection.export
reset_reset_n : in std_logic := '0'; -- reset.reset_n
uart_0_rxd : in std_logic := '0'; -- uart_0.rxd
uart_0_txd : out std_logic -- .txd
);
end entity niosii;
architecture rtl of niosii is
component niosii_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component niosii_jtag_uart_0;
component niosii_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(17 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(17 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component niosii_nios2_gen2_0;
component niosii_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component niosii_onchip_memory2_0;
component niosii_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component niosii_pio_0;
component niosii_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
chipselect : in std_logic := 'X'; -- chipselect
read_n : in std_logic := 'X'; -- read_n
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
dataavailable : out std_logic; -- dataavailable
readyfordata : out std_logic; -- readyfordata
rxd : in std_logic := 'X'; -- export
txd : out std_logic; -- export
irq : out std_logic -- irq
);
end component niosii_uart_0;
component niosii_mm_interconnect_0 is
port (
clk_0_clk_clk : in std_logic := 'X'; -- clk
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_data_master_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
jtag_uart_0_avalon_jtag_slave_address : out std_logic_vector(0 downto 0); -- address
jtag_uart_0_avalon_jtag_slave_write : out std_logic; -- write
jtag_uart_0_avalon_jtag_slave_read : out std_logic; -- read
jtag_uart_0_avalon_jtag_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_uart_0_avalon_jtag_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(13 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic; -- chipselect
uart_0_s1_address : out std_logic_vector(2 downto 0); -- address
uart_0_s1_write : out std_logic; -- write
uart_0_s1_read : out std_logic; -- read
uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
uart_0_s1_begintransfer : out std_logic; -- begintransfer
uart_0_s1_chipselect : out std_logic -- chipselect
);
end component niosii_mm_interconnect_0;
component niosii_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component niosii_irq_mapper;
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(17 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(17 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(13 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address
signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in
signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in
signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
signal irq_mapper_receiver0_irq : std_logic; -- jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
signal irq_mapper_receiver1_irq : std_logic; -- uart_0:irq -> irq_mapper:receiver1_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> rst_controller:reset_in0
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:inv -> jtag_uart_0:av_read_n
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:inv -> jtag_uart_0:av_write_n
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n
signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [jtag_uart_0:rst_n, nios2_gen2_0:reset_n, pio_0:reset_n, uart_0:reset_n]
begin
jtag_uart_0 : component niosii_jtag_uart_0
port map (
clk => clk_clk, -- clk.clk
rst_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- avalon_jtag_slave.chipselect
av_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address(0), -- .address
av_read_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv, -- .read_n
av_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
av_write_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv, -- .write_n
av_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
av_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
av_irq => irq_mapper_receiver0_irq -- irq.irq
);
nios2_gen2_0 : component niosii_nios2_gen2_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component niosii_onchip_memory2_0
port map (
clk => clk_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req -- .reset_req
);
pio_0 : component niosii_pio_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
out_port => pio_0_external_connection_export -- external_connection.export
);
uart_0 : component niosii_uart_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_uart_0_s1_address, -- s1.address
begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect
read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n
write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
dataavailable => open, -- .dataavailable
readyfordata => open, -- .readyfordata
rxd => uart_0_rxd, -- external_connection.export
txd => uart_0_txd, -- .export
irq => irq_mapper_receiver1_irq -- irq.irq
);
mm_interconnect_0 : component niosii_mm_interconnect_0
port map (
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address, -- jtag_uart_0_avalon_jtag_slave.address
jtag_uart_0_avalon_jtag_slave_write => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write, -- .write
jtag_uart_0_avalon_jtag_slave_read => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read, -- .read
jtag_uart_0_avalon_jtag_slave_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address
uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write
uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read
uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect
);
irq_mapper : component niosii_irq_mapper
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read;
mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of niosii
| mit | 7de668f4350970a2e0c8ac8e5115c876 | 0.484525 | 3.692514 | false | false | false | false |
ju994lo/syko_proj | rejestr.vhdl | 1 | 583 | library ieee;
use ieee.std_logic_1164.all;
entity rejestr is
generic
(
);
port
(
reset: in std_logic;
data: inout std_logic_vector(7 downto 0);
ag: out std_logic_vector(7 downto 0);
ctrl: in std_logic_vector(7 downto 0)
);
end rejestr;
architecture bhv of rejestr is
signal value: std_logic_vector(7 downto 0);
begin
process(reset, ctrl)
begin
if(reset='1')
then
value<="00000000";
elsif(ctrl="00000001")
then
ag<=value;
elsif(ctrl="00000010")
then
value<=data
else
data<="ZZZZZZZZ";
ag<="ZZZZZZZZ";
end if;
end process;
end bhv;
| gpl-2.0 | f37385af514aa136fc6d72743ec79000 | 0.660377 | 2.579646 | false | false | false | false |
DSP-Crowd/software | apps/mobile_rgb-led/de0_nano/src/spi2rgb.vhd | 1 | 4,486 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DSP-Crowd project --
-- https://www.dsp-crowd.com --
-- --
-- Author(s): --
-- - Johannes Natter, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.dsp-crowd.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spi2rgb_pkg.all;
entity spi2rgb is
port
(
clock : in std_ulogic;
n_reset_async : in std_ulogic;
spi_cs : in std_ulogic;
spi_clk : in std_ulogic;
spi_mosi : in std_ulogic;
data : out SPI2RGB_DATA_TYPE;
valid_bits : out std_ulogic_vector(SPI2RGB_NUM_DATA_BYTES - 1 downto 0)
);
end spi2rgb;
architecture rtl of spi2rgb is
type STATEMACHINE_STEP_TYPE is
(
SM_WAIT_CS_LOW, SM_GET_DATA_BIT, SM_WAIT_CLK_LOW
);
type REG_TYPE is record
sm_step : STATEMACHINE_STEP_TYPE;
bit_idx : natural;
byte_idx : natural;
tmp : std_ulogic_vector(7 downto 0);
logging_done : std_ulogic;
end record;
constant RSET_INIT_VAL : REG_TYPE :=
(
sm_step => SM_WAIT_CS_LOW,
bit_idx => 0,
byte_idx => 0,
tmp => (others => '0'),
logging_done => '0'
);
signal R, NxR : REG_TYPE;
begin
proc_comb: process(R, spi_cs, spi_clk, spi_mosi)
begin
NxR <= R;
data <= (others => (others => '0'));
valid_bits <= (others => '0');
case R.sm_step is
when SM_WAIT_CS_LOW =>
if(spi_cs = '0' and R.logging_done = '0')then
NxR.sm_step <= SM_GET_DATA_BIT;
NxR.bit_idx <= 7;
NxR.byte_idx <= 4;
end if;
when SM_GET_DATA_BIT =>
if(spi_clk = '1')then
NxR.sm_step <= SM_WAIT_CLK_LOW;
NxR.tmp(R.bit_idx) <= spi_mosi;
end if;
when SM_WAIT_CLK_LOW =>
if(spi_clk = '0')then
NxR.sm_step <= SM_GET_DATA_BIT;
if(R.bit_idx = 0)then
NxR.bit_idx <= 7;
if(R.byte_idx < 3)then
data(R.byte_idx) <= R.tmp;
valid_bits(R.byte_idx) <= '1';
end if;
if(R.byte_idx = 0)then
NxR.logging_done <= '1';
NxR.sm_step <= SM_WAIT_CS_LOW;
else
NxR.byte_idx <= R.byte_idx - 1;
end if;
else
NxR.bit_idx <= R.bit_idx - 1;
end if;
end if;
when others =>
NxR.logging_done <= '0';
NxR.sm_step <= SM_WAIT_CS_LOW;
end case;
if(spi_cs = '1')then
NxR.logging_done <= '0';
NxR.sm_step <= SM_WAIT_CS_LOW;
end if;
end process;
proc_reg: process(n_reset_async, clock)
begin
if(n_reset_async = '0')then
R <= RSET_INIT_VAL;
elsif(clock'event and clock = '1')then
R <= NxR;
end if;
end process;
end architecture rtl;
| gpl-2.0 | 350341b2cb5d70bbcc2b7747584ace03 | 0.430896 | 3.488336 | false | false | false | false |
airhdl/spi-to-axi-bridge | src/spi2axi.vhd | 1 | 28,055 | -------------------------------------------------------------------------------
--
-- SPI to AXI4-Lite Bridge
--
-- Description:
-- An SPI to AXI4-Lite Bridge to allow accessing AXI4-Lite register banks
-- over SPI. See https://airhdl.com for a popular, web-based AXI4 register
-- generator.
--
-- Author(s):
-- Guy Eschemann, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2022 Guy Eschemann
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity spi2axi is
generic(
SPI_CPOL : natural range 0 to 1 := 0; -- SPI clock polarity
SPI_CPHA : natural range 0 to 1 := 0; -- SPI clock phase
AXI_ADDR_WIDTH : integer := 32 -- AXI address bus width, in bits
);
port(
-- SPI interface
spi_sck : in std_logic; -- SPI clock
spi_ss_n : in std_logic; -- SPI slave select (low active)
spi_mosi : in std_logic; -- SPI master-out-slave-in
spi_miso : out std_logic; -- SPI master-in-slave-out
-- Clock and Reset
axi_aclk : in std_logic;
axi_aresetn : in std_logic;
-- AXI Write Address Channel
s_axi_awaddr : out std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0);
s_axi_awprot : out std_logic_vector(2 downto 0); -- sigasi @suppress "Unused port"
s_axi_awvalid : out std_logic;
s_axi_awready : in std_logic;
-- AXI Write Data Channel
s_axi_wdata : out std_logic_vector(31 downto 0);
s_axi_wstrb : out std_logic_vector(3 downto 0);
s_axi_wvalid : out std_logic;
s_axi_wready : in std_logic;
-- AXI Read Address Channel
s_axi_araddr : out std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0);
s_axi_arprot : out std_logic_vector(2 downto 0); -- sigasi @suppress "Unused port"
s_axi_arvalid : out std_logic;
s_axi_arready : in std_logic;
-- AXI Read Data Channel
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic;
-- AXI Write Response Channel
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic
);
end entity;
architecture rtl of spi2axi is
------------------------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------------------------
component synchronizer is
generic(
G_INIT_VALUE : std_logic := '0'; -- initial value of all flip-flops in the module
G_NUM_GUARD_FFS : positive := 1); -- number of guard flip-flops after the synchronizing flip-flop
port(
i_reset : in std_logic; -- asynchronous, high-active
i_clk : in std_logic; -- destination clock
i_data : in std_logic;
o_data : out std_logic);
end component;
------------------------------------------------------------------------------------------------
-- Subprograms
------------------------------------------------------------------------------------------------
function to_std_logic(value : natural) return std_logic is
begin
if value = 0 then
return '0';
else
return '1';
end if;
end function;
------------------------------------------------------------------------------------------------
-- Constants
------------------------------------------------------------------------------------------------
constant CMD_WRITE : std_logic_vector(7 downto 0) := x"00";
constant CMD_READ : std_logic_vector(7 downto 0) := x"01";
constant SPI_FRAME_LENGTH_BYTES : natural := 11;
------------------------------------------------------------------------------------------------
-- Types
------------------------------------------------------------------------------------------------
type spi_state_t is (SPI_RECEIVE, SPI_PROCESS_RX_BYTE, SPI_LOAD_TX_BYTE);
type axi_state_t is (AXI_IDLE, AXI_WRITE_ACK, AXI_WRITE_BRESP, AXI_READ_ADDR_ACK, AXI_READ_DATA);
------------------------------------------------------------------------------------------------
-- Signals
------------------------------------------------------------------------------------------------
-- Registered signals with initial values
signal spi_state : spi_state_t := SPI_RECEIVE;
signal axi_state : axi_state_t := AXI_IDLE;
signal spi_sck_sync_old : std_logic := to_std_logic(SPI_CPOL);
signal spi_rx_shreg : std_logic_vector(7 downto 0) := (others => '0');
signal spi_tx_shreg : std_logic_vector(7 downto 0) := (others => '0');
signal axi_bresp_valid : std_logic := '0';
signal axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal axi_rdata_valid : std_logic := '0';
signal axi_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal spi_rx_cmd : std_logic_vector(7 downto 0) := (others => '0');
signal spi_rx_addr : std_logic_vector(31 downto 0) := (others => '0');
signal spi_rx_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal spi_rx_valid : std_logic := '0';
signal s_axi_awvalid_int : std_logic := '0';
signal s_axi_wvalid_int : std_logic := '0';
signal axi_fsm_reset : std_logic := '1';
-- Unregistered signals
signal spi_sck_sync : std_logic;
signal spi_ss_n_sync : std_logic;
signal axi_areset : std_logic;
begin
axi_areset <= not axi_aresetn;
------------------------------------------------------------------------------------------------
-- SPI SCK synchronizer
------------------------------------------------------------------------------------------------
spi_sck_sync_inst : synchronizer
generic map(
G_INIT_VALUE => to_std_logic(SPI_CPOL),
G_NUM_GUARD_FFS => 1
)
port map(
i_reset => axi_areset,
i_clk => axi_aclk,
i_data => spi_sck,
o_data => spi_sck_sync
);
spi_ss_sync_inst : synchronizer
generic map(
G_INIT_VALUE => to_std_logic(SPI_CPOL),
G_NUM_GUARD_FFS => 1
)
port map(
i_reset => axi_areset,
i_clk => axi_aclk,
i_data => spi_ss_n,
o_data => spi_ss_n_sync
);
------------------------------------------------------------------------------------------------
-- SPI receive/transmit state machine
------------------------------------------------------------------------------------------------
spi_fsm : process(axi_aclk) is
variable spi_rx_bit_idx : natural range 0 to 7 := 0;
variable spi_rx_byte_idx : natural range 0 to SPI_FRAME_LENGTH_BYTES := 0;
variable spi_tx_bit_idx : natural range 0 to 7 := 0;
variable spi_tx_byte_idx : natural range 0 to SPI_FRAME_LENGTH_BYTES := 0;
variable spi_sck_re : boolean;
variable spi_sck_fe : boolean;
variable spi_tx_byte : std_logic_vector(7 downto 0);
begin
if rising_edge(axi_aclk) then
if axi_aresetn = '0' then
spi_rx_bit_idx := 0;
spi_rx_byte_idx := 0;
spi_tx_bit_idx := 0;
spi_tx_byte_idx := 0;
spi_tx_byte := (others => '0');
spi_sck_sync_old <= to_std_logic(SPI_CPOL);
spi_rx_valid <= '0';
spi_rx_cmd <= (others => '0');
spi_rx_addr <= (others => '0');
spi_rx_wdata <= (others => '0');
spi_rx_shreg <= (others => '0');
spi_tx_shreg <= (others => '0');
axi_fsm_reset <= '1';
spi_state <= SPI_RECEIVE;
else
-- defaults:
spi_rx_valid <= '0';
spi_sck_sync_old <= spi_sck_sync;
case spi_state is
------------------------------------------------------------------------------------
-- Receive the 11-byte SPI frame
-- * SPI bytes are received MSB-first
------------------------------------------------------------------------------------
when SPI_RECEIVE =>
if spi_ss_n_sync = '0' then
axi_fsm_reset <= '0';
spi_sck_re := spi_sck_sync = '1' and spi_sck_sync_old = '0';
spi_sck_fe := spi_sck_sync = '0' and spi_sck_sync_old = '1';
-- SPI clock sample edge
if (SPI_CPOL = 0 and SPI_CPHA = 0 and spi_sck_re) or
(SPI_CPOL = 0 and SPI_CPHA = 1 and spi_sck_fe) or
(SPI_CPOL = 1 and SPI_CPHA = 0 and spi_sck_fe) or
(SPI_CPOL = 1 and SPI_CPHA = 1 and spi_sck_re) then
spi_rx_shreg <= spi_rx_shreg(spi_rx_shreg'high - 1 downto 0) & spi_mosi; -- assuming `spi_mosi` is steady and does not need a synchronizer
--
if spi_rx_bit_idx = 7 then
spi_rx_bit_idx := 0;
--
if spi_rx_byte_idx < SPI_FRAME_LENGTH_BYTES then -- in case of SPI overrun, stop processing receive bytes
spi_state <= SPI_PROCESS_RX_BYTE;
end if;
else
spi_rx_bit_idx := spi_rx_bit_idx + 1;
end if;
-- SPI clock drive edge
elsif (SPI_CPOL = 0 and SPI_CPHA = 0 and spi_sck_fe) or
(SPI_CPOL = 0 and SPI_CPHA = 1 and spi_sck_re) or
(SPI_CPOL = 1 and SPI_CPHA = 0 and spi_sck_re) or
(SPI_CPOL = 1 and SPI_CPHA = 1 and spi_sck_fe) then
if SPI_CPHA = 1 and spi_tx_bit_idx = 0 then
spi_tx_shreg <= spi_tx_byte;
spi_tx_bit_idx := spi_tx_bit_idx + 1;
else
spi_tx_shreg <= spi_tx_shreg(spi_tx_shreg'high - 1 downto 0) & '0';
--
if spi_tx_bit_idx = 7 then
spi_tx_bit_idx := 0;
--
if spi_tx_byte_idx < SPI_FRAME_LENGTH_BYTES - 1 then -- in case of SPI overrun, stop loading transmit bytes
spi_tx_byte_idx := spi_tx_byte_idx + 1;
spi_state <= SPI_LOAD_TX_BYTE;
end if;
else
spi_tx_bit_idx := spi_tx_bit_idx + 1;
end if;
end if;
end if;
else
spi_rx_bit_idx := 0;
spi_rx_byte_idx := 0;
spi_tx_bit_idx := 0;
spi_tx_byte_idx := 0;
spi_tx_byte := (others => '0');
axi_fsm_reset <= '1';
end if;
------------------------------------------------------------------------------------
-- Process the last received SPI byte
------------------------------------------------------------------------------------
when SPI_PROCESS_RX_BYTE =>
if spi_rx_byte_idx = 0 then
spi_rx_cmd <= spi_rx_shreg;
else
if spi_rx_cmd = CMD_WRITE then
if spi_rx_byte_idx <= 4 then
spi_rx_addr <= spi_rx_addr(23 downto 0) & spi_rx_shreg;
elsif spi_rx_byte_idx <= 8 then
spi_rx_wdata <= spi_rx_wdata(23 downto 0) & spi_rx_shreg;
--
if spi_rx_byte_idx = 8 then
-- Write data complete -> trigger the AXI write access
spi_rx_valid <= '1';
end if;
else
null; -- don't care
end if;
else -- CMD_READ
assert spi_rx_cmd = CMD_READ report "unsupported command" severity failure;
if spi_rx_byte_idx <= 4 then
spi_rx_addr <= spi_rx_addr(23 downto 0) & spi_rx_shreg;
--
if spi_rx_byte_idx = 4 then
-- Read address complete -> trigger the AXI read access
spi_rx_valid <= '1';
end if;
else
null; -- don't care
end if;
end if;
end if;
--
spi_rx_byte_idx := spi_rx_byte_idx + 1;
spi_state <= SPI_RECEIVE;
------------------------------------------------------------------------------------
-- Load the next SPI transmit byte
------------------------------------------------------------------------------------
when SPI_LOAD_TX_BYTE =>
spi_tx_byte := (others => '0'); -- default
--
if spi_rx_cmd = CMD_WRITE then
if spi_tx_byte_idx = 10 then
-- Write status byte:
-- [7:3] reserved
-- [2] timeout
-- [1:0] BRESP
spi_tx_byte := (others => '0');
spi_tx_byte(2) := not axi_bresp_valid;
spi_tx_byte(axi_bresp'range) := axi_bresp;
end if;
else -- CMD_READ
if spi_tx_byte_idx <= 5 then
null;
elsif spi_tx_byte_idx = 6 then
spi_tx_byte := axi_rdata(31 downto 24);
elsif spi_tx_byte_idx = 7 then
spi_tx_byte := axi_rdata(23 downto 16);
elsif spi_tx_byte_idx = 8 then
spi_tx_byte := axi_rdata(15 downto 8);
elsif spi_tx_byte_idx = 9 then
spi_tx_byte := axi_rdata(7 downto 0);
else
-- Read status byte:
-- [7:3] reserved
-- [2] timeout
-- [1:0] RRESP
spi_tx_byte := (others => '0');
spi_tx_byte(2) := not axi_rdata_valid;
spi_tx_byte(1 downto 0) := axi_rresp;
end if;
end if;
--
if SPI_CPHA = 0 then
spi_tx_shreg <= spi_tx_byte;
end if;
--
spi_state <= SPI_RECEIVE;
end case;
end if;
end if;
end process spi_fsm;
spi_miso <= spi_tx_shreg(spi_tx_shreg'high);
------------------------------------------------------------------------------------------------
-- AXI4 receive/transmit state machine
------------------------------------------------------------------------------------------------
axi_fsm : process(axi_aclk) is
begin
if rising_edge(axi_aclk) then
if axi_aresetn = '0' or axi_fsm_reset = '1' then
s_axi_awvalid_int <= '0';
s_axi_awprot <= (others => '0');
s_axi_awaddr <= (others => '0');
s_axi_arvalid <= '0';
s_axi_arprot <= (others => '0');
s_axi_araddr <= (others => '0');
s_axi_wvalid_int <= '0';
s_axi_wstrb <= (others => '0');
s_axi_wdata <= (others => '0');
s_axi_bready <= '0';
s_axi_rready <= '0';
axi_bresp_valid <= '0';
axi_bresp <= (others => '0');
axi_rresp <= (others => '0');
axi_rdata_valid <= '0';
axi_rdata <= (others => '0');
axi_state <= AXI_IDLE;
else
case axi_state is
--------------------------------------------------------------------------------
-- Idle
--------------------------------------------------------------------------------
when AXI_IDLE =>
if spi_rx_valid = '1' then
axi_bresp_valid <= '0';
axi_rdata_valid <= '0';
--
if spi_rx_cmd = CMD_WRITE then
s_axi_awvalid_int <= '1';
s_axi_awaddr <= (others => '0');
s_axi_awaddr(31 downto 0) <= spi_rx_addr;
s_axi_awprot <= (others => '0'); -- unpriviledged, secure data access
s_axi_wvalid_int <= '1';
s_axi_wdata <= spi_rx_wdata;
s_axi_wstrb <= (others => '1');
axi_state <= AXI_WRITE_ACK;
else
s_axi_arvalid <= '1';
s_axi_araddr <= (others => '0');
s_axi_araddr(31 downto 0) <= spi_rx_addr;
s_axi_arprot <= (others => '0'); -- unpriviledged, secure data access
axi_state <= AXI_READ_ADDR_ACK;
end if;
end if;
--------------------------------------------------------------------------------
-- AXI write: wait for write address and data acknowledge
--------------------------------------------------------------------------------
when AXI_WRITE_ACK =>
if s_axi_awready = '1' then
s_axi_awvalid_int <= '0';
--
if s_axi_wvalid_int = '0' then
s_axi_bready <= '1';
axi_state <= AXI_WRITE_BRESP; -- move on when both write address and data have been acknowledged
end if;
end if;
--
if s_axi_wready = '1' then
s_axi_wvalid_int <= '0';
s_axi_wstrb <= (others => '0');
--
if s_axi_awvalid_int = '0' then
s_axi_bready <= '1';
axi_state <= AXI_WRITE_BRESP; -- move on when both write address and data have been acknowledged
end if;
end if;
--------------------------------------------------------------------------------
-- AXI write: wait for write response
--------------------------------------------------------------------------------
when AXI_WRITE_BRESP =>
if s_axi_bvalid = '1' then
s_axi_bready <= '0';
axi_bresp_valid <= '1';
axi_bresp <= s_axi_bresp;
axi_state <= AXI_IDLE;
end if;
--------------------------------------------------------------------------------
-- AXI read: wait for read address acknowledge
--------------------------------------------------------------------------------
when AXI_READ_ADDR_ACK =>
if s_axi_arready = '1' then
s_axi_arvalid <= '0';
s_axi_rready <= '1';
axi_state <= AXI_READ_DATA;
end if;
--------------------------------------------------------------------------------
-- AXI read: wait for read data
--------------------------------------------------------------------------------
when AXI_READ_DATA =>
if s_axi_rvalid = '1' then
s_axi_rready <= '0';
axi_rdata_valid <= '1';
axi_rdata <= s_axi_rdata;
axi_rresp <= s_axi_rresp;
axi_state <= AXI_IDLE;
end if;
end case;
end if;
end if;
end process axi_fsm;
s_axi_awvalid <= s_axi_awvalid_int;
s_axi_wvalid <= s_axi_wvalid_int;
end architecture;
-------------------------------------------------------------------------------
-- Synchronizer for clock-domain crossings.
--
-- This file is part of the noasic library.
--
-- Description:
-- Synchronizes a single-bit signal from a source clock domain
-- to a destination clock domain using a chain of flip-flops (synchronizer
-- FF followed by one or more guard FFs).
--
-- Author(s):
-- Guy Eschemann, [email protected]
-------------------------------------------------------------------------------
-- Copyright (c) 2012-2022 Guy Eschemann
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer is
generic(
G_INIT_VALUE : std_logic := '0'; -- initial value of all flip-flops in the module
G_NUM_GUARD_FFS : positive := 1); -- number of guard flip-flops after the synchronizing flip-flop
port(
i_reset : in std_logic; -- asynchronous, high-active
i_clk : in std_logic; -- destination clock
i_data : in std_logic;
o_data : out std_logic);
end synchronizer;
architecture RTL of synchronizer is
-------------------------------------------------------------------------------
-- Registered signals (with initial values):
--
signal s_data_sync_r : std_logic := G_INIT_VALUE;
signal s_data_guard_r : std_logic_vector(G_NUM_GUARD_FFS - 1 downto 0) := (others => G_INIT_VALUE);
-------------------------------------------------------------------------------
-- Attributes
--
-- Synplify Pro: disable shift-register LUT (SRL) extraction
attribute syn_srlstyle : string;
attribute syn_srlstyle of s_data_sync_r : signal is "registers";
attribute syn_srlstyle of s_data_guard_r : signal is "registers";
-- Xilinx XST: disable shift-register LUT (SRL) extraction
attribute shreg_extract : string;
attribute shreg_extract of s_data_sync_r : signal is "no";
attribute shreg_extract of s_data_guard_r : signal is "no";
-- Disable X propagation during timing simulation. In the event of
-- a timing violation, the previous value is retained on the output instead
-- of going unknown (see Xilinx UG625)
attribute ASYNC_REG : string;
attribute ASYNC_REG of s_data_sync_r : signal is "TRUE";
begin
-------------------------------------------------------------------------------
-- Synchronizer process
--
p_synchronizer : process(i_clk, i_reset)
begin
if i_reset = '1' then
s_data_sync_r <= G_INIT_VALUE;
s_data_guard_r <= (others => G_INIT_VALUE);
elsif rising_edge(i_clk) then
sync_ff : s_data_sync_r <= i_data;
guard_ffs : if s_data_guard_r'length = 1 then
s_data_guard_r(0) <= s_data_sync_r; -- avoid "Range is empty (null range)" warnings:
else
s_data_guard_r <= s_data_guard_r(s_data_guard_r'high - 1 downto 0) & s_data_sync_r;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Outputs
--
o_data <= s_data_guard_r(s_data_guard_r'high);
end RTL;
| apache-2.0 | 1b079eeb5987e25f9d1d4dd5786eaee1 | 0.36596 | 4.948845 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pwm/niosii_top.vhd | 1 | 3,482 | ----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
----------------------------------------------------------------------------------
--The MIT License (MIT)
--
--Copyright (c) 2015
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
----------------------------------------------------------------------------------
-- Library Define
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity niosii_top is
Port (
p_clk_50Mhz : in std_logic;
p_button : in std_logic_vector( 1 downto 0 );
p_led_out : out std_logic_vector( 7 downto 0 );
p_pwm_dir : out std_logic_vector(1 downto 0);
p_pwm_out : out std_logic_vector(1 downto 0);
p_uart_0_rxd : in std_logic;
p_uart_0_txd : out std_logic
);
end niosii_top;
architecture Behavioral of niosii_top is
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_rxd : in std_logic := 'X'; -- rxd
uart_0_txd : out std_logic; -- txd
ip_pwm_dir : out std_logic_vector(1 downto 0); -- dir
ip_pwm_out : out std_logic_vector(1 downto 0) -- out
);
end component niosii;
signal s_reset_n : std_logic;
begin
s_reset_n <= p_button(0);
u0 : component niosii
port map (
clk_clk => p_clk_50Mhz,
pio_0_external_connection_export => p_led_out,
reset_reset_n => s_reset_n,
uart_0_rxd => p_uart_0_rxd,
uart_0_txd => p_uart_0_txd,
ip_pwm_dir => p_pwm_dir,
ip_pwm_out => p_pwm_out
);
end Behavioral;
| mit | ca13aab75777ac648ff98fdfda262dba | 0.520678 | 4.082063 | false | false | false | false |
Dragonturtle/SHERPA | HDL/SHERPA/clock_syncer.vhd | 1 | 1,093 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity clock_syncer is
Port ( dac_clk_in : in STD_LOGIC;
adc_clk_in : in STD_LOGIC;
reset_in : in STD_LOGIC;
sync_out : out STD_LOGIC);
end clock_syncer;
architecture Behavioral of clock_syncer is
signal sync : std_logic := '0';
signal init : std_logic := '0';
signal counter : std_logic_vector(12 downto 0) := (others => '1');
alias rst : std_logic is reset_in;
begin
sync_out <= sync;
-- This solution is clearly NOT ideal, but it does work.
syncer : process (rst, dac_clk_in, adc_clk_in)
begin
if ( rst = '1' ) then
sync <= '0';
init <= '0';
counter <= (others => '1');
elsif (rising_edge(adc_clk_in)) then
if ( dac_clk_in = '1' ) then
sync <= '1';
init <= '1';
counter <= (others => '0');
elsif (to_integer(unsigned(counter)) < 8000) then
sync <= '1';
if (init = '1') then
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
else
sync <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 89bfdc29ff0fde4d6c0d4e9036e9378e | 0.581885 | 2.78117 | false | false | false | false |
josemonsalve2/cpeg324_calculator | vivado/hdl/InstructionsMemory/src/vhdl/new/InstructionsMemory.vhd | 1 | 6,201 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/09/2016 02:23:00 PM
-- Design Name:
-- Module Name: InstructionsMemory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--RAM INITIALIZATION CODE TAKEN FROM THE
--XILINX XST User guide for Virtex-4 Virtex-5 Spartan-3 and Newer CPLD Devices
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all; --include package textio.vhd
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstructionsMemory is
generic ( INIT_BRAM_FILE: string );
Port ( clk : in STD_LOGIC;
PC : in STD_LOGIC_VECTOR (7 downto 0);
Instruction : out STD_LOGIC_VECTOR (7 downto 0):=(others => '0');
reset: in STD_LOGIC;
num_instructions: out STD_LOGIC_VECTOR (7 downto 0):= (others => '0')
);
end InstructionsMemory;
architecture Behavioral of InstructionsMemory is
COMPONENT blk_mem_gen_0
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
--- CODE FOR BRAM INITIALIZATION see reference above. Modified
type RamType is array(0 to 256) of bit_vector(7 downto 0);
impure function InitRamFromFile (RamFileName : in string) return RamType is
FILE RamFile : text open READ_MODE is RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
variable I : integer := 0;
begin
while (not endfile(RamFile)) loop
readline ( RamFile, RamFileLine );
read ( RamFileLine, RAM(I) );
I:=I+1;
end loop;
return RAM;
end function;
impure function numInstructions (RamFileName : in string) return std_logic_vector(7 downto 0) is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable I : integer := 0;
begin
while (not endfile(RamFile)) loop
readline ( RamFile, RamFileLine );
I:=I+1;
end loop;
return std_logic_vector(to_unsigned(I,8));
end function;
-- Signal for telling the system we are initializing the ram
signal init_ram: STD_LOGIC := '1';
--Ram init state machine and used counters
type type_ram_init_states is (slow_start, writing, finished);
signal ram_init_state : type_ram_init_states := slow_start;
signal RAM_INIT_COUNTER : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal init_counter: unsigned(7 downto 0) := (others => '0');
--Read value from file
signal RAM : RamType := InitRamFromFile(INIT_BRAM_FILE);
-- Signals going to BRAM
signal init_address: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
--BRAM SIGNALS
signal write_enable : STD_LOGIC_VECTOR (0 downto 0) := (others => '1');
signal data_write : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal address : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
-- Other signals
signal s_numInstructions : STD_LOGIC_VECTOR (7 downto 0) := numInstructions(INIT_BRAM_FILE);
begin
--Connections
num_instructions <= s_numInstructions;
bram_0 : blk_mem_gen_0
PORT MAP (
clka => clk,
ena => '1',
wea => write_enable,
addra => address,
dina => data_write,
douta => Instruction
);
with init_ram select address <= PC when '0',
init_address when '1';
init_bram_process: process (clk,reset) is
begin
if (reset = '1') then
init_ram<='1';
ram_init_state <= slow_start;
end if;
if (rising_edge(clk) and init_ram = '1') then
write_enable(0) <= '1';
case ram_init_state is
when slow_start =>
init_counter <= init_counter + 1;
if (init_counter = x"02") then
ram_init_state <= writing;
init_counter <= (others => '0');
end if;
when writing =>
if (RAM_INIT_COUNTER = s_numInstructions) then
ram_init_state <= finished;
else
init_address <= RAM_INIT_COUNTER;
data_write <= to_stdLogicVector(RAM(to_integer(unsigned(RAM_INIT_COUNTER))));
init_counter <= (init_counter + 1);
if (init_counter = x"04") then
RAM_INIT_COUNTER <= RAM_INIT_COUNTER + 1;
init_counter <= (others => '0');
end if;
end if;
when finished =>
RAM_INIT_COUNTER <= (others => '0');
init_counter <= (others => '0');
write_enable(0) <= '0';
init_ram <= '0';
when others =>
end case;
end if;
end process;
instMem_proc: process (reset)
begin
end process;
end Behavioral;
| gpl-3.0 | 4a53c6f3116b0407e362efa87828418b | 0.506854 | 4.5 | false | false | false | false |
PsiStarPsi/firmware-general | General/rtl/K7SerialInterfaceOut.vhd | 1 | 4,204 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
library UNISIM;
use UNISIM.VComponents.all;
entity K7SerialInterfaceOut is
Generic (
GATE_DELAY_G : time := 1 ns
);
Port (
-- Parallel clock and reset
sstClk : in sl;
sstRst : in sl := '0';
-- Parallel data in
data10bIn : in slv(9 downto 0);
-- Serial clock
sstX5Clk : in sl;
sstX5Rst : in sl := '0';
-- Serial data out
dataOut : out sl
);
end K7SerialInterfaceOut;
architecture Behavioral of K7SerialInterfaceOut is
type StateType is (RESET_S, SEND_AND_READ_S);
type RegType is record
state : StateType;
dataWord : slv(9 downto 0);
bitCount : slv(3 downto 0);
serialDataOutRising : sl;
serialDataOutFalling : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => RESET_S,
dataWord => (others => '0'),
bitCount => (others => '0'),
serialDataOutRising => '0',
serialDataOutFalling => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal fifoEmpty : sl;
signal fifoRdData : slv(9 downto 0);
signal fifoRdValid : sl;
begin
-- Instantiate 10 bit FIFO, written on sstClk, read on sstX5Clk
U_SerializationFifo : entity work.SerializationFifo
PORT MAP (
rst => sstRst,
wr_clk => sstClk,
rd_clk => sstX5Clk,
din => data10bIn,
wr_en => '1',
rd_en => not(fifoEmpty),
dout => fifoRdData,
full => open,
empty => fifoEmpty,
valid => fifoRdValid
);
-- Master state machine (combinatorial)
comb : process(r, fifoRdValid, fifoRdData, sstX5Rst) is
variable v : RegType;
begin
v := r;
-- Resets for pulsed outputs
-- None for now
-- State machine
case(r.state) is
when RESET_S =>
v.bitCount := (others => '0');
if (fifoRdValid = '1') then
v.dataWord := fifoRdData;
v.state := SEND_AND_READ_S;
end if;
when SEND_AND_READ_S =>
v.serialDataOutRising := r.dataWord(r.dataWord'left - conv_integer(r.bitCount));
v.serialDataOutFalling := r.dataWord(r.dataWord'left - conv_integer(r.bitCount)-1);
if (r.bitCount = 8) then
v.bitCount := (others => '0');
v.dataWord := fifoRdData;
else
v.bitCount := r.bitCount + 2;
end if;
when others =>
v.state := RESET_S;
end case;
-- Reset logic
if (sstX5Rst = '1') then
v := REG_INIT_C;
end if;
-- Assignment of combinatorial variable to signal
rin <= v;
end process;
-- Master state machine (sequential)
seq : process (sstX5Clk) is
begin
if (rising_edge(sstX5Clk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
-- ODDR to grab the serial data
-- Template here: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf
-- Documentation here: http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
gclk_to_output : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "ASYNC" -- Reset Type ("ASYNC" or "SYNC")
)
port map (
Q => dataOut, -- 1-bit DDR output
C => sstX5Clk, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => r.serialDataOutRising, -- 1-bit data input (positive edge)
D2 => r.serialDataOutFalling, -- 1-bit data input (negative edge)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
end Behavioral;
| lgpl-2.1 | cdfd43cdd6e45a2d851dd1a5645e3c4a | 0.528544 | 3.777179 | false | false | false | false |
pkerling/ethernet_mac | xilinx/test/test_wrapper_spartan6.vhd | 1 | 2,238 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Convert std_logic_vector ports of test_instance_spartan6 (changed on compilation
-- by the Xilinx toolchain) to std_ulogic_vector
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_types.all;
use work.test_common.all;
entity test_wrapper_spartan6 is
port(
clock_125_i : in std_ulogic;
user_clock_i : in std_ulogic;
reset_i : in std_ulogic;
mii_tx_clk_i : in std_ulogic;
mii_tx_er_o : out std_ulogic;
mii_tx_en_o : out std_ulogic;
mii_txd_o : out std_ulogic_vector(7 downto 0);
mii_rx_clk_i : in std_ulogic;
mii_rx_er_i : in std_ulogic;
mii_rx_dv_i : in std_ulogic;
mii_rxd_i : in std_ulogic_vector(7 downto 0);
gmii_gtx_clk_o : out std_ulogic;
rgmii_tx_ctl_o : out std_ulogic;
rgmii_rx_ctl_i : in std_ulogic;
speed_override_i : in t_ethernet_speed;
test_mode_i : in t_test_mode
);
end entity;
architecture structure of test_wrapper_spartan6 is
signal mii_txd : std_logic_vector(7 downto 0);
signal test_mode : std_logic_vector(1 downto 0);
begin
mii_txd_o <= std_ulogic_vector(mii_txd);
-- Convert to std_logic_vector for the interface
with test_mode_i select test_mode <=
"01" when TEST_LOOPBACK,
"10" when TEST_TX_PADDING,
"00" when others;
test_instance_inst : entity work.test_instance_spartan6
port map(
clock_125_i => clock_125_i,
user_clock_i => user_clock_i,
reset_i => reset_i,
mii_tx_clk_i => mii_tx_clk_i,
mii_tx_er_o => mii_tx_er_o,
mii_tx_en_o => mii_tx_en_o,
mii_txd_o => mii_txd,
mii_rx_clk_i => mii_rx_clk_i,
mii_rx_er_i => mii_rx_er_i,
mii_rx_dv_i => mii_rx_dv_i,
mii_rxd_i => std_logic_vector(mii_rxd_i),
gmii_gtx_clk_o => gmii_gtx_clk_o,
rgmii_tx_ctl_o => rgmii_tx_ctl_o,
rgmii_rx_ctl_i => rgmii_rx_ctl_i,
speed_override_i => std_logic_vector(speed_override_i),
test_mode_i => test_mode
);
end architecture;
| bsd-3-clause | 894c37818156470f589f6911e1b9d882 | 0.618409 | 2.651659 | false | true | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii/niosii/niosii_inst.vhd | 1 | 730 | component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
pio_0_external_connection_export : out std_logic_vector(7 downto 0) -- export
);
end component niosii;
u0 : component niosii
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export -- pio_0_external_connection.export
);
| mit | c8265d51050a890c00c509967b7c7fbd | 0.463014 | 3.882979 | false | false | false | false |
Dragonturtle/SHERPA | HDL/SHERPA/sherpa_rxtx.vhdl | 1 | 6,798 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sherpa_rxtx is
port(
reset_in : in std_logic;
-- Clock interface --------------------------------------------------------------------------
usb_clk_in : in std_logic;
adc_clk_in : in std_logic;
dac_clk_in : in std_logic;
sync_clk_out : out std_logic;
-- DVR interface -----------------------------------------------------------------------------
data_out : out std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
valid_out : out std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
ready_in : in std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- Peripheral interface ----------------------------------------------------------------------
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anode_out : out std_logic_vector(3 downto 0); -- seven-segment display anodes (one for each digit)
led_out : out std_logic_vector(7 downto 0); -- eight LEDs
sw_in : in std_logic_vector(7 downto 0); -- eight switches
RX_in : in std_logic_vector(7 downto 0);
TX_out : out std_logic_vector(7 downto 0) := "00000000";
dacCW_out : out std_logic;
RXTX_out : out std_logic
);
end entity;
architecture rtl of sherpa_rxtx is
alias rst : std_logic is reset_in;
-- Flags for display on the 7-seg decimal points
signal flags : std_logic_vector(3 downto 0);
-- USB FIFO
signal fifoCount : std_logic_vector(14 downto 0);
signal fifoInputData : std_logic_vector(7 downto 0); -- producer: data
signal fifoInputValid : std_logic; -- valid flag
signal fifoInputReady : std_logic; -- ready flag
signal fifoOutputData : std_logic_vector(7 downto 0); -- consumer: data
signal fifoOutputValid : std_logic; -- valid flag
signal fifoOutputReady : std_logic; -- ready flag
-- Control states
type activityState_type is (initialize, idle, active);
type functionState_type is (transmit, receive);
signal activityState : activityState_type := initialize;
signal functionState : functionState_type := receive;
-- Data transfer
signal transmitDataReady : std_logic;
signal receiveDataReady : std_logic;
signal sync_clk : std_logic;
signal dataCount : std_logic_vector(7 downto 0) := (others => '0');
signal dataVector : std_logic_vector(98 downto 0) := (others => '1');
signal dataBit : std_logic := '0';
-- Data compression
signal shiftValue : std_logic_vector(7 downto 0) := (others => '0');
signal shiftValid : std_logic := '0';
signal adc_data : std_logic;
signal syncFlag : std_logic := '0';
signal counter : std_logic_vector(15 downto 0) := (others => '0');
signal dacControl : std_logic_vector(7 downto 0) := "01101000";
signal prnSignal : std_logic_vector(7 downto 0) := (others => '0');
signal SSCount : std_logic_vector(15 downto 0) := (others => '0');
begin
--------------------------------------
--- Generate synchronization clock ---
--------------------------------------
clock_syncer : entity work.clock_syncer
port map (
dac_clk_in => dac_clk_in,
adc_clk_in => adc_clk_in,
reset_in => rst,
sync_out => sync_clk
);
sync_clk_out <= sync_clk;
-------------------------------------------------------
--- Toggle between RX and TX at specified intervals ---
-------------------------------------------------------
transmitDataReady <= '1' when activityState = active and functionState = transmit else '0';
receiveDataReady <= '1' when activityState = active and functionState = receive else '0';
dataBit <= dataVector(to_integer(unsigned(dataCount)));
TX_out <= dacControl when activityState = initialize else prnSignal;
RXTX_out <= '1' when activityState = active and functionState = transmit else '0';
functionState <= transmit when sw_in(7) = '1' else receive;
state_machine : process(rst, sync_clk)
begin
if (rst = '1') then
dataCount <= (others => '0');
activityState <= initialize;
-- functionState <= initialize;
syncFlag <= '0';
elsif ( rising_edge(sync_clk) ) then
case activityState is
when initialize =>
if (to_integer(unsigned(dataCount)) = 2) then
dataCount <= (others => '0');
activityState <= idle;
--functionState <= transmit;
dacCW_out <= '1';
else
dacCW_out <= '0';
dataCount <= std_logic_vector(unsigned(dataCount) + 1);
end if;
when active =>
syncFlag <= not syncFlag;
if (to_integer(unsigned(dataCount)) >= 98) then
dataCount <= (others => '0');
--activityState <= idle;
else
dataCount <= std_logic_vector(unsigned(dataCount) + 1);
end if;
when idle =>
if (functionState = transmit) then
--functionState <= receive;
else
--functionState <= transmit;
end if;
activityState <= active;
end case;
end if;
end process;
-------------------------
--- Generate PRN code ---
-------------------------
prn_code_generator : entity work.prn_code_generator
generic map (
idx1 => 1,
idx2 => 5
) port map (
enable_in => transmitDataReady,
data_in => dataBit,
clock_in => dac_clk_in,
I_out => prnSignal,
Q_out => open
);
-------------------------
--- Write to USB FIFO ---
-------------------------
fifoInputValid <= '1' when receiveDataReady = '1' else '0';
fifoOutputReady <= '1' when ready_in = '1' else '0';
valid_out <= '0' when fifoOutputValid = '0' else '1';
data_out <= fifoOutputData;
read_fifo : entity work.fifo_wrapper
port map(
wr_clk_in => adc_clk_in,
rd_clk_in => usb_clk_in,
depth_out => fifoCount,
-- Production end
inputData_in => RX_in, --fifoInputData,
inputValid_in => fifoInputValid,
inputReady_out => fifoInputReady,
-- Consumption end
outputData_out => fifoOutputData,
outputValid_out => fifoOutputValid,
outputReady_in => fifoOutputReady
);
--------------------------
--- Handle LED Display ---
--------------------------
SSCount(6 downto 0) <= sw_in(6 downto 0);
SSCount(8) <= '1' when functionState = transmit else '0';
flags <= '0' & sync_clk & '0' & sync_clk;
seven_seg : entity work.seven_seg
port map(
clk_in => adc_clk_in,
data_in => SSCount,
dots_in => flags,
segs_out => sseg_out,
anodes_out => anode_out
);
end architecture;
| gpl-3.0 | 3dc9df4f8e389a2de5ef5a1e68068345 | 0.561636 | 3.433333 | false | false | false | false |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/src/tbd_rr_base.vhd | 1 | 8,452 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DSP-Crowd project --
-- https://www.dsp-crowd.com --
-- --
-- Author(s): --
-- - Johannes Natter, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2017 Authors and www.dsp-crowd.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tbd_rr_base is
generic
(
use_sdram_pll : std_ulogic := '1';
num_gpios : natural := 64
);
port
(
clock_50mhz : in std_ulogic;
keys : in std_ulogic_vector(1 downto 0);
switches : in std_ulogic_vector(3 downto 0);
leds : out std_ulogic_vector(7 downto 0);
spi_cs : in std_ulogic_vector(1 downto 0);
spi_clk : in std_ulogic;
spi_mosi : in std_ulogic;
spi_miso : out std_ulogic;
spi_epcs_cs : out std_ulogic;
spi_epcs_clk : out std_ulogic;
spi_epcs_mosi : out std_ulogic;
spi_epcs_miso : in std_ulogic;
arReconf : in std_ulogic;
gpios : inout std_logic_vector(0 to num_gpios - 1)
);
end tbd_rr_base;
architecture rtl of tbd_rr_base is
signal reset_done : std_ulogic := '0';
signal n_reset_async : std_logic;
signal inputs_unsynced : std_ulogic_vector(switches'length downto 0);
signal inputs_synced : std_ulogic_vector(inputs_unsynced'range);
signal inputs_synced_debounced : std_ulogic_vector(inputs_synced'range);
signal key_0_synced_debounced : std_ulogic;
signal switches_synced_debounced : std_ulogic_vector(switches'range);
signal spi_unsynced : std_ulogic_vector(2 downto 0);
signal spi_synced : std_ulogic_vector(2 downto 0);
signal spi_cs_user_synced : std_ulogic;
signal spi_clk_synced : std_ulogic;
signal spi_mosi_synced : std_ulogic;
signal spi_slave_miso : std_ulogic;
signal spi_slave_data : std_ulogic_vector(7 downto 0);
signal spi_slave_data_is_id : std_ulogic;
signal spi_slave_data_valid : std_ulogic;
signal spi_slave_input_state : std_ulogic_vector(0 to num_gpios - 1);
signal spi_slave_input_state_valid : std_ulogic_vector(0 to num_gpios - 1);
signal spi_slave_cmd_done : std_ulogic_vector(0 to num_gpios - 1);
signal spi_slave_input_state_res : std_ulogic_vector(0 to num_gpios - 1);
signal spi_slave_input_state_valid_res : std_ulogic_vector(0 to num_gpios - 1);
signal spi_slave_cmd_done_res : std_ulogic_vector(0 to num_gpios - 1);
signal gpio_in : std_logic_vector(0 to num_gpios - 1);
signal gpio_out : std_logic_vector(0 to num_gpios - 1);
signal gpio_en : std_logic_vector(0 to num_gpios - 1);
begin
-- Reconfiguration unit
reconfUnit: entity work.altremotePulsed(rtl)
port map
(
clock => clock_50mhz,
nResetAsync => n_reset_async,
reconf => arReconf
);
-- Give epcs64 signals to external user
-- No need to synchronize. Signals are not used within system clock
spi_epcs_cs <= spi_cs(0);
spi_epcs_clk <= spi_clk;
spi_epcs_mosi <= spi_mosi;
-- Important: MISO must not drive signal if epcs64 is not selected
spi_miso <= spi_epcs_miso when spi_cs(0) = '0' else
spi_slave_miso when spi_cs_user_synced = '0' else 'Z';
-- Synchronize inputs
inputs_unsynced <= switches & keys(0);
key_sync: entity work.input_sync(rtl)
generic map
(
num_inputs => inputs_unsynced'length,
num_sync_stages => 1
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
unsynced_inputs => inputs_unsynced,
synced_outputs => inputs_synced
);
-- Debounce inputs
key_debounce: entity work.input_debounce(rtl)
generic map
(
num_inputs => inputs_synced'length
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
synced_inputs => inputs_synced,
debounced_outputs => inputs_synced_debounced
);
key_0_synced_debounced <= inputs_synced_debounced(0);
switches_synced_debounced <= inputs_synced_debounced(inputs_synced_debounced'high downto 1);
-- Synchronize SPI
spi_unsynced <= spi_cs(1) & spi_clk & spi_mosi;
spi_sync: entity work.input_sync(rtl)
generic map
(
num_inputs => spi_unsynced'length,
num_sync_stages => 2
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
unsynced_inputs => spi_unsynced,
synced_outputs => spi_synced
);
spi_cs_user_synced <= spi_synced(2);
spi_clk_synced <= spi_synced(1);
spi_mosi_synced <= spi_synced(0);
-- Hardware-is-alive-LED
hardware_is_alive_led: entity work.frequencyDivider(rtl)
generic map
(
divideBy => 25E7
)
port map
(
clock => clock_50mhz,
nResetAsync => n_reset_async,
output => leds(0)
);
leds(7 downto 1) <= (others => '0');
-- SPI-Slave
spislave: entity work.spi_slave(rtl)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
spi_cs => spi_cs_user_synced,
spi_clk => spi_clk_synced,
spi_mosi => spi_mosi_synced,
spi_miso => spi_slave_miso,
data => spi_slave_data,
data_is_id => spi_slave_data_is_id,
data_valid => spi_slave_data_valid,
input_state => spi_slave_input_state_res(0),
input_state_valid => spi_slave_input_state_valid_res(0),
cmd_done => spi_slave_cmd_done_res(0)
);
-- GPIOs
gpio_ext_all: for i in 0 to num_gpios - 1 generate
gpio_ext_n: entity work.gpio_ext(rtl)
generic map
(
my_id => i
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
spi_cs => spi_cs_user_synced,
data => spi_slave_data,
data_is_id => spi_slave_data_is_id,
data_valid => spi_slave_data_valid,
input_state => spi_slave_input_state(i),
input_state_valid => spi_slave_input_state_valid(i),
cmd_done => spi_slave_cmd_done(i),
gpio_in => gpio_in(i),
gpio_out => gpio_out(i),
gpio_en => gpio_en(i)
);
gpios(i) <= gpio_out(i) when gpio_en(i) = '1' else 'Z';
end generate;
gpio_in <= gpios;
or_blocks: for i in 0 to num_gpios - 2 generate
spi_slave_input_state_res (i) <= spi_slave_input_state_res (i + 1) or spi_slave_input_state (i);
spi_slave_input_state_valid_res (i) <= spi_slave_input_state_valid_res (i + 1) or spi_slave_input_state_valid (i);
spi_slave_cmd_done_res (i) <= spi_slave_cmd_done_res (i + 1) or spi_slave_cmd_done (i);
end generate;
spi_slave_input_state_res(num_gpios - 1) <= '0';
spi_slave_input_state_valid_res(num_gpios - 1) <= '0';
spi_slave_cmd_done_res(num_gpios - 1) <= '0';
-- Reset
proc_reset: process(clock_50mhz)
begin
if clock_50mhz'event and clock_50mhz = '1' then
reset_done <= '1';
end if;
end process;
n_reset_async <= reset_done and keys(1);
end architecture rtl;
| gpl-2.0 | 95b310dc3b095920f308c8cd4b1f2be4 | 0.557501 | 3.113076 | false | false | false | false |
PsiStarPsi/firmware-general | General/rtl/ByteLink.vhd | 1 | 6,829 | ---------------------------------------------------------------------------------
-- Title : Byte Link
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : ByteLink.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Basic 1-byte interface link, using 8b10b protocol
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
entity ByteLink is
generic (
ALIGN_CYCLES_G : integer := 20;
GATE_DELAY_G : time := 1 ns
);
port (
-- User clock and reset
clk : in sl;
rst : in sl := '0';
-- Incoming encoded data
rxData10b : in slv(9 downto 0);
-- Received true data
rxData8b : out slv(7 downto 0);
rxData8bValid : out sl;
-- Align signal
aligned : out sl;
-- Outgoing true data
txData8b : in slv(7 downto 0);
txData8bValid : in sl;
-- Transmitted encoded data
txData10b : out slv(9 downto 0)
);
end ByteLink;
-- Define architecture
architecture rtl of ByteLink is
type StateType is (RESET_S, TRAINING_S, LOCKED_S);
type RegType is record
state : StateType;
aligned : sl;
rxData10b : slv(9 downto 0);
rxData8b : slv(7 downto 0);
rxData8bValid : sl;
txData8b : slv(7 downto 0);
txDataK : sl;
txData10b : slv(9 downto 0);
alignCnt : slv(31 downto 0);
end record RegType;
constant REG_INIT_C : RegType := (
state => RESET_S,
aligned => '0',
rxData10b => (others => '0'),
rxData8b => (others => '0'),
rxData8bValid => '0',
txData8b => (others => '0'),
txDataK => '0',
txData10b => (others => '0'),
alignCnt => (others => '0')
);
signal rxDataByte : slv(7 downto 0);
signal rxDataK : sl;
signal rxDisp : sl;
signal rxCodeErr : sl;
signal rxDispErr : sl;
signal txData10 : slv(9 downto 0);
signal txDisp : sl;
signal inputTxData8b : slv(7 downto 0);
signal inputTxData8bValid : sl;
signal inputRxData10b : slv(9 downto 0);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- Comma character definitions
constant K_COM_ALIGN_C : slv(7 downto 0) := x"3C"; --(K28.1)
constant K_COM_ZERO_C : slv(7 downto 0) := x"BC"; -- (K28.5)
-- constant K28_7_C : slv(7 downto 0) := x"FC";
constant K_CHAR : sl := '1';
constant D_CHAR : sl := '0';
begin
-- Register inputs
process(clk) begin
if rising_edge(clk) then
inputRxData10b <= rxData10b;
inputTxData8b <= txData8b;
inputTxData8bValid <= txData8bValid;
end if;
end process;
-- Instantiate 8b10b encoder and decoder
U_Encode8b10b : entity work.Encode8b10b
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
clk => clk,
rst => rst,
dataIn => r.txData8b,
dataKIn => r.txDataK,
dispIn => txDisp,
dataOut => txData10,
dispOut => txDisp
);
U_Decode8b10b : entity work.Decode8b10b
generic map (
GATE_DELAY_G => GATE_DELAY_G
)
port map (
clk => clk,
rst => rst,
dataIn => inputRxData10b,
dispIn => rxDisp,
dataOut => rxDataByte,
dataKOut => rxDataK,
dispOut => rxDisp,
codeErr => rxCodeErr,
dispErr => rxDispErr
);
-- Master state machine (combinatorial)
comb : process(rst,r,
rxDataByte,rxCodeErr,rxDispErr,rxDataK,
txData10,inputTxData8bValid,inputTxData8b) is
variable v : RegType;
begin
v := r;
-- Pipeline txData10b
v.txData10b := txData10;
-- Resets for pulsed outputs
v.rxData8bValid := '0';
-- State machine
case(r.state) is
when RESET_S =>
v.alignCnt := (others => '0');
v.txData8b := K_COM_ALIGN_C;
v.txDataK := K_CHAR;
v.aligned := '0';
v.state := TRAINING_S;
when TRAINING_S =>
v.txData8b := K_COM_ALIGN_C;
v.txDataK := K_CHAR;
if rxDataK = '0' or (rxDataByte /= K_COM_ALIGN_C and rxDataByte /= K_COM_ZERO_C) or
rxCodeErr = '1' or rxDispErr = '1' then
v.alignCnt := (others => '0');
else
v.alignCnt := r.alignCnt + 1;
end if;
if r.alignCnt = ALIGN_CYCLES_G then
v.alignCnt := (others => '0');
v.state := LOCKED_S;
end if;
when LOCKED_S =>
v.aligned := '1';
-- Start over if we see an undefined K_CHAR or code/disparity errors
if (rxDataK = '1' and (rxDataByte /= K_COM_ALIGN_C and rxDataByte /= K_COM_ZERO_C)) or
rxCodeErr = '1' or rxDispErr = '1' then
v.state := RESET_S;
end if;
-- Otherwise, send data if we have it, or K_ZERO_C otherwise
if inputTxData8bValid = '0' then
v.txData8b := K_COM_ZERO_C;
v.txDataK := K_CHAR;
else
v.txData8b := inputTxData8b;
v.txDataK := D_CHAR;
end if;
-- Handle received data
v.rxData8bValid := not(rxDataK);
v.rxData8b := rxDataByte;
when others =>
v.state := RESET_S;
end case;
-- Reset logic
if (rst = '1') then
v := REG_INIT_C;
end if;
-- Assignment of combinatorial variable to signal
rin <= v;
-- Outputs to ports
rxData8b <= r.rxData8b;
rxData8bValid <= r.rxData8bValid;
aligned <= r.aligned;
txData10b <= r.txData10b;
end process;
-- Master state machine (sequential)
seq : process (clk) is
begin
if (rising_edge(clk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | 53fb05b080a0e593893bbe2d41b0ab6f | 0.486455 | 3.866931 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_sdram/niosii/synthesis/niosii.vhd | 2 | 63,410 | -- niosii.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii is
port (
clk_clk : in std_logic := '0'; -- clk.clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- pio_0_external_connection.export
reset_reset_n : in std_logic := '0' -- reset.reset_n
);
end entity niosii;
architecture rtl of niosii is
component niosii_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c1 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component niosii_altpll_0;
component niosii_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component niosii_jtag_uart_0;
component niosii_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(17 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
d_readdatavalid : in std_logic := 'X'; -- readdatavalid
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(17 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
i_readdatavalid : in std_logic := 'X'; -- readdatavalid
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component niosii_nios2_gen2_0;
component niosii_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component niosii_onchip_memory2_0;
component niosii_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component niosii_pio_0;
component niosii_mm_interconnect_0 is
port (
altpll_0_c0_clk : in std_logic := 'X'; -- clk
altpll_0_c1_clk : in std_logic := 'X'; -- clk
clk_0_clk_clk : in std_logic := 'X'; -- clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
pio_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_data_master_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_readdatavalid : out std_logic; -- readdatavalid
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_instruction_master_readdatavalid : out std_logic; -- readdatavalid
altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address
altpll_0_pll_slave_write : out std_logic; -- write
altpll_0_pll_slave_read : out std_logic; -- read
altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_address : out std_logic_vector(0 downto 0); -- address
jtag_uart_0_avalon_jtag_slave_write : out std_logic; -- write
jtag_uart_0_avalon_jtag_slave_read : out std_logic; -- read
jtag_uart_0_avalon_jtag_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_uart_0_avalon_jtag_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(13 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic -- chipselect
);
end component niosii_mm_interconnect_0;
component niosii_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component niosii_irq_mapper;
component altera_irq_clock_crosser is
generic (
IRQ_WIDTH : integer := 1
);
port (
receiver_clk : in std_logic := 'X'; -- clk
sender_clk : in std_logic := 'X'; -- clk
receiver_reset : in std_logic := 'X'; -- reset
sender_reset : in std_logic := 'X'; -- reset
receiver_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
sender_irq : out std_logic_vector(0 downto 0) -- irq
);
end component altera_irq_clock_crosser;
component niosii_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller;
component niosii_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller_001;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [irq_mapper:clk, irq_synchronizer:sender_clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_memory2_0:clk, rst_controller_001:clk]
signal altpll_0_c1_clk : std_logic; -- altpll_0:c1 -> [mm_interconnect_0:altpll_0_c1_clk, pio_0:clk, rst_controller_002:clk]
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(17 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_readdatavalid : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_readdatavalid -> nios2_gen2_0:d_readdatavalid
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(17 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal nios2_gen2_0_instruction_master_readdatavalid : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdatavalid -> nios2_gen2_0:i_readdatavalid
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata
signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address
signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read
signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write
signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(13 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal irq_mapper_receiver0_irq : std_logic; -- irq_synchronizer:sender_irq -> irq_mapper:receiver0_irq
signal irq_synchronizer_receiver_irq : std_logic_vector(0 downto 0); -- jtag_uart_0:av_irq -> irq_synchronizer:receiver_irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, irq_synchronizer:receiver_reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset, rst_controller_reset_out_reset:in]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [irq_mapper:reset, irq_synchronizer:sender_reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_001_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal rst_controller_002_reset_out_reset : std_logic; -- rst_controller_002:reset_out -> [mm_interconnect_0:pio_0_reset_reset_bridge_in_reset_reset, rst_controller_002_reset_out_reset:in]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0]
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:inv -> jtag_uart_0:av_read_n
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:inv -> jtag_uart_0:av_write_n
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> jtag_uart_0:rst_n
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> nios2_gen2_0:reset_n
signal rst_controller_002_reset_out_reset_ports_inv : std_logic; -- rst_controller_002_reset_out_reset:inv -> pio_0:reset_n
begin
altpll_0 : component niosii_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset
read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read
write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address
readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
c1 => altpll_0_c1_clk, -- c1.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
jtag_uart_0 : component niosii_jtag_uart_0
port map (
clk => clk_clk, -- clk.clk
rst_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- avalon_jtag_slave.chipselect
av_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address(0), -- .address
av_read_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv, -- .read_n
av_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
av_write_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv, -- .write_n
av_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
av_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
av_irq => irq_synchronizer_receiver_irq(0) -- irq.irq
);
nios2_gen2_0 : component niosii_nios2_gen2_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
d_readdatavalid => nios2_gen2_0_data_master_readdatavalid, -- .readdatavalid
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
i_readdatavalid => nios2_gen2_0_instruction_master_readdatavalid, -- .readdatavalid
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component niosii_onchip_memory2_0
port map (
clk => altpll_0_c0_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_001_reset_out_reset, -- reset1.reset
reset_req => rst_controller_001_reset_out_reset_req -- .reset_req
);
pio_0 : component niosii_pio_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
out_port => pio_0_external_connection_export -- external_connection.export
);
mm_interconnect_0 : component niosii_mm_interconnect_0
port map (
altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk
altpll_0_c1_clk => altpll_0_c1_clk, -- altpll_0_c1.clk
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
pio_0_reset_reset_bridge_in_reset_reset => rst_controller_002_reset_out_reset, -- pio_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_readdatavalid => nios2_gen2_0_data_master_readdatavalid, -- .readdatavalid
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
nios2_gen2_0_instruction_master_readdatavalid => nios2_gen2_0_instruction_master_readdatavalid, -- .readdatavalid
altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address
altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read
altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address, -- jtag_uart_0_avalon_jtag_slave.address
jtag_uart_0_avalon_jtag_slave_write => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write, -- .write
jtag_uart_0_avalon_jtag_slave_read => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read, -- .read
jtag_uart_0_avalon_jtag_slave_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect -- .chipselect
);
irq_mapper : component niosii_irq_mapper
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
irq_synchronizer : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => clk_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_001_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver0_irq -- sender.irq
);
rst_controller : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component niosii_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_002 : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c1_clk, -- clk.clk
reset_out => rst_controller_002_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
rst_controller_002_reset_out_reset_ports_inv <= not rst_controller_002_reset_out_reset;
end architecture rtl; -- of niosii
| mit | 2a18143b6800719e4daa36a5861ff9a2 | 0.467986 | 3.725617 | false | false | false | false |
PsiStarPsi/firmware-general | Transceivers/S6/GtpS6Tile.vhd | 1 | 46,090 | -------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.11
-- \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
-- / / Filename : GtpS6Tile.vhd
-- /___/ /\
-- \ \ / \
-- \___\/\___\
--
--
-- Module GtpS6Tile (a GTPA1_DUAL Tile Wrapper)
-- Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
--
--
-- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity GtpS6Tile is
generic
(
-- Simulation attributes
TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
TILE_CLK25_DIVIDER_0 : integer := 5;
TILE_CLK25_DIVIDER_1 : integer := 5;
TILE_PLL_DIVSEL_FB_0 : integer := 2;
TILE_PLL_DIVSEL_FB_1 : integer := 2;
TILE_PLL_DIVSEL_REF_0 : integer := 1;
TILE_PLL_DIVSEL_REF_1 : integer := 1;
TILE_SIM_REFCLK0_SOURCE : bit_vector:= "000";
TILE_SIM_REFCLK1_SOURCE : bit_vector:= "000";
--
TILE_PLL_SOURCE_0 : string := "PLL0";
TILE_PLL_SOURCE_1 : string := "PLL1"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0_IN : in std_logic_vector(2 downto 0);
LOOPBACK1_IN : in std_logic_vector(2 downto 0);
--------------------------------- PLL Ports --------------------------------
CLK00_IN : in std_logic;
CLK01_IN : in std_logic;
CLK10_IN : in std_logic;
CLK11_IN : in std_logic;
GCLK00_IN : in std_logic;
GCLK01_IN : in std_logic;
GCLK10_IN : in std_logic;
GCLK11_IN : in std_logic;
CLKINEAST0_IN : in std_logic;
CLKINEAST1_IN : in std_logic;
CLKINWEST0_IN : in std_logic;
CLKINWEST1_IN : in std_logic;
GTPRESET0_IN : in std_logic;
GTPRESET1_IN : in std_logic;
TXRESET0_IN : in std_logic;
TXRESET1_IN : in std_logic;
RXRESET0_IN : in std_logic;
RXRESET1_IN : in std_logic;
PLLLKDET0_OUT : out std_logic;
PLLLKDET1_OUT : out std_logic;
REFSELDYPLL0_IN : in std_logic_vector(2 downto 0);
REFSELDYPLL1_IN : in std_logic_vector(2 downto 0);
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0_OUT : out std_logic_vector(1 downto 0);
RXCHARISCOMMA1_OUT : out std_logic_vector(1 downto 0);
RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
RXRUNDISP0_OUT : out std_logic_vector(1 downto 0);
RXRUNDISP1_OUT : out std_logic_vector(1 downto 0);
--------------- Receive Ports - RX Buffer and Phase Alignment --------------
RXBUFRESET0_IN : in std_logic;
RXBUFRESET1_IN : in std_logic;
RXBUFSTATUS0_OUT : out std_logic_vector(2 downto 0);
RXBUFSTATUS1_OUT : out std_logic_vector(2 downto 0);
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0_OUT : out std_logic;
RXBYTEISALIGNED1_OUT : out std_logic;
RXENMCOMMAALIGN0_IN : in std_logic;
RXENMCOMMAALIGN1_IN : in std_logic;
RXENPCOMMAALIGN0_IN : in std_logic;
RXENPCOMMAALIGN1_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0_OUT : out std_logic_vector(15 downto 0);
RXDATA1_OUT : out std_logic_vector(15 downto 0);
RXUSRCLK0_IN : in std_logic;
RXUSRCLK1_IN : in std_logic;
RXUSRCLK20_IN : in std_logic;
RXUSRCLK21_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXN0_IN : in std_logic;
RXN1_IN : in std_logic;
RXP0_IN : in std_logic;
RXP1_IN : in std_logic;
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXCHARDISPMODE0_IN : in std_logic_vector(1 downto 0);
TXCHARDISPMODE1_IN : in std_logic_vector(1 downto 0);
TXCHARDISPVAL0_IN : in std_logic_vector(1 downto 0);
TXCHARDISPVAL1_IN : in std_logic_vector(1 downto 0);
TXCHARISK0_IN : in std_logic_vector(1 downto 0);
TXCHARISK1_IN : in std_logic_vector(1 downto 0);
TXRUNDISP0_OUT : out std_logic_vector(1 downto 0);
TXRUNDISP1_OUT : out std_logic_vector(1 downto 0);
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0_OUT : out std_logic_vector(1 downto 0);
TXBUFSTATUS1_OUT : out std_logic_vector(1 downto 0);
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0_IN : in std_logic_vector(15 downto 0);
TXDATA1_IN : in std_logic_vector(15 downto 0);
TXOUTCLK0_OUT : out std_logic;
TXOUTCLK1_OUT : out std_logic;
TXUSRCLK0_IN : in std_logic;
TXUSRCLK1_IN : in std_logic;
TXUSRCLK20_IN : in std_logic;
TXUSRCLK21_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXN0_OUT : out std_logic;
TXN1_OUT : out std_logic;
TXP0_OUT : out std_logic;
TXP1_OUT : out std_logic
);
end GtpS6Tile;
architecture RTL of GtpS6Tile is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
-- RX Datapath signals
signal rxdata0_i : std_logic_vector(31 downto 0);
signal rxchariscomma0_float_i : std_logic_vector(1 downto 0);
signal rxcharisk0_float_i : std_logic_vector(1 downto 0);
signal rxdisperr0_float_i : std_logic_vector(1 downto 0);
signal rxnotintable0_float_i : std_logic_vector(1 downto 0);
signal rxrundisp0_float_i : std_logic_vector(1 downto 0);
-- TX Datapath signals
signal txdata0_i : std_logic_vector(31 downto 0);
signal txkerr0_float_i : std_logic_vector(1 downto 0);
signal txrundisp0_float_i : std_logic_vector(1 downto 0);
-- RX Datapath signals
signal rxdata1_i : std_logic_vector(31 downto 0);
signal rxchariscomma1_float_i : std_logic_vector(1 downto 0);
signal rxcharisk1_float_i : std_logic_vector(1 downto 0);
signal rxdisperr1_float_i : std_logic_vector(1 downto 0);
signal rxnotintable1_float_i : std_logic_vector(1 downto 0);
signal rxrundisp1_float_i : std_logic_vector(1 downto 0);
-- TX Datapath signals
signal txdata1_i : std_logic_vector(31 downto 0);
signal txkerr1_float_i : std_logic_vector(1 downto 0);
signal txrundisp1_float_i : std_logic_vector(1 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i <= (others => '0');
tied_to_vcc_i <= '1';
tied_to_vcc_vec_i <= (others => '1');
------------------- GTP Datapath byte mapping -----------------
-- The GTP provides little endian data (first byte received on RXDATA(7 downto 0))
RXDATA0_OUT <= rxdata0_i(15 downto 0);
txdata0_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA0_IN);
-- The GTP provides little endian data (first byte received on RXDATA(7 downto 0))
RXDATA1_OUT <= rxdata1_i(15 downto 0);
txdata1_i <= (tied_to_ground_vec_i(15 downto 0) & TXDATA1_IN);
----------------------------- GTPA1_DUAL Instance --------------------------
gtpa1_dual_i:GTPA1_DUAL
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (TRUE),
SIM_TX_ELEC_IDLE_LEVEL => ("Z"),
SIM_VERSION => ("2.0"),
SIM_REFCLK0_SOURCE => (TILE_SIM_REFCLK0_SOURCE),
SIM_REFCLK1_SOURCE => (TILE_SIM_REFCLK1_SOURCE),
SIM_GTPRESET_SPEEDUP => (TILE_SIM_GTPRESET_SPEEDUP),
CLK25_DIVIDER_0 => (TILE_CLK25_DIVIDER_0),
CLK25_DIVIDER_1 => (TILE_CLK25_DIVIDER_1),
PLL_DIVSEL_FB_0 => (TILE_PLL_DIVSEL_FB_0),
PLL_DIVSEL_FB_1 => (TILE_PLL_DIVSEL_FB_1),
PLL_DIVSEL_REF_0 => (TILE_PLL_DIVSEL_REF_0),
PLL_DIVSEL_REF_1 => (TILE_PLL_DIVSEL_REF_1),
--PLL Attributes
CLKINDC_B_0 => (TRUE),
CLKRCV_TRST_0 => (TRUE),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_RXDIVSEL_OUT_0 => (2),
PLL_SATA_0 => (FALSE),
PLL_SOURCE_0 => (TILE_PLL_SOURCE_0),
PLL_TXDIVSEL_OUT_0 => (2),
PLLLKDET_CFG_0 => ("111"),
--
CLKINDC_B_1 => (TRUE),
CLKRCV_TRST_1 => (TRUE),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_RXDIVSEL_OUT_1 => (2),
PLL_SATA_1 => (FALSE),
PLL_SOURCE_1 => (TILE_PLL_SOURCE_1),
PLL_TXDIVSEL_OUT_1 => (2),
PLLLKDET_CFG_1 => ("111"),
PMA_COM_CFG_EAST => (x"000008000"),
PMA_COM_CFG_WEST => (x"00000a000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
--TX Interface Attributes
CLK_OUT_GTP_SEL_0 => ("TXOUTCLK0"),
TX_TDCC_CFG_0 => ("00"),
CLK_OUT_GTP_SEL_1 => ("TXOUTCLK1"),
TX_TDCC_CFG_1 => ("00"),
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"00082"),
TX_BUFFER_USE_0 => (TRUE),
TX_XCLK_SEL_0 => ("TXOUT"),
TXRX_INVERT_0 => ("011"),
PMA_TX_CFG_1 => (x"00082"),
TX_BUFFER_USE_1 => (TRUE),
TX_XCLK_SEL_1 => ("TXOUT"),
TXRX_INVERT_1 => ("011"),
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => ("00"),
TX_IDLE_DELAY_0 => ("011"),
CM_TRIM_1 => ("00"),
TX_IDLE_DELAY_1 => ("011"),
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => ("1111"),
COM_BURST_VAL_1 => ("1111"),
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (TRUE),
OOBDETECT_THRESHOLD_0 => ("110"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce049"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (FALSE),
RCV_TERM_VTTRX_0 => (FALSE),
RXEQ_CFG_0 => ("01111011"),
TERMINATION_CTRL_0 => ("10100"),
TERMINATION_OVRD_0 => (FALSE),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (TRUE),
OOBDETECT_THRESHOLD_1 => ("110"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce049"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (FALSE),
RCV_TERM_VTTRX_1 => (FALSE),
RXEQ_CFG_1 => ("01111011"),
TERMINATION_CTRL_1 => ("10100"),
TERMINATION_OVRD_1 => (FALSE),
TX_DETECT_RX_CFG_1 => (x"1832"),
--PRBS Detection Attributes
RXPRBSERR_LOOPBACK_0 => ('0'),
RXPRBSERR_LOOPBACK_1 => ('0'),
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (2),
COMMA_10B_ENABLE_0 => ("0001111111"),
DEC_MCOMMA_DETECT_0 => (TRUE),
DEC_PCOMMA_DETECT_0 => (TRUE),
DEC_VALID_COMMA_ONLY_0 => (FALSE),
MCOMMA_10B_VALUE_0 => ("1010000011"),
MCOMMA_DETECT_0 => (TRUE),
PCOMMA_10B_VALUE_0 => ("0101111100"),
PCOMMA_DETECT_0 => (TRUE),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (2),
COMMA_10B_ENABLE_1 => ("0001111111"),
DEC_MCOMMA_DETECT_1 => (TRUE),
DEC_PCOMMA_DETECT_1 => (TRUE),
DEC_VALID_COMMA_ONLY_1 => (FALSE),
MCOMMA_10B_VALUE_1 => ("1010000011"),
MCOMMA_DETECT_1 => (TRUE),
PCOMMA_10B_VALUE_1 => ("0101111100"),
PCOMMA_DETECT_1 => (TRUE),
RX_SLIDE_MODE_1 => ("PCS"),
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (FALSE),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (FALSE),
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (TRUE),
RX_EN_IDLE_RESET_BUF_0 => (TRUE),
RX_IDLE_HI_CNT_0 => ("1000"),
RX_IDLE_LO_CNT_0 => ("0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (TRUE),
RX_EN_IDLE_RESET_BUF_1 => (TRUE),
RX_IDLE_HI_CNT_1 => ("1000"),
RX_IDLE_LO_CNT_1 => ("0000"),
RX_XCLK_SEL_1 => ("RXREC"),
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (2),
CLK_COR_DET_LEN_0 => (2),
CLK_COR_INSERT_IDLE_FLAG_0 => (FALSE),
CLK_COR_KEEP_IDLE_0 => (FALSE),
CLK_COR_MAX_LAT_0 => (18),
CLK_COR_MIN_LAT_0 => (16),
CLK_COR_PRECEDENCE_0 => (TRUE),
CLK_COR_REPEAT_WAIT_0 => (0),
CLK_COR_SEQ_1_1_0 => ("0110111100"),
CLK_COR_SEQ_1_2_0 => ("0001010000"),
CLK_COR_SEQ_1_3_0 => ("0000000000"),
CLK_COR_SEQ_1_4_0 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_0 => ("0011"),
CLK_COR_SEQ_2_1_0 => ("0110111100"),
CLK_COR_SEQ_2_2_0 => ("0010110101"),
CLK_COR_SEQ_2_3_0 => ("0000000000"),
CLK_COR_SEQ_2_4_0 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_0 => ("0011"),
CLK_COR_SEQ_2_USE_0 => (TRUE),
CLK_CORRECT_USE_0 => (TRUE),
RX_DECODE_SEQ_MATCH_0 => (TRUE),
CLK_COR_ADJ_LEN_1 => (2),
CLK_COR_DET_LEN_1 => (2),
CLK_COR_INSERT_IDLE_FLAG_1 => (FALSE),
CLK_COR_KEEP_IDLE_1 => (FALSE),
CLK_COR_MAX_LAT_1 => (18),
CLK_COR_MIN_LAT_1 => (16),
CLK_COR_PRECEDENCE_1 => (TRUE),
CLK_COR_REPEAT_WAIT_1 => (0),
CLK_COR_SEQ_1_1_1 => ("0110111100"),
CLK_COR_SEQ_1_2_1 => ("0001010000"),
CLK_COR_SEQ_1_3_1 => ("0000000000"),
CLK_COR_SEQ_1_4_1 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE_1 => ("0011"),
CLK_COR_SEQ_2_1_1 => ("0110111100"),
CLK_COR_SEQ_2_2_1 => ("0010110101"),
CLK_COR_SEQ_2_3_1 => ("0000000000"),
CLK_COR_SEQ_2_4_1 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE_1 => ("0011"),
CLK_COR_SEQ_2_USE_1 => (TRUE),
CLK_CORRECT_USE_1 => (TRUE),
RX_DECODE_SEQ_MATCH_1 => (TRUE),
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (FALSE),
CHAN_BOND_SEQ_1_1_0 => ("0000000000"),
CHAN_BOND_SEQ_1_2_0 => ("0000000000"),
CHAN_BOND_SEQ_1_3_0 => ("0000000000"),
CHAN_BOND_SEQ_1_4_0 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_1_0 => ("0000000000"),
CHAN_BOND_SEQ_2_2_0 => ("0000000000"),
CHAN_BOND_SEQ_2_3_0 => ("0000000000"),
CHAN_BOND_SEQ_2_4_0 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_USE_0 => (FALSE),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (FALSE),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (FALSE),
CHAN_BOND_SEQ_1_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2_1 => ("0000000000"),
CHAN_BOND_SEQ_1_3_1 => ("0000000000"),
CHAN_BOND_SEQ_1_4_1 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_1_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_3_1 => ("0000000000"),
CHAN_BOND_SEQ_2_4_1 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_USE_1 => (FALSE),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (FALSE),
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => ("01010"),
PCI_EXPRESS_MODE_0 => (FALSE),
RX_EN_IDLE_HOLD_CDR_0 => (TRUE),
RX_EN_IDLE_RESET_FR_0 => (TRUE),
RX_EN_IDLE_RESET_PH_0 => (TRUE),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => ("01010"),
PCI_EXPRESS_MODE_1 => (FALSE),
RX_EN_IDLE_HOLD_CDR_1 => (TRUE),
RX_EN_IDLE_RESET_FR_1 => (TRUE),
RX_EN_IDLE_RESET_PH_1 => (TRUE),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
--RX SATA Attributes
SATA_BURST_VAL_0 => ("100"),
SATA_IDLE_VAL_0 => ("100"),
SATA_MAX_BURST_0 => (9),
SATA_MAX_INIT_0 => (27),
SATA_MAX_WAKE_0 => (9),
SATA_MIN_BURST_0 => (5),
SATA_MIN_INIT_0 => (15),
SATA_MIN_WAKE_0 => (5),
SATA_BURST_VAL_1 => ("100"),
SATA_IDLE_VAL_1 => ("100"),
SATA_MAX_BURST_1 => (9),
SATA_MAX_INIT_1 => (27),
SATA_MAX_WAKE_1 => (9),
SATA_MIN_BURST_1 => (5),
SATA_MIN_INIT_1 => (15),
SATA_MIN_WAKE_1 => (5)
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => LOOPBACK0_IN,
LOOPBACK1 => LOOPBACK1_IN,
RXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
RXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN0 => tied_to_ground_vec_i(1 downto 0),
TXPOWERDOWN1 => tied_to_ground_vec_i(1 downto 0),
--------------------------------- PLL Ports --------------------------------
CLK00 => CLK00_IN,
CLK01 => CLK01_IN,
CLK10 => CLK10_IN,
CLK11 => CLK11_IN,
CLKINEAST0 => CLKINEAST0_IN,
CLKINEAST1 => CLKINEAST1_IN,
CLKINWEST0 => CLKINWEST0_IN,
CLKINWEST1 => CLKINWEST1_IN,
GCLK00 => GCLK00_IN,
GCLK01 => GCLK01_IN,
GCLK10 => GCLK10_IN,
GCLK11 => GCLK11_IN,
GTPRESET0 => GTPRESET0_IN,
GTPRESET1 => GTPRESET1_IN,
GTPTEST0 => "00010000",
GTPTEST1 => "00010000",
INTDATAWIDTH0 => tied_to_vcc_i,
INTDATAWIDTH1 => tied_to_vcc_i,
PLLCLK00 => tied_to_ground_i,
PLLCLK01 => tied_to_ground_i,
PLLCLK10 => tied_to_ground_i,
PLLCLK11 => tied_to_ground_i,
PLLLKDET0 => PLLLKDET0_OUT,
PLLLKDET1 => PLLLKDET1_OUT,
PLLLKDETEN0 => tied_to_vcc_i,
PLLLKDETEN1 => tied_to_vcc_i,
PLLPOWERDOWN0 => tied_to_ground_i,
PLLPOWERDOWN1 => tied_to_ground_i,
REFCLKOUT0 => open,
REFCLKOUT1 => open,
REFCLKPLL0 => open,
REFCLKPLL1 => open,
REFCLKPWRDNB0 => tied_to_vcc_i,
REFCLKPWRDNB1 => tied_to_vcc_i,
REFSELDYPLL0 => REFSELDYPLL0_IN,
REFSELDYPLL1 => REFSELDYPLL1_IN,
RESETDONE0 => RESETDONE0_OUT,
RESETDONE1 => RESETDONE1_OUT,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN0 => tied_to_ground_vec_i(11 downto 0),
TSTIN1 => tied_to_ground_vec_i(11 downto 0),
TSTOUT0 => open,
TSTOUT1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0(3 downto 2) => rxchariscomma0_float_i,
RXCHARISCOMMA0(1 downto 0) => RXCHARISCOMMA0_OUT,
RXCHARISCOMMA1(3 downto 2) => rxchariscomma1_float_i,
RXCHARISCOMMA1(1 downto 0) => RXCHARISCOMMA1_OUT,
RXCHARISK0(3 downto 2) => rxcharisk0_float_i,
RXCHARISK0(1 downto 0) => RXCHARISK0_OUT,
RXCHARISK1(3 downto 2) => rxcharisk1_float_i,
RXCHARISK1(1 downto 0) => RXCHARISK1_OUT,
RXDEC8B10BUSE0 => tied_to_vcc_i,
RXDEC8B10BUSE1 => tied_to_vcc_i,
RXDISPERR0(3 downto 2) => rxdisperr0_float_i,
RXDISPERR0(1 downto 0) => RXDISPERR0_OUT,
RXDISPERR1(3 downto 2) => rxdisperr1_float_i,
RXDISPERR1(1 downto 0) => RXDISPERR1_OUT,
RXNOTINTABLE0(3 downto 2) => rxnotintable0_float_i,
RXNOTINTABLE0(1 downto 0) => RXNOTINTABLE0_OUT,
RXNOTINTABLE1(3 downto 2) => rxnotintable1_float_i,
RXNOTINTABLE1(1 downto 0) => RXNOTINTABLE1_OUT,
RXRUNDISP0(3 downto 2) => rxrundisp0_float_i,
RXRUNDISP0(1 downto 0) => RXRUNDISP0_OUT,
RXRUNDISP1(3 downto 2) => rxrundisp1_float_i,
RXRUNDISP1(1 downto 0) => RXRUNDISP1_OUT,
USRCODEERR0 => tied_to_ground_i,
USRCODEERR1 => tied_to_ground_i,
---------------------- Receive Ports - Channel Bonding ---------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXCHBONDI => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER0 => tied_to_ground_i,
RXCHBONDMASTER1 => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE0 => tied_to_ground_i,
RXCHBONDSLAVE1 => tied_to_ground_i,
RXENCHANSYNC0 => tied_to_ground_i,
RXENCHANSYNC1 => tied_to_ground_i,
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0 => RXCLKCORCNT0_OUT,
RXCLKCORCNT1 => RXCLKCORCNT1_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => RXBYTEISALIGNED0_OUT,
RXBYTEISALIGNED1 => RXBYTEISALIGNED1_OUT,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => open,
RXCOMMADET1 => open,
RXCOMMADETUSE0 => tied_to_vcc_i,
RXCOMMADETUSE1 => tied_to_vcc_i,
RXENMCOMMAALIGN0 => RXENMCOMMAALIGN0_IN,
RXENMCOMMAALIGN1 => RXENMCOMMAALIGN1_IN,
RXENPCOMMAALIGN0 => RXENPCOMMAALIGN0_IN,
RXENPCOMMAALIGN1 => RXENPCOMMAALIGN1_IN,
RXSLIDE0 => tied_to_ground_i,
RXSLIDE1 => tied_to_ground_i,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => tied_to_ground_i,
PRBSCNTRESET1 => tied_to_ground_i,
RXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
RXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => rxdata0_i,
RXDATA1 => rxdata1_i,
RXDATAWIDTH0 => "01",
RXDATAWIDTH1 => "01",
RXRECCLK0 => open,
RXRECCLK1 => open,
RXRESET0 => RXRESET0_IN,
RXRESET1 => RXRESET1_IN,
RXUSRCLK0 => RXUSRCLK0_IN,
RXUSRCLK1 => RXUSRCLK1_IN,
RXUSRCLK20 => RXUSRCLK20_IN,
RXUSRCLK21 => RXUSRCLK21_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0 => tied_to_ground_i,
GATERXELECIDLE1 => tied_to_ground_i,
IGNORESIGDET0 => tied_to_ground_i,
IGNORESIGDET1 => tied_to_ground_i,
RCALINEAST => tied_to_ground_vec_i(4 downto 0),
RCALINWEST => tied_to_ground_vec_i(4 downto 0),
RCALOUTEAST => open,
RCALOUTWEST => open,
RXCDRRESET0 => tied_to_ground_i,
RXCDRRESET1 => tied_to_ground_i,
RXELECIDLE0 => open,
RXELECIDLE1 => open,
RXEQMIX0 => "11",
RXEQMIX1 => "11",
RXN0 => RXN0_IN,
RXN1 => RXN1_IN,
RXP0 => RXP0_IN,
RXP1 => RXP1_IN,
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXBUFRESET0 => RXBUFRESET0_IN,
RXBUFRESET1 => RXBUFRESET1_IN,
RXBUFSTATUS0 => RXBUFSTATUS0_OUT,
RXBUFSTATUS1 => RXBUFSTATUS1_OUT,
RXENPMAPHASEALIGN0 => tied_to_ground_i,
RXENPMAPHASEALIGN1 => tied_to_ground_i,
RXPMASETPHASE0 => tied_to_ground_i,
RXPMASETPHASE1 => tied_to_ground_i,
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0 => tied_to_ground_i,
RXPOLARITY1 => tied_to_ground_i,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST => open,
GTPCLKFBSEL0EAST => "10",
GTPCLKFBSEL0WEST => "00",
GTPCLKFBSEL1EAST => "11",
GTPCLKFBSEL1WEST => "01",
GTPCLKFBWEST => open,
GTPCLKOUT0 => GTPCLKOUT0_OUT,
GTPCLKOUT1 => GTPCLKOUT1_OUT,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXBYPASS8B10B0 => tied_to_ground_vec_i(3 downto 0),
TXBYPASS8B10B1 => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE0(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARDISPMODE0(1 downto 0) => TXCHARDISPMODE0_IN,
TXCHARDISPMODE1(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARDISPMODE1(1 downto 0) => TXCHARDISPMODE1_IN,
TXCHARDISPVAL0(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARDISPVAL0(1 downto 0) => TXCHARDISPVAL0_IN,
TXCHARDISPVAL1(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARDISPVAL1(1 downto 0) => TXCHARDISPVAL1_IN,
TXCHARISK0(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARISK0(1 downto 0) => TXCHARISK0_IN,
TXCHARISK1(3 downto 2) => tied_to_ground_vec_i(1 downto 0),
TXCHARISK1(1 downto 0) => TXCHARISK1_IN,
TXENC8B10BUSE0 => tied_to_vcc_i,
TXENC8B10BUSE1 => tied_to_vcc_i,
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0(3 downto 2) => txrundisp0_float_i,
TXRUNDISP0(1 downto 0) => TXRUNDISP0_OUT,
TXRUNDISP1(3 downto 2) => txrundisp1_float_i,
TXRUNDISP1(1 downto 0) => TXRUNDISP1_OUT,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0 => TXBUFSTATUS0_OUT,
TXBUFSTATUS1 => TXBUFSTATUS1_OUT,
TXENPMAPHASEALIGN0 => tied_to_ground_i,
TXENPMAPHASEALIGN1 => tied_to_ground_i,
TXPMASETPHASE0 => tied_to_ground_i,
TXPMASETPHASE1 => tied_to_ground_i,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA0 => txdata0_i,
TXDATA1 => txdata1_i,
TXDATAWIDTH0 => "01",
TXDATAWIDTH1 => "01",
TXOUTCLK0 => TXOUTCLK0_OUT,
TXOUTCLK1 => TXOUTCLK1_OUT,
TXRESET0 => TXRESET0_IN,
TXRESET1 => TXRESET1_IN,
TXUSRCLK0 => TXUSRCLK0_IN,
TXUSRCLK1 => TXUSRCLK1_IN,
TXUSRCLK20 => TXUSRCLK20_IN,
TXUSRCLK21 => TXUSRCLK21_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXDIFFCTRL0 => "0110",
TXDIFFCTRL1 => "0110",
TXINHIBIT0 => tied_to_ground_i,
TXINHIBIT1 => tied_to_ground_i,
TXN0 => TXN0_OUT,
TXN1 => TXN1_OUT,
TXP0 => TXP0_OUT,
TXP1 => TXP1_OUT,
TXPREEMPHASIS0 => "000",
TXPREEMPHASIS1 => "000",
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => tied_to_ground_vec_i(2 downto 0),
TXENPRBSTST1 => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR0 => tied_to_ground_i,
TXPRBSFORCEERR1 => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => tied_to_ground_i,
TXPOLARITY1 => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => tied_to_ground_i,
TXDETECTRX1 => tied_to_ground_i,
TXELECIDLE0 => tied_to_ground_i,
TXELECIDLE1 => tied_to_ground_i,
TXPDOWNASYNCH0 => tied_to_ground_i,
TXPDOWNASYNCH1 => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => tied_to_ground_i,
TXCOMSTART1 => tied_to_ground_i,
TXCOMTYPE0 => tied_to_ground_i,
TXCOMTYPE1 => tied_to_ground_i
);
end RTL;
| lgpl-2.1 | 6b4e549d93ec0876df9bea6974321b08 | 0.382968 | 4.455723 | false | false | false | false |
josemonsalve2/cpeg324_calculator | vivado/hdl/Top/Lab2_project_top.vhd | 1 | 5,376 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/10/2016 01:51:08 AM
-- Design Name:
-- Module Name: Lab2_project_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Lab2_project_top is
Port ( start_button : in STD_LOGIC;
printer_sw : in STD_LOGIC;
LEDS : out STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC
);
end Lab2_project_top;
architecture Behavioral of Lab2_project_top is
--New clock for calculator
signal counter : STD_LOGIC_VECTOR(31 downto 0) := (others =>'0');
--THIS IS THE ACTUAL CALCULATOR IT HAS THE PROVIDED INTERFACES
component calculator
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
PC : out STD_LOGIC_VECTOR (7 downto 0);
instruction : in STD_LOGIC_VECTOR (7 downto 0);
print : out STD_LOGIC_VECTOR (7 downto 0);
num_instructions : in STD_LOGIC_VECTOR (7 downto 0));
end component;
--Calculator's signals
signal s_calc_clk : STD_LOGIC:='0';
signal s_reset : STD_LOGIC:='0';
signal s_enable : STD_LOGIC:='0';
signal s_PC : STD_LOGIC_VECTOR (7 downto 0):= (others =>'0');
signal s_instruction : STD_LOGIC_VECTOR (7 downto 0):= (others =>'0');
signal s_print : STD_LOGIC_VECTOR (7 downto 0):= (others =>'0');
signal s_num_instructions: STD_LOGIC_VECTOR (7 downto 0):= (others =>'0');
--THIS IS THE INSTRUCTIONS MEMORY
COMPONENT InstructionsMemory
generic ( INIT_BRAM_FILE: string );
Port ( clk : in STD_LOGIC;
PC : in STD_LOGIC_VECTOR (7 downto 0);
Instruction : out STD_LOGIC_VECTOR (7 downto 0):=(others => '0');
reset: in STD_LOGIC;
num_instructions: out STD_LOGIC_VECTOR (7 downto 0):=(others => '0')
);
END COMPONENT;
--Button debouncing
signal deb_counter : STD_LOGIC_VECTOR (31 downto 0):=(others => '0');
signal button_signal : STD_LOGIC;
signal prev_button_signal : STD_LOGIC;
begin
-- INSTANCES
calc_0: calculator Port map ( clk => s_calc_clk,
reset => s_reset,
enable => s_enable,
PC => s_PC,
instruction => s_instruction,
print => s_print,
num_instructions => s_num_instructions
);
inst_memory: InstructionsMemory generic map ( INIT_BRAM_FILE => "../../../../../Instructions/example.txt" )
Port map ( clk => clk,
PC => s_PC,
Instruction => s_instruction,
reset => '0',
num_instructions => s_num_instructions
);
-- connections
with printer_sw select LEDS <=
s_print(7 downto 4) when '1',
s_print(3 downto 0) when '0';
genClkProc: process (clk) is
begin
if (rising_edge(clk)) then
counter<= counter +1 ;
if (counter = x"07735940") then -- for 1Hz clock
counter <= (others => '0');
s_Calc_clk <= not s_Calc_clk;
end if;
end if;
end process;
start_but: process(clk) is
begin
if (rising_edge (clk)) then
if (prev_button_signal /= start_button) then
deb_counter <= x"00000001";
end if;
if (deb_counter > x"00000000") then
deb_counter <= deb_counter + 1;
if (deb_counter > x"023C3460") then
if (start_button = '1') then
deb_counter <= x"00000000";
s_enable <= not s_enable;
end if;
end if;
end if;
prev_button_signal <= start_button;
end if;
end process;
end Behavioral;
| gpl-3.0 | 4acfac3f3908027aedce2110cd35e201 | 0.445313 | 4.757522 | false | false | false | false |
lincanbin/VHDL-74LS160 | ls160.vhd | 1 | 1,207 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY ls160 is
PORT(
data: in std_logic_vector(3 downto 0);--4λԤÖÃÊý£¬load·Ç¸ßµçƽÖÃÊý
clk,load,enp,ent,clr:in std_logic;--×¢Êͼûarchitecture
q: buffer std_logic_vector(3 downto 0);--4λ¼ÆÊýÖµ£¬Ê¹ÓÃbufferÈÃÆä±£³Ö״̬
rco:out std_logic--Òç³ö룬¸ßµçƽÒç³ö
);
END ls160;
architecture behavior OF ls160 IS
BEGIN
rco<='1' when (q="1001" and enp='1' and ent='1' and load='1' and clr='1') else '0';--Òç³ö½øλ
process(clk,clr,enp,ent,load) begin
if(rising_edge(clk)) then --ʱÖÓÉÏÉýÑØʱ¿ªÊ¼¹¤×÷
if(clr='1')then --CLR¸ßµçƽ¹¤×÷£¬µÍµçƽÇåÁã
if(load='1')then --load·Ç¸ßµçƽÖÃÊý
if(enp='1')then --EnableP£¬PTͬʱ·Ç¸ßµçƽ±£´æ״̬
if(ent='1')then --EnableT£¬¿ª¹Ø£¬PTͬʱ·Ç¸ßµçƽ±£´æ״̬
if(q="1001")then --CountΪ9£¬Òç³öÖØÖÃ
q<="0000";
else
q<=q+1;
end if;
else
q<=q;
end if;
else
q<=q;
end if;
else
q<=data;
end if;
else
q<="0000";
end if;
end if;
end process;
END behavior;
--ÁÖ²Ó±ó
--https://github.com/lincanbin
--20150427 | apache-2.0 | b920972dab12172022fea5e7513c5b8b | 0.560895 | 2.214679 | false | false | false | false |
pkerling/ethernet_mac | generic/single_signal_synchronizer_simple.vhd | 1 | 608 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Simple two-FF synchronizer
library ieee;
use ieee.std_logic_1164.all;
architecture simple of single_signal_synchronizer is
signal signal_tmp : std_ulogic := '0';
begin
process(clock_target_i, preset_i)
begin
if preset_i = '1' then
signal_tmp <= '1';
signal_o <= '1';
elsif rising_edge(clock_target_i) then
signal_tmp <= signal_i;
signal_o <= signal_tmp;
end if;
end process;
end architecture;
| bsd-3-clause | fc54a0aa98cd65f0b9df4572f2bfdabc | 0.702303 | 3.2 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/niosii/niosii_inst.vhd | 1 | 2,376 | component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
epcs_flash_dclk : out std_logic; -- dclk
epcs_flash_sce : out std_logic; -- sce
epcs_flash_sdo : out std_logic; -- sdo
epcs_flash_data0 : in std_logic := 'X'; -- data0
ip_pwm_dir : out std_logic_vector(1 downto 0); -- dir
ip_pwm_out : out std_logic_vector(1 downto 0); -- out
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_rxd : in std_logic := 'X'; -- rxd
uart_0_txd : out std_logic -- txd
);
end component niosii;
u0 : component niosii
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
epcs_flash_dclk => CONNECTED_TO_epcs_flash_dclk, -- epcs_flash.dclk
epcs_flash_sce => CONNECTED_TO_epcs_flash_sce, -- .sce
epcs_flash_sdo => CONNECTED_TO_epcs_flash_sdo, -- .sdo
epcs_flash_data0 => CONNECTED_TO_epcs_flash_data0, -- .data0
ip_pwm_dir => CONNECTED_TO_ip_pwm_dir, -- ip_pwm.dir
ip_pwm_out => CONNECTED_TO_ip_pwm_out, -- .out
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export, -- pio_0_external_connection.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
uart_0_rxd => CONNECTED_TO_uart_0_rxd, -- uart_0.rxd
uart_0_txd => CONNECTED_TO_uart_0_txd -- .txd
);
| mit | dd7855955a1bd8b49c26c25c3cf04191 | 0.363636 | 4.327869 | false | false | false | false |
FrankBuss/YaGraphCon | spartan3e/src/YaGraphConPackage.vhd | 1 | 1,904 | -- Copyright (c) 2009 Frank Buss ([email protected])
-- See license.txt for license
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package YaGraphConPackage is
constant RESET_COMMAND: unsigned(7 downto 0) := x"00";
constant SET_FRAMEBUFFER_START: unsigned(7 downto 0) := x"01";
constant SET_FRAMEBUFFER_PITCH: unsigned(7 downto 0) := x"02";
constant SET_DESTINATION_START: unsigned(7 downto 0) := x"03";
constant SET_DESTINATION_PITCH: unsigned(7 downto 0) := x"04";
constant SET_SOURCE_START: unsigned(7 downto 0) := x"05";
constant SET_SOURCE_PITCH: unsigned(7 downto 0) := x"06";
constant SET_COLOR: unsigned(7 downto 0) := x"07";
constant SET_PIXEL: unsigned(7 downto 0) := x"08";
constant MOVE_TO: unsigned(7 downto 0) := x"09";
constant LINE_TO: unsigned(7 downto 0) := x"0a";
constant FILL_RECT: unsigned(7 downto 0) := x"0b";
constant BLIT_SIZE: unsigned(7 downto 0) := x"0c";
constant BLIT_COMMAND: unsigned(7 downto 0) := x"0d";
constant BLIT_TRANSPARENT: unsigned(7 downto 0) := x"0e";
constant WRITE_FRAMEBUFFER: unsigned(7 downto 0) := x"0f";
function adjustLength(value: unsigned; length: natural) return unsigned;
function max(left, right: natural) return natural;
function min(left, right: natural) return natural;
end;
package body YaGraphConPackage is
function adjustLength(value: unsigned; length: natural) return unsigned is
variable result: unsigned(length-1 downto 0);
begin
if value'length >= length then
result := value(length-1 downto 0);
else
result := to_unsigned(0, length - value'length) & value;
end if;
return result;
end;
function max(left, right: natural) return natural is
begin
if left > right then
return left;
else
return right;
end if;
end;
function min(left, right: natural) return natural is
begin
if left < right then
return left;
else
return right;
end if;
end;
end;
| mit | 6318e65664826d8554f38d19a1614cdb | 0.710084 | 3.075929 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_sdram/niosii/niosii_inst.vhd | 2 | 730 | component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component niosii;
u0 : component niosii
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export, -- pio_0_external_connection.export
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);
| mit | 055dbca42521fbea972bca3431844a5b | 0.463014 | 3.882979 | false | false | false | false |
airhdl/spi-to-axi-bridge | tb/tb_spi2axi.vhd | 1 | 9,013 | ----------------------------------------------------------------------------------------------------
--
-- SPI to AXI4-Lite Bridge Testbench
--
-- Description:
-- OSVVM testbench for the SPI to AXI4-Lite Bridge component. Use SPI master verification
-- component (VC) to issue SPI transactions to the unit under test, and AXI4Lite subordinate
-- VC to emulate an AXI4 lite register bank.
--
-- Author(s):
-- Guy Eschemann, [email protected]
--
----------------------------------------------------------------------------------------------------
--
-- Copyright (c) 2022 Guy Eschemann
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library OSVVM;
context OSVVM.OsvvmContext;
library osvvm_spi;
context osvvm_spi.SpiContext;
library osvvm_axi4;
context osvvm_axi4.Axi4LiteContext;
entity tb_spi2axi is
generic(
SPI_CPOL : natural range 0 to 1 := 0; -- SPI clock polarity
SPI_CPHA : natural range 0 to 1 := 0 -- SPI clock phase
);
end entity tb_spi2axi;
architecture TestHarness of tb_spi2axi is
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component tb_spi2axi_testctrl is
generic(
SPI_CPOL : natural range 0 to 1; -- SPI clock polarity
SPI_CPHA : natural range 0 to 1 -- SPI clock phase
);
port(
-- Record Interfaces
SpiRec : inout SpiRecType;
Axi4MemRec : inout AddressBusRecType;
-- Global Signal Interface
Clk : in std_logic;
nReset : in std_logic
);
end component;
------------------------------------------------------------------------------------------------
-- Constants
------------------------------------------------------------------------------------------------
constant AXI_ADDR_WIDTH : integer := 32; -- AXI address bus width, in bits
constant AXI_DATA_WIDTH : integer := 32;
constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH / 8;
constant AXI_CLK_PERIOD : time := 10 ns;
constant TPD : time := 2 ns;
------------------------------------------------------------------------------------------------
-- Signals
------------------------------------------------------------------------------------------------
signal Axi4LiteBus : Axi4LiteRecType(
WriteAddress(Addr(AXI_ADDR_WIDTH - 1 downto 0)),
WriteData(Data(AXI_DATA_WIDTH - 1 downto 0), Strb(AXI_STRB_WIDTH - 1 downto 0)),
ReadAddress(Addr(AXI_ADDR_WIDTH - 1 downto 0)),
ReadData(Data(AXI_DATA_WIDTH - 1 downto 0))
);
signal Axi4MemRec : AddressBusRecType(
Address(AXI_ADDR_WIDTH - 1 downto 0),
DataToModel(AXI_DATA_WIDTH - 1 downto 0),
DataFromModel(AXI_DATA_WIDTH - 1 downto 0)
);
signal SpiRec : SpiRecType;
signal spi_sck : std_logic; -- SPI clock
signal spi_ss_n : std_logic; -- SPI slave select (low active)
signal spi_mosi : std_logic; -- SPI master-out-slave-in
signal spi_miso : std_logic; -- SPI master-in-slave-out
signal axi_aclk : std_logic;
signal axi_aresetn : std_logic;
signal s_axi_awvalid : std_logic;
signal s_axi_awvalid_mask : std_logic := '1'; -- @suppress "signal s_axi_awvalid_mask is never written"
signal s_axi_arvalid : std_logic;
signal s_axi_arvalid_mask : std_logic := '1'; -- @suppress "signal s_axi_arvalid_mask is never written"
begin
------------------------------------------------------------------------------------------------
-- Clock generator
------------------------------------------------------------------------------------------------
Osvvm.TbUtilPkg.CreateClock(
Clk => axi_aclk,
Period => AXI_CLK_PERIOD
);
------------------------------------------------------------------------------------------------
-- Reset generator
------------------------------------------------------------------------------------------------
Osvvm.TbUtilPkg.CreateReset(
Reset => axi_aresetn,
ResetActive => '0',
Clk => axi_aclk,
Period => 7 * AXI_CLK_PERIOD,
tpd => TPD
);
------------------------------------------------------------------------------------------------
-- Test controller
------------------------------------------------------------------------------------------------
testctrl_inst : tb_spi2axi_testctrl
generic map(
SPI_CPOL => SPI_CPOL,
SPI_CPHA => SPI_CPHA
)
port map(
SpiRec => SpiRec,
Axi4MemRec => Axi4MemRec,
Clk => axi_aclk,
nReset => axi_aresetn
);
------------------------------------------------------------------------------------------------
-- SPI master verification component
------------------------------------------------------------------------------------------------
spi_master_inst : entity osvvm_spi.Spi
generic map(
MODEL_ID_NAME => "Spi",
DEFAULT_SCLK_PERIOD => SPI_SCLK_PERIOD_1M
)
port map(
TransRec => SpiRec,
SCLK => spi_sck,
SS => spi_ss_n,
MOSI => spi_mosi,
MISO => spi_miso
);
------------------------------------------------------------------------------------------------
-- Unit under test
------------------------------------------------------------------------------------------------
uut : entity work.spi2axi
generic map(
SPI_CPOL => SPI_CPOL,
SPI_CPHA => SPI_CPHA,
AXI_ADDR_WIDTH => AXI_ADDR_WIDTH
)
port map(
spi_sck => spi_sck,
spi_ss_n => spi_ss_n,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
axi_aclk => axi_aclk,
axi_aresetn => axi_aresetn,
s_axi_awaddr => Axi4LiteBus.WriteAddress.Addr,
s_axi_awprot => Axi4LiteBus.WriteAddress.Prot,
s_axi_awvalid => s_axi_awvalid, -- Axi4LiteBus.WriteAddress.Valid,
s_axi_awready => Axi4LiteBus.WriteAddress.Ready,
s_axi_wdata => Axi4LiteBus.WriteData.Data,
s_axi_wstrb => Axi4LiteBus.WriteData.Strb,
s_axi_wvalid => Axi4LiteBus.WriteData.Valid,
s_axi_wready => Axi4LiteBus.WriteData.Ready,
s_axi_araddr => Axi4LiteBus.ReadAddress.Addr,
s_axi_arprot => Axi4LiteBus.ReadAddress.Prot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => Axi4LiteBus.ReadAddress.Ready,
s_axi_rdata => Axi4LiteBus.ReadData.Data,
s_axi_rresp => Axi4LiteBus.ReadData.Resp,
s_axi_rvalid => Axi4LiteBus.ReadData.Valid,
s_axi_rready => Axi4LiteBus.ReadData.Ready,
s_axi_bresp => Axi4LiteBus.WriteResponse.Resp,
s_axi_bvalid => Axi4LiteBus.WriteResponse.Valid,
s_axi_bready => Axi4LiteBus.WriteResponse.Ready
);
Axi4LiteBus.WriteAddress.Valid <= s_axi_awvalid and s_axi_awvalid_mask;
Axi4LiteBus.ReadAddress.Valid <= s_axi_arvalid and s_axi_arvalid_mask;
------------------------------------------------------------------------------------------------
-- AXI4 lite memory verification component
------------------------------------------------------------------------------------------------
axi4lite_memory_inst : entity osvvm_axi4.Axi4LiteMemory
generic map(
MODEL_ID_NAME => "Axi4LiteMemory",
MEMORY_NAME => "Axi4LiteMemory",
tperiod_Clk => AXI_CLK_PERIOD
)
port map(
-- Globals
Clk => axi_aclk,
nReset => axi_aresetn,
-- AXI Manager Functional Interface
AxiBus => Axi4LiteBus,
-- Testbench Transaction Interface
TransRec => Axi4MemRec
);
end architecture TestHarness;
| apache-2.0 | 3cb0c00ba5633a234feb3abf9c2a2c83 | 0.442361 | 4.822365 | false | false | false | false |
pkerling/ethernet_mac | rx_fifo.vhd | 1 | 14,045 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Storage for packet reception with FIFO user interface
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_types.all;
use work.crc32.all;
entity rx_fifo is
generic(
-- Bits to use for the size of the memory
-- The total size is then 2^(MEMORY_SIZE_BITS)
-- The generic is given as bit count because only sizes
-- that are a power of two are supported
MEMORY_SIZE_BITS : positive := 12
);
port(
clock_i : in std_ulogic;
mac_rx_reset_i : in std_ulogic;
mac_rx_clock_i : in std_ulogic;
mac_rx_frame_i : in std_ulogic;
mac_rx_data_i : in t_ethernet_data;
mac_rx_byte_received_i : in std_ulogic;
mac_rx_error_i : in std_ulogic;
empty_o : out std_ulogic;
rd_en_i : in std_ulogic;
data_o : out t_ethernet_data
);
end entity;
architecture rtl of rx_fifo is
type t_write_state is (
WRITE_WAIT,
WRITE_PACKET,
WRITE_LENGTH_HIGH,
WRITE_LENGTH_LOW,
WRITE_PACKET_VALID,
WRITE_PACKET_INVALID,
WRITE_SKIP_FRAME
);
signal write_state : t_write_state := WRITE_PACKET_INVALID;
type t_read_state is (
READ_WAIT_PACKET,
READ_WAIT_ACK,
READ_LENGTH_LOW,
READ_PACKET
);
signal read_state : t_read_state := READ_WAIT_PACKET;
constant MEMORY_SIZE : positive := 2 ** MEMORY_SIZE_BITS;
constant FLAG_BYTES : positive := 1;
constant PACKET_LENGTH_BYTES : positive := 2;
type t_memory is array (0 to (MEMORY_SIZE - 1)) of t_ethernet_data;
-- Use unsigned here instead of simple integer variables to guarantee identical behavior in behavioral and post-translate simulation
-- Integer variables will wrap around only on reaching 2^32 in behavioral simulation, unsigned will always wrap around correctly.
subtype t_memory_address is unsigned((MEMORY_SIZE_BITS - 1) downto 0);
-- Ethernet frames have to be smaller than ~1500 bytes, so 11 bits will suffice for the packet length
subtype t_packet_length is unsigned(10 downto 0);
signal memory : t_memory;
-- Signals in write side clock domain
signal write_start_address : t_memory_address;
signal write_address : t_memory_address;
signal write_packet_length : t_packet_length;
signal write_safe_address : t_memory_address;
signal write_update_safe_address_req : std_ulogic;
signal write_update_safe_address_ack : std_ulogic;
signal write_reset_read_side : std_ulogic;
-- Signals in read side clock domain
signal read_reset : std_ulogic := '1';
signal read_data : t_ethernet_data;
signal read_address : t_memory_address;
-- Address of the last byte that is still part of the currently processed frame in the read process
signal read_end_address : t_memory_address;
signal read_packet_length_high : unsigned(2 downto 0);
signal read_update_safe_address_req : std_ulogic;
signal read_update_safe_address_ack : std_ulogic;
-- Signals crossing clock domains
signal update_safe_address : t_memory_address;
-- Counts the elements in [a, b) in a ring buffer of given size
-- a and b should have the same range
function pointer_difference(a : unsigned; b : unsigned; size : positive) return unsigned is
-- Make sure the result has a matching range
variable result : unsigned(a'range);
begin
if b >= a then
result := b - a;
else
result := size - a + b;
end if;
return result;
end function;
begin
data_o <= read_data;
sync_req_inst : entity work.single_signal_synchronizer
port map(
clock_target_i => mac_rx_clock_i,
signal_i => read_update_safe_address_req,
signal_o => write_update_safe_address_req
);
sync_ack_inst : entity work.single_signal_synchronizer
port map(
clock_target_i => clock_i,
signal_i => write_update_safe_address_ack,
signal_o => read_update_safe_address_ack
);
sync_reset_inst : entity work.single_signal_synchronizer
port map(
clock_target_i => clock_i,
signal_i => write_reset_read_side,
signal_o => read_reset
);
write_get_safe_address : process(mac_rx_reset_i, mac_rx_clock_i)
begin
if mac_rx_reset_i = '1' then
write_update_safe_address_ack <= '0';
write_safe_address <= (others => '1');
elsif rising_edge(mac_rx_clock_i) then
-- Data is read when the read process changes the level on write_update_safe_address_req
if write_update_safe_address_req /= write_update_safe_address_ack then
-- Read new safe address
write_safe_address <= update_safe_address;
-- Signal read process that the change was detected
write_update_safe_address_ack <= not write_update_safe_address_ack;
end if;
end if;
end process;
write_memory : process(mac_rx_reset_i, mac_rx_clock_i)
variable write_address_now : t_memory_address;
variable write_data : t_ethernet_data;
variable write_enable : boolean;
variable packet_length_calculated : t_packet_length;
variable enough_room : boolean;
begin
if mac_rx_reset_i = '1' then
write_state <= WRITE_PACKET_INVALID;
write_start_address <= (others => '0');
write_address <= (others => '0');
write_reset_read_side <= '1';
elsif rising_edge(mac_rx_clock_i) then
-- Default values for variables so no storage is inferred
write_address_now := write_address;
write_enable := FALSE;
write_data := (others => '0');
packet_length_calculated := (others => '0');
enough_room := TRUE;
case write_state is
when WRITE_WAIT =>
-- First byte has definitely been written invalid, read side can go into action now
write_reset_read_side <= '0';
if mac_rx_frame_i = '1' then
if mac_rx_error_i = '1' then
write_state <= WRITE_SKIP_FRAME;
else
if mac_rx_byte_received_i = '1' then
-- Check whether the 3 header bytes can be written safely to the buffer afterwards
for i in 0 to 2 loop
if write_start_address + i = write_safe_address then
enough_room := FALSE;
end if;
end loop;
if enough_room then
-- Write first byte
-- Leave 3 bytes room for data validity indication and packet length
write_address_now := write_start_address + PACKET_LENGTH_BYTES + FLAG_BYTES;
write_data := mac_rx_data_i;
write_enable := TRUE;
write_address <= write_address_now + 1;
write_state <= WRITE_PACKET;
else
write_state <= WRITE_SKIP_FRAME;
end if;
end if;
end if;
end if;
when WRITE_PACKET =>
if mac_rx_error_i = '1' then
write_state <= WRITE_SKIP_FRAME;
end if;
-- Calculate packet length
-- Resize as packet_length'length can be greater than memory_address_t'length for small memories
packet_length_calculated := resize(pointer_difference(write_start_address, write_address, MEMORY_SIZE), packet_length_calculated'length);
if mac_rx_frame_i = '1' then
if mac_rx_byte_received_i = '1' then
-- Write data
write_data := mac_rx_data_i;
write_enable := TRUE;
write_address <= write_address + 1;
end if;
-- Packet length will overflow after this clock cycle
if packet_length_calculated = (packet_length_calculated'range => '1') then
-- Throw frame away
write_state <= WRITE_SKIP_FRAME;
end if;
-- Buffer memory will overflow after this clock cycle
-- This is always an error as at least one byte must be available even
-- after the frame has ended to mark the next packet invalid in the buffer.
if write_address = write_safe_address then
-- Throw frame away
write_state <= WRITE_SKIP_FRAME;
end if;
-- Error flag is irrelevant if rx_frame_i is low already
else
if packet_length_calculated <= (CRC32_BYTES + PACKET_LENGTH_BYTES + FLAG_BYTES) then
-- Frame is way too short, ignore
write_state <= WRITE_WAIT;
end if;
packet_length_calculated := packet_length_calculated - CRC32_BYTES - PACKET_LENGTH_BYTES - FLAG_BYTES;
write_packet_length <= packet_length_calculated;
-- Write next packet invalid before doing anything else
-- Read process could read past this packet faster than we can flag the following packet invalid otherwise
-- for very low network speed/system clock speed ratios
write_address_now := write_start_address + PACKET_LENGTH_BYTES + FLAG_BYTES + to_integer(packet_length_calculated);
write_data := (others => '0');
write_enable := TRUE;
-- Write data length low byte next
write_state <= WRITE_LENGTH_LOW;
end if;
when WRITE_LENGTH_LOW =>
-- Write length low byte
write_address_now := write_start_address + 2;
write_data := std_ulogic_vector(write_packet_length(7 downto 0));
write_enable := TRUE;
-- Write high byte next
write_state <= WRITE_LENGTH_HIGH;
when WRITE_LENGTH_HIGH =>
-- Write length high byte
write_address_now := write_start_address + 1;
write_data := "00000" & std_ulogic_vector(write_packet_length(10 downto 8));
write_enable := TRUE;
-- Write packet validity indicator next
write_state <= WRITE_PACKET_VALID;
when WRITE_PACKET_VALID =>
write_address_now := write_start_address;
write_data := (others => '1'); -- mark valid
write_enable := TRUE;
-- Packet received correctly and completely, move start pointer for next packet ->
-- Move write pointer past the data of the current frame (excluding FCS) so the next
-- packet can be written
-- The FCS will get overwritten as it is not needed for operation of the higher layers.
write_start_address <= write_start_address + PACKET_LENGTH_BYTES + FLAG_BYTES + to_integer(write_packet_length);
write_state <= WRITE_WAIT;
when WRITE_PACKET_INVALID =>
-- Mark current/first packet as invalid
-- This cannot be merged into the WRITE_WAIT state, as WRITE_WAIT needs to write an incoming data byte
-- into the buffer immediately.
write_address_now := write_start_address;
write_data := (others => '0');
write_enable := TRUE;
write_state <= WRITE_WAIT;
when WRITE_SKIP_FRAME =>
if mac_rx_frame_i = '0' then
report "Skipped frame" severity note;
write_state <= WRITE_WAIT;
end if;
end case;
if write_enable then
memory(to_integer(write_address_now)) <= write_data;
end if;
end if;
end process;
read_memory : process(clock_i)
variable read_address_now : t_memory_address;
begin
if rising_edge(clock_i) then
-- Default output value
empty_o <= '1';
-- Default variable value to avoid storage
read_address_now := read_address;
if read_reset = '1' then
read_state <= READ_WAIT_PACKET;
read_address <= (others => '0');
read_end_address <= (others => '0');
read_data <= (others => '0');
read_update_safe_address_req <= '0';
else
case read_state is
when READ_WAIT_PACKET =>
-- Wait until data is ready, nobody is trying to get data out (in case the previous state was READ_PACKET)
-- to prevent read overruns, and the write FSM has ack'ed the update request
if read_data = (read_data'range => '1') and rd_en_i = '0' and read_update_safe_address_req = read_update_safe_address_ack then
read_state <= READ_WAIT_ACK;
-- Advance to address high byte
read_address_now := read_address + 1;
-- Tell the receiver that something is here
empty_o <= '1';
end if;
when READ_WAIT_ACK =>
empty_o <= '0';
if rd_en_i = '1' then
-- Read address high byte
read_address_now := read_address + 1;
read_state <= READ_LENGTH_LOW;
read_packet_length_high <= unsigned(read_data(2 downto 0));
end if;
when READ_LENGTH_LOW =>
empty_o <= '0';
if rd_en_i = '1' then
-- Read address low byte
read_address_now := read_address + 1;
read_state <= READ_PACKET;
-- The end address is the address of the last byte that is still valid, so one byte
-- needs to be subtracted.
read_end_address <= read_address_now + to_integer(read_packet_length_high & unsigned(read_data)) - 1;
end if;
when READ_PACKET =>
empty_o <= '0';
if read_address = read_end_address then
-- Wait for the last byte to be read out
if rd_en_i = '1' then
-- Guarantee that rx_empty_o is high for at least one clock cycle (needed so that the
-- receiver can sense the end of the packet)
empty_o <= '1';
read_state <= READ_WAIT_PACKET;
-- Update safe address for write process
update_safe_address <= read_end_address;
read_update_safe_address_req <= not read_update_safe_address_req;
end if;
end if;
if rd_en_i = '1' then
-- If this was the last byte: go to the first byte following this packet (-> header of the next packet)
-- No need to skip the FCS here, this is already taken care of in the write process.
read_address_now := read_address + 1;
end if;
end case;
-- Read data at new address in this clock cycle,
-- save the value to the signal for the next clock cycle.
read_data <= memory(to_integer(read_address_now));
read_address <= read_address_now;
end if;
end if;
end process;
end architecture;
| bsd-3-clause | 1d513463312ca69ad52247408f29be0e | 0.62848 | 3.480793 | false | false | false | false |
ju994lo/syko_proj | reg.vhd | 1 | 924 | library ieee;
use ieee.std_logic_1164.all;
entity reg is
generic
(
LW : integer := 8
);
port
(
clk, ie, oe, reset : in std_logic;
data_in : in std_logic_vector(LW-1 downto 0);
data_out : out std_logic_vector(LW-1 downto 0)
);
end reg;
architecture behav of reg is
--signal reg: std_logic_vector(LW-1 downto 0);
begin
process(reset, clk, ie, oe)
variable reg_v : std_logic_vector(LW-1 downto 0);
begin
if falling_edge(clk) then
if(reset = '1') then
reg_v := "00000000";
elsif(ie = '1') then
reg_v := data_in;
elsif(oe = '1') then
data_out <= reg_v;
elsif (oe = '0') then
data_out <= (others => 'Z');
-- if(reset = '1') then
-- reg <= (others => '0');
-- elsif(ie = '1') then
-- reg <= data_in;
-- elsif(oe = '1') then
-- data_out <= reg;
-- elsif (oe = '0') then
-- data_out <= (others => 'Z');
end if;
end if;
end process;
end behav;
| gpl-2.0 | 42449d9e14a9c05efbdc8878cd8f659a | 0.557359 | 2.418848 | false | false | false | false |
DSP-Crowd/software | apps/mobile_rgb-led/de0_nano/src/tbd_rr_base.vhd | 1 | 7,425 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spi2rgb_pkg.all;
entity tbd_rr_base is
generic
(
use_sdram_pll : std_ulogic := '1'
);
port
(
clock_50mhz : in std_ulogic;
keys : in std_ulogic_vector(1 downto 0);
switches : in std_ulogic_vector(3 downto 0);
leds : out std_ulogic_vector(7 downto 0);
uart_rx : in std_ulogic;
uart_tx : out std_ulogic;
spi_cs : in std_ulogic_vector(1 downto 0);
spi_clk : in std_ulogic;
spi_mosi : in std_ulogic;
spi_miso : out std_ulogic;
spi_epcs_cs : out std_ulogic;
spi_epcs_clk : out std_ulogic;
spi_epcs_mosi : out std_ulogic;
spi_epcs_miso : in std_ulogic;
arReconf : in std_ulogic;
pwm_red : out std_ulogic;
pwm_green : out std_ulogic;
pwm_blue : out std_ulogic;
sdram_addr : out std_logic_vector(12 downto 0);
sdram_ba : out std_logic_vector(1 downto 0);
sdram_cke : out std_logic;
sdram_clk : out std_logic;
sdram_cs_n : out std_logic;
--sdram_dq : inout std_logic_vector(15 downto 0);
sdram_dq : in std_logic_vector(15 downto 0);
sdram_dqm : out std_logic_vector(1 downto 0);
sdram_cas_n : out std_logic;
sdram_ras_n : out std_logic;
sdram_we_n : out std_logic
);
end tbd_rr_base;
architecture rtl of tbd_rr_base is
signal reset_done : std_ulogic := '0';
signal n_reset_async : std_logic;
signal inputs_unsynced : std_ulogic_vector(switches'length downto 0);
signal inputs_synced : std_ulogic_vector(inputs_unsynced'range);
signal inputs_synced_debounced : std_ulogic_vector(inputs_synced'range);
signal key_0_synced_debounced : std_ulogic;
signal switches_synced_debounced : std_ulogic_vector(switches'range);
signal spi_unsynced : std_ulogic_vector(2 downto 0);
signal spi_synced : std_ulogic_vector(2 downto 0);
signal spi_cs_user_synced : std_ulogic;
signal spi_clk_synced : std_ulogic;
signal spi_mosi_synced : std_ulogic;
signal spi2rgb_data : SPI2RGB_DATA_TYPE;
signal spi2rgb_valid_bits : std_ulogic_vector(SPI2RGB_NUM_DATA_BYTES - 1 downto 0);
begin
-- Reconfiguration unit
reconfUnit: entity work.altremotePulsed(rtl)
port map
(
clock => clock_50mhz,
nResetAsync => n_reset_async,
reconf => arReconf
);
-- Give epcs64 signals to external user
-- No need to synchronize. Signals are not used within system clock
spi_epcs_cs <= spi_cs(0);
spi_epcs_clk <= spi_clk;
spi_epcs_mosi <= spi_mosi;
-- Important: MISO must not drive signal if epcs64 is not selected
spi_miso <= spi_epcs_miso when spi_cs(0) = '0' else 'Z';
-- Synchronize inputs
inputs_unsynced <= switches & keys(0);
key_sync: entity work.input_sync(rtl)
generic map
(
num_inputs => inputs_unsynced'length,
num_sync_stages => 2
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
unsynced_inputs => inputs_unsynced,
synced_outputs => inputs_synced
);
-- Debounce inputs
key_debounce: entity work.input_debounce(rtl)
generic map
(
num_inputs => inputs_synced'length
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
synced_inputs => inputs_synced,
debounced_outputs => inputs_synced_debounced
);
key_0_synced_debounced <= inputs_synced_debounced(0);
switches_synced_debounced <= inputs_synced_debounced(inputs_synced_debounced'high downto 1);
-- Synchronize SPI
spi_unsynced <= spi_cs(1) & spi_clk & spi_mosi;
spi_sync: entity work.input_sync(rtl)
generic map
(
num_inputs => spi_unsynced'length,
num_sync_stages => 2
)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
unsynced_inputs => spi_unsynced,
synced_outputs => spi_synced
);
spi_cs_user_synced <= spi_synced(2);
spi_clk_synced <= spi_synced(1);
spi_mosi_synced <= spi_synced(0);
-- Hardware-is-alive-LED
hardware_is_alive_led: entity work.frequencyDivider(rtl)
generic map
(
divideBy => 25E7
)
port map
(
clock => clock_50mhz,
nResetAsync => n_reset_async,
output => leds(0)
);
-- SPI-Slave
spislave: entity work.spi2rgb(rtl)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
spi_cs => spi_cs_user_synced,
spi_clk => spi_clk_synced,
spi_mosi => spi_mosi_synced,
data => spi2rgb_data,
valid_bits => spi2rgb_valid_bits
);
-- RGB PWMs
pwmred: entity work.byte2pwm(rtl)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
data => spi2rgb_data(2),
data_valid => spi2rgb_valid_bits(2),
led_pwm => pwm_red
);
pwmgreen: entity work.byte2pwm(rtl)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
data => spi2rgb_data(1),
data_valid => spi2rgb_valid_bits(1),
led_pwm => pwm_green
);
pwmblue: entity work.byte2pwm(rtl)
port map
(
clock => clock_50mhz,
n_reset_async => n_reset_async,
data => spi2rgb_data(0),
data_valid => spi2rgb_valid_bits(0),
led_pwm => pwm_blue
);
-- Reset
proc_reset: process(clock_50mhz)
begin
if clock_50mhz'event and clock_50mhz = '1' then
reset_done <= '1';
end if;
end process;
n_reset_async <= reset_done and keys(1);
end architecture rtl;
| gpl-2.0 | 513cd676ab08cabe0bcde92cf2bbe3cf | 0.542626 | 3.2523 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii/unsaved/unsaved_inst.vhd | 1 | 733 | component unsaved is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
pio_0_external_connection_export : out std_logic_vector(7 downto 0) -- export
);
end component unsaved;
u0 : component unsaved
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export -- pio_0_external_connection.export
);
| mit | 4c3c639f5d122693e82273188f9b61c2 | 0.465211 | 3.898936 | false | false | false | false |
DSP-Crowd/software | apps/mobile_rgb-led/de0_nano/src/byte2pwm.vhd | 1 | 3,598 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DSP-Crowd project --
-- https://www.dsp-crowd.com --
-- --
-- Author(s): --
-- - Johannes Natter, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.dsp-crowd.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity byte2pwm is
port
(
clock : in std_ulogic;
n_reset_async : in std_ulogic;
data : in std_ulogic_vector(7 downto 0);
data_valid : in std_ulogic;
led_pwm : out std_ulogic
);
end byte2pwm;
architecture rtl of byte2pwm is
type REG_TYPE is record
counter : natural;
counter_max : natural;
end record;
constant RSET_INIT_VAL : REG_TYPE :=
(
counter => 0,
counter_max => 0
);
signal R, NxR : REG_TYPE;
signal cnt_strobe : std_ulogic;
begin
proc_comb: process(R, data, data_valid, cnt_strobe)
begin
NxR <= R;
if(cnt_strobe = '1')then
if(R.counter < 254)then
NxR.counter <= R.counter + 1;
else
NxR.counter <= 0;
end if;
end if;
if(R.counter < R.counter_max)then
led_pwm <= '1';
else
led_pwm <= '0';
end if;
if(data_valid = '1')then
NxR.counter_max <= to_integer(unsigned(data));
end if;
end process;
mainstrobe: entity work.strobe_gen(rtl)
generic map
(
num_clock_cycles => 50E1 -- 1us strobe
-- num_clock_cycles => 3 -- Test
)
port map
(
clock => clock,
n_reset_async => n_reset_async,
strobe_output => cnt_strobe
);
proc_reg: process(n_reset_async, clock)
begin
if(n_reset_async = '0')then
R <= RSET_INIT_VAL;
elsif(clock'event and clock = '1')then
R <= NxR;
end if;
end process;
end architecture rtl;
| gpl-2.0 | 5cf7298a61f03b339f91f7f61e351800 | 0.415787 | 4.169177 | false | false | false | false |
Dragonturtle/SHERPA | HDL/FPGALink/FIFO/xilinx_fifo.vhd | 1 | 10,281 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2017 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file xilinx_fifo.vhd when simulating
-- the core, xilinx_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY xilinx_fifo IS
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END xilinx_fifo;
ARCHITECTURE xilinx_fifo_a OF xilinx_fifo IS
-- synthesis translate_off
COMPONENT wrapped_xilinx_fifo
PORT (
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_xilinx_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 15,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 1,
c_has_rd_rst => 0,
c_has_rst => 0,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "8kx4",
c_prog_empty_thresh_assert_val => 2,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 32765,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 32764,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 15,
c_rd_depth => 32768,
c_rd_freq => 1,
c_rd_pntr_width => 15,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 0,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 15,
c_wr_depth => 32768,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 15,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_xilinx_fifo
PORT MAP (
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
rd_data_count => rd_data_count
);
-- synthesis translate_on
END xilinx_fifo_a;
| gpl-3.0 | 93ed2cd27484e3c2d9520e73402850ef | 0.538761 | 3.333658 | false | false | false | false |
pkerling/ethernet_mac | miim_registers.vhd | 1 | 9,676 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- MIIM register definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_types.all;
use work.miim_types.all;
package miim_registers is
-- Register numbers
constant CONTROL_REG : t_register_address := to_register_address(0);
constant STATUS_REG : t_register_address := to_register_address(1);
constant PHY_ID1_REG : t_register_address := to_register_address(2);
constant PHY_ID2_REG : t_register_address := to_register_address(3);
constant AUTONEG_ADVERTISEMENT_REG : t_register_address := to_register_address(4);
constant AUTONEG_LP_BASEPAGEABILITY_REG : t_register_address := to_register_address(5);
constant AUTONEG_EXPANSION_REG : t_register_address := to_register_address(6);
constant AUTONEG_NEXTPAGETX_REG : t_register_address := to_register_address(7);
constant AUTONEG_LP_NEXTPAGERECV_REG : t_register_address := to_register_address(8);
constant MASTERSLAVE_CTRL_REG : t_register_address := to_register_address(9);
constant MASTERSLAVE_STATUS_REG : t_register_address := to_register_address(10);
constant PSE_CONTROL_REG : t_register_address := to_register_address(11);
constant PSE_STATUS_REG : t_register_address := to_register_address(12);
constant MMD_ACCESSCONTROL_REG : t_register_address := to_register_address(13);
constant MMD_ACCESSADDRESSDATA_REG : t_register_address := to_register_address(14);
constant EXTENDED_STATUS_REG : t_register_address := to_register_address(15);
constant VENDOR_SPECIFIC_REG_BASE : t_register_address := to_register_address(16);
-- Register contents of selected registers
-- See Ethernet specification for the meaning of the fields
type t_control_register is record
reset : std_ulogic;
loopback : std_ulogic;
speed_10_100 : std_ulogic;
speed_1000 : std_ulogic;
auto_negotiation_enable : std_ulogic;
power_down : std_ulogic;
isolate : std_ulogic;
restart_auto_negotiation : std_ulogic;
duplex_mode : std_ulogic;
enable_collision_test : std_ulogic;
unidirectional_enable : std_ulogic;
end record;
type t_status_register is record
can_100base_t4 : std_ulogic;
can_100base_x_fd : std_ulogic;
can_100base_x_hd : std_ulogic;
can_10mbps_fd : std_ulogic;
can_10mbps_hd : std_ulogic;
can_100base_t2_fd : std_ulogic;
can_100base_t2_hd : std_ulogic;
extended_status : std_ulogic;
undirectional_ability : std_ulogic;
mf_preamble_suppression : std_ulogic;
auto_negotiation_complete : std_ulogic;
remote_fault : std_ulogic;
auto_negotiation_ability : std_ulogic;
link_status : std_ulogic;
jabber_detect : std_ulogic;
extended_capability : std_ulogic;
end record;
type t_auto_negotiation_advertisement_register_802_3 is record
next_page : std_ulogic;
remote_fault : std_ulogic;
extended_next_page : std_ulogic;
asymmetric_pause : std_ulogic;
pause : std_ulogic;
advertise_100base_t4 : std_ulogic;
advertise_100base_tx_fd : std_ulogic;
advertise_100base_tx_hd : std_ulogic;
advertise_10base_t_fd : std_ulogic;
advertise_10base_t_hd : std_ulogic;
end record;
type auto_negotiation_lp_base_page_ability_register_802_3_t is record
next_page : std_ulogic;
acknowledge : std_ulogic;
remote_fault : std_ulogic;
extended_next_page : std_ulogic;
asymmetric_pause : std_ulogic;
pause : std_ulogic;
can_100base_t4 : std_ulogic;
can_100base_tx_fd : std_ulogic;
can_100base_tx_hd : std_ulogic;
can_10base_t_fd : std_ulogic;
can_10base_t_hd : std_ulogic;
end record;
type t_master_slave_control_register is record
test_mode_bits : std_ulogic_vector(2 downto 0);
master_slave_manual_config_enable : std_ulogic;
master_slave_manual_config_value : std_ulogic;
port_type_is_multiport : std_ulogic;
advertise_1000base_t_fd : std_ulogic;
advertise_1000base_t_hd : std_ulogic;
end record;
type t_master_slave_status_register is record
master_slave_config_fault : std_ulogic;
master_slave_config_resolution : std_ulogic;
local_receiver_status : std_ulogic;
remote_receiver_status : std_ulogic;
lp_1000base_t_fd : std_ulogic;
lp_1000base_t_hd : std_ulogic;
idle_error_count : unsigned(7 downto 0);
end record;
constant AUTO_NEGOTATION_802_3_SELECTOR : std_ulogic_vector(4 downto 0) := "00001";
-- Selected conversion functions
-- Register records to 16-bit data values
function control_register_to_data(reg : in t_control_register) return t_data;
function auto_negotiation_advertisement_register_802_3_to_data(reg : in t_auto_negotiation_advertisement_register_802_3) return t_data;
function master_slave_control_register_to_data(reg : in t_master_slave_control_register) return t_data;
-- 16-bit data values to registers
function data_to_status_register(data : in t_data) return t_status_register;
function data_to_master_slave_status_register(data : in t_data) return t_master_slave_status_register;
function data_to_auto_negotiation_lp_base_page_ability_register(data : in t_data) return auto_negotiation_lp_base_page_ability_register_802_3_t;
end package;
package body miim_registers is
function control_register_to_data(reg : in t_control_register) return t_data is
variable data : t_data;
begin
data := (
15 => reg.reset,
14 => reg.loopback,
13 => reg.speed_10_100,
12 => reg.auto_negotiation_enable,
11 => reg.power_down,
10 => reg.isolate,
9 => reg.restart_auto_negotiation,
8 => reg.duplex_mode,
7 => reg.enable_collision_test,
6 => reg.speed_1000,
5 => reg.unidirectional_enable,
others => '0'
);
return data;
end function;
function auto_negotiation_advertisement_register_802_3_to_data(reg : in t_auto_negotiation_advertisement_register_802_3) return t_data is
variable data : t_data;
begin
data := (
15 => reg.next_page,
13 => reg.remote_fault,
12 => reg.extended_next_page,
11 => reg.asymmetric_pause,
10 => reg.pause,
9 => reg.advertise_100base_t4,
8 => reg.advertise_100base_tx_fd,
7 => reg.advertise_100base_tx_hd,
6 => reg.advertise_10base_t_fd,
5 => reg.advertise_10base_t_hd,
others => '0'
);
data(4 downto 0) := AUTO_NEGOTATION_802_3_SELECTOR;
return data;
end function;
function master_slave_control_register_to_data(reg : in t_master_slave_control_register) return t_data is
variable data : t_data;
begin
data := (
12 => reg.master_slave_manual_config_enable,
11 => reg.master_slave_manual_config_value,
10 => reg.port_type_is_multiport,
9 => reg.advertise_1000base_t_fd,
8 => reg.advertise_1000base_t_hd,
others => '0'
);
data(15 downto 13) := reg.test_mode_bits;
return data;
end function;
function data_to_status_register(data : in t_data) return t_status_register is
variable status : t_status_register;
begin
status := (
can_100base_t4 => data(15),
can_100base_x_fd => data(14),
can_100base_x_hd => data(13),
can_10mbps_fd => data(12),
can_10mbps_hd => data(11),
can_100base_t2_fd => data(10),
can_100base_t2_hd => data(9),
extended_status => data(8),
undirectional_ability => data(7),
mf_preamble_suppression => data(6),
auto_negotiation_complete => data(5),
remote_fault => data(4),
auto_negotiation_ability => data(3),
link_status => data(2),
jabber_detect => data(1),
extended_capability => data(0)
);
return status;
end function;
function data_to_master_slave_status_register(data : in t_data) return t_master_slave_status_register is
variable status : t_master_slave_status_register;
begin
status := (
master_slave_config_fault => data(15),
master_slave_config_resolution => data(14),
local_receiver_status => data(13),
remote_receiver_status => data(12),
lp_1000base_t_fd => data(11),
lp_1000base_t_hd => data(10),
idle_error_count => unsigned(data(7 downto 0))
);
return status;
end function;
function data_to_auto_negotiation_lp_base_page_ability_register(data : in t_data) return auto_negotiation_lp_base_page_ability_register_802_3_t is
variable ability : auto_negotiation_lp_base_page_ability_register_802_3_t;
begin
ability := (
next_page => data(15),
acknowledge => data(14),
remote_fault => data(13),
extended_next_page => data(12),
asymmetric_pause => data(11),
pause => data(10),
can_100base_t4 => data(9),
can_100base_tx_fd => data(8),
can_100base_tx_hd => data(7),
can_10base_t_fd => data(6),
can_10base_t_hd => data(5)
);
return ability;
end function;
end package body;
| bsd-3-clause | 0b923a6cdaf6ba360472d0a551074984 | 0.629496 | 3.126333 | false | false | false | false |
pkerling/ethernet_mac | xilinx/input_buffer.vhd | 1 | 1,844 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Configurable input buffer forced into the IO block
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity input_buffer is
generic(
-- If TRUE, fixed_input_delay is inserted between the pad and the flip-flop
HAS_DELAY : boolean := FALSE;
IDELAY_VALUE : natural range 0 to 255 := 0
);
port(
-- Connect to pad or IBUF
pad_i : in std_ulogic;
-- Connect to user logic
buffer_o : out std_ulogic;
-- Capture clock
clock_i : in std_ulogic
);
end entity;
architecture spartan_6 of input_buffer is
signal delayed : std_ulogic := '0';
-- Force putting input Flip-Flop into IOB so it doesn't end up in a normal logic tile
-- which would ruin the timing.
attribute iob : string;
attribute iob of FDRE_inst : label is "FORCE";
begin
-- When delay activated: Instantiate IODELAY2 and then capture its output
delay_gen : if HAS_DELAY = TRUE generate
fixed_input_delay_inst : entity work.fixed_input_delay
generic map(
IDELAY_VALUE => IDELAY_VALUE
)
port map(
pad_i => pad_i,
delayed_o => delayed
);
end generate;
-- When delay deactivated: Directly capture the signal
no_delay_gen : if HAS_DELAY = FALSE generate
delayed <= pad_i;
end generate;
FDRE_inst : FDRE
generic map(
INIT => '0') -- Initial value of register ('0' or '1')
port map(
Q => buffer_o, -- Data output
C => clock_i, -- Clock input
CE => '1', -- Clock enable input
R => '0', -- Synchronous reset input
D => delayed -- Data input
);
end architecture;
| bsd-3-clause | f391d3cbad76765ad8e482eda3db3d18 | 0.637202 | 3.499051 | false | false | false | false |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/project/altremote/simulation/submodules/altremote_remote_update_0.vhd | 3 | 113,598 | --altremote_update CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" check_app_pof="false" config_device_addr_width=24 DEVICE_FAMILY="Cyclone IV E" in_data_width=24 is_epcq="false" operation_mode="remote" out_data_width=29 busy clock data_in data_out param read_param read_source reconfig reset reset_timer write_param
--VERSION_BEGIN 14.0 cbx_altremote_update 2014:06:05:09:45:41:SJ cbx_cycloneii 2014:06:05:09:45:41:SJ cbx_lpm_add_sub 2014:06:05:09:45:41:SJ cbx_lpm_compare 2014:06:05:09:45:41:SJ cbx_lpm_counter 2014:06:05:09:45:41:SJ cbx_lpm_decode 2014:06:05:09:45:41:SJ cbx_lpm_shiftreg 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_nightfury 2014:06:05:09:45:41:SJ cbx_stratix 2014:06:05:09:45:41:SJ cbx_stratixii 2014:06:05:09:45:41:SJ VERSION_END
-- Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus II License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY cycloneive;
USE cycloneive.all;
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = cycloneive_rublock 1 lpm_counter 2 reg 62
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altremote_remote_update_0 IS
PORT
(
busy : OUT STD_LOGIC;
clock : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (23 DOWNTO 0) := (OTHERS => '0');
data_out : OUT STD_LOGIC_VECTOR (28 DOWNTO 0);
param : IN STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0');
read_param : IN STD_LOGIC := '0';
read_source : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
reconfig : IN STD_LOGIC := '0';
reset : IN STD_LOGIC;
reset_timer : IN STD_LOGIC := '0';
write_param : IN STD_LOGIC := '0'
);
END altremote_remote_update_0;
ARCHITECTURE RTL OF altremote_remote_update_0 IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "suppress_da_rule_internal=c104;suppress_da_rule_internal=C101;suppress_da_rule_internal=C103";
SIGNAL check_busy_dffe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dffe1a0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dffe1a1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dffe1a_ena : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL dffe2a0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dffe2a1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dffe2a2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dffe2a_ena : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL dffe3a0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dffe3a1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dffe3a2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dffe3a_ena : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL dffe7a : STD_LOGIC_VECTOR(28 DOWNTO 0)
-- synopsys translate_off
:= "00000000000000000000000000000"
-- synopsys translate_on
;
SIGNAL wire_dffe7a_ena : STD_LOGIC_VECTOR(28 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range335w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range340w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range345w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range350w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range355w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range360w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range365w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range370w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range380w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range385w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range395w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range400w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range405w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range300w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range305w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dffe7a_w_q_range320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL dffe8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dffe9a : STD_LOGIC_VECTOR(6 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_dffe9a_ena : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL idle_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL idle_write_wait : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_address_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_read_address_state_ena : STD_LOGIC;
SIGNAL read_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_init_counter_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_init_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_post_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_pre_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL read_source_update_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_init_counter_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_init_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_load_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_post_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_pre_data_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_source_update_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL write_wait_state : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_cntr5_w_lg_w_q_range39w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_cntr5_w_lg_w_q_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_cntr5_q : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cntr5_w_q_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_cntr5_w_q_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_cntr6_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_sd4_regout : STD_LOGIC;
SIGNAL wire_w1042w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1072w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1054w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1049w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1076w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1082w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1061w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1098w1099w1100w1101w1103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1098w1124w1125w1126w1127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1064w1110w1111w1112w1113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1064w1065w1066w1067w1068w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1064w1065w1133w1134w1135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1084w1092w1093w1094w1095w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1084w1085w1086w1087w1088w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1034w1037w1040w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1034w1070w1071w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1051w1052w1053w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1047w1048w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1047w1115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1074w1075w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1079w1080w1081w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1079w1137w1138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1105w1106w1107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1058w1059w1060w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1058w1129w1130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1056w1118w1119w1120w1121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_w1056w1118w1141w1142w1143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1098w1099w1100w1101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1098w1124w1125w1126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1064w1110w1111w1112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1064w1065w1066w1067w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1064w1065w1133w1134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1084w1092w1093w1094w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1084w1085w1086w1087w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1031w1034w1037w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1031w1034w1070w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1031w1051w1052w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1045w1046w1047w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1045w1046w1074w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1045w1079w1080w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1028w1045w1079w1137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1056w1057w1105w1106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1056w1057w1058w1059w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1056w1057w1058w1129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1056w1118w1119w1120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w1056w1118w1141w1142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1098w1099w1100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1098w1124w1125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1064w1110w1111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1064w1065w1066w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1064w1065w1133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1084w1092w1093w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1084w1085w1086w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1028w1031w1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1028w1031w1051w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1028w1045w1046w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1028w1045w1079w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1056w1057w1105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1056w1057w1058w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1056w1118w1119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w1056w1118w1141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w235w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1098w1099w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1098w1124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1064w1110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1064w1065w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1084w1092w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1084w1085w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1028w1031w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1028w1045w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1056w1057w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1056w1118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_idle1179w1180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_param_range109w110w111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1098w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1064w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1084w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w240w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w356w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w366w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w371w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w386w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w401w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w301w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address278w321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_rsource_load13w14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_rsource_load13w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_rsource_load13w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_rsource_load13w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_rsource_load13w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w232w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w239w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable101w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1028w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w1056w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_source_update1237w1238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_idle1179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address347w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address352w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address357w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address362w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address377w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address392w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address297w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address302w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address307w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_data1196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_init_counter1192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_post1202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_pre_data1191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rublock_regout_reg1243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable230w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable244w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_data1214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_init_counter1211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_post_data1220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_pre_data1210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_range109w110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1024w1097w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1024w1063w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_w4w_range1264w1265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_w4w_range1268w1269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_bit_counter_all_done1213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_bit_counter_param_start_match1190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_idle1160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_address278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_data1155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_init1159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_init_counter1157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_post1154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_pre_data1156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_source_update1158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_update_done1187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_select_shift_nloop1242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w1w1178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w2w1177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w8w274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_width_counter_all_done1194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_width_counter_param_width_match1195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_data1149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_init1153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_init_counter1152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_load1147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_post_data1148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_pre_data1150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_source_update1151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_write_wait1146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_wsource_update_done1207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_range107w108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1024w1025w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1026w1027w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1029w1030w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1032w1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1035w1036w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1038w1039w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_param_decoder_param_latch_range1041w1102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w250w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_idle1179w1180w1181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address287w288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address337w338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address342w343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address347w348w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address352w353w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address357w358w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address362w363w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address367w368w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address372w373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address377w378w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address382w383w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address292w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address387w388w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address392w393w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address397w398w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address402w403w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address407w408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address412w413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address417w418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address297w298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address302w303w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address307w308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address312w313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address317w318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address322w323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address327w328w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_read_address332w333w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_w4w_range1264w1265w1266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_w4w_range1268w1269w1270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_shift_reg_load_enable99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_read_source_update1237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_rsource_load9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_shift_reg_load_enable99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL bit_counter_all_done : STD_LOGIC;
SIGNAL bit_counter_clear : STD_LOGIC;
SIGNAL bit_counter_enable : STD_LOGIC;
SIGNAL bit_counter_param_start : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL bit_counter_param_start_match : STD_LOGIC;
SIGNAL combine_port : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL global_gnd : STD_LOGIC;
SIGNAL global_vcc : STD_LOGIC;
SIGNAL idle : STD_LOGIC;
SIGNAL param_decoder_param_latch : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL param_decoder_select : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL power_up : STD_LOGIC;
SIGNAL read_address : STD_LOGIC;
SIGNAL read_data : STD_LOGIC;
SIGNAL read_init : STD_LOGIC;
SIGNAL read_init_counter : STD_LOGIC;
SIGNAL read_post : STD_LOGIC;
SIGNAL read_pre_data : STD_LOGIC;
SIGNAL read_source_update : STD_LOGIC;
SIGNAL rsource_load : STD_LOGIC;
SIGNAL rsource_parallel_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL rsource_serial_out : STD_LOGIC;
SIGNAL rsource_shift_enable : STD_LOGIC;
SIGNAL rsource_state_par_ini : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL rsource_update_done : STD_LOGIC;
SIGNAL rublock_captnupdt : STD_LOGIC;
SIGNAL rublock_clock : STD_LOGIC;
SIGNAL rublock_reconfig : STD_LOGIC;
SIGNAL rublock_reconfig_st : STD_LOGIC;
SIGNAL rublock_regin : STD_LOGIC;
SIGNAL rublock_regout : STD_LOGIC;
SIGNAL rublock_regout_reg : STD_LOGIC;
SIGNAL rublock_shiftnld : STD_LOGIC;
SIGNAL select_shift_nloop : STD_LOGIC;
SIGNAL shift_reg_clear : STD_LOGIC;
SIGNAL shift_reg_load_enable : STD_LOGIC;
SIGNAL shift_reg_serial_in : STD_LOGIC;
SIGNAL shift_reg_serial_out : STD_LOGIC;
SIGNAL shift_reg_shift_enable : STD_LOGIC;
SIGNAL start_bit_decoder_out : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL start_bit_decoder_param_select : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL w1w : STD_LOGIC;
SIGNAL w2w : STD_LOGIC;
SIGNAL w4w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL w53w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL w83w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL w8w : STD_LOGIC;
SIGNAL width_counter_all_done : STD_LOGIC;
SIGNAL width_counter_clear : STD_LOGIC;
SIGNAL width_counter_enable : STD_LOGIC;
SIGNAL width_counter_param_width : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL width_counter_param_width_match : STD_LOGIC;
SIGNAL width_decoder_out : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL width_decoder_param_select : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL write_data : STD_LOGIC;
SIGNAL write_init : STD_LOGIC;
SIGNAL write_init_counter : STD_LOGIC;
SIGNAL write_load : STD_LOGIC;
SIGNAL write_post_data : STD_LOGIC;
SIGNAL write_pre_data : STD_LOGIC;
SIGNAL write_source_update : STD_LOGIC;
SIGNAL write_wait : STD_LOGIC;
SIGNAL wsource_state_par_ini : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wsource_update_done : STD_LOGIC;
SIGNAL wire_w_data_in_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_in_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_range109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1024w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1026w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1029w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1032w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1035w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1038w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_param_decoder_param_latch_range1041w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rsource_parallel_in_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rsource_state_par_ini_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rsource_state_par_ini_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_w4w_range1264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_w4w_range1268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_wsource_state_par_ini_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_wsource_state_par_ini_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_counter
GENERIC
(
lpm_avalue : STRING := "0";
lpm_direction : STRING := "DEFAULT";
lpm_modulus : NATURAL := 0;
lpm_port_updown : STRING := "PORT_CONNECTIVITY";
lpm_pvalue : STRING := "0";
lpm_svalue : STRING := "0";
lpm_width : NATURAL;
lpm_type : STRING := "lpm_counter"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aload : IN STD_LOGIC := '0';
aset : IN STD_LOGIC := '0';
cin : IN STD_LOGIC := '1';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
cout : OUT STD_LOGIC;
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0';
sset : IN STD_LOGIC := '0';
updown : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT cycloneive_rublock
PORT
(
captnupdt : IN STD_LOGIC;
clk : IN STD_LOGIC;
rconfig : IN STD_LOGIC;
regin : IN STD_LOGIC;
regout : OUT STD_LOGIC;
rsttimer : IN STD_LOGIC;
shiftnld : IN STD_LOGIC
);
END COMPONENT;
BEGIN
wire_w1042w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1034w1037w1040w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1072w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1034w1070w1071w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1054w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1051w1052w1053w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1049w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1047w1048w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1116w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1047w1115w(0) AND wire_w_lg_w_param_decoder_param_latch_range1041w1102w(0);
wire_w1076w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1074w1075w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1082w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1079w1080w1081w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1139w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1079w1137w1138w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1108w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1105w1106w1107w(0) AND wire_w_lg_w_param_decoder_param_latch_range1041w1102w(0);
wire_w1061w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1058w1059w1060w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1131w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1058w1129w1130w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w1122w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1056w1118w1119w1120w1121w(0) AND wire_w_lg_w_param_decoder_param_latch_range1041w1102w(0);
wire_w1144w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1056w1118w1141w1142w1143w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1098w1099w1100w1101w1103w(0) <= wire_w_lg_w_lg_w_lg_w1098w1099w1100w1101w(0) AND wire_w_lg_w_param_decoder_param_latch_range1041w1102w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1098w1124w1125w1126w1127w(0) <= wire_w_lg_w_lg_w_lg_w1098w1124w1125w1126w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1064w1110w1111w1112w1113w(0) <= wire_w_lg_w_lg_w_lg_w1064w1110w1111w1112w(0) AND wire_w_lg_w_param_decoder_param_latch_range1041w1102w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1064w1065w1066w1067w1068w(0) <= wire_w_lg_w_lg_w_lg_w1064w1065w1066w1067w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1064w1065w1133w1134w1135w(0) <= wire_w_lg_w_lg_w_lg_w1064w1065w1133w1134w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1084w1092w1093w1094w1095w(0) <= wire_w_lg_w_lg_w_lg_w1084w1092w1093w1094w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1084w1085w1086w1087w1088w(0) <= wire_w_lg_w_lg_w_lg_w1084w1085w1086w1087w(0) AND wire_w_param_decoder_param_latch_range1041w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1034w1037w1040w(0) <= wire_w_lg_w_lg_w_lg_w1028w1031w1034w1037w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1034w1070w1071w(0) <= wire_w_lg_w_lg_w_lg_w1028w1031w1034w1070w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1031w1051w1052w1053w(0) <= wire_w_lg_w_lg_w_lg_w1028w1031w1051w1052w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1047w1048w(0) <= wire_w_lg_w_lg_w_lg_w1028w1045w1046w1047w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1047w1115w(0) <= wire_w_lg_w_lg_w_lg_w1028w1045w1046w1047w(0) AND wire_w_param_decoder_param_latch_range1038w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1046w1074w1075w(0) <= wire_w_lg_w_lg_w_lg_w1028w1045w1046w1074w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1079w1080w1081w(0) <= wire_w_lg_w_lg_w_lg_w1028w1045w1079w1080w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1028w1045w1079w1137w1138w(0) <= wire_w_lg_w_lg_w_lg_w1028w1045w1079w1137w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1105w1106w1107w(0) <= wire_w_lg_w_lg_w_lg_w1056w1057w1105w1106w(0) AND wire_w_param_decoder_param_latch_range1038w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1058w1059w1060w(0) <= wire_w_lg_w_lg_w_lg_w1056w1057w1058w1059w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1056w1057w1058w1129w1130w(0) <= wire_w_lg_w_lg_w_lg_w1056w1057w1058w1129w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1056w1118w1119w1120w1121w(0) <= wire_w_lg_w_lg_w_lg_w1056w1118w1119w1120w(0) AND wire_w_param_decoder_param_latch_range1038w(0);
wire_w_lg_w_lg_w_lg_w_lg_w1056w1118w1141w1142w1143w(0) <= wire_w_lg_w_lg_w_lg_w1056w1118w1141w1142w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w1098w1099w1100w1101w(0) <= wire_w_lg_w_lg_w1098w1099w1100w(0) AND wire_w_param_decoder_param_latch_range1038w(0);
wire_w_lg_w_lg_w_lg_w1098w1124w1125w1126w(0) <= wire_w_lg_w_lg_w1098w1124w1125w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w1064w1110w1111w1112w(0) <= wire_w_lg_w_lg_w1064w1110w1111w(0) AND wire_w_param_decoder_param_latch_range1038w(0);
wire_w_lg_w_lg_w_lg_w1064w1065w1066w1067w(0) <= wire_w_lg_w_lg_w1064w1065w1066w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w1064w1065w1133w1134w(0) <= wire_w_lg_w_lg_w1064w1065w1133w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w1084w1092w1093w1094w(0) <= wire_w_lg_w_lg_w1084w1092w1093w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w1084w1085w1086w1087w(0) <= wire_w_lg_w_lg_w1084w1085w1086w(0) AND wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0);
wire_w_lg_w_lg_w_lg_w1028w1031w1034w1037w(0) <= wire_w_lg_w_lg_w1028w1031w1034w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1028w1031w1034w1070w(0) <= wire_w_lg_w_lg_w1028w1031w1034w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w_lg_w1028w1031w1051w1052w(0) <= wire_w_lg_w_lg_w1028w1031w1051w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1028w1045w1046w1047w(0) <= wire_w_lg_w_lg_w1028w1045w1046w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1028w1045w1046w1074w(0) <= wire_w_lg_w_lg_w1028w1045w1046w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w_lg_w1028w1045w1079w1080w(0) <= wire_w_lg_w_lg_w1028w1045w1079w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1028w1045w1079w1137w(0) <= wire_w_lg_w_lg_w1028w1045w1079w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w_lg_w1056w1057w1105w1106w(0) <= wire_w_lg_w_lg_w1056w1057w1105w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1056w1057w1058w1059w(0) <= wire_w_lg_w_lg_w1056w1057w1058w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1056w1057w1058w1129w(0) <= wire_w_lg_w_lg_w1056w1057w1058w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w_lg_w1056w1118w1119w1120w(0) <= wire_w_lg_w_lg_w1056w1118w1119w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w_lg_w1056w1118w1141w1142w(0) <= wire_w_lg_w_lg_w1056w1118w1141w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w1098w1099w1100w(0) <= wire_w_lg_w1098w1099w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w1098w1124w1125w(0) <= wire_w_lg_w1098w1124w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w1064w1110w1111w(0) <= wire_w_lg_w1064w1110w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w1064w1065w1066w(0) <= wire_w_lg_w1064w1065w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w1064w1065w1133w(0) <= wire_w_lg_w1064w1065w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w1084w1092w1093w(0) <= wire_w_lg_w1084w1092w(0) AND wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_lg_w1084w1085w1086w(0) <= wire_w_lg_w1084w1085w(0) AND wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0);
wire_w_lg_w_lg_w1028w1031w1034w(0) <= wire_w_lg_w1028w1031w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w_lg_w1028w1031w1051w(0) <= wire_w_lg_w1028w1031w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w_lg_w1028w1045w1046w(0) <= wire_w_lg_w1028w1045w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w_lg_w1028w1045w1079w(0) <= wire_w_lg_w1028w1045w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w_lg_w1056w1057w1105w(0) <= wire_w_lg_w1056w1057w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w_lg_w1056w1057w1058w(0) <= wire_w_lg_w1056w1057w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w_lg_w1056w1118w1119w(0) <= wire_w_lg_w1056w1118w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w_lg_w1056w1118w1141w(0) <= wire_w_lg_w1056w1118w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w172w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range171w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w179w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range178w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w186w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range185w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w193w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range192w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w200w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range199w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w207w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range206w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w214w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range213w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w221w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range220w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w228w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range227w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w235w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range234w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w242w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range241w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w249w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range248w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w256w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range255w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w263w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range262w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w115w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range114w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w123w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range122w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w130w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range129w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w137w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range136w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w144w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range143w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w151w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range150w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w158w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range157w(0);
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w165w(0) <= wire_w_lg_w_lg_w_param_range109w110w111w(0) AND wire_w_data_in_range164w(0);
wire_w_lg_w1098w1099w(0) <= wire_w1098w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w1098w1124w(0) <= wire_w1098w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w1064w1110w(0) <= wire_w1064w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w1064w1065w(0) <= wire_w1064w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w1084w1092w(0) <= wire_w1084w(0) AND wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0);
wire_w_lg_w1084w1085w(0) <= wire_w1084w(0) AND wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w1028w1031w(0) <= wire_w1028w(0) AND wire_w_lg_w_param_decoder_param_latch_range1029w1030w(0);
wire_w_lg_w1028w1045w(0) <= wire_w1028w(0) AND wire_w_param_decoder_param_latch_range1029w(0);
wire_w_lg_w1056w1057w(0) <= wire_w1056w(0) AND wire_w_lg_w_param_decoder_param_latch_range1029w1030w(0);
wire_w_lg_w1056w1118w(0) <= wire_w1056w(0) AND wire_w_param_decoder_param_latch_range1029w(0);
wire_w_lg_w_lg_idle1179w1180w(0) <= wire_w_lg_idle1179w(0) AND wire_w_lg_w2w1177w(0);
wire_w_lg_w_lg_w_param_range109w110w111w(0) <= wire_w_lg_w_param_range109w110w(0) AND wire_w_lg_w_param_range105w106w(0);
wire_w1098w(0) <= wire_w_lg_w_param_decoder_param_latch_range1024w1097w(0) AND wire_w_lg_w_param_decoder_param_latch_range1029w1030w(0);
wire_w1064w(0) <= wire_w_lg_w_param_decoder_param_latch_range1024w1063w(0) AND wire_w_lg_w_param_decoder_param_latch_range1029w1030w(0);
wire_w1084w(0) <= wire_w_lg_w_param_decoder_param_latch_range1024w1063w(0) AND wire_w_param_decoder_param_latch_range1029w(0);
wire_w113w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range104w(0);
wire_w184w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range171w(0);
wire_w191w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range178w(0);
wire_w198w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range185w(0);
wire_w205w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range192w(0);
wire_w212w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range199w(0);
wire_w219w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range206w(0);
wire_w226w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range213w(0);
wire_w233w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range220w(0);
wire_w240w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range227w(0);
wire_w247w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range234w(0);
wire_w121w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range120w(0);
wire_w254w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range241w(0);
wire_w261w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range248w(0);
wire_w128w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range114w(0);
wire_w135w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range122w(0);
wire_w142w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range129w(0);
wire_w149w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range136w(0);
wire_w156w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range143w(0);
wire_w163w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range150w(0);
wire_w170w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range157w(0);
wire_w177w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) AND wire_w_data_in_range164w(0);
wire_w_lg_w_lg_read_address278w279w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range277w(0);
wire_w_lg_w_lg_read_address278w326w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range325w(0);
wire_w_lg_w_lg_read_address278w331w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range330w(0);
wire_w_lg_w_lg_read_address278w336w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range335w(0);
wire_w_lg_w_lg_read_address278w341w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range340w(0);
wire_w_lg_w_lg_read_address278w346w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range345w(0);
wire_w_lg_w_lg_read_address278w351w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range350w(0);
wire_w_lg_w_lg_read_address278w356w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range355w(0);
wire_w_lg_w_lg_read_address278w361w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range360w(0);
wire_w_lg_w_lg_read_address278w366w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range365w(0);
wire_w_lg_w_lg_read_address278w371w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range370w(0);
wire_w_lg_w_lg_read_address278w283w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range282w(0);
wire_w_lg_w_lg_read_address278w376w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range375w(0);
wire_w_lg_w_lg_read_address278w381w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range380w(0);
wire_w_lg_w_lg_read_address278w386w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range385w(0);
wire_w_lg_w_lg_read_address278w391w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range390w(0);
wire_w_lg_w_lg_read_address278w396w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range395w(0);
wire_w_lg_w_lg_read_address278w401w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range400w(0);
wire_w_lg_w_lg_read_address278w406w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range405w(0);
wire_w_lg_w_lg_read_address278w411w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range410w(0);
wire_w_lg_w_lg_read_address278w416w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range415w(0);
wire_w_lg_w_lg_read_address278w286w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range285w(0);
wire_w_lg_w_lg_read_address278w291w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range290w(0);
wire_w_lg_w_lg_read_address278w296w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range295w(0);
wire_w_lg_w_lg_read_address278w301w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range300w(0);
wire_w_lg_w_lg_read_address278w306w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range305w(0);
wire_w_lg_w_lg_read_address278w311w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range310w(0);
wire_w_lg_w_lg_read_address278w316w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range315w(0);
wire_w_lg_w_lg_read_address278w321w(0) <= wire_w_lg_read_address278w(0) AND wire_dffe7a_w_q_range320w(0);
wire_w_lg_w_lg_rsource_load13w14w(0) <= wire_w_lg_rsource_load13w(0) AND dffe1a1;
wire_w_lg_w_lg_rsource_load13w21w(0) <= wire_w_lg_rsource_load13w(0) AND dffe2a1;
wire_w_lg_w_lg_rsource_load13w25w(0) <= wire_w_lg_rsource_load13w(0) AND dffe2a2;
wire_w_lg_w_lg_rsource_load13w31w(0) <= wire_w_lg_rsource_load13w(0) AND dffe3a1;
wire_w_lg_w_lg_rsource_load13w35w(0) <= wire_w_lg_rsource_load13w(0) AND dffe3a2;
wire_w_lg_w_lg_shift_reg_load_enable101w103w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(1);
wire_w_lg_w_lg_shift_reg_load_enable101w176w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(10);
wire_w_lg_w_lg_shift_reg_load_enable101w183w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(11);
wire_w_lg_w_lg_shift_reg_load_enable101w190w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(12);
wire_w_lg_w_lg_shift_reg_load_enable101w197w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(13);
wire_w_lg_w_lg_shift_reg_load_enable101w204w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(14);
wire_w_lg_w_lg_shift_reg_load_enable101w211w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(15);
wire_w_lg_w_lg_shift_reg_load_enable101w218w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(16);
wire_w_lg_w_lg_shift_reg_load_enable101w225w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(17);
wire_w_lg_w_lg_shift_reg_load_enable101w232w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(18);
wire_w_lg_w_lg_shift_reg_load_enable101w239w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(19);
wire_w_lg_w_lg_shift_reg_load_enable101w119w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(2);
wire_w_lg_w_lg_shift_reg_load_enable101w246w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(20);
wire_w_lg_w_lg_shift_reg_load_enable101w253w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(21);
wire_w_lg_w_lg_shift_reg_load_enable101w260w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(22);
wire_w_lg_w_lg_shift_reg_load_enable101w127w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(3);
wire_w_lg_w_lg_shift_reg_load_enable101w134w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(4);
wire_w_lg_w_lg_shift_reg_load_enable101w141w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(5);
wire_w_lg_w_lg_shift_reg_load_enable101w148w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(6);
wire_w_lg_w_lg_shift_reg_load_enable101w155w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(7);
wire_w_lg_w_lg_shift_reg_load_enable101w162w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(8);
wire_w_lg_w_lg_shift_reg_load_enable101w169w(0) <= wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(9);
wire_w1028w(0) <= wire_w_lg_w_param_decoder_param_latch_range1024w1025w(0) AND wire_w_lg_w_param_decoder_param_latch_range1026w1027w(0);
wire_w1056w(0) <= wire_w_lg_w_param_decoder_param_latch_range1024w1025w(0) AND wire_w_param_decoder_param_latch_range1026w(0);
wire_w_lg_w_lg_read_source_update1237w1238w(0) <= wire_w_lg_read_source_update1237w(0) AND rsource_serial_out;
wire_w_lg_idle1179w(0) <= idle AND wire_w_lg_w1w1178w(0);
wire_w_lg_read_address287w(0) <= read_address AND wire_dffe7a_w_q_range277w(0);
wire_w_lg_read_address337w(0) <= read_address AND wire_dffe7a_w_q_range325w(0);
wire_w_lg_read_address342w(0) <= read_address AND wire_dffe7a_w_q_range330w(0);
wire_w_lg_read_address347w(0) <= read_address AND wire_dffe7a_w_q_range335w(0);
wire_w_lg_read_address352w(0) <= read_address AND wire_dffe7a_w_q_range340w(0);
wire_w_lg_read_address357w(0) <= read_address AND wire_dffe7a_w_q_range345w(0);
wire_w_lg_read_address362w(0) <= read_address AND wire_dffe7a_w_q_range350w(0);
wire_w_lg_read_address367w(0) <= read_address AND wire_dffe7a_w_q_range355w(0);
wire_w_lg_read_address372w(0) <= read_address AND wire_dffe7a_w_q_range360w(0);
wire_w_lg_read_address377w(0) <= read_address AND wire_dffe7a_w_q_range365w(0);
wire_w_lg_read_address382w(0) <= read_address AND wire_dffe7a_w_q_range370w(0);
wire_w_lg_read_address292w(0) <= read_address AND wire_dffe7a_w_q_range282w(0);
wire_w_lg_read_address387w(0) <= read_address AND wire_dffe7a_w_q_range375w(0);
wire_w_lg_read_address392w(0) <= read_address AND wire_dffe7a_w_q_range380w(0);
wire_w_lg_read_address397w(0) <= read_address AND wire_dffe7a_w_q_range385w(0);
wire_w_lg_read_address402w(0) <= read_address AND wire_dffe7a_w_q_range390w(0);
wire_w_lg_read_address407w(0) <= read_address AND wire_dffe7a_w_q_range395w(0);
wire_w_lg_read_address412w(0) <= read_address AND wire_dffe7a_w_q_range400w(0);
wire_w_lg_read_address417w(0) <= read_address AND wire_dffe7a_w_q_range405w(0);
wire_w_lg_read_address297w(0) <= read_address AND wire_dffe7a_w_q_range285w(0);
wire_w_lg_read_address302w(0) <= read_address AND wire_dffe7a_w_q_range290w(0);
wire_w_lg_read_address307w(0) <= read_address AND wire_dffe7a_w_q_range295w(0);
wire_w_lg_read_address312w(0) <= read_address AND wire_dffe7a_w_q_range300w(0);
wire_w_lg_read_address317w(0) <= read_address AND wire_dffe7a_w_q_range305w(0);
wire_w_lg_read_address322w(0) <= read_address AND wire_dffe7a_w_q_range310w(0);
wire_w_lg_read_address327w(0) <= read_address AND wire_dffe7a_w_q_range315w(0);
wire_w_lg_read_address332w(0) <= read_address AND wire_dffe7a_w_q_range320w(0);
wire_w_lg_read_data1196w(0) <= read_data AND wire_w_lg_width_counter_param_width_match1195w(0);
wire_w_lg_read_init_counter1192w(0) <= read_init_counter AND wire_w_lg_bit_counter_param_start_match1190w(0);
wire_w_lg_read_post1202w(0) <= read_post AND wire_w_lg_width_counter_all_done1194w(0);
wire_w_lg_read_pre_data1191w(0) <= read_pre_data AND wire_w_lg_bit_counter_param_start_match1190w(0);
wire_w_lg_rsource_load16w(0) <= rsource_load AND wire_w_rsource_parallel_in_range15w(0);
wire_w_lg_rsource_load23w(0) <= rsource_load AND wire_w_rsource_state_par_ini_range22w(0);
wire_w_lg_rsource_load27w(0) <= rsource_load AND wire_w_rsource_state_par_ini_range26w(0);
wire_w_lg_rsource_load33w(0) <= rsource_load AND wire_w_wsource_state_par_ini_range32w(0);
wire_w_lg_rsource_load37w(0) <= rsource_load AND wire_w_wsource_state_par_ini_range36w(0);
wire_w_lg_rublock_regout_reg1243w(0) <= rublock_regout_reg AND wire_w_lg_select_shift_nloop1242w(0);
wire_w_lg_shift_reg_load_enable174w(0) <= shift_reg_load_enable AND wire_w173w(0);
wire_w_lg_shift_reg_load_enable181w(0) <= shift_reg_load_enable AND wire_w180w(0);
wire_w_lg_shift_reg_load_enable188w(0) <= shift_reg_load_enable AND wire_w187w(0);
wire_w_lg_shift_reg_load_enable195w(0) <= shift_reg_load_enable AND wire_w194w(0);
wire_w_lg_shift_reg_load_enable202w(0) <= shift_reg_load_enable AND wire_w201w(0);
wire_w_lg_shift_reg_load_enable209w(0) <= shift_reg_load_enable AND wire_w208w(0);
wire_w_lg_shift_reg_load_enable216w(0) <= shift_reg_load_enable AND wire_w215w(0);
wire_w_lg_shift_reg_load_enable223w(0) <= shift_reg_load_enable AND wire_w222w(0);
wire_w_lg_shift_reg_load_enable230w(0) <= shift_reg_load_enable AND wire_w229w(0);
wire_w_lg_shift_reg_load_enable237w(0) <= shift_reg_load_enable AND wire_w236w(0);
wire_w_lg_shift_reg_load_enable244w(0) <= shift_reg_load_enable AND wire_w243w(0);
wire_w_lg_shift_reg_load_enable251w(0) <= shift_reg_load_enable AND wire_w250w(0);
wire_w_lg_shift_reg_load_enable258w(0) <= shift_reg_load_enable AND wire_w257w(0);
wire_w_lg_shift_reg_load_enable265w(0) <= shift_reg_load_enable AND wire_w264w(0);
wire_w_lg_shift_reg_load_enable117w(0) <= shift_reg_load_enable AND wire_w116w(0);
wire_w_lg_shift_reg_load_enable125w(0) <= shift_reg_load_enable AND wire_w124w(0);
wire_w_lg_shift_reg_load_enable132w(0) <= shift_reg_load_enable AND wire_w131w(0);
wire_w_lg_shift_reg_load_enable139w(0) <= shift_reg_load_enable AND wire_w138w(0);
wire_w_lg_shift_reg_load_enable146w(0) <= shift_reg_load_enable AND wire_w145w(0);
wire_w_lg_shift_reg_load_enable153w(0) <= shift_reg_load_enable AND wire_w152w(0);
wire_w_lg_shift_reg_load_enable160w(0) <= shift_reg_load_enable AND wire_w159w(0);
wire_w_lg_shift_reg_load_enable167w(0) <= shift_reg_load_enable AND wire_w166w(0);
wire_w_lg_write_data1214w(0) <= write_data AND wire_w_lg_width_counter_param_width_match1195w(0);
wire_w_lg_write_init_counter1211w(0) <= write_init_counter AND wire_w_lg_bit_counter_param_start_match1190w(0);
wire_w_lg_write_post_data1220w(0) <= write_post_data AND wire_w_lg_bit_counter_all_done1213w(0);
wire_w_lg_write_pre_data1210w(0) <= write_pre_data AND wire_w_lg_bit_counter_param_start_match1190w(0);
wire_w_lg_w_param_range109w110w(0) <= wire_w_param_range109w(0) AND wire_w_lg_w_param_range107w108w(0);
wire_w_lg_w_param_decoder_param_latch_range1024w1097w(0) <= wire_w_param_decoder_param_latch_range1024w(0) AND wire_w_lg_w_param_decoder_param_latch_range1026w1027w(0);
wire_w_lg_w_param_decoder_param_latch_range1024w1063w(0) <= wire_w_param_decoder_param_latch_range1024w(0) AND wire_w_param_decoder_param_latch_range1026w(0);
wire_w_lg_w_w4w_range1264w1265w(0) <= wire_w_w4w_range1264w(0) AND w1w;
wire_w_lg_w_w4w_range1268w1269w(0) <= wire_w_w4w_range1268w(0) AND w1w;
wire_w_lg_w_lg_w_lg_w_param_range109w110w111w112w(0) <= NOT wire_w_lg_w_lg_w_param_range109w110w111w(0);
wire_w_lg_bit_counter_all_done1213w(0) <= NOT bit_counter_all_done;
wire_w_lg_bit_counter_param_start_match1190w(0) <= NOT bit_counter_param_start_match;
wire_w_lg_idle1160w(0) <= NOT idle;
wire_w_lg_read_address278w(0) <= NOT read_address;
wire_w_lg_read_data1155w(0) <= NOT read_data;
wire_w_lg_read_init1159w(0) <= NOT read_init;
wire_w_lg_read_init_counter1157w(0) <= NOT read_init_counter;
wire_w_lg_read_post1154w(0) <= NOT read_post;
wire_w_lg_read_pre_data1156w(0) <= NOT read_pre_data;
wire_w_lg_read_source_update1158w(0) <= NOT read_source_update;
wire_w_lg_rsource_load13w(0) <= NOT rsource_load;
wire_w_lg_rsource_update_done1187w(0) <= NOT rsource_update_done;
wire_w_lg_select_shift_nloop1242w(0) <= NOT select_shift_nloop;
wire_w_lg_shift_reg_load_enable101w(0) <= NOT shift_reg_load_enable;
wire_w_lg_w1w1178w(0) <= NOT w1w;
wire_w_lg_w2w1177w(0) <= NOT w2w;
wire_w_lg_w8w274w(0) <= NOT w8w;
wire_w_lg_width_counter_all_done1194w(0) <= NOT width_counter_all_done;
wire_w_lg_width_counter_param_width_match1195w(0) <= NOT width_counter_param_width_match;
wire_w_lg_write_data1149w(0) <= NOT write_data;
wire_w_lg_write_init1153w(0) <= NOT write_init;
wire_w_lg_write_init_counter1152w(0) <= NOT write_init_counter;
wire_w_lg_write_load1147w(0) <= NOT write_load;
wire_w_lg_write_post_data1148w(0) <= NOT write_post_data;
wire_w_lg_write_pre_data1150w(0) <= NOT write_pre_data;
wire_w_lg_write_source_update1151w(0) <= NOT write_source_update;
wire_w_lg_write_wait1146w(0) <= NOT write_wait;
wire_w_lg_wsource_update_done1207w(0) <= NOT wsource_update_done;
wire_w_lg_w_param_range105w106w(0) <= NOT wire_w_param_range105w(0);
wire_w_lg_w_param_range107w108w(0) <= NOT wire_w_param_range107w(0);
wire_w_lg_w_param_decoder_param_latch_range1024w1025w(0) <= NOT wire_w_param_decoder_param_latch_range1024w(0);
wire_w_lg_w_param_decoder_param_latch_range1026w1027w(0) <= NOT wire_w_param_decoder_param_latch_range1026w(0);
wire_w_lg_w_param_decoder_param_latch_range1029w1030w(0) <= NOT wire_w_param_decoder_param_latch_range1029w(0);
wire_w_lg_w_param_decoder_param_latch_range1032w1033w(0) <= NOT wire_w_param_decoder_param_latch_range1032w(0);
wire_w_lg_w_param_decoder_param_latch_range1035w1036w(0) <= NOT wire_w_param_decoder_param_latch_range1035w(0);
wire_w_lg_w_param_decoder_param_latch_range1038w1039w(0) <= NOT wire_w_param_decoder_param_latch_range1038w(0);
wire_w_lg_w_param_decoder_param_latch_range1041w1102w(0) <= NOT wire_w_param_decoder_param_latch_range1041w(0);
wire_w173w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w172w(0) OR wire_w170w(0);
wire_w180w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w179w(0) OR wire_w177w(0);
wire_w187w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w186w(0) OR wire_w184w(0);
wire_w194w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w193w(0) OR wire_w191w(0);
wire_w201w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w200w(0) OR wire_w198w(0);
wire_w208w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w207w(0) OR wire_w205w(0);
wire_w215w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w214w(0) OR wire_w212w(0);
wire_w222w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w221w(0) OR wire_w219w(0);
wire_w229w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w228w(0) OR wire_w226w(0);
wire_w236w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w235w(0) OR wire_w233w(0);
wire_w243w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w242w(0) OR wire_w240w(0);
wire_w250w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w249w(0) OR wire_w247w(0);
wire_w257w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w256w(0) OR wire_w254w(0);
wire_w264w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w263w(0) OR wire_w261w(0);
wire_w116w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w115w(0) OR wire_w113w(0);
wire_w124w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w123w(0) OR wire_w121w(0);
wire_w131w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w130w(0) OR wire_w128w(0);
wire_w138w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w137w(0) OR wire_w135w(0);
wire_w145w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w144w(0) OR wire_w142w(0);
wire_w152w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w151w(0) OR wire_w149w(0);
wire_w159w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w158w(0) OR wire_w156w(0);
wire_w166w(0) <= wire_w_lg_w_lg_w_lg_w_param_range109w110w111w165w(0) OR wire_w163w(0);
wire_w_lg_w_lg_w_lg_idle1179w1180w1181w(0) <= wire_w_lg_w_lg_idle1179w1180w(0) OR write_wait;
wire_w_lg_w_lg_read_address287w288w(0) <= wire_w_lg_read_address287w(0) OR wire_w_lg_w_lg_read_address278w286w(0);
wire_w_lg_w_lg_read_address337w338w(0) <= wire_w_lg_read_address337w(0) OR wire_w_lg_w_lg_read_address278w336w(0);
wire_w_lg_w_lg_read_address342w343w(0) <= wire_w_lg_read_address342w(0) OR wire_w_lg_w_lg_read_address278w341w(0);
wire_w_lg_w_lg_read_address347w348w(0) <= wire_w_lg_read_address347w(0) OR wire_w_lg_w_lg_read_address278w346w(0);
wire_w_lg_w_lg_read_address352w353w(0) <= wire_w_lg_read_address352w(0) OR wire_w_lg_w_lg_read_address278w351w(0);
wire_w_lg_w_lg_read_address357w358w(0) <= wire_w_lg_read_address357w(0) OR wire_w_lg_w_lg_read_address278w356w(0);
wire_w_lg_w_lg_read_address362w363w(0) <= wire_w_lg_read_address362w(0) OR wire_w_lg_w_lg_read_address278w361w(0);
wire_w_lg_w_lg_read_address367w368w(0) <= wire_w_lg_read_address367w(0) OR wire_w_lg_w_lg_read_address278w366w(0);
wire_w_lg_w_lg_read_address372w373w(0) <= wire_w_lg_read_address372w(0) OR wire_w_lg_w_lg_read_address278w371w(0);
wire_w_lg_w_lg_read_address377w378w(0) <= wire_w_lg_read_address377w(0) OR wire_w_lg_w_lg_read_address278w376w(0);
wire_w_lg_w_lg_read_address382w383w(0) <= wire_w_lg_read_address382w(0) OR wire_w_lg_w_lg_read_address278w381w(0);
wire_w_lg_w_lg_read_address292w293w(0) <= wire_w_lg_read_address292w(0) OR wire_w_lg_w_lg_read_address278w291w(0);
wire_w_lg_w_lg_read_address387w388w(0) <= wire_w_lg_read_address387w(0) OR wire_w_lg_w_lg_read_address278w386w(0);
wire_w_lg_w_lg_read_address392w393w(0) <= wire_w_lg_read_address392w(0) OR wire_w_lg_w_lg_read_address278w391w(0);
wire_w_lg_w_lg_read_address397w398w(0) <= wire_w_lg_read_address397w(0) OR wire_w_lg_w_lg_read_address278w396w(0);
wire_w_lg_w_lg_read_address402w403w(0) <= wire_w_lg_read_address402w(0) OR wire_w_lg_w_lg_read_address278w401w(0);
wire_w_lg_w_lg_read_address407w408w(0) <= wire_w_lg_read_address407w(0) OR wire_w_lg_w_lg_read_address278w406w(0);
wire_w_lg_w_lg_read_address412w413w(0) <= wire_w_lg_read_address412w(0) OR wire_w_lg_w_lg_read_address278w411w(0);
wire_w_lg_w_lg_read_address417w418w(0) <= wire_w_lg_read_address417w(0) OR wire_w_lg_w_lg_read_address278w416w(0);
wire_w_lg_w_lg_read_address297w298w(0) <= wire_w_lg_read_address297w(0) OR wire_w_lg_w_lg_read_address278w296w(0);
wire_w_lg_w_lg_read_address302w303w(0) <= wire_w_lg_read_address302w(0) OR wire_w_lg_w_lg_read_address278w301w(0);
wire_w_lg_w_lg_read_address307w308w(0) <= wire_w_lg_read_address307w(0) OR wire_w_lg_w_lg_read_address278w306w(0);
wire_w_lg_w_lg_read_address312w313w(0) <= wire_w_lg_read_address312w(0) OR wire_w_lg_w_lg_read_address278w311w(0);
wire_w_lg_w_lg_read_address317w318w(0) <= wire_w_lg_read_address317w(0) OR wire_w_lg_w_lg_read_address278w316w(0);
wire_w_lg_w_lg_read_address322w323w(0) <= wire_w_lg_read_address322w(0) OR wire_w_lg_w_lg_read_address278w321w(0);
wire_w_lg_w_lg_read_address327w328w(0) <= wire_w_lg_read_address327w(0) OR wire_w_lg_w_lg_read_address278w326w(0);
wire_w_lg_w_lg_read_address332w333w(0) <= wire_w_lg_read_address332w(0) OR wire_w_lg_w_lg_read_address278w331w(0);
wire_w_lg_w_lg_w_w4w_range1264w1265w1266w(0) <= wire_w_lg_w_w4w_range1264w1265w(0) OR w2w;
wire_w_lg_w_lg_w_w4w_range1268w1269w1270w(0) <= wire_w_lg_w_w4w_range1268w1269w(0) OR w2w;
wire_w_lg_w_lg_shift_reg_load_enable99w100w(0) <= wire_w_lg_shift_reg_load_enable99w(0) OR shift_reg_clear;
wire_w_lg_read_source_update1237w(0) <= read_source_update OR write_source_update;
wire_w_lg_rsource_load18w(0) <= rsource_load OR global_vcc;
wire_w_lg_rsource_load9w(0) <= rsource_load OR rsource_shift_enable;
wire_w_lg_shift_reg_load_enable99w(0) <= shift_reg_load_enable OR shift_reg_shift_enable;
bit_counter_all_done <= ((((wire_cntr5_w_lg_w_q_range39w42w(0) AND (NOT wire_cntr5_q(2))) AND wire_cntr5_q(3)) AND (NOT wire_cntr5_q(4))) AND wire_cntr5_q(5));
bit_counter_clear <= (rsource_update_done OR wsource_update_done);
bit_counter_enable <= (((((((((rsource_update_done OR wsource_update_done) OR read_init_counter) OR write_init_counter) OR read_pre_data) OR write_pre_data) OR read_data) OR write_data) OR read_post) OR write_post_data);
bit_counter_param_start <= start_bit_decoder_out;
bit_counter_param_start_match <= ((((((NOT w53w(0)) AND (NOT w53w(1))) AND (NOT w53w(2))) AND (NOT w53w(3))) AND (NOT w53w(4))) AND (NOT w53w(5)));
busy <= wire_w_lg_idle1160w(0);
combine_port <= ( read_param & write_param & read_source & param);
data_out <= ( wire_w_lg_w_lg_read_address417w418w & wire_w_lg_w_lg_read_address412w413w & wire_w_lg_w_lg_read_address407w408w & wire_w_lg_w_lg_read_address402w403w & wire_w_lg_w_lg_read_address397w398w & wire_w_lg_w_lg_read_address392w393w & wire_w_lg_w_lg_read_address387w388w & wire_w_lg_w_lg_read_address382w383w & wire_w_lg_w_lg_read_address377w378w & wire_w_lg_w_lg_read_address372w373w & wire_w_lg_w_lg_read_address367w368w & wire_w_lg_w_lg_read_address362w363w & wire_w_lg_w_lg_read_address357w358w & wire_w_lg_w_lg_read_address352w353w & wire_w_lg_w_lg_read_address347w348w & wire_w_lg_w_lg_read_address342w343w & wire_w_lg_w_lg_read_address337w338w & wire_w_lg_w_lg_read_address332w333w & wire_w_lg_w_lg_read_address327w328w & wire_w_lg_w_lg_read_address322w323w & wire_w_lg_w_lg_read_address317w318w & wire_w_lg_w_lg_read_address312w313w & wire_w_lg_w_lg_read_address307w308w & wire_w_lg_w_lg_read_address302w303w & wire_w_lg_w_lg_read_address297w298w & wire_w_lg_w_lg_read_address292w293w & wire_w_lg_w_lg_read_address287w288w & wire_w_lg_w_lg_read_address278w283w & wire_w_lg_w_lg_read_address278w279w);
global_gnd <= '0';
global_vcc <= '1';
idle <= idle_state;
param_decoder_param_latch <= dffe9a;
param_decoder_select <= ( wire_w1144w & wire_w1139w & wire_w_lg_w_lg_w_lg_w_lg_w1064w1065w1133w1134w1135w & wire_w1131w & wire_w_lg_w_lg_w_lg_w_lg_w1098w1124w1125w1126w1127w & wire_w1122w & wire_w1116w & wire_w_lg_w_lg_w_lg_w_lg_w1064w1110w1111w1112w1113w & wire_w1108w & wire_w_lg_w_lg_w_lg_w_lg_w1098w1099w1100w1101w1103w & wire_w_lg_w_lg_w_lg_w_lg_w1084w1092w1093w1094w1095w & wire_w1076w & wire_w1072w & wire_w_lg_w_lg_w_lg_w_lg_w1084w1085w1086w1087w1088w & wire_w1082w & wire_w1054w & wire_w1076w & wire_w1072w & wire_w_lg_w_lg_w_lg_w_lg_w1064w1065w1066w1067w1068w & wire_w1061w & wire_w1054w & wire_w1049w & wire_w1042w);
power_up <= ((((((((((((((wire_w_lg_idle1160w(0) AND wire_w_lg_read_init1159w(0)) AND wire_w_lg_read_source_update1158w(0)) AND wire_w_lg_read_init_counter1157w(0)) AND wire_w_lg_read_pre_data1156w(0)) AND wire_w_lg_read_data1155w(0)) AND wire_w_lg_read_post1154w(0)) AND wire_w_lg_write_init1153w(0)) AND wire_w_lg_write_init_counter1152w(0)) AND wire_w_lg_write_source_update1151w(0)) AND wire_w_lg_write_pre_data1150w(0)) AND wire_w_lg_write_data1149w(0)) AND wire_w_lg_write_post_data1148w(0)) AND wire_w_lg_write_load1147w(0)) AND wire_w_lg_write_wait1146w(0));
read_address <= read_address_state;
read_data <= read_data_state;
read_init <= read_init_state;
read_init_counter <= read_init_counter_state;
read_post <= read_post_state;
read_pre_data <= read_pre_data_state;
read_source_update <= read_source_update_state;
rsource_load <= (idle AND (write_param OR read_param));
rsource_parallel_in <= ( wire_w_lg_w_lg_w_w4w_range1268w1269w1270w & wire_w_lg_w_lg_w_w4w_range1264w1265w1266w);
rsource_serial_out <= dffe1a0;
rsource_shift_enable <= wire_w_lg_read_source_update1237w(0);
rsource_state_par_ini <= ( read_param & global_gnd & global_gnd);
rsource_update_done <= dffe2a0;
rublock_captnupdt <= wire_w_lg_write_load1147w(0);
rublock_clock <= (NOT (clock OR idle_write_wait));
rublock_reconfig <= rublock_reconfig_st;
rublock_reconfig_st <= (idle AND reconfig);
rublock_regin <= ((((wire_w_lg_rublock_regout_reg1243w(0) AND wire_w_lg_read_source_update1158w(0)) AND wire_w_lg_write_source_update1151w(0)) OR (((shift_reg_serial_out AND select_shift_nloop) AND wire_w_lg_read_source_update1158w(0)) AND wire_w_lg_write_source_update1151w(0))) OR wire_w_lg_w_lg_read_source_update1237w1238w(0));
rublock_regout <= wire_sd4_regout;
rublock_regout_reg <= dffe8;
rublock_shiftnld <= (((((((read_pre_data OR write_pre_data) OR read_data) OR write_data) OR read_post) OR write_post_data) OR read_source_update) OR write_source_update);
select_shift_nloop <= (wire_w_lg_read_data1196w(0) OR wire_w_lg_write_data1214w(0));
shift_reg_clear <= rsource_update_done;
shift_reg_load_enable <= (idle AND write_param);
shift_reg_serial_in <= (rublock_regout_reg AND select_shift_nloop);
shift_reg_serial_out <= dffe7a(0);
shift_reg_shift_enable <= (((read_data OR write_data) OR read_post) OR write_post_data);
start_bit_decoder_out <= ((((((((((((((((((((((( "0" & start_bit_decoder_param_select(0) & start_bit_decoder_param_select(0) & start_bit_decoder_param_select(0) & start_bit_decoder_param_select(0) & "0") OR ( "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & start_bit_decoder_param_select(2) & start_bit_decoder_param_select(2) & start_bit_decoder_param_select(2) & start_bit_decoder_param_select(2) & "0")) OR ( "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & start_bit_decoder_param_select(4) & start_bit_decoder_param_select(4) & start_bit_decoder_param_select(4) & "0" & start_bit_decoder_param_select(4))) OR ( "0" & start_bit_decoder_param_select(5) & start_bit_decoder_param_select(5) & start_bit_decoder_param_select(5) & start_bit_decoder_param_select(5) & "0")) OR ( "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & start_bit_decoder_param_select(7) & start_bit_decoder_param_select(7) & "0" & "0" & "0")) OR ( "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & start_bit_decoder_param_select(9) & start_bit_decoder_param_select(9) & "0" & start_bit_decoder_param_select(9) & "0")) OR ( "0" & start_bit_decoder_param_select(10) & start_bit_decoder_param_select(10) & "0" & "0" & "0")) OR ( "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & start_bit_decoder_param_select(12) & start_bit_decoder_param_select(12) & "0" & start_bit_decoder_param_select(12) & "0")) OR ( start_bit_decoder_param_select(13) & "0" & "0" & start_bit_decoder_param_select(13) & "0" & start_bit_decoder_param_select(13))) OR ( "0" & "0" & "0" & "0" & "0" & "0")) OR ( start_bit_decoder_param_select(15) & "0" & "0" & "0" & start_bit_decoder_param_select(15) & start_bit_decoder_param_select(15))) OR ( "0" & "0" & start_bit_decoder_param_select(16) & start_bit_decoder_param_select(16) & "0" & "0")) OR ( start_bit_decoder_param_select(17) & "0" & "0" & start_bit_decoder_param_select(17) & "0" & "0")) OR ( start_bit_decoder_param_select(18) & "0" & "0" & start_bit_decoder_param_select(18) & "0" & start_bit_decoder_param_select(18))) OR ( "0" & "0" & "0" & "0" & "0" & "0"
)) OR ( start_bit_decoder_param_select(20) & "0" & "0" & "0" & start_bit_decoder_param_select(20) & start_bit_decoder_param_select(20))) OR ( "0" & "0" & start_bit_decoder_param_select(21) & start_bit_decoder_param_select(21) & "0" & "0")) OR ( start_bit_decoder_param_select(22) & "0" & "0" & start_bit_decoder_param_select(22) & "0" & "0"));
start_bit_decoder_param_select <= param_decoder_select;
w1w <= read_param;
w2w <= write_param;
w4w <= read_source;
w53w <= (wire_cntr5_q XOR bit_counter_param_start);
w83w <= (wire_cntr6_q XOR width_counter_param_width);
w8w <= wire_w_lg_idle1160w(0);
width_counter_all_done <= (((((NOT wire_cntr6_q(0)) AND (NOT wire_cntr6_q(1))) AND wire_cntr6_q(2)) AND wire_cntr6_q(3)) AND wire_cntr6_q(4));
width_counter_clear <= (rsource_update_done OR wsource_update_done);
width_counter_enable <= ((read_data OR write_data) OR read_post);
width_counter_param_width <= width_decoder_out;
width_counter_param_width_match <= (((((NOT w83w(0)) AND (NOT w83w(1))) AND (NOT w83w(2))) AND (NOT w83w(3))) AND (NOT w83w(4)));
width_decoder_out <= ((((((((((((((((((((((( "0" & "0" & "0" & width_decoder_param_select(0) & "0") OR ( width_decoder_param_select(1) & width_decoder_param_select(1) & "0" & "0" & "0")) OR ( "0" & "0" & "0" & width_decoder_param_select(2) & "0")) OR ( width_decoder_param_select(3) & width_decoder_param_select(3) & width_decoder_param_select(3) & "0" & width_decoder_param_select(3))) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(4))) OR ( "0" & "0" & "0" & width_decoder_param_select(5) & "0")) OR ( width_decoder_param_select(6) & width_decoder_param_select(6) & "0" & "0" & "0")) OR ( "0" & "0" & "0" & width_decoder_param_select(7) & "0")) OR ( width_decoder_param_select(8) & width_decoder_param_select(8) & "0" & "0" & "0")) OR ( "0" & "0" & width_decoder_param_select(9) & "0" & width_decoder_param_select(9))) OR ( "0" & "0" & "0" & width_decoder_param_select(10) & "0")) OR ( width_decoder_param_select(11) & width_decoder_param_select(11) & "0" & "0" & "0")) OR ( "0" & "0" & width_decoder_param_select(12) & "0" & width_decoder_param_select(12))) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(13))) OR ( "0" & width_decoder_param_select(14) & width_decoder_param_select(14) & "0" & "0")) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(15))) OR ( width_decoder_param_select(16) & "0" & width_decoder_param_select(16) & width_decoder_param_select(16) & "0")) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(17))) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(18))) OR ( "0" & width_decoder_param_select(19) & width_decoder_param_select(19) & "0" & "0")) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(20))) OR ( width_decoder_param_select(21) & "0" & width_decoder_param_select(21) & width_decoder_param_select(21) & "0")) OR ( "0" & "0" & "0" & "0" & width_decoder_param_select(22)));
width_decoder_param_select <= param_decoder_select;
write_data <= write_data_state;
write_init <= write_init_state;
write_init_counter <= write_init_counter_state;
write_load <= write_load_state;
write_post_data <= write_post_data_state;
write_pre_data <= write_pre_data_state;
write_source_update <= write_source_update_state;
write_wait <= write_wait_state;
wsource_state_par_ini <= ( write_param & global_gnd & global_gnd);
wsource_update_done <= dffe3a0;
wire_w_data_in_range104w(0) <= data_in(0);
wire_w_data_in_range171w(0) <= data_in(10);
wire_w_data_in_range178w(0) <= data_in(11);
wire_w_data_in_range185w(0) <= data_in(12);
wire_w_data_in_range192w(0) <= data_in(13);
wire_w_data_in_range199w(0) <= data_in(14);
wire_w_data_in_range206w(0) <= data_in(15);
wire_w_data_in_range213w(0) <= data_in(16);
wire_w_data_in_range220w(0) <= data_in(17);
wire_w_data_in_range227w(0) <= data_in(18);
wire_w_data_in_range234w(0) <= data_in(19);
wire_w_data_in_range120w(0) <= data_in(1);
wire_w_data_in_range241w(0) <= data_in(20);
wire_w_data_in_range248w(0) <= data_in(21);
wire_w_data_in_range255w(0) <= data_in(22);
wire_w_data_in_range262w(0) <= data_in(23);
wire_w_data_in_range114w(0) <= data_in(2);
wire_w_data_in_range122w(0) <= data_in(3);
wire_w_data_in_range129w(0) <= data_in(4);
wire_w_data_in_range136w(0) <= data_in(5);
wire_w_data_in_range143w(0) <= data_in(6);
wire_w_data_in_range150w(0) <= data_in(7);
wire_w_data_in_range157w(0) <= data_in(8);
wire_w_data_in_range164w(0) <= data_in(9);
wire_w_param_range105w(0) <= param(0);
wire_w_param_range107w(0) <= param(1);
wire_w_param_range109w(0) <= param(2);
wire_w_param_decoder_param_latch_range1024w(0) <= param_decoder_param_latch(0);
wire_w_param_decoder_param_latch_range1026w(0) <= param_decoder_param_latch(1);
wire_w_param_decoder_param_latch_range1029w(0) <= param_decoder_param_latch(2);
wire_w_param_decoder_param_latch_range1032w(0) <= param_decoder_param_latch(3);
wire_w_param_decoder_param_latch_range1035w(0) <= param_decoder_param_latch(4);
wire_w_param_decoder_param_latch_range1038w(0) <= param_decoder_param_latch(5);
wire_w_param_decoder_param_latch_range1041w(0) <= param_decoder_param_latch(6);
wire_w_rsource_parallel_in_range15w(0) <= rsource_parallel_in(0);
wire_w_rsource_state_par_ini_range22w(0) <= rsource_state_par_ini(0);
wire_w_rsource_state_par_ini_range26w(0) <= rsource_state_par_ini(1);
wire_w_w4w_range1264w(0) <= w4w(0);
wire_w_w4w_range1268w(0) <= w4w(1);
wire_w_wsource_state_par_ini_range32w(0) <= wsource_state_par_ini(0);
wire_w_wsource_state_par_ini_range36w(0) <= wsource_state_par_ini(1);
check_busy_dffe <= (OTHERS => '0');
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe1a0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe1a_ena(0) = '1') THEN dffe1a0 <= (wire_w_lg_rsource_load16w(0) OR wire_w_lg_w_lg_rsource_load13w14w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe1a1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe1a_ena(1) = '1') THEN dffe1a1 <= (rsource_parallel_in(1) AND rsource_load);
END IF;
END IF;
END PROCESS;
loop0 : FOR i IN 0 TO 1 GENERATE
wire_dffe1a_ena(i) <= wire_w_lg_rsource_load9w(0);
END GENERATE loop0;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe2a0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe2a_ena(0) = '1') THEN dffe2a0 <= (wire_w_lg_rsource_load23w(0) OR wire_w_lg_w_lg_rsource_load13w21w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe2a1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe2a_ena(1) = '1') THEN dffe2a1 <= (wire_w_lg_rsource_load27w(0) OR wire_w_lg_w_lg_rsource_load13w25w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe2a2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe2a_ena(2) = '1') THEN dffe2a2 <= (rsource_state_par_ini(2) AND rsource_load);
END IF;
END IF;
END PROCESS;
loop1 : FOR i IN 0 TO 2 GENERATE
wire_dffe2a_ena(i) <= wire_w_lg_rsource_load18w(0);
END GENERATE loop1;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe3a0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe3a_ena(0) = '1') THEN dffe3a0 <= (wire_w_lg_rsource_load33w(0) OR wire_w_lg_w_lg_rsource_load13w31w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe3a1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe3a_ena(1) = '1') THEN dffe3a1 <= (wire_w_lg_rsource_load37w(0) OR wire_w_lg_w_lg_rsource_load13w35w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe3a2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe3a_ena(2) = '1') THEN dffe3a2 <= (wsource_state_par_ini(2) AND rsource_load);
END IF;
END IF;
END PROCESS;
loop2 : FOR i IN 0 TO 2 GENERATE
wire_dffe3a_ena(i) <= wire_w_lg_rsource_load18w(0);
END GENERATE loop2;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(0) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(0) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(0) <= '0';
ELSE dffe7a(0) <= (wire_w_lg_shift_reg_load_enable117w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w103w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(1) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(1) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(1) <= '0';
ELSE dffe7a(1) <= (wire_w_lg_shift_reg_load_enable125w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w119w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(2) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(2) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(2) <= '0';
ELSE dffe7a(2) <= (wire_w_lg_shift_reg_load_enable132w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w127w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(3) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(3) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(3) <= '0';
ELSE dffe7a(3) <= (wire_w_lg_shift_reg_load_enable139w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w134w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(4) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(4) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(4) <= '0';
ELSE dffe7a(4) <= (wire_w_lg_shift_reg_load_enable146w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w141w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(5) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(5) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(5) <= '0';
ELSE dffe7a(5) <= (wire_w_lg_shift_reg_load_enable153w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w148w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(6) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(6) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(6) <= '0';
ELSE dffe7a(6) <= (wire_w_lg_shift_reg_load_enable160w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w155w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(7) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(7) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(7) <= '0';
ELSE dffe7a(7) <= (wire_w_lg_shift_reg_load_enable167w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w162w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(8) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(8) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(8) <= '0';
ELSE dffe7a(8) <= (wire_w_lg_shift_reg_load_enable174w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w169w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(9) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(9) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(9) <= '0';
ELSE dffe7a(9) <= (wire_w_lg_shift_reg_load_enable181w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w176w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(10) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(10) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(10) <= '0';
ELSE dffe7a(10) <= (wire_w_lg_shift_reg_load_enable188w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w183w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(11) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(11) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(11) <= '0';
ELSE dffe7a(11) <= (wire_w_lg_shift_reg_load_enable195w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w190w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(12) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(12) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(12) <= '0';
ELSE dffe7a(12) <= (wire_w_lg_shift_reg_load_enable202w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w197w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(13) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(13) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(13) <= '0';
ELSE dffe7a(13) <= (wire_w_lg_shift_reg_load_enable209w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w204w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(14) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(14) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(14) <= '0';
ELSE dffe7a(14) <= (wire_w_lg_shift_reg_load_enable216w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w211w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(15) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(15) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(15) <= '0';
ELSE dffe7a(15) <= (wire_w_lg_shift_reg_load_enable223w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w218w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(16) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(16) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(16) <= '0';
ELSE dffe7a(16) <= (wire_w_lg_shift_reg_load_enable230w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w225w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(17) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(17) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(17) <= '0';
ELSE dffe7a(17) <= (wire_w_lg_shift_reg_load_enable237w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w232w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(18) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(18) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(18) <= '0';
ELSE dffe7a(18) <= (wire_w_lg_shift_reg_load_enable244w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w239w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(19) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(19) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(19) <= '0';
ELSE dffe7a(19) <= (wire_w_lg_shift_reg_load_enable251w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w246w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(20) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(20) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(20) <= '0';
ELSE dffe7a(20) <= (wire_w_lg_shift_reg_load_enable258w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w253w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(21) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(21) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(21) <= '0';
ELSE dffe7a(21) <= (wire_w_lg_shift_reg_load_enable265w(0) OR wire_w_lg_w_lg_shift_reg_load_enable101w260w(0));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(22) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(22) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(22) <= '0';
ELSE dffe7a(22) <= (wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(23));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(23) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(23) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(23) <= '0';
ELSE dffe7a(23) <= (wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(24));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(24) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(24) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(24) <= '0';
ELSE dffe7a(24) <= (wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(25));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(25) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(25) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(25) <= '0';
ELSE dffe7a(25) <= (wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(26));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(26) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(26) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(26) <= '0';
ELSE dffe7a(26) <= (wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(27));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(27) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(27) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(27) <= '0';
ELSE dffe7a(27) <= (wire_w_lg_shift_reg_load_enable101w(0) AND dffe7a(28));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe7a(28) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe7a_ena(28) = '1') THEN
IF (shift_reg_clear = '1') THEN dffe7a(28) <= '0';
ELSE dffe7a(28) <= (wire_w_lg_shift_reg_load_enable101w(0) AND shift_reg_serial_in);
END IF;
END IF;
END IF;
END PROCESS;
loop3 : FOR i IN 0 TO 28 GENERATE
wire_dffe7a_ena(i) <= wire_w_lg_w_lg_shift_reg_load_enable99w100w(0);
END GENERATE loop3;
wire_dffe7a_w_q_range277w(0) <= dffe7a(0);
wire_dffe7a_w_q_range325w(0) <= dffe7a(10);
wire_dffe7a_w_q_range330w(0) <= dffe7a(11);
wire_dffe7a_w_q_range335w(0) <= dffe7a(12);
wire_dffe7a_w_q_range340w(0) <= dffe7a(13);
wire_dffe7a_w_q_range345w(0) <= dffe7a(14);
wire_dffe7a_w_q_range350w(0) <= dffe7a(15);
wire_dffe7a_w_q_range355w(0) <= dffe7a(16);
wire_dffe7a_w_q_range360w(0) <= dffe7a(17);
wire_dffe7a_w_q_range365w(0) <= dffe7a(18);
wire_dffe7a_w_q_range370w(0) <= dffe7a(19);
wire_dffe7a_w_q_range282w(0) <= dffe7a(1);
wire_dffe7a_w_q_range375w(0) <= dffe7a(20);
wire_dffe7a_w_q_range380w(0) <= dffe7a(21);
wire_dffe7a_w_q_range385w(0) <= dffe7a(22);
wire_dffe7a_w_q_range390w(0) <= dffe7a(23);
wire_dffe7a_w_q_range395w(0) <= dffe7a(24);
wire_dffe7a_w_q_range400w(0) <= dffe7a(25);
wire_dffe7a_w_q_range405w(0) <= dffe7a(26);
wire_dffe7a_w_q_range410w(0) <= dffe7a(27);
wire_dffe7a_w_q_range415w(0) <= dffe7a(28);
wire_dffe7a_w_q_range285w(0) <= dffe7a(2);
wire_dffe7a_w_q_range290w(0) <= dffe7a(3);
wire_dffe7a_w_q_range295w(0) <= dffe7a(4);
wire_dffe7a_w_q_range300w(0) <= dffe7a(5);
wire_dffe7a_w_q_range305w(0) <= dffe7a(6);
wire_dffe7a_w_q_range310w(0) <= dffe7a(7);
wire_dffe7a_w_q_range315w(0) <= dffe7a(8);
wire_dffe7a_w_q_range320w(0) <= dffe7a(9);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN dffe8 <= rublock_regout;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(0) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(0) = '1') THEN dffe9a(0) <= combine_port(0);
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(1) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(1) = '1') THEN dffe9a(1) <= combine_port(1);
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(2) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(2) = '1') THEN dffe9a(2) <= combine_port(2);
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(3) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(3) = '1') THEN dffe9a(3) <= combine_port(3);
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(4) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(4) = '1') THEN dffe9a(4) <= combine_port(4);
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(5) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(5) = '1') THEN dffe9a(5) <= combine_port(5);
END IF;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN dffe9a(6) <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_dffe9a_ena(6) = '1') THEN dffe9a(6) <= combine_port(6);
END IF;
END IF;
END PROCESS;
loop4 : FOR i IN 0 TO 6 GENERATE
wire_dffe9a_ena(i) <= (idle AND (write_param OR read_param));
END GENERATE loop4;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN idle_state <= '1';
ELSIF (clock = '1' AND clock'event) THEN idle_state <= (((wire_w_lg_w_lg_w_lg_idle1179w1180w1181w(0) OR (read_data AND width_counter_all_done)) OR (read_post AND width_counter_all_done)) OR power_up);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN idle_write_wait <= '0';
ELSIF (clock = '1' AND clock'event) THEN idle_write_wait <= ((((wire_w_lg_w_lg_w_lg_idle1179w1180w1181w(0) OR (read_data AND width_counter_all_done)) OR (read_post AND width_counter_all_done)) OR power_up) AND write_load);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_address_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (wire_read_address_state_ena = '1') THEN read_address_state <= (((read_param OR write_param) AND wire_w_lg_w_lg_w_param_range109w110w111w(0)) AND wire_w_lg_w8w274w(0));
END IF;
END IF;
END PROCESS;
wire_read_address_state_ena <= (read_param OR write_param);
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_data_state <= (((read_init_counter AND bit_counter_param_start_match) OR (read_pre_data AND bit_counter_param_start_match)) OR (wire_w_lg_read_data1196w(0) AND wire_w_lg_width_counter_all_done1194w(0)));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_init_counter_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_init_counter_state <= rsource_update_done;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_init_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_init_state <= (idle AND read_param);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_post_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_post_state <= (((read_data AND width_counter_param_width_match) AND wire_w_lg_width_counter_all_done1194w(0)) OR wire_w_lg_read_post1202w(0));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_pre_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_pre_data_state <= (wire_w_lg_read_init_counter1192w(0) OR wire_w_lg_read_pre_data1191w(0));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN read_source_update_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN read_source_update_state <= ((read_init OR read_source_update) AND wire_w_lg_rsource_update_done1187w(0));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_data_state <= (((write_init_counter AND bit_counter_param_start_match) OR (write_pre_data AND bit_counter_param_start_match)) OR (wire_w_lg_write_data1214w(0) AND wire_w_lg_bit_counter_all_done1213w(0)));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_init_counter_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_init_counter_state <= wsource_update_done;
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_init_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_init_state <= (idle AND write_param);
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_load_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_load_state <= ((write_data AND bit_counter_all_done) OR (write_post_data AND bit_counter_all_done));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_post_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_post_data_state <= (((write_data AND width_counter_param_width_match) AND wire_w_lg_bit_counter_all_done1213w(0)) OR wire_w_lg_write_post_data1220w(0));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_pre_data_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_pre_data_state <= (wire_w_lg_write_init_counter1211w(0) OR wire_w_lg_write_pre_data1210w(0));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_source_update_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_source_update_state <= ((write_init OR write_source_update) AND wire_w_lg_wsource_update_done1207w(0));
END IF;
END PROCESS;
PROCESS (clock, reset)
BEGIN
IF (reset = '1') THEN write_wait_state <= '0';
ELSIF (clock = '1' AND clock'event) THEN write_wait_state <= write_load;
END IF;
END PROCESS;
wire_cntr5_w_lg_w_q_range39w42w(0) <= wire_cntr5_w_q_range39w(0) AND wire_cntr5_w_lg_w_q_range40w41w(0);
wire_cntr5_w_lg_w_q_range40w41w(0) <= NOT wire_cntr5_w_q_range40w(0);
wire_cntr5_w_q_range39w(0) <= wire_cntr5_q(0);
wire_cntr5_w_q_range40w(0) <= wire_cntr5_q(1);
cntr5 : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_width => 6
)
PORT MAP (
aclr => reset,
clock => clock,
cnt_en => bit_counter_enable,
q => wire_cntr5_q,
sclr => bit_counter_clear
);
cntr6 : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_width => 5
)
PORT MAP (
aclr => reset,
clock => clock,
cnt_en => width_counter_enable,
q => wire_cntr6_q,
sclr => width_counter_clear
);
sd4 : cycloneive_rublock
PORT MAP (
captnupdt => rublock_captnupdt,
clk => rublock_clock,
rconfig => rublock_reconfig,
regin => rublock_regin,
regout => wire_sd4_regout,
rsttimer => reset_timer,
shiftnld => rublock_shiftnld
);
END RTL; --altremote_remote_update_0
--VALID FILE
| gpl-2.0 | 2004825a68ac16bab07e6128511b22a6 | 0.69716 | 2.280169 | false | false | false | false |
pkerling/ethernet_mac | xilinx/output_buffer.vhd | 1 | 1,171 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Configurable output buffer forced into the IO block
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity output_buffer is
port(
-- Connect to pad or OBUF
pad_o : out std_ulogic;
-- Connect to user logic
buffer_i : in std_ulogic;
-- Capture clock
clock_i : in std_ulogic
);
end entity;
architecture spartan_6 of output_buffer is
-- Force putting input Flip-Flop into IOB so it doesn't end up in a normal logic tile
-- which would ruin the timing.
attribute iob : string;
attribute iob of FDRE_inst : label is "FORCE";
begin
FDRE_inst : FDRE
generic map(
INIT => '0') -- Initial value of register ('0' or '1')
port map(
Q => pad_o, -- Data output
C => clock_i, -- Clock input
CE => '1', -- Clock enable input
R => '0', -- Synchronous reset input
D => buffer_i -- Data input
);
end architecture;
| bsd-3-clause | 84bed1950e37c6e1c8f38253fc6039b5 | 0.624253 | 3.548485 | false | false | false | false |
FrankBuss/YaGraphCon | spartan3e/src/OutputGenerator.vhd | 1 | 4,118 | --
-- VGA video pattern generator
--
-- Copyright (c) 2009 Frank Buss ([email protected])
-- See license.txt for license
--
-- VGA timings:
-- clocks per line:
-- 1. HSync low pulse for 96 clocks
-- 2. back porch for 48 clocks
-- 3. data for 640 clocks
-- 4. front porch for 16 clocks
--
-- VSync timing per picture (800 clocks = 1 line):
-- 1. VSync low pulse for 2 lines
-- 2. back porch for 29 lines
-- 3. data for 480 lines
-- 4. front porch for 10 lines
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
use work.YaGraphConPackage.all;
entity OutputGenerator is
generic(
ADDRESS_WIDTH: natural;
BIT_DEPTH: natural;
PITCH_WIDTH: natural
);
port(
clock: in std_logic;
-- VGA output
pixel: out unsigned(BIT_DEPTH-1 downto 0);
vgaHsync: out std_logic;
vgaVsync: out std_logic;
-- microcontroller interface
vsync: out std_logic;
-- framebuffer
readAddress: out unsigned(ADDRESS_WIDTH-1 downto 0);
q: in unsigned(BIT_DEPTH-1 downto 0);
framebufferStart: in unsigned(ADDRESS_WIDTH-1 downto 0);
framebufferPitch: in unsigned(PITCH_WIDTH-1 downto 0)
);
end entity OutputGenerator;
architecture rtl of OutputGenerator is
constant H_SYNC_PULSE: natural := 96;
constant H_BACK_PORCH: natural := 48 + H_SYNC_PULSE;
constant H_DATA: natural := 640 + H_BACK_PORCH;
constant H_FRONT_PORCH: natural := 16 + H_DATA;
constant V_SYNC_PULSE: natural := 2;
constant V_BACK_PORCH: natural := 29 + V_SYNC_PULSE;
constant V_DATA: natural := 480 + V_BACK_PORCH;
constant V_FRONT_PORCH: natural := 10 + V_DATA;
signal pixelCounter: natural range 0 to 1023 := 0;
signal lineCounter: natural range 0 to 1023 := 0;
signal devide2: std_logic := '0';
signal pixelRepeat: std_logic := '0';
signal lineRepeat: std_logic := '0';
signal framebufferPitchLatched: unsigned(PITCH_WIDTH-1 downto 0);
signal framebufferCurrentAddress: unsigned(ADDRESS_WIDTH-1 downto 0);
signal framebufferLastLineAddress: unsigned(ADDRESS_WIDTH-1 downto 0);
signal lastPixel: unsigned(BIT_DEPTH-1 downto 0);
begin
vgaOut: process(clock)
begin
if rising_edge(clock) then
devide2 <= not devide2;
if devide2 = '1' then
-- default values
pixel <= (others => '0');
-- horizontal timing for one line
pixelCounter <= pixelCounter + 1;
if pixelCounter < H_SYNC_PULSE then
vgaHsync <= '0';
elsif pixelCounter < H_BACK_PORCH then
vgaHsync <= '1';
elsif pixelCounter = H_FRONT_PORCH then
pixelCounter <= 0;
lineCounter <= lineCounter + 1;
end if;
-- vertical timing for one screen
if lineCounter < V_SYNC_PULSE then
vgaVsync <= '0';
vsync <= '1';
elsif lineCounter < V_BACK_PORCH then
vgaVsync <= '1';
vsync <= '0';
elsif lineCounter = V_FRONT_PORCH then
lineCounter <= 0;
-- latch framebuffer start on VSync
framebufferPitchLatched <= framebufferPitch;
framebufferCurrentAddress <= framebufferStart;
framebufferLastLineAddress <= framebufferStart;
lineRepeat <= '1';
pixelRepeat <= '0';
end if;
-- display pixels
if lineCounter >= V_BACK_PORCH and lineCounter < V_DATA then
if pixelCounter >= H_BACK_PORCH and pixelCounter < H_DATA then
if pixelRepeat = '1' then
pixel <= lastPixel;
framebufferCurrentAddress <= framebufferCurrentAddress + 1;
else
lastPixel <= q;
pixel <= q;
end if;
pixelRepeat <= not pixelRepeat;
end if;
if pixelCounter = H_DATA then
pixelRepeat <= '0';
if lineRepeat = '1' then
framebufferCurrentAddress <= framebufferLastLineAddress;
else
framebufferLastLineAddress <= adjustLength(framebufferLastLineAddress + framebufferPitchLatched, framebufferLastLineAddress'length);
framebufferCurrentAddress <= adjustLength(framebufferLastLineAddress + framebufferPitchLatched, framebufferCurrentAddress'length);
end if;
lineRepeat <= not lineRepeat;
end if;
end if;
end if;
end if;
end process;
readAddress <= framebufferCurrentAddress;
end architecture rtl;
| mit | 468c99374d1be303c22e424d21c67dc6 | 0.68067 | 3.463415 | false | false | false | false |
pkerling/ethernet_mac | ethernet_with_fifos.vhd | 1 | 7,061 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Prebuilt Ethernet MAC with FIFOs connected
library ieee;
use ieee.std_logic_1164.all;
use work.ethernet_types.all;
use work.miim_types.all;
entity ethernet_with_fifos is
generic(
MIIM_PHY_ADDRESS : t_phy_address := (others => '0');
MIIM_RESET_WAIT_TICKS : natural := 0;
MIIM_POLL_WAIT_TICKS : natural := DEFAULT_POLL_WAIT_TICKS;
-- See comment in miim for values
-- Default is fine for 125 MHz MIIM clock
MIIM_CLOCK_DIVIDER : positive := 50;
MIIM_DISABLE : boolean := FALSE;
-- See comment in rx_fifo for values
RX_FIFO_SIZE_BITS : positive := 12
);
port(
-- Unbuffered 125 MHz clock input
clock_125_i : in std_ulogic;
-- Asynchronous reset
reset_i : in std_ulogic;
-- MAC address of this station
-- Must not change after reset is deasserted
mac_address_i : in t_mac_address;
-- MII (Media-independent interface)
mii_tx_clk_i : in std_ulogic;
mii_tx_er_o : out std_ulogic;
mii_tx_en_o : out std_ulogic;
mii_txd_o : out std_ulogic_vector(7 downto 0);
mii_rx_clk_i : in std_ulogic;
mii_rx_er_i : in std_ulogic;
mii_rx_dv_i : in std_ulogic;
mii_rxd_i : in std_ulogic_vector(7 downto 0);
-- GMII (Gigabit media-independent interface)
gmii_gtx_clk_o : out std_ulogic;
-- RGMII (Reduced pin count gigabit media-independent interface)
rgmii_tx_ctl_o : out std_ulogic;
rgmii_rx_ctl_i : in std_ulogic;
-- MII Management Interface
-- Clock, can be identical to clock_125_i
-- If not, adjust MIIM_CLOCK_DIVIDER accordingly
miim_clock_i : in std_ulogic;
mdc_o : out std_ulogic;
mdio_io : inout std_ulogic;
-- Status, synchronous to miim_clock_i
link_up_o : out std_ulogic;
speed_o : out t_ethernet_speed;
-- Also synchronous to miim_clock_i if used!
speed_override_i : in t_ethernet_speed := SPEED_UNSPECIFIED;
-- TX FIFO
tx_clock_i : in std_ulogic;
-- Synchronous reset
-- When asserted, the content of the buffer was lost.
-- When full is deasserted the next time, a packet size must be written.
-- The data of the packet previously being written is not available anymore then.
tx_reset_o : out std_ulogic;
tx_data_i : in t_ethernet_data;
tx_wr_en_i : in std_ulogic;
tx_full_o : out std_ulogic;
-- RX FIFO
rx_clock_i : in std_ulogic;
-- Synchronous reset
-- When asserted, the content of the buffer was lost.
-- When empty is deasserted the next time, a packet size must be read out.
-- The data of the packet previously being read out is not available anymore then.
rx_reset_o : out std_ulogic;
rx_empty_o : out std_ulogic;
rx_rd_en_i : in std_ulogic;
rx_data_o : out t_ethernet_data
);
end entity;
architecture rtl of ethernet_with_fifos is
signal mac_reset : std_ulogic := '1';
signal mac_tx_reset : std_ulogic := '1';
signal mac_tx_clock : std_ulogic;
signal mac_tx_enable : std_ulogic := '0';
signal mac_tx_data : t_ethernet_data;
signal mac_tx_byte_sent : std_ulogic;
signal mac_tx_busy : std_ulogic;
signal mac_tx_busy_int : std_ulogic;
signal mac_rx_reset : std_ulogic := '1';
signal mac_rx_clock : std_ulogic;
signal mac_rx_frame : std_ulogic;
signal mac_rx_data : t_ethernet_data;
signal mac_rx_byte_received : std_ulogic;
signal mac_rx_error : std_ulogic;
begin
-- Needed for correct simulation of the inter-packet gap
-- Without any delay, tx_fifo_adapter would see the tx_busy indication too early
-- This generally applies to all signals, but the behavior of the other ones
-- does not cause simulation mismatches.
mac_tx_busy <= transport mac_tx_busy_int after 1 ns;
-- Synchronize user resets
sync_tx_reset_inst : entity work.single_signal_synchronizer
port map(
clock_target_i => tx_clock_i,
signal_i => mac_reset,
signal_o => tx_reset_o
);
sync_rx_reset_inst : entity work.single_signal_synchronizer
port map(
clock_target_i => rx_clock_i,
signal_i => mac_reset,
signal_o => rx_reset_o
);
ethernet_inst : entity work.ethernet
generic map(
MIIM_PHY_ADDRESS => MIIM_PHY_ADDRESS,
MIIM_RESET_WAIT_TICKS => MIIM_RESET_WAIT_TICKS,
MIIM_POLL_WAIT_TICKS => MIIM_POLL_WAIT_TICKS,
MIIM_CLOCK_DIVIDER => MIIM_CLOCK_DIVIDER,
MIIM_DISABLE => MIIM_DISABLE
)
port map(
clock_125_i => clock_125_i,
reset_i => reset_i,
reset_o => mac_reset,
mac_address_i => mac_address_i,
mii_tx_clk_i => mii_tx_clk_i,
mii_tx_er_o => mii_tx_er_o,
mii_tx_en_o => mii_tx_en_o,
mii_txd_o => mii_txd_o,
mii_rx_clk_i => mii_rx_clk_i,
mii_rx_er_i => mii_rx_er_i,
mii_rx_dv_i => mii_rx_dv_i,
mii_rxd_i => mii_rxd_i,
gmii_gtx_clk_o => gmii_gtx_clk_o,
rgmii_tx_ctl_o => rgmii_tx_ctl_o,
rgmii_rx_ctl_i => rgmii_rx_ctl_i,
miim_clock_i => miim_clock_i,
mdc_o => mdc_o,
mdio_io => mdio_io,
tx_reset_o => mac_tx_reset,
tx_clock_o => mac_tx_clock,
tx_enable_i => mac_tx_enable,
tx_data_i => mac_tx_data,
tx_byte_sent_o => mac_tx_byte_sent,
tx_busy_o => mac_tx_busy_int,
rx_reset_o => mac_rx_reset,
rx_clock_o => mac_rx_clock,
rx_frame_o => mac_rx_frame,
rx_data_o => mac_rx_data,
rx_byte_received_o => mac_rx_byte_received,
rx_error_o => mac_rx_error,
link_up_o => link_up_o,
speed_o => speed_o,
speed_override_i => speed_override_i
);
rx_fifo_inst : entity work.rx_fifo
generic map(
MEMORY_SIZE_BITS => RX_FIFO_SIZE_BITS
)
port map(
clock_i => rx_clock_i,
mac_rx_reset_i => mac_rx_reset,
mac_rx_clock_i => mac_rx_clock,
mac_rx_frame_i => mac_rx_frame,
mac_rx_data_i => mac_rx_data,
mac_rx_byte_received_i => mac_rx_byte_received,
mac_rx_error_i => mac_rx_error,
empty_o => rx_empty_o,
rd_en_i => rx_rd_en_i,
data_o => rx_data_o
);
tx_fifo_inst : entity work.tx_fifo
port map(
clock_i => tx_clock_i,
data_i => tx_data_i,
wr_en_i => tx_wr_en_i,
full_o => tx_full_o,
mac_tx_reset_i => mac_tx_reset,
mac_tx_clock_i => mac_tx_clock,
mac_tx_enable_o => mac_tx_enable,
mac_tx_data_o => mac_tx_data,
mac_tx_byte_sent_i => mac_tx_byte_sent,
mac_tx_busy_i => mac_tx_busy
);
end architecture;
| bsd-3-clause | b7b5bee1754efb39a5ee219d7e315aef | 0.580938 | 2.866829 | false | false | false | false |
PsiStarPsi/firmware-general | General/rtl/CommandInterpreter.vhd | 1 | 19,662 | ---------------------------------------------------------------------------------
-- Title : Command Interpreter
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : CommandInterpreter.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Packet parser for old Belle II format.
-- See: http://www.phys.hawaii.edu/~kurtisn/doku.php?id=itop:documentation:data_format
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
entity CommandInterpreter is
generic (
REG_ADDR_BITS_G : integer := 16;
REG_DATA_BITS_G : integer := 16;
TIMEOUT_G : integer := 1250000;
GATE_DELAY_G : time := 1 ns
);
port (
-- User clock and reset
usrClk : in sl;
usrRst : in sl := '0';
-- Incoming data
rxData : in slv(31 downto 0);
rxDataValid : in sl;
rxDataLast : in sl;
rxDataReady : out sl;
-- Outgoing response
txData : out slv(31 downto 0);
txDataValid : out sl;
txDataLast : out sl;
txDataReady : in sl;
-- This board ID
myId : in slv(15 downto 0);
-- Register interfaces
regAddr : out slv(REG_ADDR_BITS_G-1 downto 0);
regWrData : out slv(REG_DATA_BITS_G-1 downto 0);
regRdData : in slv(REG_DATA_BITS_G-1 downto 0);
regReq : out sl;
regOp : out sl;
regAck : in sl
);
end CommandInterpreter;
-- Define architecture
architecture rtl of CommandInterpreter is
type StateType is (IDLE_S,PACKET_SIZE_S,PACKET_TYPE_S,
COMMAND_TARGET_S,COMMAND_ID_S,COMMAND_TYPE_S,
COMMAND_DATA_S,COMMAND_CHECKSUM_S,
PING_S,READ_S,WRITE_S,
READ_RESPONSE_S,WRITE_RESPONSE_S,PING_RESPONSE_S,
ERR_RESPONSE_S,
CHECK_MORE_S,PACKET_CHECKSUM_S,DUMP_S);
type RegType is record
state : StateType;
regAddr : slv(REG_ADDR_BITS_G-1 downto 0);
regWrData : slv(REG_DATA_BITS_G-1 downto 0);
regRdData : slv(REG_DATA_BITS_G-1 downto 0);
regReq : sl;
regOp : sl;
sendResp : sl;
rxDataReady : sl;
txData : slv(31 downto 0);
txDataValid : sl;
txDataLast : sl;
wordsLeft : slv(31 downto 0);
wordOutCnt : slv( 7 downto 0);
checksum : slv(31 downto 0);
command : slv(31 downto 0);
commandId : slv(23 downto 0);
noResponse : sl;
errFlags : slv(31 downto 0);
timeoutCnt : slv(31 downto 0);
end record RegType;
constant REG_INIT_C : RegType := (
state => IDLE_S,
regAddr => (others => '0'),
regWrData => (others => '0'),
regRdData => (others => '0'),
regReq => '0',
regOp => '0',
sendResp => '0',
rxDataReady => '0',
txData => (others => '0'),
txDataValid => '0',
txDataLast => '0',
wordsLeft => (others => '0'),
wordOutCnt => (others => '0'),
checksum => (others => '0'),
command => (others => '0'),
commandId => (others => '0'),
noResponse => '0',
errFlags => (others => '0'),
timeoutCnt => (others => '0')
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
constant WORD_HEADER_C : slv(31 downto 0) := x"00BE11E2";
constant WORD_COMMAND_C : slv(31 downto 0) := x"646F6974";
constant WORD_PING_C : slv(31 downto 0) := x"70696E67";
constant WORD_READ_C : slv(31 downto 0) := x"72656164";
constant WORD_WRITE_C : slv(31 downto 0) := x"72697465";
constant WORD_ACK_C : slv(31 downto 0) := x"6F6B6179";
constant WORD_ERR_C : slv(31 downto 0) := x"7768613f";
constant ERR_BIT_SIZE_C : slv(31 downto 0) := x"00000001";
constant ERR_BIT_TYPE_C : slv(31 downto 0) := x"00000002";
constant ERR_BIT_DEST_C : slv(31 downto 0) := x"00000004";
constant ERR_BIT_COMM_TY_C : slv(31 downto 0) := x"00000008";
constant ERR_BIT_COMM_CS_C : slv(31 downto 0) := x"00000010";
constant ERR_BIT_CS_C : slv(31 downto 0) := x"00000020";
constant ERR_BIT_TIMEOUT_C : slv(31 downto 0) := x"00000040";
signal wordScrodRevC : slv(31 downto 0) := X"00A20000";
signal stateNum : slv(4 downto 0);
-- attribute keep : string;
-- attribute keep of stateNum : signal is "true";
begin
stateNum <= "00000" when r.state = IDLE_S else -- 0 x00
"00001" when r.state = PACKET_SIZE_S else -- 1 x01
"00010" when r.state = PACKET_TYPE_S else -- 2 x02
"00011" when r.state = COMMAND_TARGET_S else -- 3 x03
"00100" when r.state = COMMAND_ID_S else -- 4 x04
"00101" when r.state = COMMAND_TYPE_S else -- 5 x05
"00110" when r.state = COMMAND_DATA_S else -- 6 x06
"00111" when r.state = COMMAND_CHECKSUM_S else -- 7 x07
"01000" when r.state = PING_S else -- 8 x08
"01001" when r.state = READ_S else -- 9 x09
"01010" when r.state = WRITE_S else -- 10 x0A
"01011" when r.state = READ_RESPONSE_S else -- 11 x0B
"01100" when r.state = WRITE_RESPONSE_S else -- 12 x0C
"01101" when r.state = PING_RESPONSE_S else -- 13 x0D
"01110" when r.state = ERR_RESPONSE_S else -- 14 x0E
"01111" when r.state = CHECK_MORE_S else -- 15 x0F
"10000" when r.state = PACKET_CHECKSUM_S else -- 16 x10
"10001" when r.state = DUMP_S else -- 17 x11
"10010" when r.state = IDLE_S else -- 18 x12
"11111"; -- 19 x1F
wordScrodRevC(31 downto 0) <= x"00A2" & myId;
comb : process(r,usrRst,rxData,rxDataValid,rxDataLast,
txDataReady,regRdData,regAck,wordScrodRevC) is
variable v : RegType;
begin
v := r;
-- Resets for pulsed outputs
v.regReq := '0';
v.txDataValid := '0';
v.txDataLast := '0';
rxDataReady <= '0';
-- State machine
case(r.state) is
when IDLE_S =>
v.errFlags := (others => '0');
v.checksum := (others => '0');
if rxDataValid = '1' then
rxDataReady <= '1';
-- Possible errors:
-- This is last, stay here
if rxDataLast = '1' then
v.state := IDLE_S;
-- Header doesn't match format
elsif rxData /= WORD_HEADER_C then
v.state := DUMP_S;
-- Otherwise, move on
else
v.state := PACKET_SIZE_S;
end if;
end if;
when PACKET_SIZE_S =>
if rxDataValid = '1' then
rxDataReady <= '1';
v.wordsLeft := rxData;
-- Possible errors:
-- This is last, go back to IDLE
if rxDataLast = '1' or rxData > 300 then
v.errFlags := r.errFlags + ERR_BIT_SIZE_C;
v.state := ERR_RESPONSE_S;
-- Otherwise, move on
else
v.state := PACKET_TYPE_S;
end if;
end if;
when PACKET_TYPE_S =>
if rxDataValid = '1' then
rxDataReady <= '1';
v.wordsLeft := r.wordsLeft - 1;
-- Possible errors:
-- This is last, go back to IDLE
if rxDataLast = '1' then
v.errFlags := r.errFlags + ERR_BIT_SIZE_C;
v.state := ERR_RESPONSE_S;
-- Packet type isn't understood
elsif rxData /= WORD_COMMAND_C then
v.errFlags := r.errFlags + ERR_BIT_TYPE_C;
v.state := ERR_RESPONSE_S;
-- Otherwise, move on
else
v.state := COMMAND_TARGET_S;
end if;
end if;
when COMMAND_TARGET_S =>
if rxDataValid = '1' then
rxDataReady <= '1';
v.wordsLeft := r.wordsLeft - 1;
-- Possible errors:
-- This is last, go back to IDLE
if rxDataLast = '1' then
v.errFlags := r.errFlags + ERR_BIT_SIZE_C;
v.state := ERR_RESPONSE_S;
-- Target doesn't match this SCROD or broadcast
elsif rxData /= wordScrodRevC and
rxData /= x"00000000" then
v.errFlags := r.errFlags + ERR_BIT_DEST_C;
v.state := ERR_RESPONSE_S;
-- Otherwise, move on
else
v.state := COMMAND_ID_S;
end if;
end if;
when COMMAND_ID_S =>
v.wordOutCnt := (others => '0');
v.timeoutCnt := (others => '0');
if rxDataValid = '1' then
rxDataReady <= '1';
-- Checksum calculation starts here
v.checksum := rxData;
v.wordsLeft := r.wordsLeft - 1;
v.commandId := rxData(23 downto 0);
v.noResponse := rxData(31);
-- Possible errors:
-- This is last, go back to IDLE
if rxDataLast = '1' then
v.errFlags := r.errFlags + ERR_BIT_SIZE_C;
v.state := ERR_RESPONSE_S;
-- Otherwise, move on
else
v.state := COMMAND_TYPE_S;
end if;
end if;
when COMMAND_TYPE_S =>
if rxDataValid = '1' then
rxDataReady <= '1';
v.checksum := r.checksum + rxData;
v.command := rxData;
v.wordsLeft := r.wordsLeft - 1;
-- Possible errors:
-- This is last, go back to IDLE
if rxDataLast = '1' then
v.errFlags := r.errFlags + ERR_BIT_SIZE_C;
v.state := ERR_RESPONSE_S;
-- Move on for recognized commands
elsif rxData = WORD_PING_C then
v.state := COMMAND_CHECKSUM_S;
elsif rxData = WORD_READ_C or rxData = WORD_WRITE_C then
v.state := COMMAND_DATA_S;
-- Unrecognized command, dump
else
v.errFlags := r.errFlags + ERR_BIT_COMM_TY_C;
v.state := ERR_RESPONSE_S;
end if;
end if;
when COMMAND_DATA_S =>
if rxDataValid = '1' then
rxDataReady <= '1';
v.checksum := r.checksum + rxData;
v.regAddr := rxData(15 downto 0);
v.regWrData := rxData(31 downto 16);
v.wordsLeft := r.wordsLeft - 1;
-- Possible errors:
-- This is last, go back to IDLE
if rxDataLast = '1' then
v.errFlags := r.errFlags + ERR_BIT_SIZE_C;
v.state := ERR_RESPONSE_S;
-- Move on for recognized commands
else
v.state := COMMAND_CHECKSUM_S;
end if;
end if;
when COMMAND_CHECKSUM_S =>
if rxDataValid = '1' then
rxDataReady <= '1';
v.wordsLeft := r.wordsLeft - 1;
-- Possible errors:
-- This is last, go back to IDLE
if rxDataLast = '1' then
v.errFlags := r.errFlags + ERR_BIT_SIZE_C;
v.state := ERR_RESPONSE_S;
-- Bad checksum
elsif r.checksum /= rxData then
v.errFlags := r.errFlags + ERR_BIT_COMM_CS_C;
v.state := ERR_RESPONSE_S;
-- Command accepted, move to execute state
elsif r.command = WORD_PING_C then
v.state := PING_S;
elsif r.command = WORD_WRITE_C then
v.state := WRITE_S;
elsif r.command = WORD_READ_C then
v.state := READ_S;
-- Unrecognized command
else
v.errFlags := r.errFlags + ERR_BIT_COMM_TY_C;
v.state := ERR_RESPONSE_S;
end if;
end if;
when PING_S =>
if r.noResponse = '1' then
v.state := CHECK_MORE_S;
else
v.checksum := (others => '0');
v.state := PING_RESPONSE_S;
end if;
when READ_S =>
v.regOp := '0';
v.regReq := '1';
v.timeoutCnt := r.timeoutCnt + 1;
if (regAck = '1') then
v.regRdData := regRdData;
v.regReq := '0';
if r.noResponse = '1' then
v.state := CHECK_MORE_S;
else
v.checksum := (others => '0');
v.state := READ_RESPONSE_S;
end if;
elsif r.timeoutCnt = TIMEOUT_G then
v.errFlags := r.errFlags + ERR_BIT_TIMEOUT_C;
v.state := ERR_RESPONSE_S;
end if;
when WRITE_S =>
v.regOp := '1';
v.regReq := '1';
v.timeoutCnt := r.timeoutCnt + 1;
if (regAck = '1') then
v.regReq := '0';
if r.noResponse = '1' then
v.state := CHECK_MORE_S;
else
v.checksum := (others => '0');
v.state := WRITE_RESPONSE_S;
end if;
elsif r.timeoutCnt = TIMEOUT_G then
v.errFlags := r.errFlags + ERR_BIT_TIMEOUT_C;
v.state := ERR_RESPONSE_S;
end if;
when READ_RESPONSE_S =>
if regAck = '0' and r.regReq = '0' then
v.txDataValid := '1';
case conv_integer(r.wordOutCnt) is
when 0 => v.txData := WORD_HEADER_C;
when 1 => v.txData := x"00000006";
when 2 => v.txData := WORD_ACK_C;
when 3 => v.txData := wordScrodRevC;
when 4 => v.txData := x"00" & r.commandId;
when 5 => v.txData := WORD_READ_C;
when 6 => v.txData := r.regRdData & r.regAddr;
when 7 => v.txData := r.checksum;
v.txDataLast := '1';
v.state := CHECK_MORE_S;
when others => v.txData := (others => '1');
end case;
if txDataReady = '1' then
v.checksum := r.checksum + v.txData;
v.wordOutCnt := r.wordOutCnt + 1;
end if;
end if;
when WRITE_RESPONSE_S =>
if regAck = '0' and r.regReq = '0' then
v.txDataValid := '1';
case conv_integer(r.wordOutCnt) is
when 0 => v.txData := WORD_HEADER_C;
when 1 => v.txData := x"00000006";
when 2 => v.txData := WORD_ACK_C;
when 3 => v.txData := wordScrodRevC;
when 4 => v.txData := x"00" & r.commandId;
when 5 => v.txData := WORD_WRITE_C;
when 6 => v.txData := r.regWrData & r.regAddr;
when 7 => v.txData := v.checksum;
v.txDataLast := '1';
v.state := CHECK_MORE_S;
when others => v.txData := (others => '1');
end case;
if txDataReady = '1' then
v.checksum := r.checksum + v.txData;
v.wordOutCnt := r.wordOutCnt + 1;
end if;
end if;
when PING_RESPONSE_S =>
v.txDataValid := '1';
case conv_integer(r.wordOutCnt) is
when 0 => v.txData := WORD_HEADER_C;
when 1 => v.txData := x"00000005";
when 2 => v.txData := WORD_ACK_C;
when 3 => v.txData := wordScrodRevC;
when 4 => v.txData := x"00" & r.commandId;
when 5 => v.txData := WORD_PING_C;
when 6 => v.txData := v.checksum;
v.txDataLast := '1';
v.state := CHECK_MORE_S;
when others => v.txData := (others => '1');
end case;
if txDataReady = '1' then
v.checksum := r.checksum + v.txData;
v.wordOutCnt := r.wordOutCnt + 1;
end if;
when ERR_RESPONSE_S =>
if txDataReady = '1' then
v.checksum := r.checksum + r.txData;
v.wordOutCnt := r.wordOutCnt + 1;
end if;
v.txDataValid := '1';
case conv_integer(r.wordOutCnt) is
when 0 => v.txData := WORD_HEADER_C;
when 1 => v.txData := x"00000005";
when 2 => v.txData := WORD_ERR_C;
when 3 => v.txData := wordScrodRevC;
when 4 => v.txData := x"00" & r.commandId;
when 5 => v.txData := r.errFlags;
when 6 => v.txData := r.checksum;
v.txDataLast := '1';
v.state := DUMP_S;
when others => v.txData := (others => '1');
end case;
when CHECK_MORE_S =>
if r.wordsLeft /= 1 then
v.state := COMMAND_ID_S;
else
v.state := PACKET_CHECKSUM_S;
end if;
when PACKET_CHECKSUM_S =>
-- Not checking this for now...
v.state := DUMP_S;
when DUMP_S =>
rxDataReady <= '1';
if rxDataLast = '1' then
v.state := IDLE_S;
end if;
when others =>
v.state := IDLE_S;
end case;
-- Reset logic
if (usrRst = '1') then
v := REG_INIT_C;
end if;
-- Outputs to ports
txData <= r.txData;
txDataValid <= r.txDataValid;
txDataLast <= r.txDataLast;
-- Register interfaces
regAddr <= r.regAddr;
regWrData <= r.regWrData;
regReq <= r.regReq;
regOp <= r.regOp;
-- Assignment of combinatorial variable to signal
rin <= v;
end process;
seq : process (usrClk) is
begin
if (rising_edge(usrClk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | 798026d0e5e9f284083523eb79685fbc | 0.449649 | 4.020859 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pwm/niosii/synthesis/niosii_rst_controller_002.vhd | 2 | 9,084 | -- niosii_rst_controller_002.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_rst_controller_002 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity niosii_rst_controller_002;
architecture rtl of niosii_rst_controller_002 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_002 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of niosii_rst_controller_002
| mit | f84eaa81e9203aa102f06954126ff38d | 0.546786 | 2.726291 | false | false | false | false |
FrankBuss/YaGraphCon | spartan3e/src/test.vhd | 1 | 3,485 | -- Copyright (c) 2009 Frank Buss ([email protected])
-- See license.txt for license
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity test is
port(
clk_50mhz: in std_logic;
rs232_dce_txd: out std_logic;
rs232_dce_rxd: in std_logic;
led: out unsigned(7 downto 0);
VGA_BLUE: out std_logic;
VGA_GREEN: out std_logic;
VGA_HSYNC: out std_logic;
VGA_RED: out std_logic;
VGA_VSYNC: out std_logic
);
end entity test;
architecture rtl of test is
constant ADDRESS_WIDTH: natural := 17;
constant BIT_DEPTH: natural := 1;
constant SYSTEM_SPEED: natural := 50e6;
constant BAUDRATE: natural := 115200;
signal rs232DataReceived: std_logic := '0';
signal rs232DataIn: unsigned(7 downto 0) := (others => '0');
signal rs232SendTrigger: std_logic := '0';
signal rs232DataOut: unsigned(7 downto 0);
signal ledLatch: unsigned(7 downto 0) := (others => '0');
signal counter: natural range 0 to (system_speed / 2) := 0;
signal spiChipSelect: std_logic;
signal spiData: std_logic;
signal spiClock: std_logic;
signal busy: std_logic;
signal busyVector: unsigned(1 downto 0);
signal vsync: std_logic;
signal pixel: unsigned(BIT_DEPTH-1 downto 0);
signal vgaHsync: std_logic;
signal vgaVsync: std_logic;
begin
YaGraphCon_instance: entity YaGraphCon
generic map(ADDRESS_WIDTH, BIT_DEPTH)
port map(
clock => clk_50mhz,
spiChipSelect => spiChipSelect,
spiData => spiData,
spiClock => spiClock,
busy => busy,
vsync => vsync,
pixel => pixel,
vgaHsync => vgaHsync,
vgaVsync => vgaVsync
);
sender: entity rs232_sender
generic map(SYSTEM_SPEED, BAUDRATE)
port map(
clock => clk_50mhz,
data => rs232DataOut,
tx => rs232_dce_txd,
sendTrigger => rs232SendTrigger,
dataSent => ledLatch(4)
);
receiver: entity rs232_receiver
generic map(SYSTEM_SPEED, BAUDRATE)
port map(
clock => clk_50mhz,
reset => '0',
data => rs232DataIn,
rx => rs232_dce_rxd,
dataReceived => rs232DataReceived
);
process(clk_50mhz)
begin
if rising_edge(clk_50mhz) then
rs232SendTrigger <= '0';
if rs232DataReceived = '1' then
case rs232DataIn is
-- "t" for testing: invert LED
when x"74" =>
ledLatch(3) <= not ledLatch(3);
-- other commands for the SPI signals
when x"00" =>
spiChipSelect <= '1';
when x"01" =>
spiChipSelect <= '0';
when x"02" =>
spiClock <= '1';
when x"03" =>
spiClock <= '0';
when x"04" =>
spiData <= '1';
when x"05" =>
spiData <= '0';
-- other bytes: echo, for RS232 TX/RX test
when others =>
rs232DataOut <= rs232DataIn;
rs232SendTrigger <= '1';
end case;
end if;
-- signal falling busy signal with "o" for "ok"
busyVector <= busyVector(0) & busy;
if busyVector = "10" then
rs232DataOut <= x"6f";
rs232SendTrigger <= '1';
end if;
-- 1 Hz LED blinker
if counter = 0 then
ledLatch(0) <= not ledLatch(0);
counter <= SYSTEM_SPEED / 2;
else
counter <= counter - 1;
end if;
-- routing some internal signals to the LEDs
ledLatch(1) <= busy;
ledLatch(2) <= vsync;
ledLatch(3) <= rs232_dce_rxd;
ledLatch(5) <= pixel(0);
ledLatch(6) <= vgaHsync;
ledLatch(7) <= vgaVsync;
end if;
end process;
led <= ledLatch;
VGA_RED <= pixel(0);
VGA_GREEN <= pixel(0);
VGA_BLUE <= pixel(0);
VGA_HSYNC <= vgaHsync;
VGA_VSYNC <= vgaVsync;
end architecture rtl;
| mit | 998c8ce9b31044ffbeae7e9e3aeeac28 | 0.633572 | 2.940928 | false | false | false | false |
PsiStarPsi/firmware-general | General/rtl/Decode8b10b.vhd | 1 | 9,150 | -- Translated to vhdl from verilog module decode_8b10b.v
-- by Kurtis Nishimura, 2015
-- from source obtained at:
--
-- http://asics.chuckbenz.com/decode.v
--
-- Original copyright information:
-- // Chuck Benz, Hollis, NH Copyright (c)2002
-- //
-- // The information and description contained herein is the
-- // property of Chuck Benz.
-- //
-- // Permission is granted for any reuse of this information
-- // and description as long as this copyright notice is
-- // preserved. Modifications may be made as long as this
-- // notice is preserved.
--
-- // per Widmer and Franaszek
--
--
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.UtilityPkg.all;
entity Decode8b10b is
generic (
GATE_DELAY_G : time := 1 ns
);
port (
clk : in sl;
clkEn : in sl := '1';
rst : in sl := '0';
dataIn : in slv(9 downto 0);
dispIn : in sl;
dataOut : out slv(7 downto 0);
dataKOut : out sl;
dispOut : out sl;
codeErr : out sl;
dispErr : out sl
);
end Decode8b10b;
architecture rtl of Decode8b10b is
signal ai, bi, ci, di, ei, fi, gi, hi, ii, ji : sl;
signal aeqb, ceqd, p22, p40, p04, p13, p31 : sl;
signal disp6a, disp6a2, disp6a0, disp6b : sl;
signal p22bceeqi, p22bncneeqi, p13in, p3li, p13dei : sl;
signal p22aceeqi, p22ancneeqi, p13en, anbnenin : sl;
signal abei, cdei, cndnenin : sl;
signal p22enin, p22ei, p31dnenin, p31i, p31e : sl;
signal compa, compb, compc, compd, compe : sl;
signal ao, bo, co, do, eo : sl;
signal feqg, heqj, fghj22, fghjp13, fghjp31, dispoutRaw : sl;
signal ko, alt7, k28, k28p, fo, go, ho : sl;
signal disp6p, disp6n, disp4p, disp4n : sl;
signal code_err : sl;
signal disp_err : sl;
signal dataOutRaw : slv(7 downto 0);
signal dataKOutRaw : sl;
begin
-- Combinatorial logic
ai <= dataIn(0);
bi <= dataIn(1);
ci <= dataIn(2);
di <= dataIn(3);
ei <= dataIn(4);
ii <= dataIn(5);
fi <= dataIn(6);
gi <= dataIn(7);
hi <= dataIn(8);
ji <= dataIn(9);
aeqb <= (ai and bi) or (not(ai) and not(bi));
ceqd <= (ci and di) or (not(ci) and not(di));
p22 <= (ai and bi and not(ci) and not(di)) or
(ci and di and not(ai) and not(bi)) or
(not(aeqb) and not(ceqd));
p13 <= (not(aeqb) and not(ci) and not(di)) or
(not(ceqd) and not(ai) and not(bi));
p31 <= (not(aeqb) and ci and di) or
(not(ceqd) and ai and bi);
p40 <= ai and bi and ci and di;
p04 <= not(ai) and not(bi) and not(ci) and not(di);
disp6a <= p31 or (p22 and dispin); -- pos disp if p22 and was pos, or p31.
disp6a2 <= p31 and dispin; -- disp is ++ after 4 bits
disp6a0 <= p13 and not(dispin); -- -- disp after 4 bits
disp6b <= (((ei and ii and not(disp6a0)) or (disp6a and (ei or ii)) or disp6a2 or
(ei and ii and di)) and (ei or ii or di));
-- The 5B/6B decoding special cases where ABCDE != abcde
p22bceeqi <= p22 and bi and ci when (ei = ii) else '0';
p22bncneeqi <= p22 and not(bi) and not(ci) when (ei = ii) else '0';
p13in <= p13 and not(ii);
p31i <= p31 and ii;
p13dei <= p13 and di and ei and ii;
p22aceeqi <= p22 and ai and ci when (ei = ii) else '0';
p22ancneeqi <= p22 and not(ai) and not(ci) when (ei = ii) else '0';
p13en <= p13 and not(ei);
anbnenin <= not(ai) and not(bi) and not(ei) and not(ii);
abei <= ai and bi and ei and ii;
cdei <= ci and di and ei and ii;
cndnenin <= not(ci) and not(di) and not(ei) and not(ii);
-- non-zero disparity cases:
p22enin <= p22 and not(ei) and not(ii);
p22ei <= p22 and ei and ii;
p31dnenin <= p31 and not(di) and not(ei) and not(ii);
p31e <= p31 and ei;
compa <= p22bncneeqi or p31i or p13dei or p22ancneeqi or
p13en or abei or cndnenin ;
compb <= p22bceeqi or p31i or p13dei or p22aceeqi or
p13en or abei or cndnenin ;
compc <= p22bceeqi or p31i or p13dei or p22ancneeqi or
p13en or anbnenin or cndnenin ;
compd <= p22bncneeqi or p31i or p13dei or p22aceeqi or
p13en or abei or cndnenin ;
compe <= p22bncneeqi or p13in or p13dei or p22ancneeqi or
p13en or anbnenin or cndnenin ;
ao <= ai xor compa;
bo <= bi xor compb;
co <= ci xor compc;
do <= di xor compd;
eo <= ei xor compe;
feqg <= (fi and gi) or (not(fi) and not(gi));
heqj <= (hi and ji) or (not(hi) and not(ji));
fghj22 <= (fi and gi and not(hi) and not(ji)) or
(not(fi) and not(gi) and hi and ji) or
(not(feqg) and not(heqj));
fghjp13 <= (not(feqg) and not(hi) and not(ji)) or
(not(heqj) and not(fi) and not(gi));
fghjp31 <= ( not(feqg) and hi and ji) or
(not(heqj) and fi and gi);
dispoutRaw <= (fghjp31 or (disp6b and fghj22) or (hi and ji)) and (hi or ji);
ko <= ( (ci and di and ei and ii) or (not(ci) and not(di) and not(ei) and not(ii)) or
(p13 and not(ei) and ii and gi and hi and ji) or
(p31 and ei and not(ii) and not(gi) and not(hi) and not(ji)));
alt7 <= (fi and not(gi) and not(hi) and -- 1000 cases, where disp6b is 1
((dispin and ci and di and not(ei) and not(ii)) or ko or
(dispin and not(ci) and di and not(ei) and not(ii)))) or
(not(fi) and gi and hi and -- 0111 cases, where disp6b is 0
((not(dispin) and not(ci) and not(di) and ei and ii) or ko or
(not(dispin) and ci and not(di) and ei and ii)));
k28 <= (ci and di and ei and ii) or not(ci or di or ei or ii);
-- k28 with positive disp into fghi - .1, .2, .5, and .6 special cases
k28p <= not(ci or di or ei or ii);
fo <= (ji and not(fi) and (hi or not(gi) or k28p)) or
(fi and not(ji) and (not(hi) or gi or not(k28p))) or
(k28p and gi and hi) or
(not(k28p) and not(gi) and not(hi));
go <= (ji and not(fi) and (hi or not(gi) or not(k28p))) or
(fi and not(ji) and (not(hi) or gi or k28p)) or
(not(k28p) and gi and hi) or
(k28p and not(gi) and not(hi));
ho <= ((ji xor hi) and not((not(fi) and gi and not(hi) and ji and not(k28p)) or (not(fi) and gi and hi and not(ji) and k28p) or
(fi and not(gi) and not(hi) and ji and not(k28p)) or (fi and not(gi) and hi and not(ji) and k28p))) or
(not(fi) and gi and hi and ji) or (fi and not(gi) and not(hi) and not(ji));
disp6p <= (p31 and (ei or ii)) or (p22 and ei and ii);
disp6n <= (p13 and not(ei and ii)) or (p22 and not(ei) and not(ii));
disp4p <= fghjp31;
disp4n <= fghjp13;
code_err <= p40 or p04 or (fi and gi and hi and ji) or (not(fi) and not(gi) and not(hi) and not(ji)) or
(p13 and not(ei) and not(ii)) or (p31 and ei and ii) or
(ei and ii and fi and gi and hi) or (not(ei) and not(ii) and not(fi) and not(gi) and not(hi)) or
(ei and not(ii) and gi and hi and ji) or (not(ei) and ii and not(gi) and not(hi) and not(ji)) or
(not(p31) and ei and not(ii) and not(gi) and not(hi) and not(ji)) or
(not(p13) and not(ei) and ii and gi and hi and ji) or
(((ei and ii and not(gi) and not(hi) and not(ji)) or
(not(ei) and not(ii) and gi and hi and ji)) and
not((ci and di and ei) or (not(ci) and not(di) and not(ei)))) or
(disp6p and disp4p) or (disp6n and disp4n) or
(ai and bi and ci and not(ei) and not(ii) and ((not(fi) and not(gi)) or fghjp13)) or
(not(ai) and not(bi) and not(ci) and ei and ii and ((fi and gi) or fghjp31)) or
(fi and gi and not(hi) and not(ji) and disp6p) or
(not(fi) and not(gi) and hi and ji and disp6n) or
(ci and di and ei and ii and not(fi) and not(gi) and not(hi)) or
(not(ci) and not(di) and not(ei) and not(ii) and fi and gi and hi) ;
dataKOutRaw <= ko;
dataOutRaw(7) <= ho;
dataOutRaw(6) <= go;
dataOutRaw(5) <= fo;
dataOutRaw(4) <= eo;
dataOutRaw(3) <= do;
dataOutRaw(2) <= co;
dataOutRaw(1) <= bo;
dataOutRaw(0) <= ao;
-- my disp err fires for any legal codes that violate disparity, may fire for illegal codes
disp_err <= ((dispin and disp6p) or (disp6n and not(dispin)) or
(dispin and not(disp6n) and fi and gi) or
(dispin and ai and bi and ci) or
(dispin and not(disp6n) and disp4p) or
(not(dispin) and not(disp6p) and not(fi) and not(gi)) or
(not(dispin) and not(ai) and not(bi) and not(ci)) or
(not(dispin) and not(disp6p) and disp4n) or
(disp6p and disp4p) or (disp6n and disp4n)) ;
process(clk) begin
if rising_edge(clk) then
if rst = '1' then
dataOut <= (others => '0');
dataKOut <= '0';
dispOut <= '0';
codeErr <= '0';
dispErr <= '0';
elsif clkEn = '1' then
dataOut <= dataOutRaw;
dataKOut <= dataKOutRaw;
dispOut <= dispoutRaw;
codeErr <= code_err;
dispErr <= disp_err;
end if;
end if;
end process;
end rtl;
| lgpl-2.1 | 4159004d598780edb1b667042808aec5 | 0.574536 | 2.88917 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_uart/niosii/niosii_inst.vhd | 2 | 1,140 | component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_rxd : in std_logic := 'X'; -- rxd
uart_0_txd : out std_logic -- txd
);
end component niosii;
u0 : component niosii
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export, -- pio_0_external_connection.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
uart_0_rxd => CONNECTED_TO_uart_0_rxd, -- uart_0.rxd
uart_0_txd => CONNECTED_TO_uart_0_txd -- .txd
);
| mit | 83cef87dca865ad0682d02980d1e02a8 | 0.392105 | 4.145455 | false | false | false | false |
PsiStarPsi/firmware-general | General/rtl/InitRst.vhd | 1 | 3,140 | ---------------------------------------------------------------------------------
-- Title : Startup Reset
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : InitRst.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Simple one-bit synchronizer.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
entity InitRst is
generic (
SYNC_STAGES_G : integer := 2;
RST_POL_G : sl := '1';
RST_CNT_G : integer := 12500000;
GATE_DELAY_G : time := 1 ns
);
port (
-- Clock and reset
clk : in sl;
-- Incoming reset, asynchronous
asyncRst : in sl := '0';
-- Outgoing reset, synced to clk
syncRst : out sl
);
end InitRst;
-- Define architecture
architecture rtl of InitRst is
type StateType is (IN_RESET_S, DONE_S);
type RegType is record
state : StateType;
count : slv(31 downto 0);
syncRst : sl;
end record RegType;
constant REG_INIT_C : RegType := (
state => IN_RESET_S,
count => (others => '0'),
syncRst => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
signal internalRst : sl := '1';
begin
U_RstSync : entity work.SyncBit
generic map (
RST_POL_G => RST_POL_G,
GATE_DELAY_G => GATE_DELAY_G
)
port map (
clk => clk,
rst => asyncRst,
asyncBit => not(RST_POL_G),
syncBit => internalRst
);
comb : process(internalRst,r) is
variable v : RegType;
begin
v := r;
-- Resets for pulsed outputs
-- State machine
case(r.state) is
when IN_RESET_S =>
v.syncRst := RST_POL_G;
v.count := r.count + 1;
if r.count = RST_CNT_G then
v.state := DONE_S;
end if;
when DONE_S =>
v.syncRst := not(RST_POL_G);
when others =>
end case;
-- Reset logic
if (internalRst = RST_POL_G) then
v := REG_INIT_C;
end if;
-- Outputs to ports
syncRst <= r.syncRst;
-- Assignment of combinatorial variable to signal
rin <= v;
end process;
seq : process (clk) is
begin
if (rising_edge(clk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
| lgpl-2.1 | 6fc42e79b4f1e75ad2043d67bac143b4 | 0.473885 | 4.197861 | false | false | false | false |
PsiStarPsi/firmware-general | General/sim/RstSim.vhd | 1 | 3,931 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:32:20 09/25/2015
-- Design Name:
-- Module Name: /home/kurtisn/mtc/Scrod_mTC_Firmware/src/firmware-general/General/sim/RstSim.vhd
-- Project Name: scrodMtc
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: InitRst
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY RstSim IS
END RstSim;
ARCHITECTURE behavior OF RstSim IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT InitRst
PORT(
clk : IN std_logic;
asyncRst : IN std_logic;
syncRst : OUT std_logic
);
END COMPONENT;
--Inputs
signal fabClk : std_logic;
signal fabClkRst : std_logic;
signal ethClk62 : std_logic;
signal ethClk62Rst : std_logic;
signal ethClk125 : std_logic;
signal ethClk125Rst : std_logic;
signal userRst : std_logic;
-- Clock period definitions
constant clk125_period : time := 8 ns;
constant clk62_period : time := 16 ns;
constant fabclk_period : time := 4 ns;
BEGIN
---------------------------------------------------------------------------
-- Resets
---------------------------------------------------------------------------
-- Generate stable reset signal
U_PwrUpRst : entity work.InitRst
generic map (
RST_CNT_G => 12500,
GATE_DELAY_G => 0 ns
)
port map (
clk => fabClk,
syncRst => fabClkRst
);
-- Synchronize the reset to the 125 MHz domain
U_RstSync125 : entity work.SyncBit
generic map (
INIT_STATE_G => '1',
GATE_DELAY_G => 0 ns
)
port map (
clk => ethClk125,
rst => '0',
asyncBit => ethClk62Rst,
syncBit => ethClk125Rst
);
-- Synchronize the reset to the 62 MHz domain
U_RstSync62 : entity work.SyncBit
generic map (
INIT_STATE_G => '1',
GATE_DELAY_G => 0 ns
)
port map (
clk => ethClk125,
rst => '0',
asyncBit => fabClkRst,
syncBit => ethClk62Rst
);
-- User reset
U_RstSyncUser : entity work.SyncBit
generic map (
INIT_STATE_G => '1',
GATE_DELAY_G => 0 ns
)
port map (
clk => ethClk125,
rst => '0',
asyncBit => ethClk62Rst,
syncBit => userRst
);
-- Clock process definitions
clk125_process :process
begin
ethClk125 <= '0';
wait for clk125_period/2;
ethClk125 <= '1';
wait for clk125_period/2;
end process;
-- Clock process definitions
clk62_process :process
begin
ethClk62 <= '0';
wait for clk62_period/2;
ethClk62 <= '1';
wait for clk62_period/2;
end process;
-- Clock process definitions
fabclk_process :process
begin
fabclk <= '0';
wait for fabclk_period/2;
fabclk <= '1';
wait for fabclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
| lgpl-2.1 | 23d1076cf1a4ecf4ce218217d93b9375 | 0.547952 | 4.035934 | false | false | false | false |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/src/tbd_rr_base_tb.vhd | 1 | 11,945 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_rr_base is
end tb_rr_base;
architecture bhv of tb_rr_base is
----------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------
-- System
constant c_spi_rate : natural := 99E5; -- Should be something weird => Detect more errors
constant c_bit_with_half_t : time := 1E9 ns / (2 * c_spi_rate);
constant c_byte_pad_t : time := 5 * c_bit_with_half_t;
constant SPI_USER_CS_IDX : natural := 1;
-- User
constant c_clk_frequency : natural := 50E6;
constant c_use_issi_sdram : std_ulogic := '1';
constant c_use_sdram_pll : std_ulogic := '1';
constant num_gpios : natural := 6;
-- Derived
----------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------
signal clk : std_ulogic := '1';
signal keys : std_ulogic_vector(1 downto 0);
signal switches : std_ulogic_vector(3 downto 0);
signal leds : std_ulogic_vector(7 downto 0);
signal spi_cs : std_ulogic_vector(1 downto 0) := (others => '1');
signal spi_clk : std_ulogic := '0';
signal spi_mosi : std_ulogic := '0';
signal spi_miso : std_ulogic := '0';
signal spi_epcs_cs : std_ulogic;
signal spi_epcs_clk : std_ulogic;
signal spi_epcs_mosi : std_ulogic;
signal spi_epcs_miso : std_ulogic;
signal arReconf : std_ulogic;
signal gpios : std_logic_vector(0 to num_gpios - 1);
begin
clk <= not clk after 1E9 ns / (2 * c_clk_frequency);
keys <= (others => '1');
switches <= (others => '0');
testbed: entity work.tbd_rr_base(rtl)
generic map
(
use_sdram_pll => c_use_sdram_pll,
num_gpios => num_gpios
)
port map
(
clock_50mhz => clk,
keys => keys,
switches => switches,
leds => leds,
spi_cs => spi_cs,
spi_clk => spi_clk,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
spi_epcs_cs => spi_epcs_cs,
spi_epcs_clk => spi_epcs_clk,
spi_epcs_mosi => spi_epcs_mosi,
spi_epcs_miso => spi_epcs_miso,
arReconf => arReconf,
gpios => gpios
);
----------------------------------------------------------------------------------------------------------------------------
-- Testing process
Stimu : process
procedure spi_select is
begin
wait for c_byte_pad_t;
wait for c_byte_pad_t;
spi_cs(SPI_USER_CS_IDX) <= '0';
wait for c_byte_pad_t;
end procedure;
procedure spi_deselect is
begin
wait for c_byte_pad_t;
spi_cs(SPI_USER_CS_IDX) <= '1';
wait for c_byte_pad_t;
wait for c_byte_pad_t;
end procedure;
procedure spi_send_byte(dat : in std_ulogic_vector(7 downto 0)) is
begin
for i in 7 downto 0 loop
spi_mosi <= dat(i);
wait for c_bit_with_half_t;
spi_clk <= '1';
wait for c_bit_with_half_t;
spi_clk <= '0';
end loop;
spi_mosi <= '0';
wait for c_byte_pad_t;
end procedure;
procedure spi_send_byte_broken(dat : in std_ulogic_vector(7 downto 0)) is
begin
for i in 3 downto 0 loop
spi_mosi <= dat(i);
wait for c_bit_with_half_t;
spi_clk <= '1';
wait for c_bit_with_half_t;
spi_clk <= '0';
end loop;
spi_mosi <= '0';
wait for c_byte_pad_t;
end procedure;
begin
-- ########################################################################################################
-----------------------------------------------------------------------------------------------------------
-- Testing Code
wait for 10 ns;
gpios <= (others => 'H');
wait for 1 us;
spi_select;
gpios(2) <= 'L';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
--spi_send_byte(X"C3"); -- Garbage
wait for 1 us;
gpios(2) <= 'H';
spi_send_byte(X"02"); -- OUT
spi_send_byte(X"01");
spi_send_byte(X"00");
--spi_send_byte(X"C3"); -- Garbage
spi_send_byte(X"02"); -- OUT
spi_send_byte(X"01");
spi_send_byte(X"01");
--spi_send_byte(X"C3"); -- Garbage
spi_send_byte(X"02"); -- OUT
spi_send_byte(X"01");
spi_send_byte(X"00");
wait for 1 us;
gpios(2) <= 'L';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"01");
--spi_send_byte(X"C3"); -- Garbage
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"02");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"04");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"03");
wait for 1 us;
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'L';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
--spi_send_byte(X"00");
spi_deselect;
spi_select;
gpios(2) <= 'L';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
wait for 1 us;
gpios(2) <= 'H';
spi_send_byte(X"02"); -- OUT
spi_send_byte(X"01");
spi_send_byte(X"00");
spi_send_byte(X"02"); -- OUT
spi_send_byte(X"01");
spi_send_byte(X"01");
spi_send_byte(X"02"); -- OUT
spi_send_byte(X"01");
spi_send_byte(X"00");
wait for 1 us;
gpios(2) <= 'L';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"01");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"02");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"04");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
wait for 1 us;
spi_send_byte(X"02"); -- PWM
spi_send_byte(X"02");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"05");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_send_byte(X"03");
wait for 1 us;
gpios(2) <= 'H';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
gpios(2) <= 'L';
spi_send_byte(X"02"); -- IN
spi_send_byte(X"00");
spi_send_byte(X"00");
spi_deselect;
-----------------------------------------------------------------------------------------------------------
-- ########################################################################################################
assert false report "SIMULATION ENDED SUCCESSFULLY" severity note;
wait;
end process;
----------------------------------------------------------------------------------------------------------------------------
end bhv;
| gpl-2.0 | 54fa186c0ac89a6c741c690b51566e96 | 0.458518 | 2.979546 | false | false | false | false |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/src/frequency_divider.vhd | 3 | 3,282 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity frequencyDivider is
generic
(
divideBy : integer := 2
);
port
(
clock : in std_ulogic;
nResetAsync : in std_ulogic;
output : out std_ulogic
);
begin
assert (divideBy >= 4)
report "frequencyDivider: divideBy must be at least 4"
severity error;
assert (divideBy rem 2 = 0)
report "frequencyDivider: divideBy must be an even number"
severity error;
end frequencyDivider;
architecture rtl of frequencyDivider is
constant cHalfPeriodCounter : natural := divideBy / 2;
signal counter : unsigned(logDualis(cHalfPeriodCounter) - 1 downto 0);
signal sOutput : std_ulogic;
begin
procReset: process(nResetAsync, clock)
begin
if(nResetAsync = '0')then
counter <= (others => '0');
sOutput <= '0';
elsif(clock'event and clock = '1')then
if(counter = cHalfPeriodCounter - 1)then
counter <= (others => '0');
sOutput <= not(sOutput);
else
counter <= counter + 1;
end if;
end if;
end process;
output <= sOutput;
end architecture rtl;
| gpl-2.0 | 7327e399d4cca4e82008bfee0b228626 | 0.415905 | 5.080495 | false | false | false | false |
PsiStarPsi/firmware-general | General/rtl/UtilityPkg.vhd | 1 | 3,355 | -------------------------------------------------------------------------------
-- Title :
-------------------------------------------------------------------------------
-- File : UtilityPkg.vhd
-- Author : Kurtis Nishimura
-------------------------------------------------------------------------------
-- Description: A set of common useful definitions. Some of these ideas
-- originate from Ben Reese @ SLAC and his StdRtlPkg.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package UtilityPkg is
-- Shorthand names for common types
subtype sl is std_logic;
subtype slv is std_logic_vector;
-- Useful array types
type Word8Array is array (natural range <>) of slv( 7 downto 0);
type Word9Array is array (natural range <>) of slv( 8 downto 0);
type Word10Array is array (natural range <>) of slv( 9 downto 0);
type Word13Array is array (natural range <>) of slv(12 downto 0);
type Word16Array is array (natural range <>) of slv(15 downto 0);
type Word32Array is array (natural range <>) of slv(31 downto 0);
-----------------------
-- Function prototypes
-----------------------
-- Grab 1 byte of an input SLV
function getByte (byteNum : integer; input : slv) return slv;
-- Conditional selection of constants
function sel (conditional : boolean; if_true : natural; if_false : natural) return natural;
-- Count number of 1's in a std_logic_vector
function countOnes (input : slv) return integer;
-- Sum up number of bytes
function sumBytes (input : Word8Array) return integer;
-- Sum up an array of 2-byte inputs
function sum2Bytes (input : Word16Array) return integer;
end UtilityPkg;
package body UtilityPkg is
function getByte (byteNum : integer; input : slv) return slv is
variable retVar : slv(7 downto 0) := (others => '0');
begin
-- Make sure that we're not looking out of range of the input
assert(byteNum*8 <= input'length and byteNum >= 0) report "Byte number is out of range!" severity failure;
-- Calculate the byte we want
retVar := input(8*byteNum+7 downto 8*byteNum);
return retVar;
end function;
function sel (conditional : boolean; if_true : natural; if_false : natural) return natural is
begin
if (conditional = true) then
return(if_true);
else
return(if_false);
end if;
end function;
function countOnes (input : slv) return integer is
variable retVal : integer := 0;
begin
for i in input'range loop
if
input(i) = '1' then retVal := retVal + 1;
end if;
end loop;
return retVal;
end function;
function sumBytes (input : Word8Array) return integer is
variable retVal : integer := 0;
begin
for i in input'range loop
retVal := retVal + conv_integer(input(i));
end loop;
return retVal;
end function;
function sum2Bytes (input : Word16Array) return integer is
variable retVal : integer := 0;
begin
for i in input'range loop
retVal := retVal + conv_integer(input(i));
end loop;
return retVal;
end function;
end package body UtilityPkg;
| lgpl-2.1 | d249c41f9092d60501b5db73c1dd505b | 0.579732 | 4.397117 | false | false | false | false |
pkerling/ethernet_mac | miim_control.vhd | 1 | 9,027 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_types.all;
use work.miim_types.all;
use work.miim_registers.all;
entity miim_control is
generic(
-- Ticks to wait before writing any registers after reset low
RESET_WAIT_TICKS : natural := 0;
-- Ticks to wait between polling the status register
POLL_WAIT_TICKS : natural := DEFAULT_POLL_WAIT_TICKS;
-- Activate debug output
DEBUG_OUTPUT : boolean := FALSE
-- Example for Marvell PHY 88E1111 and 125 MHz MIIM clock:
-- RESET_WAIT_TICKS => 1250000 (10 ms at 125 MHz, minimum: 5 ms)
);
port(
reset_i : in std_ulogic;
clock_i : in std_ulogic;
miim_register_address_o : out t_register_address;
miim_data_read_i : in t_data;
miim_data_write_o : out t_data;
miim_req_o : out std_ulogic;
miim_ack_i : in std_ulogic;
miim_we_o : out std_ulogic;
speed_o : out t_ethernet_speed;
link_up_o : out std_ulogic;
-- Only used if DEBUG_OUTPUT is TRUE
debug_fifo_we_o : out std_ulogic;
debug_fifo_write_data_o : out std_ulogic_vector(7 downto 0)
);
end entity;
architecture rtl of miim_control is
signal register_address : t_register_address;
type t_state is (
RESET_WAIT,
WRITE_AUTONEG,
WRITE_GIGABIT_AUTONEG,
WRITE_SOFTRESET,
WAIT_POLL,
READ_STATUS,
READ_SPEED_10_100,
READ_SPEED_1000,
DEBUG_START,
DEBUG_WRITE_REGAD,
DEBUG_WRITE_BYTE1,
DEBUG_WRITE_BYTE2,
WAIT_ACK_LOW,
DEBUG_DONE
);
signal state : t_state := RESET_WAIT;
signal after_ack_state : t_state;
-- Initial register write contents
-- Reset the PHY
constant control_register_reset : t_control_register := (
reset => '1',
loopback => '0',
speed_10_100 => '0',
speed_1000 => '1',
auto_negotiation_enable => '1',
power_down => '0',
isolate => '0',
restart_auto_negotiation => '0',
duplex_mode => '1',
enable_collision_test => '0',
unidirectional_enable => '0'
);
-- Activate only full-duplex 10/100
constant auto_negotiation_set_fd : t_auto_negotiation_advertisement_register_802_3 := (
next_page => '0',
remote_fault => '0',
extended_next_page => '0',
asymmetric_pause => '0',
pause => '0',
advertise_100base_t4 => '0',
advertise_100base_tx_fd => '1',
advertise_100base_tx_hd => '0',
advertise_10base_t_fd => '1',
advertise_10base_t_hd => '0'
);
-- Activate only full-duplex 1000
constant master_slave_set_fd : t_master_slave_control_register := (
test_mode_bits => "000",
master_slave_manual_config_enable => '0',
master_slave_manual_config_value => '0',
port_type_is_multiport => '0',
advertise_1000base_t_fd => '1',
advertise_1000base_t_hd => '0'
);
signal init_done : boolean := FALSE;
signal reset_wait_counter : natural range 0 to RESET_WAIT_TICKS + 1;
signal poll_wait_counter : natural range 0 to POLL_WAIT_TICKS + 1;
signal lp_supports_10 : std_ulogic;
signal lp_supports_100 : std_ulogic;
begin
miim_register_address_o <= register_address;
fsm : process(clock_i)
begin
if rising_edge(clock_i) then
-- Default values
miim_req_o <= '0';
debug_fifo_we_o <= '0';
if reset_i = '1' then
state <= RESET_WAIT;
link_up_o <= '0';
speed_o <= SPEED_UNSPECIFIED;
reset_wait_counter <= 0;
poll_wait_counter <= 0;
else
miim_we_o <= '0';
case state is
-- Initialization
when RESET_WAIT =>
-- Keep in mind that zero is a valid (and the default) value for RESET_WAIT_TICKS
if reset_wait_counter = RESET_WAIT_TICKS then
state <= WRITE_AUTONEG;
end if;
reset_wait_counter <= reset_wait_counter + 1;
when WRITE_AUTONEG =>
-- Advertise 100 MBit/10 MBit full-duplex, no PAUSE support
register_address <= AUTONEG_ADVERTISEMENT_REG;
miim_data_write_o <= auto_negotiation_advertisement_register_802_3_to_data(auto_negotiation_set_fd);
miim_req_o <= '1';
miim_we_o <= '1';
if miim_ack_i = '1' then
miim_req_o <= '0';
state <= WAIT_ACK_LOW;
after_ack_state <= WRITE_GIGABIT_AUTONEG;
end if;
when WRITE_GIGABIT_AUTONEG =>
-- Advertise 1000 MBit full-duplex
register_address <= MASTERSLAVE_CTRL_REG;
miim_data_write_o <= master_slave_control_register_to_data(master_slave_set_fd);
miim_req_o <= '1';
miim_we_o <= '1';
if miim_ack_i = '1' then
miim_req_o <= '0';
state <= WAIT_ACK_LOW;
after_ack_state <= WRITE_SOFTRESET;
end if;
when WRITE_SOFTRESET =>
-- Reset the PHY to apply the autonegotiation values
register_address <= CONTROL_REG;
miim_data_write_o <= control_register_to_data(control_register_reset);
miim_req_o <= '1';
miim_we_o <= '1';
if miim_ack_i = '1' then
miim_req_o <= '0';
init_done <= TRUE;
state <= WAIT_ACK_LOW;
after_ack_state <= WAIT_POLL;
end if;
-- State polling
when WAIT_POLL =>
-- Don't poll continuously to reduce unnecessary switching noise
poll_wait_counter <= poll_wait_counter + 1;
if poll_wait_counter = POLL_WAIT_TICKS then
poll_wait_counter <= 0;
state <= READ_STATUS;
end if;
when READ_STATUS =>
-- Read status register
register_address <= STATUS_REG;
miim_req_o <= '1';
if miim_ack_i = '1' then
-- Link is up when the link status indicator and auto-negotiation is OK
link_up_o <= data_to_status_register(miim_data_read_i).link_status and data_to_status_register(miim_data_read_i).auto_negotiation_complete;
miim_req_o <= '0';
state <= WAIT_ACK_LOW;
after_ack_state <= READ_SPEED_10_100;
end if;
when READ_SPEED_10_100 =>
-- Read link partner ability register
register_address <= AUTONEG_LP_BASEPAGEABILITY_REG;
miim_req_o <= '1';
if miim_ack_i = '1' then
miim_req_o <= '0';
lp_supports_10 <= data_to_auto_negotiation_lp_base_page_ability_register(miim_data_read_i).can_10base_t_fd;
lp_supports_100 <= data_to_auto_negotiation_lp_base_page_ability_register(miim_data_read_i).can_100base_tx_fd;
state <= WAIT_ACK_LOW;
after_ack_state <= READ_SPEED_1000;
end if;
when READ_SPEED_1000 =>
register_address <= MASTERSLAVE_STATUS_REG;
miim_req_o <= '1';
if miim_ack_i = '1' then
miim_req_o <= '0';
-- Detect highest supported data rate
if data_to_master_slave_status_register(miim_data_read_i).lp_1000base_t_fd = '1' then
speed_o <= SPEED_1000MBPS;
elsif lp_supports_100 = '1' then
speed_o <= SPEED_100MBPS;
elsif lp_supports_10 = '1' then
speed_o <= SPEED_10MBPS;
else
-- Nothing is supported
speed_o <= SPEED_UNSPECIFIED;
end if;
state <= WAIT_ACK_LOW;
register_address <= (others => '0');
if DEBUG_OUTPUT = TRUE then
after_ack_state <= DEBUG_START;
else
after_ack_state <= WAIT_POLL;
end if;
end if;
-- Debug states
when DEBUG_START =>
if miim_ack_i = '1' then
state <= DEBUG_WRITE_REGAD;
debug_fifo_we_o <= '1';
debug_fifo_write_data_o <= "000" & std_ulogic_vector(register_address);
else
miim_req_o <= '1';
end if;
when DEBUG_WRITE_REGAD =>
debug_fifo_we_o <= '1';
debug_fifo_write_data_o <= miim_data_read_i(15 downto 8);
state <= DEBUG_WRITE_BYTE1;
when DEBUG_WRITE_BYTE1 =>
debug_fifo_we_o <= '1';
debug_fifo_write_data_o <= miim_data_read_i(7 downto 0);
state <= DEBUG_WRITE_BYTE2;
when DEBUG_WRITE_BYTE2 =>
if register_address = "11111" then
register_address <= (others => '0');
state <= DEBUG_DONE;
else
register_address <= register_address + 1;
after_ack_state <= DEBUG_START;
state <= WAIT_ACK_LOW;
end if;
when DEBUG_DONE =>
--state <= WAIT_DEBUG_START;
state <= WAIT_POLL;
-- Auxiliary state
when WAIT_ACK_LOW =>
if miim_ack_i = '0' then
state <= after_ack_state;
end if;
end case;
end if;
end if;
end process;
end architecture;
| bsd-3-clause | bb50d420a9bddface12fbbcfaaf0a414 | 0.568074 | 3.065195 | false | false | false | false |
Dragonturtle/SHERPA | HDL/SHERPA/prn_code_generator.vhd | 1 | 2,026 | library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all;
entity prn_code_generator is
generic (
idx1 : natural := 1;
idx2 : natural := 5
) ;
port (
enable_in : in std_logic ;
data_in : in std_logic ;
clock_in : in std_logic ;
I_out : out std_logic_vector(7 downto 0) ;
Q_out : out std_logic_vector(7 downto 0) := "00000000"
) ;
end entity ;
architecture arch of prn_code_generator is
alias ena : std_logic is enable_in;
alias clk : std_logic is clock_in;
begin
----------------------------
-- PRN Generation Process --
----------------------------
prncode : process( clk, ena )
variable G1 : bit_vector(14 downto 0) := "111111111111111";
variable G2 : bit_vector(14 downto 0) := "111111111111111";
variable data_q : bit := '0';
variable G1_q : bit := '0';
variable G2_q : bit := '0';
variable counter : natural range 0 to 32767 := 0 ;
begin
if( ena = '0' ) then
I_out <= "10000000" ; -- 0
Q_out <= "10000000" ; -- 0
G1 := "111111111111111";
G2 := "111111111111111";
data_q := '0';
G1_q := '0';
G2_q := '0';
counter := 0;
elsif( rising_edge( clk ) ) then
-------------------------
-- PRN Code Generation --
-------------------------
data_q := (G1(14) xor G2(idx1) xor G2(idx2) xor to_bit(data_in));
if ( data_q = '1' ) then
I_out <= "11111111"; -- 127
else
I_out <= "00000000"; -- -128
end if;
-- G1_q := G1(7) xor G1(4) xor G1(6) xor G1(14);
-- G2_q := G2(1) xor G2(2) xor G2(3) xor G2(5) xor G2(7) xor G2(9) xor G2(10) xor G2(11) xor G2(13) xor G2(14);
G1_q := G1(7) xor G1(14);
G2_q := G2(8) xor G2(10) xor G2(11) xor G2(12) xor G2(13) xor G2(14);
G1(14 downto 1) := G1(13 downto 0);-- sll 1;
G2(14 downto 1) := G2(13 downto 0);-- sll 1;
G1(0) := G1_q;
G2(0) := G2_q;
end if ;
end process ;
end architecture; | gpl-3.0 | 51c6616bf0ff0c9365e6a246eed362cb | 0.495558 | 2.694149 | false | false | false | false |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/src/altremote_pulsed.vhd | 3 | 7,770 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
use work.global.all;
entity altremotePulsed is
port
(
clock : in std_ulogic;
nResetAsync : in std_ulogic;
reconf : in std_ulogic -- One clock cycle high => Reconf
);
end entity altremotePulsed;
architecture rtl of altremotePulsed is
component altremote is
port (
read_param : in std_logic := 'X'; -- read_param
param : in std_logic_vector(2 downto 0) := (others => 'X'); -- param
reconfig : in std_logic := 'X'; -- reconfig
reset_timer : in std_logic := 'X'; -- reset_timer
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
busy : out std_logic; -- busy
data_out : out std_logic_vector(28 downto 0); -- data_out
read_source : in std_logic_vector(1 downto 0) := (others => 'X'); -- read_source
write_param : in std_logic := 'X'; -- write_param
data_in : in std_logic_vector(23 downto 0) := (others => 'X') -- data_in
);
end component altremote;
type STATEMACHINE_STEP_TYPE is
(
SM_INIT, SM_SET_RESET, SM_WRITE_BOOT_ADDRESS, SM_TURN_OFF_WDT, SM_SET_EARLY_CONF_DONE_CHECK, SM_WRITE_PARAM, SM_WAIT_BUSY, SM_IDLE, SM_RECONF_READY
);
type REG_TYPE is record
sm_step : STATEMACHINE_STEP_TYPE;
sm_step_ret : STATEMACHINE_STEP_TYPE;
param : std_logic_vector(2 downto 0);
data_in : std_logic_vector(23 downto 0);
ar_reset_cnt : natural;
end record;
constant RSET_INIT_VAL : REG_TYPE :=
(
sm_step => SM_INIT,
sm_step_ret => SM_INIT,
param => "000",
data_in => (others => '0'),
ar_reset_cnt => 0
);
signal R, NxR : REG_TYPE;
signal clk_3 : std_ulogic;
signal ar_data_in : std_logic_vector(23 downto 0);
signal ar_param : std_logic_vector(2 downto 0);
signal ar_reconfig : std_logic;
signal ar_reset : std_logic;
signal ar_write_param : std_logic;
signal ar_busy : std_logic;
begin
altremote_inst : altremote
port map
(
clock => clk_3,
data_in => ar_data_in,
param => ar_param,
read_param => '0',
read_source => "00",
reconfig => ar_reconfig,
reset => ar_reset,
reset_timer => '0',
write_param => ar_write_param,
busy => ar_busy,
data_out => open
);
eALTREMOTE_CLK: entity work.frequencyDivider(rtl)
generic map
(
divideBy => 16
)
port map
(
clock => clock,
nResetAsync => nResetAsync,
output => clk_3
);
proc_comb: process(R, reconf, ar_busy)
begin
NxR <= R;
-- standard values
ar_data_in <= (others => '0');
ar_param <= "000";
ar_write_param <= '0';
ar_reconfig <= '0';
ar_reset <= '0';
-- fsm
case R.sm_step is
when SM_IDLE =>
if(reconf = '0')then
NxR.sm_step <= SM_RECONF_READY;
end if;
when SM_RECONF_READY =>
if(reconf = '1')then
ar_reconfig <= '1';
end if;
when SM_INIT =>
NxR.sm_step <= SM_SET_RESET;
when SM_SET_RESET =>
ar_reset <= '1';
if(R.ar_reset_cnt = 15)then
NxR.sm_step <= SM_WRITE_BOOT_ADDRESS;
else
NxR.ar_reset_cnt <= R.ar_reset_cnt + 1;
end if;
when SM_WRITE_BOOT_ADDRESS =>
NxR.param <= "100";
NxR.data_in <= (others => '0');
NxR.sm_step <= SM_WRITE_PARAM;
NxR.sm_step_ret <= SM_TURN_OFF_WDT;
when SM_TURN_OFF_WDT =>
NxR.param <= "011";
NxR.data_in <= (others => '0');
NxR.sm_step <= SM_WRITE_PARAM;
NxR.sm_step_ret <= SM_SET_EARLY_CONF_DONE_CHECK;
when SM_SET_EARLY_CONF_DONE_CHECK =>
NxR.param <= "001";
NxR.data_in <= (others => '1');
NxR.sm_step <= SM_WRITE_PARAM;
NxR.sm_step_ret <= SM_IDLE;
when SM_WRITE_PARAM =>
ar_param <= R.param;
ar_data_in <= R.data_in;
ar_write_param <= '1';
if(ar_busy = '1')then
NxR.sm_step <= SM_WAIT_BUSY;
end if;
when SM_WAIT_BUSY =>
ar_data_in <= R.data_in;
if(ar_busy = '0')then
NxR.sm_step <= R.sm_step_ret;
end if;
when others =>
null;
end case;
end process;
proc_reg: process(nResetAsync, clock)
begin
if(nResetAsync = '0')then
R <= RSET_INIT_VAL;
elsif(clock'event and clock = '1')then
R <= NxR;
end if;
end process;
end architecture rtl;
| gpl-2.0 | 7a9e5cb359ea0a7d5d199dab01ddb90e | 0.397941 | 4.259868 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_uart/niosii_top.vhd | 2 | 3,050 | ----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
----------------------------------------------------------------------------------
--The MIT License (MIT)
--
--Copyright (c) 2015
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
----------------------------------------------------------------------------------
-- Library Define
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity niosii_top is
Port (
p_clk_50Mhz : in std_logic;
p_button : in std_logic_vector( 1 downto 0 );
p_led_out : out std_logic_vector( 7 downto 0 );
p_uart_0_rxd : in std_logic;
p_uart_0_txd : out std_logic
);
end niosii_top;
architecture Behavioral of niosii_top is
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_rxd : in std_logic := 'X'; -- rxd
uart_0_txd : out std_logic -- txd
);
end component niosii;
signal s_reset_n : std_logic;
begin
s_reset_n <= p_button(0);
u0 : component niosii
port map (
clk_clk => p_clk_50Mhz,
pio_0_external_connection_export => p_led_out,
reset_reset_n => s_reset_n,
uart_0_rxd => p_uart_0_rxd,
uart_0_txd => p_uart_0_txd
);
end Behavioral;
| mit | 55dc08aa50b704ff2274c7d3bc1739aa | 0.54 | 4.138399 | false | false | false | false |
pkerling/ethernet_mac | crc32_tb.vhd | 1 | 5,049 | -- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Simple testbench for playing around with the CRC calculation code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.crc32.all;
use work.utility.all;
entity crc32_tb is
end entity;
architecture behavioral of crc32_tb is
-- "Known good" function for comparison
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8(DATA : std_ulogic_vector(7 downto 0);
CRC : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
variable D : std_ulogic_vector(7 downto 0);
variable C : std_ulogic_vector(31 downto 0);
variable NEWCRC : std_ulogic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0) := C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1) := C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(2) := C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(3) := C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(4) := C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(5) := C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6) := C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7) := C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24) xor D(7);
NewCRC(8) := C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6) xor C(24) xor D(7);
NewCRC(9) := C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5) xor C(25) xor D(6);
NewCRC(10) := C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24) xor D(7);
NewCRC(11) := C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6) xor C(24) xor D(7);
NewCRC(12) := C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13) := C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14) := C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15) := C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4);
NewCRC(16) := C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17) := C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18) := C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19) := C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20) := C(12) xor C(28) xor D(3);
NewCRC(21) := C(13) xor C(29) xor D(2);
NewCRC(22) := C(14) xor C(24) xor D(7);
NewCRC(23) := C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24) := C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25) := C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26) := C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(27) := C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(28) := C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29) := C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30) := C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31) := C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Signals as isim cannot trace variables
signal crc : t_crc32;
signal comparison_crc : t_crc32;
signal data : std_ulogic_vector(7 downto 0);
constant WAIT_PERIOD : time := 40 ns;
begin
test_crc32 : process
variable saved_crc : t_crc32;
begin
crc <= (others => '1');
comparison_crc <= (others => '1');
data <= (others => '0');
wait for WAIT_PERIOD;
for cnt in 0 to 10 loop
crc <= update_crc32(crc, data);
comparison_crc <= NEXTCRC32_D8(data, crc);
if cnt >= 7 then
data <= (others => '0');
else
data <= std_ulogic_vector(to_unsigned(cnt + 1, 8));
end if;
wait for WAIT_PERIOD;
if crc /= comparison_crc then
report "CRC mismatch" severity note;
end if;
end loop;
saved_crc := not reverse_vector(crc);
wait for 100 ns;
for j in 0 to 3 loop
crc <= update_crc32(crc, saved_crc(((j + 1) * 8) - 1 downto j * 8));
comparison_crc <= NEXTCRC32_D8(saved_crc(((j + 1) * 8) - 1 downto j * 8), crc);
wait for WAIT_PERIOD;
end loop;
--crc <= reverse_vector(crc);
wait for WAIT_PERIOD;
if crc /= X"C704dd7B" then
report "Final CRC wrong" severity note;
end if;
wait;
end process;
end architecture;
| bsd-3-clause | eacd24a97c38c594307882a511f66fb2 | 0.584076 | 2.287721 | false | false | false | false |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/src/input_sync.vhd | 2 | 3,389 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity input_sync is
generic
(
num_inputs : integer := 1;
num_sync_stages : integer := 1
);
port
(
clock : in std_ulogic;
n_reset_async : in std_ulogic;
unsynced_inputs : in std_ulogic_vector(num_inputs - 1 downto 0);
synced_outputs : out std_ulogic_vector(num_inputs - 1 downto 0)
);
begin
assert 0 < num_inputs report "'num_inputs' must be greater than zero" severity error;
assert 0 < num_sync_stages report "'num_sync_stages' must be greater than zero" severity error;
end input_sync;
architecture rtl of input_sync is
type stages is array (0 to num_sync_stages - 1) of std_ulogic_vector(num_inputs - 1 downto 0);
signal q : stages;
begin
process(clock)
begin
if(clock'event and clock = '1') then
if('0' = n_reset_async) then
q(0) <= (others => '0');
else
q(0) <= unsynced_inputs;
end if;
end if;
end process;
lbl_stages: for i in 0 to num_sync_stages - 2 generate
process(clock)
begin
if(clock'event and clock = '1') then
q(i + 1) <= q(i);
end if;
end process;
end generate;
synced_outputs <= q(num_sync_stages - 1);
end architecture rtl;
| gpl-2.0 | ff4d0b17997e7f9de46febe49ad72e9f | 0.414577 | 4.746499 | false | false | false | false |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/src/strobe_gen.vhd | 2 | 3,184 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DSP-Crowd project --
-- https://www.dsp-crowd.com --
-- --
-- Author(s): --
-- - Johannes Natter, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.dsp-crowd.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity strobe_gen is
generic
(
num_clock_cycles : natural := 1
);
port
(
clock : in std_ulogic;
n_reset_async : in std_ulogic;
strobe_output : out std_ulogic
);
begin
assert (num_clock_cycles >= 1)
report "strobe_gen: num_clock_cycles must be at least 1"
severity error;
end strobe_gen;
architecture rtl of strobe_gen is
type REG_TYPE is record
counter : natural;
end record;
constant RSET_INIT_VAL : REG_TYPE :=
(
counter => 0
);
signal R, NxR : REG_TYPE;
begin
proc_comb: process(R)
begin
NxR <= R;
NxR.counter <= R.counter + 1;
strobe_output <= '0';
if(R.counter = num_clock_cycles - 1)then
NxR.counter <= 0;
strobe_output <= '1';
end if;
end process;
proc_reg: process(n_reset_async, clock)
begin
if(n_reset_async = '0')then
R <= RSET_INIT_VAL;
elsif(clock'event and clock = '1')then
R <= NxR;
end if;
end process;
end architecture rtl;
| gpl-2.0 | 65968c3eba55060bd3e373bc00c8ce1c | 0.394158 | 4.675477 | false | false | false | false |
chcbaram/Altera_DE0_nano_Exam | prj_niosii/niosii/synthesis/niosii.vhd | 1 | 42,861 | -- niosii.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii is
port (
clk_clk : in std_logic := '0'; -- clk.clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- pio_0_external_connection.export
reset_reset_n : in std_logic := '0' -- reset.reset_n
);
end entity niosii;
architecture rtl of niosii is
component niosii_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component niosii_jtag_uart_0;
component niosii_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(17 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
d_readdatavalid : in std_logic := 'X'; -- readdatavalid
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(17 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
i_readdatavalid : in std_logic := 'X'; -- readdatavalid
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component niosii_nios2_gen2_0;
component niosii_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component niosii_onchip_memory2_0;
component niosii_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component niosii_pio_0;
component niosii_mm_interconnect_0 is
port (
clk_0_clk_clk : in std_logic := 'X'; -- clk
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_data_master_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_readdatavalid : out std_logic; -- readdatavalid
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_instruction_master_readdatavalid : out std_logic; -- readdatavalid
jtag_uart_0_avalon_jtag_slave_address : out std_logic_vector(0 downto 0); -- address
jtag_uart_0_avalon_jtag_slave_write : out std_logic; -- write
jtag_uart_0_avalon_jtag_slave_read : out std_logic; -- read
jtag_uart_0_avalon_jtag_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_uart_0_avalon_jtag_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(13 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic -- chipselect
);
end component niosii_mm_interconnect_0;
component niosii_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component niosii_irq_mapper;
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(17 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_readdatavalid : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_readdatavalid -> nios2_gen2_0:d_readdatavalid
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(17 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal nios2_gen2_0_instruction_master_readdatavalid : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdatavalid -> nios2_gen2_0:i_readdatavalid
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(13 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal irq_mapper_receiver0_irq : std_logic; -- jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> rst_controller:reset_in0
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:inv -> jtag_uart_0:av_read_n
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:inv -> jtag_uart_0:av_write_n
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [jtag_uart_0:rst_n, nios2_gen2_0:reset_n, pio_0:reset_n]
begin
jtag_uart_0 : component niosii_jtag_uart_0
port map (
clk => clk_clk, -- clk.clk
rst_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- avalon_jtag_slave.chipselect
av_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address(0), -- .address
av_read_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv, -- .read_n
av_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
av_write_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv, -- .write_n
av_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
av_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
av_irq => irq_mapper_receiver0_irq -- irq.irq
);
nios2_gen2_0 : component niosii_nios2_gen2_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
d_readdatavalid => nios2_gen2_0_data_master_readdatavalid, -- .readdatavalid
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
i_readdatavalid => nios2_gen2_0_instruction_master_readdatavalid, -- .readdatavalid
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component niosii_onchip_memory2_0
port map (
clk => clk_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req -- .reset_req
);
pio_0 : component niosii_pio_0
port map (
clk => clk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
out_port => pio_0_external_connection_export -- external_connection.export
);
mm_interconnect_0 : component niosii_mm_interconnect_0
port map (
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_readdatavalid => nios2_gen2_0_data_master_readdatavalid, -- .readdatavalid
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
nios2_gen2_0_instruction_master_readdatavalid => nios2_gen2_0_instruction_master_readdatavalid, -- .readdatavalid
jtag_uart_0_avalon_jtag_slave_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address, -- jtag_uart_0_avalon_jtag_slave.address
jtag_uart_0_avalon_jtag_slave_write => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write, -- .write
jtag_uart_0_avalon_jtag_slave_read => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read, -- .read
jtag_uart_0_avalon_jtag_slave_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect -- .chipselect
);
irq_mapper : component niosii_irq_mapper
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of niosii
| mit | 2d279565846284bc1068477d6d3f0700 | 0.494972 | 3.659267 | false | false | false | false |
DSP-Crowd/software | _install/de0_nano/src/input_sync.vhd | 1 | 3,385 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity input_sync is
generic
(
num_inputs : integer := 1;
num_sync_stages : integer := 1
);
port
(
clock : in std_ulogic;
n_reset_async : in std_ulogic;
unsynced_inputs : in std_ulogic_vector(num_inputs - 1 downto 0);
synced_outputs : out std_ulogic_vector(num_inputs - 1 downto 0)
);
begin
assert 0 < num_inputs report "'num_inputs' must be greater than zero" severity error;
assert 0 < num_sync_stages report "'num_sync_stages' must be greater than zero" severity error;
end input_sync;
architecture rtl of input_sync is
type stages is array (0 to num_sync_stages - 1) of std_ulogic_vector(num_inputs - 1 downto 0);
signal q : stages;
begin
process(clock, n_reset_async)
begin
if(n_reset_async = '0') then
q(0) <= (others => '0');
elsif(clock'event and clock = '1') then
q(0) <= unsynced_inputs;
end if;
end process;
lbl_stages: for i in 0 to num_sync_stages - 2 generate
process(clock)
begin
if(clock'event and clock = '1') then
q(i + 1) <= q(i);
end if;
end process;
end generate;
synced_outputs <= q(num_sync_stages - 1);
end architecture rtl;
| gpl-2.0 | c9e8f99c96245c31fa260d0bb6d6592b | 0.416544 | 4.754213 | false | false | false | false |
DSP-Crowd/software | apps/mobile_rgb-led/de0_nano/src/sdram_0_test_component.vhd | 2 | 22,747 | --Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
--synthesis translate_off
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity sdram_0_test_component_ram_module is
port (
-- inputs:
signal data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
signal rdclken : IN STD_LOGIC;
signal wraddress : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
signal wrclock : IN STD_LOGIC;
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end entity sdram_0_test_component_ram_module;
architecture europa of sdram_0_test_component_ram_module is
signal internal_q : STD_LOGIC_VECTOR (15 DOWNTO 0);
TYPE mem_array is ARRAY( 16777215 DOWNTO 0) of STD_LOGIC_VECTOR(15 DOWNTO 0);
signal memory_has_been_read : STD_LOGIC;
signal read_address : STD_LOGIC_VECTOR (23 DOWNTO 0);
FUNCTION convert_string_to_number(string_to_convert : STRING;
final_char_index : NATURAL := 0)
RETURN NATURAL IS
VARIABLE result: NATURAL := 0;
VARIABLE current_index : NATURAL := 1;
VARIABLE the_char : CHARACTER;
BEGIN
IF final_char_index = 0 THEN
result := 0;
ELSE
WHILE current_index <= final_char_index LOOP
the_char := string_to_convert(current_index);
IF '0' <= the_char AND the_char <= '9' THEN
result := result * 16 + character'pos(the_char) - character'pos('0');
ELSIF 'A' <= the_char AND the_char <= 'F' THEN
result := result * 16 + character'pos(the_char) - character'pos('A') + 10;
ELSIF 'a' <= the_char AND the_char <= 'f' THEN
result := result * 16 + character'pos(the_char) - character'pos('a') + 10;
ELSE
report "Ack, a formatting error!";
END IF;
current_index := current_index + 1;
END LOOP;
END IF;
RETURN result;
END convert_string_to_number;
FUNCTION convert_string_to_std_logic(value : STRING; num_chars : INTEGER; mem_width_bits : INTEGER)
RETURN STD_LOGIC_VECTOR is
VARIABLE conv_string: std_logic_vector((mem_width_bits + 4)-1 downto 0);
VARIABLE result : std_logic_vector((mem_width_bits -1) downto 0);
VARIABLE curr_char : integer;
BEGIN
result := (others => '0');
conv_string := (others => '0');
FOR I IN 1 TO num_chars LOOP
curr_char := num_chars - (I-1);
CASE value(I) IS
WHEN '0' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0000";
WHEN '1' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0001";
WHEN '2' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0010";
WHEN '3' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0011";
WHEN '4' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0100";
WHEN '5' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0101";
WHEN '6' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0110";
WHEN '7' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "0111";
WHEN '8' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1000";
WHEN '9' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1001";
WHEN 'A' | 'a' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1010";
WHEN 'B' | 'b' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1011";
WHEN 'C' | 'c' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1100";
WHEN 'D' | 'd' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1101";
WHEN 'E' | 'e' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1110";
WHEN 'F' | 'f' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "1111";
WHEN 'X' | 'x' => conv_string((4*curr_char)-1 DOWNTO 4*(curr_char-1)) := "XXXX";
WHEN ' ' => EXIT;
WHEN HT => exit;
WHEN others =>
ASSERT False
REPORT "function From_Hex: string """ & value & """ contains non-hex character"
severity Error;
EXIT;
END case;
END loop;
-- convert back to normal bit size
result(mem_width_bits - 1 downto 0) := conv_string(mem_width_bits - 1 downto 0);
RETURN result;
END convert_string_to_std_logic;
begin
process (wrclock, rdaddress) -- MG
VARIABLE data_line : LINE;
VARIABLE the_character_from_data_line : CHARACTER;
VARIABLE b_munging_address : BOOLEAN := FALSE;
VARIABLE converted_number : NATURAL := 0;
VARIABLE found_string_array : STRING(1 TO 128);
VARIABLE string_index : NATURAL := 0;
VARIABLE line_length : NATURAL := 0;
VARIABLE b_convert : BOOLEAN := FALSE;
VARIABLE b_found_new_val : BOOLEAN := FALSE;
VARIABLE load_address : NATURAL := 0;
VARIABLE mem_index : NATURAL := 0;
VARIABLE mem_init : BOOLEAN := FALSE;
VARIABLE wr_address_internal : STD_LOGIC_VECTOR (23 DOWNTO 0) := (others => '0');
FILE memory_contents_file : TEXT OPEN read_mode IS "../../DCD_APP1/SYS_DE0N/objs/dcd_app1.dat";
variable Marc_Gaucherons_Memory_Variable : mem_array; -- MG
begin
-- need an initialization process
-- this process initializes the whole memory array from a named file by copying the
-- contents of the *.dat file to the memory array.
-- find the @<address> thingy to load the memory from this point
IF(NOT mem_init) THEN
WHILE NOT(endfile(memory_contents_file)) LOOP
readline(memory_contents_file, data_line);
line_length := data_line'LENGTH;
WHILE line_length > 0 LOOP
read(data_line, the_character_from_data_line);
-- check for the @ character indicating a new address wad
-- if not found, we're either still reading the new address _or_loading data
IF '@' = the_character_from_data_line AND NOT b_munging_address THEN
b_munging_address := TRUE;
b_found_new_val := TRUE;
-- get the rest of characters before white space and then convert them
-- to a number
ELSE
IF (' ' = the_character_from_data_line AND b_found_new_val)
OR (line_length = 1) THEN
b_convert := TRUE;
END IF;
IF NOT(' ' = the_character_from_data_line) THEN
string_index := string_index + 1;
found_string_array(string_index) := the_character_from_data_line;
-- IF NOT(b_munging_address) THEN
-- dat_string_array(string_index) := the_character_from_data_line;
-- END IF;
b_found_new_val := TRUE;
END IF;
END IF;
IF b_convert THEN
IF b_munging_address THEN
converted_number := convert_string_to_number(found_string_array, string_index);
load_address := converted_number;
mem_index := load_address;
-- mem_index := load_address / 2;
b_munging_address := FALSE;
ELSE
IF (mem_index < 16777216) THEN
Marc_Gaucherons_Memory_Variable(mem_index) := convert_string_to_std_logic(found_string_array, string_index, 16);
mem_index := mem_index + 1;
END IF;
END IF;
b_convert := FALSE;
b_found_new_val := FALSE;
string_index := 0;
END IF;
line_length := line_length - 1;
END LOOP;
END LOOP;
-- get the first _real_ block of data, sized to our memory width
-- and keep on loading.
mem_init := TRUE;
END IF;
-- END OF READMEM
-- Write data
if wrclock'event and wrclock = '1' then
wr_address_internal := wraddress;
if wren = '1' then
Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(wr_address_internal))) := data;
end if;
end if;
-- read data
q <= Marc_Gaucherons_Memory_Variable(CONV_INTEGER(UNSIGNED(rdaddress))) after 6.5 ns;
end process;
end europa;
--synthesis translate_on
--synthesis read_comments_as_HDL on
--library altera;
--use altera.altera_europa_support_lib.all;
--
--library ieee;
--use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--
--library std;
--use std.textio.all;
--
--entity sdram_0_test_component_ram_module is
-- port (
--
-- signal data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- signal rdaddress : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-- signal rdclken : IN STD_LOGIC;
-- signal wraddress : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-- signal wrclock : IN STD_LOGIC;
-- signal wren : IN STD_LOGIC;
--
--
-- signal q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
-- );
--end entity sdram_0_test_component_ram_module;
--
--
--architecture europa of sdram_0_test_component_ram_module is
-- component lpm_ram_dp is
--GENERIC (
-- lpm_file : STRING;
-- lpm_hint : STRING;
-- lpm_indata : STRING;
-- lpm_outdata : STRING;
-- lpm_rdaddress_control : STRING;
-- lpm_width : NATURAL;
-- lpm_widthad : NATURAL;
-- lpm_wraddress_control : STRING;
-- suppress_memory_conversion_warnings : STRING
-- );
-- PORT (
-- signal q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
-- signal rdaddress : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-- signal wren : IN STD_LOGIC;
-- signal wrclock : IN STD_LOGIC;
-- signal wraddress : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
-- signal data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-- signal rdclken : IN STD_LOGIC
-- );
-- end component lpm_ram_dp;
-- signal internal_q : STD_LOGIC_VECTOR (15 DOWNTO 0);
-- TYPE mem_array is ARRAY( 16777215 DOWNTO 0) of STD_LOGIC_VECTOR(15 DOWNTO 0);
-- signal memory_has_been_read : STD_LOGIC;
-- signal read_address : STD_LOGIC_VECTOR (23 DOWNTO 0);
--
--begin
--
-- process (rdaddress)
-- begin
-- read_address <= rdaddress;
--
-- end process;
--
-- lpm_ram_dp_component : lpm_ram_dp
-- generic map(
-- lpm_file => "UNUSED",
-- lpm_hint => "USE_EAB=ON",
-- lpm_indata => "REGISTERED",
-- lpm_outdata => "UNREGISTERED",
-- lpm_rdaddress_control => "UNREGISTERED",
-- lpm_width => 16,
-- lpm_widthad => 24,
-- lpm_wraddress_control => "REGISTERED",
-- suppress_memory_conversion_warnings => "ON"
-- )
-- port map(
-- data => data,
-- q => internal_q,
-- rdaddress => read_address,
-- rdclken => rdclken,
-- wraddress => wraddress,
-- wrclock => wrclock,
-- wren => wren
-- );
--
--
-- q <= internal_q;
--end europa;
--
--synthesis read_comments_as_HDL off
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity sdram_0_test_component is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal zs_addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
signal zs_ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal zs_cas_n : IN STD_LOGIC;
signal zs_cke : IN STD_LOGIC;
signal zs_cs_n : IN STD_LOGIC;
signal zs_dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal zs_ras_n : IN STD_LOGIC;
signal zs_we_n : IN STD_LOGIC;
-- outputs:
signal zs_dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end entity sdram_0_test_component;
architecture europa of sdram_0_test_component is
component sdram_0_test_component_ram_module is
port (
-- inputs:
signal data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
signal rdaddress : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
signal rdclken : IN STD_LOGIC;
signal wraddress : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
signal wrclock : IN STD_LOGIC;
signal wren : IN STD_LOGIC;
-- outputs:
signal q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component sdram_0_test_component_ram_module;
signal CODE : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal a : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal addr_col : STD_LOGIC_VECTOR (8 DOWNTO 0);
signal addr_crb : STD_LOGIC_VECTOR (14 DOWNTO 0);
signal ba : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal cas_n : STD_LOGIC;
signal cke : STD_LOGIC;
signal cmd_code : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal cs_n : STD_LOGIC;
signal dqm : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal index : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal latency : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal mask : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal mem_bytes : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal module_input : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal module_input1 : STD_LOGIC;
signal module_input2 : STD_LOGIC;
signal ras_n : STD_LOGIC;
signal rd_addr_pipe_0 : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal rd_addr_pipe_1 : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal rd_addr_pipe_2 : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal rd_mask_pipe_0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rd_mask_pipe_1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rd_mask_pipe_2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal rd_valid_pipe : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal read_addr : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal read_data : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal read_mask : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal read_temp : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal read_valid : STD_LOGIC;
signal rmw_temp : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal test_addr : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal txt_code : STD_LOGIC_VECTOR (23 DOWNTO 0);
signal we_n : STD_LOGIC;
begin
process
VARIABLE write_line : line;
VARIABLE write_line1 : line;
VARIABLE write_line2 : line;
VARIABLE write_line3 : line;
VARIABLE write_line4 : line;
begin
write(write_line, string'("************************************************************"));
write(output, write_line.all & CR);
deallocate (write_line);
write(write_line1, string'("This testbench includes an SOPC Builder Generated Altera model:"));
write(output, write_line1.all & CR);
deallocate (write_line1);
write(write_line2, string'("'sdram_0_test_component.vhd', to simulate accesses to SDRAM."));
write(output, write_line2.all & CR);
deallocate (write_line2);
write(write_line3, string'("Initial contents are loaded from the file: '../../DCD_APP1/SYS_DE0N/objs/dcd_app1.dat'."));
write(output, write_line3.all & CR);
deallocate (write_line3);
write(write_line4, string'("************************************************************"));
write(output, write_line4.all & CR);
deallocate (write_line4);
wait;
end process;
--Synchronous write when (CODE == 24'h205752 (write))
sdram_0_test_component_ram : sdram_0_test_component_ram_module
port map(
q => read_data,
data => rmw_temp,
rdaddress => module_input,
rdclken => module_input1,
wraddress => test_addr,
wrclock => clk,
wren => module_input2
);
module_input <= A_WE_StdLogicVector(((CODE = std_logic_vector'("001000000101011101010010"))), test_addr, read_addr);
module_input1 <= std_logic'('1');
module_input2 <= to_std_logic((CODE = std_logic_vector'("001000000101011101010010")));
cke <= zs_cke;
cs_n <= zs_cs_n;
ras_n <= zs_ras_n;
cas_n <= zs_cas_n;
we_n <= zs_we_n;
dqm <= zs_dqm;
ba <= zs_ba;
a <= zs_addr;
cmd_code <= Std_Logic_Vector'(A_ToStdLogicVector(ras_n) & A_ToStdLogicVector(cas_n) & A_ToStdLogicVector(we_n));
CODE <= A_WE_StdLogicVector((std_logic'((cs_n)) = '1'), std_logic_vector'("010010010100111001001000"), txt_code);
addr_col <= a(8 DOWNTO 0);
test_addr <= addr_crb & addr_col;
mem_bytes <= read_data;
rmw_temp(7 DOWNTO 0) <= A_WE_StdLogicVector((std_logic'(dqm(0)) = '1'), mem_bytes(7 DOWNTO 0), zs_dq(7 DOWNTO 0));
rmw_temp(15 DOWNTO 8) <= A_WE_StdLogicVector((std_logic'(dqm(1)) = '1'), mem_bytes(15 DOWNTO 8), zs_dq(15 DOWNTO 8));
-- Handle Input.
process (clk)
begin
if clk'event and clk = '1' then
-- No Activity of Clock Disabled
if std_logic'(cke) = '1' then
-- LMR: Get CAS_Latency.
if CODE = std_logic_vector'("010011000100110101010010") then
latency <= a(6 DOWNTO 4);
end if;
-- ACT: Get Row/Bank Address.
if CODE = std_logic_vector'("010000010100001101010100") then
addr_crb <= Std_Logic_Vector'(A_ToStdLogicVector(ba(1)) & A_ToStdLogicVector(ba(0))) & a;
end if;
rd_valid_pipe(2) <= rd_valid_pipe(1);
rd_valid_pipe(1) <= rd_valid_pipe(0);
rd_valid_pipe(0) <= to_std_logic((CODE = std_logic_vector'("001000000101001001000100")));
rd_addr_pipe_2 <= rd_addr_pipe_1;
rd_addr_pipe_1 <= rd_addr_pipe_0;
rd_addr_pipe_0 <= test_addr;
rd_mask_pipe_2 <= rd_mask_pipe_1;
rd_mask_pipe_1 <= rd_mask_pipe_0;
rd_mask_pipe_0 <= dqm;
end if;
end if;
end process;
read_temp(7 DOWNTO 0) <= A_WE_StdLogicVector((std_logic'(mask(0)) = '1'), std_logic_vector'("ZZZZZZZZ"), read_data(7 DOWNTO 0));
read_temp(15 DOWNTO 8) <= A_WE_StdLogicVector((std_logic'(mask(1)) = '1'), std_logic_vector'("ZZZZZZZZ"), read_data(15 DOWNTO 8));
--use index to select which pipeline stage drives addr
read_addr <= A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000") & (index)) = std_logic_vector'("00000000000000000000000000000000"))), rd_addr_pipe_0, A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000") & (index)) = std_logic_vector'("00000000000000000000000000000001"))), rd_addr_pipe_1, rd_addr_pipe_2));
--use index to select which pipeline stage drives mask
read_mask <= A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000") & (index)) = std_logic_vector'("00000000000000000000000000000000"))), rd_mask_pipe_0, A_WE_StdLogicVector((((std_logic_vector'("00000000000000000000000000000") & (index)) = std_logic_vector'("00000000000000000000000000000001"))), rd_mask_pipe_1, rd_mask_pipe_2));
--use index to select which pipeline stage drives valid
read_valid <= A_WE_StdLogic((((std_logic_vector'("00000000000000000000000000000") & (index)) = std_logic_vector'("00000000000000000000000000000000"))), rd_valid_pipe(0), A_WE_StdLogic((((std_logic_vector'("00000000000000000000000000000") & (index)) = std_logic_vector'("00000000000000000000000000000001"))), rd_valid_pipe(1), rd_valid_pipe(2)));
index <= A_EXT (((std_logic_vector'("0") & (latency)) - (std_logic_vector'("000") & (A_TOSTDLOGICVECTOR(std_logic'('1'))))), 3);
mask <= read_mask;
zs_dq <= A_WE_StdLogicVector((std_logic'(read_valid) = '1'), read_temp, A_REP(std_logic'('Z'), 16));
--synthesis translate_off
txt_code <= A_WE_StdLogicVector(((cmd_code = std_logic_vector'("000"))), std_logic_vector'("010011000100110101010010"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("001"))), std_logic_vector'("010000010101001001000110"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("010"))), std_logic_vector'("010100000101001001000101"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("011"))), std_logic_vector'("010000010100001101010100"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("100"))), std_logic_vector'("001000000101011101010010"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("101"))), std_logic_vector'("001000000101001001000100"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("110"))), std_logic_vector'("010000100101001101010100"), A_WE_StdLogicVector(((cmd_code = std_logic_vector'("111"))), std_logic_vector'("010011100100111101010000"), std_logic_vector'("010000100100000101000100")))))))));
--synthesis translate_on
end europa;
| gpl-2.0 | 28bd6f06ab1ea99b1f50b239a8455bc2 | 0.576296 | 3.673611 | false | false | false | false |
AleChir/Digital_Filter_VHDL | Digital_Filter/datapath.vhd | 1 | 5,426 | library ieee;
use ieee.std_logic_1164.all;
entity datapath is
port( x: in std_logic_vector(7 downto 0);
y: out std_logic_vector(7 downto 0);
clock: in std_logic;
rst_shift, enable_shift: in std_logic;
rst_sum, enable_sum: in std_logic;
rst_count, enable_count: in std_logic;
count_out: buffer std_logic_vector(9 downto 0);
module, cntrl: in std_logic;
mux1_sel: in std_logic_vector(2 downto 0);
terminal_count: out std_logic );
end datapath;
architecture behavior of datapath is
component b82to1MUX
port( in0,in1: in std_logic_vector(7 downto 0);
m: out std_logic_vector(7 downto 0);
sel: in std_logic);
end component;
component count_n
generic( N: integer:=16);
port( clk, clear, enable: IN std_logic;
q: OUT std_logic_vector(N-1 downto 0));
end component;
component b115to1MUX
port( in0,in1,in2,in3,in4: in std_logic_vector(10 downto 0);
m: out std_logic_vector(10 downto 0);
sel: in std_logic_vector(2 downto 0));
end component;
component mux_2to1_11bit
port( data0: in std_logic_vector (10 downto 0);
data1: in std_logic_vector (10 downto 0);
sel: in std_logic;
data_out: out std_logic_vector(10 downto 0) );
end component;
component divider_2
port( data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector( 10 downto 0) );
end component;
component divider_4
port( data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector( 10 downto 0));
end component;
component multiplier_2
port( data_in: in std_logic_vector (7 downto 0);
data_out: out std_logic_vector (10 downto 0));
end component;
component multiplier_4
port( data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(10 downto 0));
end component;
component ram_1024X8
port( data_in: in std_logic_vector(7 downto 0);
address: in integer range 1023 downto 0;
cs: in std_logic;
clk: in std_logic;
rd_wr_n: in std_logic;
data_out: out std_logic_vector (7 downto 0));
end component;
component regn_std_logic
generic( N: integer:=8);
port( R: in std_logic_vector(N-1 downto 0);
Clock, Resetn, enable : in std_logic;
Q: out std_logic_vector(N-1 downto 0));
end component;
component fulladder_generic is
GENERIC ( N: integer:=8);
port( a, b: IN std_logic_vector (N-1 downto 0);
ci: IN std_logic;
co: OUT std_logic;
s: OUT std_logic_vector (N-1 downto 0);
overf: out std_logic );
end component;
signal q_shift0, q_shift1, q_shift2, q_shift3: std_logic_vector(7 downto 0);
signal in_mux0, in_mux1, in_mux2, in_mux3, in_mux4: std_logic_vector(10 downto 0);
signal out_mux1, out_mux1n: std_logic_vector(10 downto 0);
signal mux2_sel, mux3_sel: std_logic;
signal out_mux2, out_mux3: std_logic_vector(10 downto 0);
signal out_sum: std_logic_vector(10 downto 0);
signal saturation: std_logic;
signal co, ovf: std_logic;
begin
count: count_n generic map(10) port map(clock,rst_count, enable_count, count_out);
terminal_count<=count_out(9) and count_out(8) and count_out(7) and
count_out(6) and count_out(5) and count_out(4) and count_out(3) and
count_out(2) and count_out(1) and count_out(0);
shift_0: regn_std_logic generic map(8) port map(x, clock, rst_shift, enable_shift, q_shift0);
shift_1: regn_std_logic generic map(8) port map(q_shift0,clock, rst_shift, enable_shift, q_shift1);
shift_2: regn_std_logic generic map(8) port map(q_shift1,clock, rst_shift, enable_shift, q_shift2);
shift_3: regn_std_logic generic map(8) port map(q_shift2,clock, rst_shift, enable_shift, q_shift3);
div_2: divider_2 port map(q_shift0, in_mux0);
mult_2: multiplier_2 port map(q_shift1, in_mux1);
mult_4: multiplier_4 port map(q_shift2, in_mux2);
div_4: divider_4 port map(q_shift3, in_mux3);
mux_1: b115to1MUX port map(in_mux0, in_mux1, in_mux2, in_mux3, in_mux4, out_mux1, mux1_sel);
out_mux1n(0)<= not out_mux1(0);
out_mux1n(1)<= not out_mux1(1);
out_mux1n(2)<= not out_mux1(2);
out_mux1n(3)<= not out_mux1(3);
out_mux1n(4)<= not out_mux1(4);
out_mux1n(5)<= not out_mux1(5);
out_mux1n(6)<= not out_mux1(6);
out_mux1n(7)<= not out_mux1(7);
out_mux1n(8)<= not out_mux1(8);
out_mux1n(9)<= not out_mux1(9);
out_mux1n(10)<=not out_mux1(10);
mux_2: mux_2to1_11bit port map(out_mux1, out_mux1n, mux2_sel,out_mux2);
sum: fulladder_generic generic map(11) port map(out_mux3, out_mux2, mux2_sel, co, out_sum, ovf);
reg_sum: regn_std_logic generic map(11) port map(out_sum, clock, rst_sum, enable_sum, in_mux4);
mux_3: mux_2to1_11bit port map(in_mux4, "00000000000", mux3_sel, out_mux3);
mux3_sel<= module;
mux2_sel<= cntrl xor (module and in_mux4(10));
saturation<=in_mux4(7) or in_mux4(8) or in_mux4(9);
mux_4: b82to1MUX port map(in_mux4(7 downto 0), "01111111", y, saturation);
end behavior;
| gpl-3.0 | d8179c3ce1a6d0eed7ef12e105a4f06c | 0.60505 | 2.99118 | false | false | false | false |
shio-phys/SPI-FLASH-Programmer | fpga/SPI_CommandSender.vhd | 1 | 5,139 | --------------------------------------------------------------------------------
--! @file SPI_CommandSender.vhd
--! @brief Send command to SPI FLASH and receive data from SPI FLASH
--! @author Takehiro Shiozaki
--! @date 2014-06-24
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SPI_CommandSender is
port(
CLK : in std_logic;
RESET : in std_logic;
START : in std_logic;
BUSY : out std_logic;
LENGTH : in std_logic_vector(12 downto 0);
WE : out std_logic;
DOUT : out std_logic_vector(7 downto 0);
WADDR : out std_logic_vector(12 downto 0);
DIN : in std_logic_vector(7 downto 0);
RADDR : out std_logic_vector(8 downto 0);
SPI_SCLK : out std_logic;
SPI_SS_N : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic
);
end SPI_CommandSender;
architecture RTL of SPI_CommandSender is
component SPI_IF is
port(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
START : in std_logic;
BUSY : out std_logic;
SPI_SCLK : out std_logic;
SPI_MISO : in std_logic;
SPI_MOSI : out std_logic
);
end component;
signal int_WADDR : std_logic_vector(12 downto 0);
signal WaddrCountUp : std_logic;
signal WaddrCountClear : std_logic;
signal int_RADDR : std_logic_vector(8 downto 0);
signal RaddrCountUp : std_logic;
signal RaddrCountClear : std_logic;
signal LengthReg : std_logic_vector(12 downto 0);
signal LengthRegCountDown : std_logic;
signal StartIf : std_logic;
signal BusyIf : std_logic;
signal SpiSSNPre : std_logic;
type State is (IDLE, START_IF, WAIT_BUSY, WRITE_DATA);
signal CurrentState, NextState : State;
begin
SPI_IF_0: SPI_IF
port map(
CLK => CLK,
RESET => RESET,
DIN => DIN,
DOUT => DOUT,
START => StartIf,
BUSY => BusyIf,
SPI_SCLK => SPI_SCLK,
SPI_MISO => SPI_MISO,
SPI_MOSI => SPI_MOSI
);
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(WaddrCountClear = '1') then
int_WADDR <= (others => '0');
elsif(WaddrCountUp = '1') then
int_WADDR <= int_WADDR + 1;
end if;
end if;
end process;
WADDR <= int_WADDR;
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(RaddrCountClear = '1') then
int_RADDR <= (others => '0');
elsif(RaddrCountUp = '1') then
int_RADDR <= int_RADDR + 1;
end if;
end if;
end process;
RADDR <= int_RADDR;
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(START = '1') then
LengthReg <= LENGTH;
elsif(LengthRegCountDown = '1') then
LengthReg <= LengthReg - 1;
end if;
end if;
end process;
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(RESET = '1') then
CurrentState <= IDLE;
else
CurrentState <= NextState;
end if;
end if;
end process;
process(CurrentState, START, BusyIf, LengthReg)
begin
case CurrentState is
when IDLE =>
if(START = '1') then
NextState <= START_IF;
else
NextState <= CurrentState;
end if;
when START_IF =>
NextState <= WAIT_BUSY;
when WAIT_BUSY =>
if(BusyIf = '1') then
NextState <= CurrentState;
else
NextState <= WRITE_DATA;
end if;
when WRITE_DATA =>
if(LengthReg = 0) then
NextState <= IDLE;
else
NextState <= START_IF;
end if;
end case;
end process;
WaddrCountUp <= '1' when(CurrentState = WRITE_DATA) else
'0';
WaddrCountClear <= '1' when(CurrentState = IDLE) else
'0';
RaddrCountUp <= '1' when(CurrentState = START_IF) else
'0';
RaddrCountClear <= '1' when(CurrentState = IDLE) else
'0';
LengthRegCountDown <= '1' when(CurrentState = WRITE_DATA) else
'0';
StartIf <= '1' when(CurrentState = START_IF) else
'0';
SpiSSNPre <= '1' when(CurrentState = IDLE) else
'0';
WE <= '1' when(CurrentState = WRITE_DATA) else
'0';
BUSY <= '0' when(CurrentState = IDLE) else
'1';
process(CLK)
begin
if(CLK'event and CLK = '1') then
SPI_SS_N <= SpiSSNPre;
end if;
end process;
end RTL;
| mit | 056fccc96350fba8fcda5edeaa503d7d | 0.487644 | 4.134352 | false | false | false | false |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/Altera_UP_SD_Card_Buffer.vhd | 2 | 12,347 | -------------------------------------------------------------------------------------
-- This module is a dual port memory block. It has a 16-bit port and a 1-bit port.
-- The 1-bit port is used to either send or receive data, while the 16-bit port is used
-- by Avalon interconnet to store and retrieve data.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Buffer is
generic (
TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- 1 bit port to transmit and receive data on the data line.
i_begin : in std_logic;
i_sd_clock_pulse_trigger : in std_logic;
i_transmit : in std_logic;
i_1bit_data_in : in std_logic;
o_1bit_data_out : out std_logic;
o_operation_complete : out std_logic;
o_crc_passed : out std_logic;
o_timed_out : out std_logic;
o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port : in std_logic;
i_address_16bit_port : in std_logic_vector(7 downto 0);
i_write_16bit : in std_logic;
i_16bit_data_in : in std_logic_vector(15 downto 0);
o_16bit_data_out : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_Buffer is
component Altera_UP_SD_CRC16_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end component;
component Altera_UP_SD_Card_Memory_Block
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_RESET, s_WAIT_REQUEST, s_SEND_START_BIT, s_SEND_DATA, s_SEND_CRC, s_SEND_STOP, s_WAIT_BUSY, s_WAIT_BUSY_END,
s_WAIT_DATA_START, s_RECEIVING_LEADING_BITS, s_RECEIVING_DATA, s_RECEIVING_STOP_BIT, s_WAIT_DEASSERT);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-- Local wires
-- REGISTERED
signal crc_counter : std_logic_vector(3 downto 0);
signal local_mode : std_logic;
signal dataout_1bit : std_logic;
signal bit_counter : std_logic_vector(2 downto 0);
signal byte_counter : std_logic_vector(8 downto 0);
signal shift_register : std_logic_vector(16 downto 0);
signal timeout_register : std_logic_vector(15 downto 0);
signal data_in_reg : std_logic;
-- UNREGISTERED
signal crc_out : std_logic_vector(15 downto 0);
signal single_bit_conversion, single_bit_out : std_logic_vector( 0 downto 0);
signal local_reset, to_crc_generator, from_crc_generator, from_mem_1_bit, shift_crc,
recv_data, crc_generator_enable : std_logic;
begin
-- State transitions
state_transitions: process( current_state, i_begin, i_sd_clock_pulse_trigger, i_transmit, byte_counter,
bit_counter, crc_counter, i_1bit_data_in, timeout_register, data_in_reg)
begin
case (current_state) is
when s_RESET =>
-- Reset local registers and begin waiting for user input.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for i_begin to be high
if ((i_begin = '1') and (i_sd_clock_pulse_trigger = '1')) then
if (i_transmit = '1') then
next_state <= s_SEND_START_BIT;
else
next_state <= s_WAIT_DATA_START;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_SEND_START_BIT =>
-- Send a 0 first, followed by 4096 bits of data, 16 CRC bits, and stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_SEND_DATA;
else
next_state <= s_SEND_START_BIT;
end if;
when s_SEND_DATA =>
-- Send 4096 data bits
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_SEND_CRC;
else
next_state <= s_SEND_DATA;
end if;
when s_SEND_CRC =>
-- Send 16 CRC bits
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_SEND_STOP;
else
next_state <= s_SEND_CRC;
end if;
when s_SEND_STOP =>
-- Send stop bit.
if (i_sd_clock_pulse_trigger = '1') then
next_state <= s_WAIT_BUSY;
else
next_state <= s_SEND_STOP;
end if;
when s_WAIT_BUSY =>
-- After a write, wait for the busy signal. Do not return a done signal until you receive a busy signal.
-- If you do not and a long time expires, then the data must have been rejected (due to CRC error maybe).
-- In such a case return failure.
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0') and (timeout_register = "0000000000010000")) then
next_state <= s_WAIT_BUSY_END;
else
if (timeout_register = BUSY_WAIT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY;
end if;
end if;
when s_WAIT_BUSY_END =>
if (i_sd_clock_pulse_trigger = '1') then
if (data_in_reg = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_BUSY_END;
end if;
else
next_state <= s_WAIT_BUSY_END;
end if;
when s_WAIT_DATA_START =>
-- Wait for the start bit
if ((i_sd_clock_pulse_trigger = '1') and (data_in_reg = '0')) then
next_state <= s_RECEIVING_LEADING_BITS;
else
if (timeout_register = TIMEOUT) then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_DATA_START;
end if;
end if;
when s_RECEIVING_LEADING_BITS =>
-- shift the start bit in as well as the next 16 bits. Once they are all in you can start putting data into memory.
if ((i_sd_clock_pulse_trigger = '1') and (crc_counter = "1111")) then
next_state <= s_RECEIVING_DATA;
else
next_state <= s_RECEIVING_LEADING_BITS;
end if;
when s_RECEIVING_DATA =>
-- Wait until all bits arrive.
if ((i_sd_clock_pulse_trigger = '1') and (bit_counter = "000") and (byte_counter = "111111111")) then
next_state <= s_RECEIVING_STOP_BIT;
else
next_state <= s_RECEIVING_DATA;
end if;
when s_RECEIVING_STOP_BIT =>
-- Wait until all bits arrive.
if (i_sd_clock_pulse_trigger = '1')then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_RECEIVING_STOP_BIT;
end if;
when s_WAIT_DEASSERT =>
if (i_begin = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_REQUEST;
end if;
when others =>
next_state <= s_RESET;
end case;
end process;
-- State registers
state_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
-- FSM outputs
to_crc_generator <= shift_register(16) when (current_state = s_RECEIVING_DATA) else
from_mem_1_bit when (current_state = s_SEND_DATA) else
'0';
shift_crc <= '1' when (current_state = s_SEND_CRC) else '0';
local_reset <= '1' when ((current_state = s_RESET) or (current_state = s_WAIT_REQUEST)) else '0';
recv_data <= '1' when (current_state = s_RECEIVING_DATA) else '0';
single_bit_conversion(0) <= shift_register(15);
crc_generator_enable <= '0' when (current_state = s_WAIT_DEASSERT) else i_sd_clock_pulse_trigger;
o_operation_complete <= '1' when (current_state = s_WAIT_DEASSERT) else '0';
o_dat_direction <= '1' when ( (current_state = s_SEND_START_BIT) or
(current_state = s_SEND_DATA) or
(current_state = s_SEND_CRC) or
(current_state = s_SEND_STOP))
else '0';
o_1bit_data_out <= dataout_1bit;
o_crc_passed <= '1' when ((crc_out = shift_register(16 downto 1)) and (shift_register(0) = '1')) else '0';
o_timed_out <= '1' when (timeout_register = TIMEOUT) else '0';
-- Local components
local_regs: process(i_clock, i_reset_n, local_reset)
begin
if (i_reset_n = '0') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
-- counters and serial output
if (local_reset = '1') then
bit_counter <= (OTHERS => '1');
byte_counter <= (OTHERS => '0');
dataout_1bit <= '1';
data_in_reg <= '1';
crc_counter <= (OTHERS => '0');
shift_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
if ((not (current_state = s_RECEIVING_LEADING_BITS)) and (not (current_state = s_SEND_CRC))) then
crc_counter <= (OTHERS => '0');
else
if (not (crc_counter = "1111")) then
crc_counter <= crc_counter + '1';
end if;
end if;
if ((current_state = s_RECEIVING_DATA) or (current_state = s_SEND_DATA)) then
if (not ((bit_counter = "000") and (byte_counter = "111111111"))) then
if (bit_counter = "000") then
byte_counter <= byte_counter + '1';
bit_counter <= "111";
else
bit_counter <= bit_counter - '1';
end if;
end if;
end if;
-- Output data bit.
if (current_state = s_SEND_START_BIT) then
dataout_1bit <= '0';
elsif (current_state = s_SEND_DATA) then
dataout_1bit <= from_mem_1_bit;
elsif (current_state = s_SEND_CRC) then
dataout_1bit <= from_crc_generator;
else
dataout_1bit <= '1'; -- Stop bit.
end if;
-- Shift register to store the CRC bits once the message is received.
if ((current_state = s_RECEIVING_DATA) or
(current_state = s_RECEIVING_LEADING_BITS) or
(current_state = s_RECEIVING_STOP_BIT)) then
shift_register(16 downto 1) <= shift_register(15 downto 0);
shift_register(0) <= data_in_reg;
end if;
data_in_reg <= i_1bit_data_in;
end if;
end if;
end process;
-- Register holding the timeout value for data transmission.
timeout_reg: process(i_clock, i_reset_n, current_state, i_sd_clock_pulse_trigger)
begin
if (i_reset_n = '0') then
timeout_register <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
if ((current_state = s_SEND_STOP) or
(current_state = s_WAIT_REQUEST)) then
timeout_register <= (OTHERS => '0');
elsif (i_sd_clock_pulse_trigger = '1') then
-- Increment the timeout counter
if (((current_state = s_WAIT_DATA_START) or
(current_state = s_WAIT_BUSY)) and (not (timeout_register = TIMEOUT))) then
timeout_register <= timeout_register + '1';
end if;
end if;
end if;
end process;
-- Instantiated components.
crc16_checker: Altera_UP_SD_CRC16_Generator
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_sync_reset => local_reset,
i_enable => crc_generator_enable,
i_shift => shift_crc,
i_datain => to_crc_generator,
o_dataout => from_crc_generator,
o_crcout => crc_out
);
packet_memory: Altera_UP_SD_Card_Memory_Block
PORT MAP
(
address_a => i_address_16bit_port,
address_b => (byte_counter & bit_counter),
clock_a => i_clock,
clock_b => i_clock,
data_a => i_16bit_data_in,
data_b => single_bit_conversion,
enable_a => i_enable_16bit_port,
enable_b => '1',
wren_a => i_write_16bit,
wren_b => recv_data,
q_a => o_16bit_data_out,
q_b => single_bit_out
);
from_mem_1_bit <= single_bit_out(0);
end rtl; | mit | 189f485eff8f4fc13e06a34e83b854dc | 0.606949 | 2.80869 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/tb_complex_abs_esaustivo.vhd | 1 | 3,645 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03.07.2017 10:01:38
-- Design Name:
-- Module Name: tb_complex_abs_esaustivo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.math_real.all;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_complex_abs_esaustivo is
-- Port ( );
end tb_complex_abs_esaustivo;
architecture Behavioral of tb_complex_abs_esaustivo is
component complex_abs is
Generic ( complex_width : natural := 32 ); --! Parallelismo in bit del numero complesso (inteso come somma di parte reale e immaginaria)
Port ( clock : in STD_LOGIC; --! Segnale di temporizzazione
reset_n : in STD_LOGIC; --! Segnale di reset 0-attivo
enable : in STD_LOGIC;
complex_value : in STD_LOGIC_VECTOR (complex_width-1 downto 0); --! Numero complesso di cui calcolare il modulo
abs_value : out STD_LOGIC_VECTOR (complex_width-1 downto 0); --! Modulo del numero complesso
done : out STD_LOGIC); --! Segnale di terminazione delle operazioni
end component complex_abs;
constant complex_width : natural:= 32;
constant clock_period : time := 10 ns;
constant num_cicli : natural := 10000;
signal clock : std_logic := '0';
signal reset_n : std_logic := '0';
signal enable : std_logic := '0';
signal done : std_logic := '0';
signal complex_value : std_logic_vector(complex_width-1 downto 0) := (others => '0');
signal abs_value : std_logic_vector(complex_width-1 downto 0) := (others => '0');
begin
uut: complex_abs
port map (
clock => clock,
reset_n => reset_n,
enable => enable,
complex_value => complex_value,
abs_value => abs_value,
done => done
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
variable valore_assoluto : std_logic_vector(complex_width-1 downto 0) := (others => '0');
variable complex_value_variable : integer := -(2 ** ((complex_width/2)-1));
begin
-- hold reset state for 100 ns.
reset_n<='0';
complex_value <= (complex_width-1 => '1', (complex_width/2)-1 => '1', others => '0');
wait for 95 ns;
reset_n<='1';
enable <= '1';
for i in 0 to num_cicli-1 loop
--sommo in esadecimale 0x00010001 ad ogni iterazione al valore di cui calcolo il valore assoluto
complex_value <= complex_value + 65537;
complex_value_variable := complex_value_variable + 1;
valore_assoluto := std_logic_vector(to_signed(complex_value_variable * complex_value_variable * 2, 32));
wait until done = '1';
assert(valore_assoluto = abs_value) report "Test Fallito valore assoluto trovato errato!";
wait for clock_period;
end loop;
wait;
end process;
end Behavioral;
| gpl-2.0 | 4021a21e8dabf79afdf435fe71b3e326 | 0.616735 | 3.645 | false | false | false | false |
imr/Mandelbrot-VHDL | src/PLL.vhd | 1 | 15,309 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: PLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY PLL IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END PLL;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
locked <= sub_wire0;
sub_wire2 <= sub_wire1(0);
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 10,
clk0_duty_cycle => 50,
clk0_multiply_by => 13,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=PLL",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
locked => sub_wire0,
clk => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "65.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "65.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "13"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| bsd-3-clause | 6acc27dc1ab4cee6b22633ff6a46ef8f | 0.697694 | 3.350624 | false | false | false | false |
terpstra/opa | opa_pkg.vhd | 1 | 5,564 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Open Processor Architecture
package opa_pkg is
-- Target Instruction Set Architecture
type t_opa_isa is (T_OPA_RV32, T_OPA_LM32);
type t_opa_config is record
reg_width : natural; -- Register width; must conform to ISA
adr_width : natural; -- Virtual address space
num_fetch : natural; -- # of instructions fetched concurrently
num_rename : natural; -- # of instructions decoded concurrently
num_stat : natural; -- # of reservation stations
num_fast : natural; -- # of fast EUs (logic, add/sub, branch, ...)
num_slow : natural; -- # of slow EUs (load/store, mul, fp, ...)
ieee_fp : boolean; -- Floating point support
ic_ways : natural; -- Instruction cache ways (each is 4KB=page_size)
iline_size : natural; -- Instruction cache line size (bytes)
dc_ways : natural; -- Data cache ways (each is 4KB=page_size)
dline_size : natural; -- Data cache line size (bytes)
dtlb_ways : natural; -- Data TLB ways
end record;
-- Tiny processor: 1-issue, 6 stations, 1+1 EU, 4+4KB i+dcache
constant c_opa_tiny : t_opa_config := (32, 17, 1, 1, 6, 1, 1, false, 1, 8, 1, 8, 1);
-- Small processor: 2-issue, 18 stations, 1+1 EU, 8+8KB i+dcache
constant c_opa_small : t_opa_config := (32, 32, 2, 2, 18, 1, 1, false, 2, 16, 1, 16, 1);
-- Large processor: 3-issue, 27 stations, 2+1 EU, 16+16KB i+dcache
constant c_opa_large : t_opa_config := (32, 32, 4, 3, 27, 2, 1, false, 2, 16, 2, 16, 2);
-- Huge processor: 4-issue, 44 stations, 2+2 EU, 32+32KB i+dcache
constant c_opa_huge : t_opa_config := (32, 32, 4, 4, 44, 2, 2, true, 8, 16, 8, 16, 4);
type t_opa_target is record
lut_width : natural; -- How many inputs to combine at once
add_width : natural; -- Hardware support for simultaneous adders
mul_width : natural; -- Widest DSP multiplier block
mem_depth : natural; -- Minimum depth of a memory block
post_adder : boolean; -- Can add two products (a*b)<<wide + (c*d)
end record;
-- FPGA flavors supported
constant c_opa_cyclone_iv : t_opa_target := (4, 2, 18, 256, true);
constant c_opa_arria_ii : t_opa_target := (6, 2, 18, 256, true);
constant c_opa_cyclone_v : t_opa_target := (6, 3, 27, 256, false);
constant c_opa_asic : t_opa_target := (4, 2, 1, 1, false);
component opa is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone instruction bus
i_cyc_o : out std_logic;
i_stb_o : out std_logic;
i_stall_i : in std_logic;
i_ack_i : in std_logic;
i_err_i : in std_logic;
i_addr_o : out std_logic_vector(g_config.adr_width -1 downto 0);
i_data_i : in std_logic_vector(g_config.reg_width -1 downto 0);
-- Wishbone data bus
d_cyc_o : out std_logic;
d_stb_o : out std_logic;
d_we_o : out std_logic;
d_stall_i : in std_logic;
d_ack_i : in std_logic;
d_err_i : in std_logic;
d_addr_o : out std_logic_vector(g_config.adr_width -1 downto 0);
d_sel_o : out std_logic_vector(g_config.reg_width/8-1 downto 0);
d_data_o : out std_logic_vector(g_config.reg_width -1 downto 0);
d_data_i : in std_logic_vector(g_config.reg_width -1 downto 0);
-- Wishbone peripheral bus
p_cyc_o : out std_logic;
p_stb_o : out std_logic;
p_we_o : out std_logic;
p_stall_i : in std_logic;
p_ack_i : in std_logic;
p_err_i : in std_logic;
p_addr_o : out std_logic_vector(g_config.adr_width -1 downto 0);
p_sel_o : out std_logic_vector(g_config.reg_width/8-1 downto 0);
p_data_o : out std_logic_vector(g_config.reg_width -1 downto 0);
p_data_i : in std_logic_vector(g_config.reg_width -1 downto 0);
-- Execution unit acitivity indication
status_o : out std_logic_vector(g_config.num_fast+g_config.num_slow-1 downto 0));
end component;
end package;
| gpl-3.0 | c0e7e61cfdb603825ff292c6fc74cf43 | 0.626348 | 3.154195 | false | true | false | false |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/Multiplier_2x16.vhd | 1 | 1,517 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Multiplier_2x16 is
Port (
input_A, input_B : in STD_LOGIC_VECTOR (15 downto 0);
outputLow, outputHigh : out STD_LOGIC_VECTOR (15 downto 0);
carryOut : out STD_LOGIC);
end Multiplier_2x16;
architecture skeleton of Multiplier_2x16 is
begin
process(input_A, input_B)
variable helper: std_logic_vector (31 downto 0);
variable carry, current, prev: std_logic;
function shifter (number : std_logic_vector(31 downto 0)) return std_logic_vector is
variable TMP : std_logic_vector(31 downto 0);
begin
for i in 30 downto 0 loop
TMP(i) := number(i + 1);
end loop;
TMP(31) := number(31);
return TMP;
end shifter;
begin
helper:="0000000000000000" & input_B;
carry:='0';
--helper := input_A * input_B;
current := '0';
for i in 0 to 15 loop
prev := current;
current := helper(0);
if(prev = '0') then
if(current = '1')
then
helper(31 downto 16) := helper(31 downto 16) + not(input_A) + 1;
end if;
elsif(prev = '1') then
if(current = '0') then
helper(31 downto 16) := helper(31 downto 16) + input_A;
end if;
end if;
helper := shifter(helper);
end loop;
outputHigh <= helper(31 downto 16);
outputLow <= helper(15 downto 0);
carryOut <= '0';
end process;
end skeleton; | gpl-3.0 | f583f3f085974ee60da93a393539d40c | 0.587343 | 3.193684 | false | false | false | false |
AleChir/Digital_Filter_VHDL | Digital_Filter/b115to1MUX.vhd | 1 | 675 | library ieee;
use ieee.std_logic_1164.all;
entity b115to1MUX is
port( in0,in1,in2,in3,in4: in std_logic_vector(10 downto 0);
m: out std_logic_vector(10 downto 0);
sel: in std_logic_vector(2 downto 0));
end b115to1MUX;
architecture behavior of b115to1MUX is
begin
process(sel, in0, in1, in2, in3, in4)
begin
case sel is
when "000" => m<=in0;
when "001" => m<=in1;
when "010" => m<=in2;
when "011" => m<=in3;
when "100" => m<=in4;
when others => m<= (others=> 'Z');
end case;
end process;
end behavior; | gpl-3.0 | 237da711a34bd724d177dd4f4b59cd36 | 0.505185 | 3.199052 | false | false | false | false |
terpstra/opa | opa_syn_tb.vhd | 1 | 12,227 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity opa_syn_tb is
port(
osc : in std_logic;
dip : in std_logic_vector(1 to 3);
but : in std_logic_vector(1 to 2);
led : out std_logic_vector(7 downto 0) := (others => 'Z'));
end opa_syn_tb;
architecture rtl of opa_syn_tb is
constant c_config : t_opa_config := c_opa_large;
-- How many words to run it with?
constant c_log_ram : natural := 14; -- 4*2^14 = 64kB of memory
component pll is
port(
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic); -- export
end component pll;
component jtag is
port(
addr_o : out std_logic_vector(31 downto 0);
data_o : out std_logic_vector(31 downto 0);
data_i : in std_logic_vector(31 downto 0);
gpio_o : out std_logic_vector( 3 downto 0);
we_xor_o : out std_logic;
rstn_o : out std_logic);
end component jtag;
component uart is
generic(
g_wide : natural := 8;
g_deep : natural := 10);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
stb_i : in std_logic;
stall_o : out std_logic;
dat_i : in std_logic_vector(g_wide-1 downto 0);
stb_o : out std_logic;
stall_i : in std_logic;
dat_o : out std_logic_vector(g_wide-1 downto 0));
end component uart;
-- Reset
signal clk_free : std_logic;
signal locked : std_logic;
signal r_delock : std_logic := '1';
signal s_rstin : std_logic;
signal r_rstin : std_logic_vector(2 downto 0) := (others => '0');
signal r_rsth : std_logic_vector(2 downto 0) := (others => '0');
signal r_rstc : unsigned(19 downto 0) := (others => '1');
signal r_rstn : std_logic := '0';
signal r_rsttg : std_logic_vector(4 downto 0) := (others => '0');
signal rstn : std_logic;
-- Clocking
signal clk_100m : std_logic;
signal r_dip2 : std_logic_vector(dip'range);
signal r_dip1 : std_logic_vector(dip'range);
signal r_dip : std_logic_vector(dip'range);
signal r_ena : std_logic;
signal r_div : unsigned(27 downto 0);
signal r_cnt : unsigned(27 downto 0);
signal r_gate : std_logic;
signal clk : std_logic;
signal r_clk : std_logic; -- pretty clock output (1/2 clk)
-- OPA signals
signal i_cyc : std_logic;
signal i_stb : std_logic;
signal i_stall: std_logic;
signal i_ack : std_logic;
signal i_addr : std_logic_vector(c_config.adr_width-1 downto 0);
signal i_dat : std_logic_vector(31 downto 0);
signal d_cyc : std_logic;
signal d_stb : std_logic;
signal d_stall: std_logic;
signal d_we : std_logic;
signal d_ack : std_logic;
signal d_addr : std_logic_vector(c_config.adr_width-1 downto 0);
signal d_sel : std_logic_vector( 3 downto 0);
signal d_dati : std_logic_vector(31 downto 0);
signal d_dato : std_logic_vector(31 downto 0);
signal p_cyc : std_logic;
signal p_stb : std_logic;
signal p_stall: std_logic;
signal p_we : std_logic;
signal p_ack : std_logic;
signal p_addr : std_logic_vector(c_config.adr_width-1 downto 0);
signal p_sel : std_logic_vector( 3 downto 0);
signal p_dati : std_logic_vector(31 downto 0);
signal p_dato : std_logic_vector(31 downto 0);
signal s_led : std_logic_vector(c_config.num_fast+c_config.num_slow-1 downto 0);
signal d_wem : std_logic;
-- JTAG connection
signal jtag_addr : std_logic_vector(31 downto 0);
signal jtag_data : std_logic_vector(31 downto 0);
signal gpio : std_logic_vector( 3 downto 0);
signal s_we_xor : std_logic;
signal jtag_rstn : std_logic;
signal s_a_addr : std_logic_vector(c_config.adr_width-1 downto 0);
signal r_we_xor2 : std_logic;
signal r_we_xor1 : std_logic;
signal r_we_xor0 : std_logic;
signal r_we : std_logic;
-- UART flow control
signal s_uart_we : std_logic;
signal s_uart_re : std_logic;
signal s_pin : std_logic_vector(8 downto 0);
signal r_pin : std_logic_vector(8 downto 0);
signal s_uart_stall : std_logic;
-- User button presed?
signal r_but2 : std_logic;
signal r_but1 : std_logic;
signal r_but0 : std_logic;
begin
-- The free running external clock
clk_free <= osc;
-- Derive an on-chip clock
clockpll : pll
port map(
refclk => clk_free,
rst => r_delock,
outclk_0 => clk_100m,
locked => locked);
-- If we lose lock, assert r_delock
delock : process(clk_free) is
begin
if rising_edge(clk_free) then
r_delock <= not locked and r_rstn;
end if;
end process;
-- Pulse extend any short/glitchy lock loss to at least one clock period
s_rstin <= locked and but(1) and jtag_rstn;
reset_in : process(clk_free, s_rstin) is
begin
if s_rstin = '0' then
r_rstin <= (others => '0');
elsif rising_edge(clk_free) then
r_rstin <= '1' & r_rstin(r_rstin'high downto r_rstin'low+1);
end if;
end process;
-- Safely transfer reset signal into free-running clock domain (meta-stable)
reset_meta : process(clk_free) is
begin
if rising_edge(clk_free) then
r_rsth <= r_rstin(r_rstin'low) & r_rsth(r_rsth'high downto r_rsth'low+1);
end if;
end process;
-- Derive a reasonable duration reset (debounce)
reset : process(clk_free, r_rsth(r_rsth'low)) is
begin
if r_rsth(r_rsth'low) = '0' then
r_rstn <= '0';
r_rstc <= (others => '1');
elsif rising_edge(clk_free) then
if r_rstc = 0 then
r_rstn <= '1';
r_rstc <= (others => '0');
else
r_rstn <= '0';
r_rstc <= r_rstc - 1;
end if;
end if;
end process;
-- Select clock divider
clocksel : process(clk_free) is
begin
if rising_edge(clk_free) then
-- Eliminate any meta-stability (still bounces, but does not matter)
r_dip2 <= dip;
r_dip1 <= r_dip2;
r_dip <= r_dip1;
-- Decode the target clock rate
if r_dip(1) = '0' then -- dip0 => 100MHz
r_ena <= '1';
r_div <= to_unsigned(1, r_div'length);
elsif r_dip(2) = '0' then -- dip1 => 10kHz
r_ena <= '1';
r_div <= to_unsigned(10000, r_div'length);
elsif r_dip(3) = '0' then -- dip2 => 1Hz
r_ena <= '1';
r_div <= to_unsigned(100000000, r_div'length);
else -- no dip => clock disabled
r_ena <= '0';
r_div <= (others => '-');
end if;
end if;
end process;
-- Gate the clock
gate : process(clk_100m) is
begin
if rising_edge(clk_100m) then
if r_cnt >= r_div then
r_gate <= r_ena;
r_cnt <= to_unsigned(1, r_cnt'length);
else
r_gate <= '0';
r_cnt <= r_cnt + 1;
end if;
end if;
end process;
-- Use a hardware clock gate at the clock network source
clockmux : altclkctrl
generic map(
number_of_clocks => 1)
port map(
ena => r_gate,
inclk(0) => clk_100m,
outclk => clk);
-- Inject reset from free running clock to target domain (remove meta-stability)
reset_target : process(clk) is
begin
if rising_edge(clk) then
r_rsttg <= r_rstn & r_rsttg(r_rsttg'high downto r_rsttg'low+1);
end if;
end process;
rstn <= r_rsttg(0);
opa_core : opa
generic map(
g_isa => T_OPA_LM32,
g_config => c_config,
g_target => c_opa_cyclone_v)
port map(
clk_i => clk,
rst_n_i => rstn,
i_cyc_o => i_cyc,
i_stb_o => i_stb,
i_stall_i => i_stall,
i_ack_i => i_ack,
i_err_i => '0',
i_addr_o => i_addr,
i_data_i => i_dat,
d_cyc_o => d_cyc,
d_stb_o => d_stb,
d_we_o => d_we,
d_stall_i => d_stall,
d_ack_i => d_ack,
d_err_i => '0',
d_addr_o => d_addr,
d_sel_o => d_sel,
d_data_o => d_dato,
d_data_i => d_dati,
p_cyc_o => p_cyc,
p_stb_o => p_stb,
p_we_o => p_we,
p_stall_i => p_stall,
p_ack_i => p_ack,
p_err_i => '0',
p_addr_o => p_addr,
p_sel_o => p_sel,
p_data_o => p_dato,
p_data_i => p_dati,
status_o => s_led);
led(7) <= '0' when r_clk ='1' else 'Z';
led(6) <= '0' when gpio(3) ='1' else 'Z';
led(5) <= '0' when gpio(2) ='1' else 'Z';
led(4) <= '0' when gpio(1) ='1' else 'Z';
led(3) <= '0' when gpio(0) ='1' else 'Z';
activity : for i in s_led'range generate
led(i) <= '0' when s_led(i)='1' else 'Z';
end generate;
d_wem <= d_cyc and d_stb and d_we;
ext : jtag
port map(
addr_o => jtag_addr,
data_o => jtag_data,
data_i => i_dat,
gpio_o => gpio,
we_xor_o => s_we_xor,
rstn_o => jtag_rstn);
a_we : process(clk) is
begin
if rising_edge(clk) then
r_we_xor0 <= s_we_xor;
r_we_xor1 <= r_we_xor0;
r_we_xor2 <= r_we_xor1;
r_we <= r_we_xor1 xor r_we_xor2;
end if;
end process;
s_a_addr <= jtag_addr(s_a_addr'range) when jtag_rstn='0' else i_addr;
i_stall <= '0';
d_stall <= '0';
ram : opa_tdpram
generic map(
g_width => 8,
g_size => 2**c_log_ram,
g_hunks => 4)
port map(
clk_i => clk,
rst_n_i => '1', -- run even while CPU reset
a_wen_i => r_we,
a_sel_i => (others => '1'),
a_addr_i => s_a_addr(c_log_ram+1 downto 2),
a_data_i => jtag_data,
a_data_o => i_dat,
b_wen_i => d_wem,
b_sel_i => d_sel,
b_addr_i => d_addr(c_log_ram+1 downto 2),
b_data_i => d_dato,
b_data_o => d_dati);
idpbus : process(clk) is
begin
if rising_edge(clk) then
i_ack <= i_cyc and i_stb and not i_stall;
d_ack <= d_cyc and d_stb and not d_stall;
p_ack <= p_cyc and p_stb and not p_stall;
r_pin <= s_pin;
r_clk <= not r_clk;
end if;
end process;
s_uart_we <= p_cyc and p_stb and p_we and p_sel(0);
s_uart_re <= p_cyc and p_stb and not p_we;
p_stall <= s_uart_stall and p_we;
io : uart
port map(
clk_i => clk,
rst_n_i => rstn,
stb_i => s_uart_we,
stall_o => s_uart_stall,
dat_i => p_dato(7 downto 0),
stb_o => s_pin(8),
stall_i => "not"(s_uart_re),
dat_o => s_pin(7 downto 0));
button : process(clk) is
begin
if rising_edge(clk) then
r_but2 <= but(2);
r_but1 <= r_but2;
r_but0 <= r_but1;
end if;
end process;
p_dati(31) <= not r_but0;
p_dati(30 downto 9) <= (others => '0');
p_dati( 8 downto 0) <= r_pin;
end rtl;
| gpl-3.0 | eac9e69fdf6985249163175961b38c48 | 0.569723 | 2.92582 | false | false | false | false |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/Altera_UP_SD_Card_Control_FSM.vhd | 2 | 12,308 | ----------------------------------------------------------------------------------------------------------------
-- This is an FSM that controls the SD Card interface circuitry.
--
-- On reset, the FSM will initiate a predefined set of commands in an attempt to connect to the SD Card.
-- When successful, it will allow commands to be issued to the SD Card, otherwise it will return a signal that
-- no card is present in the SD Card slot.
--
-- NOTES/REVISIONS:
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Control_FSM is
generic (
PREDEFINED_COMMAND_GET_STATUS : STD_LOGIC_VECTOR(3 downto 0) := "1001"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC;
-- FSM Inputs
i_user_command_ready : in std_logic;
i_response_received : in STD_LOGIC;
i_response_timed_out : in STD_LOGIC;
i_response_crc_passed : in STD_LOGIC;
i_command_sent : in STD_LOGIC;
i_powerup_busy_n : in STD_LOGIC;
i_clocking_pulse_enable : in std_logic;
i_current_clock_mode : in std_logic;
i_user_message_valid : in std_logic;
i_last_cmd_was_55 : in std_logic;
i_allow_partial_rw : in std_logic;
-- FSM Outputs
o_generate_command : out STD_LOGIC;
o_predefined_command_ID : out STD_LOGIC_VECTOR(3 downto 0);
o_receive_response : out STD_LOGIC;
o_drive_CMD_line : out STD_LOGIC;
o_SD_clock_mode : out STD_LOGIC; -- 0 means slow clock for card identification, 1 means fast clock for transfer mode.
o_resetting : out std_logic;
o_card_connected : out STD_LOGIC;
o_command_completed : out std_logic;
o_clear_response_register : out std_logic;
o_enable_clock_generator : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Control_FSM is
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_RESET, s_WAIT_74_CYCLES, s_GENERATE_PREDEFINED_COMMAND, s_WAIT_PREDEFINED_COMMAND_TRANSMITTED, s_WAIT_PREDEFINED_COMMAND_RESPONSE,
s_GO_TO_NEXT_COMMAND, s_TOGGLE_CLOCK_FREQUENCY, s_AWAIT_USER_COMMAND, s_REACTIVATE_CLOCK,
s_GENERATE_COMMAND, s_SEND_COMMAND, s_WAIT_RESPONSE, s_WAIT_FOR_CLOCK_EDGE_BEFORE_DISABLE, s_WAIT_DEASSERT,
s_PERIODIC_STATUS_CHECK);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal SD_clock_mode, waiting_for_vdd_setup : std_logic;
signal id_sequence_step_index : std_logic_vector(3 downto 0);
signal delay_counter : std_logic_vector(6 downto 0);
signal periodic_status_check : std_logic_vector(23 downto 0);
-- UNREGISTERED
begin
-- Define state transitions.
state_transitions: process (current_state, i_command_sent, i_response_received, id_sequence_step_index,
i_response_timed_out, i_response_crc_passed, delay_counter, waiting_for_vdd_setup,
i_user_command_ready, i_clocking_pulse_enable, i_current_clock_mode,
i_user_message_valid, i_last_cmd_was_55, periodic_status_check)
begin
case current_state is
when s_RESET =>
-- Reset local registers and begin identification process.
next_state <= s_WAIT_74_CYCLES;
when s_WAIT_74_CYCLES =>
-- Wait 74 cycles before the card can be sent commands to.
if (delay_counter = "1001010") then
next_state <= s_GENERATE_PREDEFINED_COMMAND;
else
next_state <= s_WAIT_74_CYCLES;
end if;
when s_GENERATE_PREDEFINED_COMMAND =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
next_state <= s_WAIT_PREDEFINED_COMMAND_TRANSMITTED;
when s_WAIT_PREDEFINED_COMMAND_TRANSMITTED =>
-- Send a predefined command to the SD card. This is the identification process for the SD card.
if (i_command_sent = '1') then
next_state <= s_WAIT_PREDEFINED_COMMAND_RESPONSE;
else
next_state <= s_WAIT_PREDEFINED_COMMAND_TRANSMITTED;
end if;
when s_WAIT_PREDEFINED_COMMAND_RESPONSE =>
-- Wait for a response from SD card.
if (i_response_received = '1') then
if (i_response_timed_out = '1') then
if (waiting_for_vdd_setup = '1') then
next_state <= s_GO_TO_NEXT_COMMAND;
else
next_state <= s_RESET;
end if;
else
if (i_response_crc_passed = '0') then
next_state <= s_GENERATE_PREDEFINED_COMMAND;
else
next_state <= s_GO_TO_NEXT_COMMAND;
end if;
end if;
else
next_state <= s_WAIT_PREDEFINED_COMMAND_RESPONSE;
end if;
when s_GO_TO_NEXT_COMMAND =>
-- Process the next command in the ID sequence.
if (id_sequence_step_index = PREDEFINED_COMMAND_GET_STATUS) then
next_state <= s_TOGGLE_CLOCK_FREQUENCY;
else
next_state <= s_GENERATE_PREDEFINED_COMMAND;
end if;
when s_TOGGLE_CLOCK_FREQUENCY =>
-- Now that the card has been initialized, increase the SD card clock frequency to 25MHz.
-- Wait for the clock generator to switch operating mode before proceeding further.
if (i_current_clock_mode = '1') then
next_state <= s_AWAIT_USER_COMMAND;
else
next_state <= s_TOGGLE_CLOCK_FREQUENCY;
end if;
when s_AWAIT_USER_COMMAND =>
-- Wait for the user to send a command to the SD card
if (i_user_command_ready = '1') then
next_state <= s_REACTIVATE_CLOCK;
else
-- Every 5 million cycles, or 0.1 of a second.
if (periodic_status_check = "010011000100101101000000") then
next_state <= s_PERIODIC_STATUS_CHECK;
else
next_state <= s_AWAIT_USER_COMMAND;
end if;
end if;
when s_PERIODIC_STATUS_CHECK =>
-- Update status every now and then.
next_state <= s_GENERATE_PREDEFINED_COMMAND;
when s_REACTIVATE_CLOCK =>
-- Activate the clock signal and wait 8 clock cycles.
if (delay_counter = "0001000") then
next_state <= s_GENERATE_COMMAND;
else
next_state <= s_REACTIVATE_CLOCK;
end if;
when s_GENERATE_COMMAND =>
-- Generate user command. If valid, proceed further. Otherwise, indicate that the command is invalid.
if (i_user_message_valid = '0') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_SEND_COMMAND;
end if;
when s_SEND_COMMAND =>
-- Wait for the command to be sent.
if (i_command_sent = '1') then
next_state <= s_WAIT_RESPONSE;
else
next_state <= s_SEND_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Wait for the SD card to respond.
if (i_response_received = '1') then
if (i_response_timed_out = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_FOR_CLOCK_EDGE_BEFORE_DISABLE;
end if;
else
next_state <= s_WAIT_RESPONSE;
end if;
when s_WAIT_FOR_CLOCK_EDGE_BEFORE_DISABLE =>
-- Wait for a positive clock edge before you disable the clock.
if (i_clocking_pulse_enable = '1') then
next_state <= s_WAIT_DEASSERT;
else
next_state <= s_WAIT_FOR_CLOCK_EDGE_BEFORE_DISABLE;
end if;
when s_WAIT_DEASSERT =>
-- wait for the user to release command generation request.
if (i_user_command_ready = '1') then
next_state <= s_WAIT_DEASSERT;
else
if (i_last_cmd_was_55 = '1') then
next_state <= s_AWAIT_USER_COMMAND;
else
-- Send a get status command to obtain the result of sending the last command.
next_state <= s_GENERATE_PREDEFINED_COMMAND;
end if;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State registers.
state_registers: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
-- Local FFs:
local_ffs:process ( i_clock, i_reset_n, i_powerup_busy_n, current_state,
id_sequence_step_index, i_response_received, i_response_timed_out,
i_allow_partial_rw)
begin
if (i_reset_n = '0') then
SD_clock_mode <= '0';
id_sequence_step_index <= (OTHERS => '0');
periodic_status_check <= (OTHERS => '0');
waiting_for_vdd_setup <= '0';
elsif (rising_edge(i_clock)) then
-- Set SD clock mode to 0 initially, thereby using a clock with frequency between 100 kHz and 400 kHz as
-- per SD card specifications. When the card is initialized change the clock to run at 25 MHz.
if (current_state = s_WAIT_DEASSERT) then
periodic_status_check <= (OTHERS => '0');
elsif (current_state = s_AWAIT_USER_COMMAND) then
periodic_status_check <= periodic_status_check + '1';
end if;
if (current_state = s_RESET) then
SD_clock_mode <= '0';
elsif (current_state = s_TOGGLE_CLOCK_FREQUENCY) then
SD_clock_mode <= '1';
end if;
-- Update the ID sequence step as needed.
if (current_state = s_RESET) then
id_sequence_step_index <= (OTHERS => '0');
elsif (current_state = s_GO_TO_NEXT_COMMAND) then
if ((i_powerup_busy_n = '0') and (id_sequence_step_index = "0010")) then
id_sequence_step_index <= "0001";
else
if (id_sequence_step_index = "0110") then
if (i_allow_partial_rw = '0') then
-- If partial read-write not allowed, then skip SET_BLK_LEN command - it will fail.
id_sequence_step_index <= "1000";
else
id_sequence_step_index <= "0111";
end if;
else
id_sequence_step_index <= id_sequence_step_index + '1';
end if;
end if;
elsif (current_state = s_WAIT_DEASSERT) then
if (i_last_cmd_was_55 = '0') then
-- After each command execute a get status command.
id_sequence_step_index <= PREDEFINED_COMMAND_GET_STATUS;
end if;
elsif (current_state = s_PERIODIC_STATUS_CHECK) then
id_sequence_step_index <= PREDEFINED_COMMAND_GET_STATUS;
end if;
-- Do not reset the card when SD card is having its VDD set up. Wait for it to respond, this may take some time.
if (id_sequence_step_index = "0010") then
waiting_for_vdd_setup <= '1';
elsif ((id_sequence_step_index = "0011") or (current_state = s_RESET)) then
waiting_for_vdd_setup <= '0';
end if;
end if;
end process;
-- Counter that counts to 74 to delay any commands.
initial_delay_counter: process(i_clock, i_reset_n, i_clocking_pulse_enable )
begin
if (i_reset_n = '0') then
delay_counter <= (OTHERS => '0');
elsif (rising_edge(i_clock)) then
if ((current_state = s_RESET) or (current_state = s_AWAIT_USER_COMMAND))then
delay_counter <= (OTHERS => '0');
elsif (((current_state = s_WAIT_74_CYCLES) or (current_state = s_REACTIVATE_CLOCK)) and
(i_clocking_pulse_enable = '1')) then
delay_counter <= delay_counter + '1';
end if;
end if;
end process;
-- FSM outputs.
o_SD_clock_mode <= SD_clock_mode;
o_generate_command <= '1' when ((current_state = s_GENERATE_PREDEFINED_COMMAND) or
(current_state = s_GENERATE_COMMAND))
else '0';
o_receive_response <= '1' when ((current_state = s_WAIT_PREDEFINED_COMMAND_RESPONSE) or
(current_state = s_WAIT_RESPONSE))
else '0';
o_drive_CMD_line <= '1' when ( (current_state = s_WAIT_PREDEFINED_COMMAND_TRANSMITTED) or
(current_state = s_SEND_COMMAND)) else '0';
o_predefined_command_ID <= id_sequence_step_index;
o_card_connected <= '1' when (id_sequence_step_index(3) = '1') and (
(id_sequence_step_index(2) = '1') or
(id_sequence_step_index(1) = '1') or
(id_sequence_step_index(0) = '1'))
else '0';
o_resetting <= '1' when (current_state = s_RESET) else '0';
o_command_completed <= '1' when (current_state = s_WAIT_DEASSERT) else '0';
o_enable_clock_generator <= '0' when (current_state = s_AWAIT_USER_COMMAND) else '1';
o_clear_response_register <= '1' when (current_state = s_REACTIVATE_CLOCK) else '0';
end rtl;
| mit | 8d1f3761b9f1b60dc55c1acd23813e0a | 0.63284 | 3.113585 | false | false | false | false |
freecores/grain | src/VHDL/test_synth/hw4_grain128.vhd | 1 | 775 | --
-- synthesis test 4:
-- * without clock enable
-- * fast
--
-- Altera EP2C-8, Quartus 8.0: (same as hw3_grain128)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw4_grain128 is
port (
CLK_I : in std_logic;
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of hw4_grain128 is
begin
top: entity work.grain128
generic map (
DEBUG => false,
FAST => true
)
port map (
CLK_I => CLK_I,
CLKEN_I => '1',
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INIT_I=> INIT_I,
KEYSTREAM_O => KEYSTREAM_O,
KEYSTREAM_VALID_O => KEYSTREAM_VALID_O
);
end behav;
| lgpl-3.0 | ebc296d7346063749f98b5857a7ecc13 | 0.621935 | 2.437107 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/compute_max/tb_compute_max_arch_non_countinous.vhd | 1 | 21,418 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:30:47 06/28/2017
-- Design Name:
-- Module Name: tb_compute_max_arch_non_countinous.vhd
-- Project Name: compute_max
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: compute_max
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_compute_max_arch_non_countinous IS
END tb_compute_max_arch_non_countinous;
ARCHITECTURE behavior OF tb_compute_max_arch_non_countinous IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT compute_max
GENERIC ( sample_width : natural := 32;
s : natural := 2;
d : natural := 2;
c : natural := 3);
PORT(
clock : IN std_logic;
reset_n : IN std_logic;
enable : IN std_logic;
sample_abs : IN std_logic_vector(sample_width-1 downto 0);
sample : IN std_logic_vector(sample_width-1 downto 0);
pos_campione : OUT std_logic_vector(natural(ceil(log2(real(c))))-1 downto 0);
pos_doppler : OUT std_logic_vector(natural(ceil(log2(real(d))))-1 downto 0);
pos_satellite : OUT std_logic_vector(natural(ceil(log2(real(s))))-1 downto 0);
max : OUT std_logic_vector(sample_width-1 downto 0);
sample_max : OUT std_logic_vector(sample_width-1 downto 0);
done : OUT std_logic
);
END COMPONENT;
for all : compute_max use entity work.compute_max(Structural_non_continous);
constant sample_width : natural:= 32;
constant s : natural:= 5;
constant d : natural:= 4;
constant c : natural:= 5;
--Inputs
signal clock : std_logic := '0';
signal reset_n : std_logic := '0';
signal enable : std_logic := '0';
signal sample_abs : std_logic_vector(sample_width-1 downto 0) := (others => '0');
signal sample : std_logic_vector(sample_width-1 downto 0) := (others => '0');
--Outputs
signal pos_campione : std_logic_vector(natural(ceil(log2(real(c))))-1 downto 0);
signal pos_doppler : std_logic_vector(natural(ceil(log2(real(d))))-1 downto 0);
signal pos_satellite : std_logic_vector(natural(ceil(log2(real(s))))-1 downto 0);
signal max : std_logic_vector(sample_width-1 downto 0);
signal done : std_logic;
signal sample_max : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: compute_max
GENERIC MAP(
sample_width => 32,
s => 5,
d => 4,
c => 5
)
PORT MAP (
clock => clock,
reset_n => reset_n,
enable => enable,
sample_abs => sample_abs,
pos_campione => pos_campione,
sample => sample,
sample_max => sample_max,
pos_doppler => pos_doppler,
pos_satellite => pos_satellite,
max => max,
done => done
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
reset_n <= '1';
wait for clock_period;
wait for 5 ns;
sample <= x"00010001";
-- TEST CASE: primo in assoluto (0,0,0,0x00010001)
--sample_abs <= x"00000050";
sample_abs <= x"00000002";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000008";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000007";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000002";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000001E";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000b";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000f";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000009";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000008";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000002";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000002";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000002";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000004";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000a";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000b";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000c";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000002";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000007";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000000";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000a";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000004";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000008";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000f";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000014";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000010";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000011";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000012";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000013";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
-- TEST CASE: ultimo di un satellite (4,3,1,0x00280028)
--sample_abs <= x"00000050";
sample_abs <= x"00000000";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
-- TEST CASE: primo di un satellite in mezzo (0,0,2,0x00290029)
--sample_abs <= x"00000050";
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000002";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000004";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000005";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000a";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000f";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000e";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000c";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000b";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000008";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000007";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000006";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000005";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000004";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000004";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000004";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000001c";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000010";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000000";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000004";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000008";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000006";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
-- TEST CASE: massimo interno all'intervallo doppler (2,1,3,0x00440044)
-- sample_abs <= x"00000050";
sample_abs <= x"00000000";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000000";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000002";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"0000000a";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000009";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000000";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000007";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000002";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000000";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000000";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000005";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000006";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000000";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000008";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000000";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000008";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000001";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000005";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000004";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000004";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000005";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000000";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000006";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
sample_abs <= x"00000003";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
sample <= sample + 65537;
-- TEST CASE: ultimo in assoluto (4,3,4,0x00640064)
-- sample_abs <= x"00000050";
sample_abs <= x"0000000a";
enable <= '1';
wait for clock_period;
enable <= '0';
wait for clock_period*2;
wait until done = '1';
wait for 20 ns;
reset_n <= '0';
wait;
end process;
END;
| gpl-2.0 | 6df4fbb28cec5e3854b617655702e56c | 0.536605 | 3.578613 | false | false | false | false |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/ALU_x16.vhd | 1 | 4,845 | library ieee;
use ieee.std_logic_1164.all;
entity ALU_x16 is
port (
opcode : IN STD_LOGIC_VECTOR(3 downto 0);
negate : IN STD_LOGIC;
input_A, input_B : IN STD_LOGIC_VECTOR(15 downto 0);
output, overflowMultDiv : OUT STD_LOGIC_VECTOR(15 downto 0)
);
end ALU_x16;
architecture skeleton of ALU_x16 is
component Multiplexer_4x16 is
Port ( Selector : in STD_LOGIC_VECTOR (3 downto 0);
input_A, input_B, input_C, input_D, input_E, input_F, input_G, input_H: in STD_LOGIC_VECTOR (15 downto 0);
input_I, input_J, input_K, input_L, input_M, input_N, input_O, input_P: in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component Adder_2x16 is
port (
isSubtraction: in STD_LOGIC;
input_A, input_B: in STD_LOGIC_VECTOR(15 DOWNTO 0);
carry_out: out STD_LOGIC;
output: out STD_LOGIC_VECTOR(15 DOWNTO 0));
end component;
component ArithmeticalRightShifter_x16 is
Port (
input : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component LogicalRightShifter_x16 is
Port (
input : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component ArithmeticalLogicalLeftShifter_x16 is
Port (
input : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component ArithmeticalComparator_x16 is
Port (
opcodeComp : STD_LOGIC_VECTOR(2 downto 0);
input_A, input_B : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component Multiplier_2x16 is
Port (
input_A, input_B : in STD_LOGIC_VECTOR (15 downto 0);
outputLow, outputHigh : out STD_LOGIC_VECTOR (15 downto 0);
carryOut : out STD_LOGIC);
end component;
component Divider_2x16 is
Port (
input_A, input_B : in STD_LOGIC_VECTOR (15 downto 0);
outputLow, outputHigh : out STD_LOGIC_VECTOR (15 downto 0);
carryOut : out STD_LOGIC);
end component;
component LogicalAND_2x16 is
Port (
input_A, input_B: in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component LogicalOR_2x16 is
Port (
input_A, input_B: in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component LogicalXOR_2x16 is
Port (
input_A, input_B: in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal output1, output2, output3, output4, output5, output6 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal output7, outputComparator : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal output14, output15, output0, outputand, outputor, outputxor : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal carryoutMul, carryoutDiv, carryoutAddSub : STD_LOGIC;
signal overMult, overDiv : STD_LOGIC_VECTOR(15 downto 0);
begin
-- 0000
-- 12
-- Soma e Subtração
P0: Adder_2x16 port map(negate, input_A, input_B, carryoutAddSub, output0);
-- 0001
-- Retorna o segundo valor
output1 <= input_B;
P2: LogicalAND_2x16 port map(input_A, input_B, outputand);
P3: LogicalOR_2x16 port map(input_A, input_B, outputor);
P4: LogicalXOR_2x16 port map(input_A, input_B, outputxor);
process(input_A, input_B) begin
if(negate = '0')
then
-- 0010
-- 1
-- And
output2 <= outputand;
-- 0011
-- 1
-- Or
output3 <= outputor;
-- 0100
-- 1
-- Xor
output4 <= outputxor;
else
-- 0010
-- 1
-- Nand
output2 <= not outputand;
-- 0011
-- 1
-- Nor
output3 <= not outputor;
-- 0100
-- 1
-- Xnor
output4 <= not outputxor;
end if;
if(opcode(0) = '0') then
overflowMultDiv <= overMult;
else
overflowMultDiv <= overDiv;
end if;
end process;
-- 0101
-- Shift aritmetico para direita
P5: ArithmeticalRightShifter_x16 port map(input_A, output5);
-- 0110
-- Shift logico para direita
P6: LogicalRightShifter_x16 port map(input_A, output6);
-- 0111
-- Shift aritmetico e logico para esquerda
P7: ArithmeticalLogicalLeftShifter_x16 port map(input_A, output7);
-- 1000
-- Comparadores
P8: ArithmeticalComparator_x16 port map(opcode(2 downto 0), input_A, input_B, outputComparator);
-- 1110
-- 12
-- Multiplicação
p14: Multiplier_2x16 port map(input_A, input_B, output14, overMult, carryoutMul);
-- 1111
-- 12
-- Divisão
p15: Divider_2x16 port map(input_A, input_B, output15, overDiv, carryoutDiv);
Poutput: Multiplexer_4x16 port map (opcode, output0, output1, output2, output3, output4, output5, output6,
output7, outputComparator, outputComparator, outputComparator,
outputComparator, outputComparator,
outputComparator, output14, output15, output);
end skeleton; | gpl-3.0 | c3bc463ad20c73f2fc728c5bb7320336 | 0.671694 | 2.991347 | false | false | false | false |
jfdelnero/CPLD_USBHxCFloppyEmulator | rtl/vhdl/TrackCore.vhd | 1 | 8,403 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-----------H----H--X----X-----CCCCC----22222----0000-----0000------11----------
----------H----H----X-X-----C--------------2---0----0---0----0--1--1-----------
---------HHHHHH-----X------C----------22222---0----0---0----0-----1------------
--------H----H----X--X----C----------2-------0----0---0----0-----1-------------
-------H----H---X-----X---CCCCC-----222222----0000-----0000----1111------------
-------------------------------------------------------------------------------
----------------------------------------- http://jeanfrancoisdelnero.free.fr --
--===========================================================================--
-- HxCFloppyEmu
-- Floppy drive emulator Project
--
-- http://jeanfrancoisdelnero.free.fr
-- HxC2001 - 2006 - 2008
--
-- Design units :
--
-- File name : TrackCore.vhd
--
-- Purpose : Track counter
--
--
-- Dependencies : IEEE.Std_Logic_1164
-- IEEE.std_logic_signed
--
--============================================================================-
-- --
-- Copyright (C) 2006, 2007, 2008 Jean-François DEL NERO --
-- --
-- This file is part of HxCFloppyEmulator. --
-- --
-- HxCFloppyEmulator may be used and distributed without restriction provided--
-- that this copyright statement is not removed from the file and that any --
-- derivative work contains the original copyright notice and the associated --
-- disclaimer. --
-- --
-- HxCFloppyEmulator is free software; you can redistribute it --
-- and/or modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 2 --
-- of the License, or (at your option) any later version. --
-- --
-- HxCFloppyEmulator is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. --
-- See the GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with HxCFloppyEmulator; if not, write to the Free Software --
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA--
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 1.0 Jean-François DEL NERO 23 march 2008 Major update:
--
-- MFM/FM output generator (HeadShifter) rewritten.
-- It can now do any bitrate between
-- 63kbit/s and 1Mbit/s with a 62.5ns step.
-- The emulator can now handle bitrate-protected floppies ;-)
--
-- The SRAM is now used like a ring buffer (1 buffer of 8KB).
--
-- The master state machine run now at 16Mhz
-- to allow fast opcode execution / mfm loading.
--
-- "Validate Track" opcode removed (same functionnality in "SENDTRACKCODE opcode".
-- "SETINDEX" opcode modified:
-- "SENDTRACKCODE" added (2 byte : 0x3 <track number>)
-- "SETBITRATE" opcode added (2 bytes: 0xD <period value>)
-- "NOP" opcode added (2 bytes : 0x7 XX)
-- "Disk Changed" and "Ready" signals
-- are now software driven
--
-- Track position register is now 8 bits.
--
-- SRAM_CS_not is now driven (for the SRAM standby mode)
--
-- 0.5 Jean-François DEL NERO 19 November 2006 Jumper-free drive select added
-- jeanfrancoisdelnero < > free.fr
-- 0.4 Jean-François DEL NERO 11 November 2006 500kbits/s support added
-- 2*1Ko and 2*2Ko buffer size available
-- Write protect signal added
-- Shugart and IBM PC mode available
-- 0.2 Jean-François DEL NERO 16 September 2006 MFM Pulse Generator rewritten
-- 0.1 Jean-François DEL NERO 25 June 2006 First public version
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- package TrackCore
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_signed.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity TrackCore is
port (
FLOPPY_DRIVE_SELECT: in std_logic;
HEADTRACKPOSITION: out std_logic_vector(7 downto 0); -- track position value
HEADMOVED: out std_logic;
ackheadmove: in std_logic;
FLOPPY_STEP: in std_logic; -- Step command
FLOPPY_DIR: in std_logic; -- Step direction
FLOPPY_TRK00 : out std_logic; -- Track 0 indicator
clear_cnt: in std_logic;
clock: in std_logic;
reset_not: in std_logic
);
end TrackCore;
------------------------------------------------------------------------------------------
architecture arch of TrackCore is
signal track00signal: std_logic;
signal trackposition : std_logic_vector(7 downto 0);
signal stepsignal : std_logic;
signal stepsignal2 : std_logic;
begin
FLOPPY_TRK00<=track00signal and FLOPPY_DRIVE_SELECT;
-------------------------------------------------------
-- Track Circuit
trackcounter : process(FLOPPY_STEP,FLOPPY_DIR,trackposition,clock,reset_not)
begin
if (reset_not='0')
then
track00signal<='1';
trackposition<=(others=>'0');
elsif (clock='1' and clock'EVENT)
then
-- resync step signal (metastability issue)
stepsignal<=FLOPPY_STEP;
stepsignal2<=stepsignal;
if(ackheadmove='1')
then
HEADMOVED<='0';
end if;
if(FLOPPY_DRIVE_SELECT='1')
then
if(stepsignal2='1')
then
HEADMOVED<='1';
end if;
if(stepsignal/=stepsignal2 and stepsignal='1')
then
if(FLOPPY_DIR='1') then
trackposition<=trackposition + conv_std_logic_vector(1, 8);
else
if (trackposition/="00000000")
then
trackposition<=trackposition - conv_std_logic_vector(1, 8);
end if;
end IF;
end if;
end IF;
if(trackposition="00000000")
then
track00signal<='1';
else
track00signal<='0';
end if;
if(clear_cnt='1')
then
trackposition<="00000000";
end if;
end IF;
end process;
HEADTRACKPOSITION<=trackposition;
end arch; | gpl-3.0 | b47b7b7672a0fcafd3289fc3f319cd31 | 0.403427 | 4.670928 | false | false | false | false |
AleChir/Digital_Filter_VHDL | Digital_Filter/fulladder_generic.vhd | 1 | 912 | library ieee;
use ieee.std_logic_1164.all;
entity fulladder_generic is
generic (N: integer:=8);
port( a, b: in std_logic_vector (N-1 downto 0);
ci: in std_logic;
co: out std_logic;
s: out std_logic_vector (N-1 downto 0);
overf: out std_logic);
end fulladder_generic;
architecture behavior of fulladder_generic is
component b1fulladder
port( a, b, ci: IN std_logic;
s,co: OUT std_logic);
end component;
signal internalco: std_logic_vector(N downto 0);
signal sum: std_logic_vector(N-1 downto 0);
begin
internalco(0)<= ci;
G1: for i in 1 to N generate
additions: b1fulladder port map (a(i-1), b(i-1), internalco(i-1), sum(i-1), internalco(i));
end generate;
co<=internalco(N);
s<=sum;
overf<=(a(N-1) and b(N-1) and (not sum(N-1))) or (not(a(N-1)) and not(b(N-1)) and
sum(N-1));
end behavior;
| gpl-3.0 | 092351dc5aa50d759f595830a44a6056 | 0.60636 | 2.895238 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/moltiplicatore_booth/contatore_modulo_n.vhd | 1 | 1,766 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:25:45 11/23/2015
-- Design Name:
-- Module Name: contatore_modulo_n - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity contatore_modulo_n is
generic (n : natural := 4);
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
count_en : in STD_LOGIC;
up_down : in STD_LOGIC;
mod_n : out STD_LOGIC);
end contatore_modulo_n;
architecture Behavioral of contatore_modulo_n is
begin
process (clock, reset_n, up_down)
variable conteggio : natural range 0 to n-1 := 0;
begin
if (reset_n = '0') then
mod_n <= '0';
if(up_down = '0') then
conteggio := 0;
else
conteggio := n-1;
end if;
elsif (clock = '1' and clock'event) then
if (count_en = '1') then
if (up_down = '0') then
if(conteggio = n-1) then
mod_n <= '1';
conteggio := 0;
else
mod_n <= '0';
conteggio := conteggio + 1;
end if;
else
if(conteggio = 0) then
mod_n <= '1';
conteggio := n-1;
else
mod_n <= '0';
conteggio := conteggio - 1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 8298fcd25dcc1757d3d02d7a0b4961d2 | 0.563986 | 3.153571 | false | false | false | false |
imr/Mandelbrot-VHDL | src/ConstRAM.vhd | 1 | 9,332 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ConstRAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ConstRAM IS
PORT
(
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END ConstRAM;
ARCHITECTURE SYN OF constram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_b : STRING;
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(35 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_b => "NONE",
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => 10,
widthad_b => 10,
width_a => 36,
width_b => 36,
width_byteena_a => 1
)
PORT MAP (
address_a => wraddress,
clock0 => clock,
data_a => data,
wren_a => wren,
address_b => rdaddress,
q_b => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "36864"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "36"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "36"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "36"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "36"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL "data[35..0]"
-- Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL "q[35..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 36 0 data 0 0 36 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 36 0 @q_b 0 0 36 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ConstRAM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| bsd-3-clause | 4b2c9302cbc313ed7a9819bfccfe51d8 | 0.683026 | 3.469145 | false | false | false | false |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/Altera_UP_SD_Signal_Trigger.vhd | 2 | 955 | ---------------------------------------------------------------------------------------
-- This module generates a trigger pulse every time it sees a transition
-- from 0 to 1 on signal i_signal.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_Signal_Trigger is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_signal : in std_logic;
o_trigger : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Signal_Trigger is
-- Local wires
-- REGISTERED
signal local_reg : std_logic;
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
local_reg <= '0';
else
if (rising_edge(i_clock)) then
local_reg <= i_signal;
end if;
end if;
end process;
o_trigger <= '1' when ((local_reg = '0') and (i_signal = '1'))
else '0';
end rtl; | mit | 5e8df3531baf8df631e3a60754b28470 | 0.526702 | 3.183333 | false | false | false | false |
Xion345/fpga-projects | library/uart/uart_rxtx_clock.vhd | 1 | 1,395 | -- UART RX/TX with clock
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_rxtx_clock is
port(
clk, reset: in std_logic; -- Clock and reset
--
rx: in std_logic; -- UART RX (Receive) pin
tx: out std_logic; -- UART TX (Send) pin
data_rx: out std_logic_vector(7 downto 0); -- Data byte to send
data_tx: in std_logic_vector(7 downto 0); -- Received data byte
rx_done_tick: out std_logic; -- Sent done tick
tx_done_tick: out std_logic; -- Receive done tick
tx_start: in std_logic -- Start transmission tick
);
end uart_rxtx_clock;
architecture uart_rxtx_clock_arch of uart_rxtx_clock is
signal baud16_tick: std_logic;
begin
uart_clock: entity work.counter_mod_m
generic map(N => 10, M => 54) -- 115200 bauds from 100Mhz clock (16x oversampling)
port map(clk => clk, reset => reset, max_tick => baud16_tick);
receiver: entity work.uart_rx
port map(clk => clk, reset => reset,
rx => rx, baud16_tick => baud16_tick,
data_out => data_rx, rx_done_tick => rx_done_tick);
transmitter: entity work.uart_tx
port map(clk => clk, reset => reset,
tx => tx, baud16_tick => baud16_tick,
data_in => data_tx, tx_done_tick => tx_done_tick,
tx_start => tx_start);
end uart_rxtx_clock_arch; | mit | 46bfe01d71877a028f73177962f29777 | 0.602151 | 3.369565 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/compute_max/d_edge_triggered.vhd | 1 | 1,342 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:16:54 11/06/2015
-- Design Name:
-- Module Name: d_edge_triggered - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity d_edge_triggered is
generic (delay : time := 0 ns);
Port (data_in : in STD_LOGIC;
reset_n : in STD_LOGIC;
clock : in STD_LOGIC;
data_out : out STD_LOGIC);
end d_edge_triggered;
architecture Behavioral of d_edge_triggered is
begin
process(clock, reset_n, data_in)
begin
-- Reset asincrono
if (reset_n = '0') then
data_out <= '0' after delay;
--elsif (clk = '1' and clock'event) then
elsif (rising_edge(clock)) then
data_out <= data_in after delay;
end if;
end process;
end Behavioral;
| gpl-2.0 | cd0a8a50d884e9f4b1007a14d831f041 | 0.596125 | 3.759104 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/tb_wrapper_complex_abs_esaustivo.vhd | 1 | 5,476 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09.07.2017 17:24:32
-- Design Name:
-- Module Name: tb_wrapper_complex_abs_esaustivo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.math_real.all;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_wrapper_complex_abs_esaustivo is
end tb_wrapper_complex_abs_esaustivo;
architecture Behavioral of tb_wrapper_complex_abs_esaustivo is
component wrapper_complex_abs is
Generic ( complex_width : natural := 32 );
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
complex_value : in STD_LOGIC_VECTOR (complex_width-1 downto 0);
complex_value_out :out STD_LOGIC_VECTOR(complex_width-1 downto 0);
abs_value : out STD_LOGIC_VECTOR (complex_width-1 downto 0);
valid_out : out STD_LOGIC;
valid_in : in STD_LOGIC;
ready_out : out STD_LOGIC;
ready_in : in STD_LOGIC);
end component wrapper_complex_abs;
--Constants
constant clock_period : time := 10 ns;
constant complex_width : natural := 32;
constant num_cicli : natural := 2 ** (complex_width-1)-1;
--constant num_cicli : natural := 10;
--Inputs
signal clock : std_logic := '0';
signal reset_n : std_logic := '1';
signal complex_value : std_logic_vector(complex_width-1 downto 0) := (others => '0');
signal valid_in : std_logic := '0';
signal ready_in : std_logic := '0';
--Outputs
signal abs_value : std_logic_vector(complex_width-1 downto 0);
signal valid_out: std_logic := '0';
signal ready_out : std_logic := '0';
signal complex_value_out : STD_LOGIC_VECTOR(complex_width-1 downto 0);
begin
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
uut : wrapper_complex_abs
port map(
clock => clock,
reset_n => reset_n,
complex_value => complex_value,
complex_value_out => complex_value_out,
abs_value => abs_value,
valid_out => valid_out,
valid_in => valid_in,
ready_out => ready_out,
ready_in => ready_in);
--Questo test incrementa ad ogni colpo di clock il valore in ingresso di 1 da 1 a 2^31 (non 2^32 perche in vivado non si puo rappresentare
-- come intero un numero piu grande di 2^31).
-- le due variabili rappresentano la parte real e quella immaginaria del segnale in ingresso in particolare
-- devo considerare che i valori ammissibili per entrambi siano compresi tra (-32768,32767) cioe
-- -2^complex_width-1 e 2^(complex_width-1)-1
stim_proc: process
variable modulo : std_logic_vector(complex_width-1 downto 0) := (others=> '0');
variable complex_value_variable_real, complex_value_variable_img : integer := 0;
begin
-- TEST partenza da 0
reset_n <= '0';
complex_value <= x"00000000";
complex_value_variable_real := 0;
complex_value_variable_img := 0;
--TEST PARTENZA DAL PRIMO NEGATIVO
-- complex_value <=x"7fff7fff";
-- complex_value_variable_real := 32767;
-- complex_value_variable_img := 32767;
wait for 100 ns;
reset_n <= '1';
ready_in <= '1';
--Gli if sono messi per evitare che l'assert dia problemi durante la simulazione
--I trattini indicano dei don't care.
for i in 0 to num_cicli loop
complex_value <= complex_value + 1;
complex_value_variable_real := complex_value_variable_real + 1;
--Se ho esaminato tutti i negativi della parte reale cioe il segnale in ingresso valeva al ciclo precedente
-- ----FFFF e ora quindi mi trovo che la parte reale è 0 e devo incrementare quella immaginaria
if(complex_value_variable_real = 0) then
complex_value_variable_img := complex_value_variable_img + 1;
--Se ho esaminato tutti i numeri positivi della parte reale cioè il segnale in ingresso valeva al ciclo
--precedente ----7FFF e ora quindi mi trovo che la parte reale deve essere portata al numero negativo piu grande
elsif(complex_value_variable_real = 32768)then
complex_value_variable_real := -2**((complex_width/2)-1);
end if;
--stessa considerazione del commento precendete solo applicata alla parte immaginaria
if(complex_value_variable_img = 32768)then
complex_value_variable_img := -2**((complex_width/2)-1);
end if;
valid_in <= '1';
wait for clock_period * 2;
valid_in <= '0';
wait until valid_out<= '1';
modulo := std_logic_vector(to_signed(complex_value_variable_real * complex_value_variable_real + complex_value_variable_img * complex_value_variable_img , 32));
assert(abs_value = modulo)report "Modulo calcolato sbagliato!";
wait until ready_out <= '1';
end loop;
wait;
end process;
end Behavioral;
| gpl-2.0 | a4fe0a7168dd771cc6408daa705fa993 | 0.646876 | 3.484405 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core1/test_dds_wrapper.vhd | 1 | 7,398 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1756540 Mon Jan 23 19:11:19 MST 2017
--Date : Mon Jul 10 15:30:57 2017
--Host : sistemiEmbedded running 64-bit Ubuntu 16.10
--Command : generate_target test_dds_wrapper.bd
--Design : test_dds_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
--! @file test_dds_wrapper.vhd
--! @author Antonio Riccio, Andrea Scognamiglio, Stefano Sorrentino
--! @brief Entità top-level
--! @example tb_wrapper_dds.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--! @brief Componente top-level
--! @details Il componente genera campioni di un segnale periodico la cui frequenza
--! e fase possono essere configurate dinamicamente.
--!
--! Gli incrementi di fase e di frequenza sono dei valori espressi su 24 bit e
--! sono concatenati nel segnale poff_pinc con poff che occupa i primi 24 bit e pinc
--! che occupa gli ultimi 24 bit.
--!
--! Il segnale di uscita è un valore complesso che ha la
--! parte immaginaria nella metà più significativa e la parte reale nella metà meno significativa.
--!
--! Il componente inizia a generare il numero richiesto di campioni ogni volta che
--! il segnale valid_in è alto. Il segnale done viene asserito ogni volta
--! che termina la generazione dei campioni, in tal caso il blocco si mette in attesa che valid_in sia nuovamente alto
--! per poter generare altri campioni.
entity test_dds_wrapper is
generic (
campioni : natural := 20460 ); --! Numero di campioni da generare
port (
clock : in STD_LOGIC; --! Segnale di temporizzazione
reset_n : in STD_LOGIC; --! Segnale di reset 0-attivo
poff_pinc : in STD_LOGIC_VECTOR(47 downto 0); --! Spiazzamenti di fase e di frequenza (poff + pinc)
valid_in : in STD_LOGIC; --! Indica che il dato sulla linea di ingresso è valido
ready_in : in STD_LOGIC; --! Indica che il componente a valle è pronto ad accettare valori in ingresso
valid_out : out STD_LOGIC; --! Indica che il dato sulla linea di uscita è valido
ready_out : out STD_LOGIC; --! Indica che questo componente è pronto ad accettare valori in ingresso
sine_cosine : out STD_LOGIC_VECTOR(31 downto 0); --! Campioni complessi del segnale periodico (immaginaria + reale)
done : out STD_LOGIC --! Segnale di terminazione delle operazioni
);
end test_dds_wrapper;
--! @brief Architettura top-level descritta nel dominio strutturale
--! @details Il componente fa uso del blocco DDS_compiler della Xilinx per generare
--! campioni di un segnale periodico con una fase ed una frequenza configurabili.
architecture STRUCTURE of test_dds_wrapper is
--! @brief Blocco che genera i campioni del segnale periodico
component test_dds is
port (
ready_out : out STD_LOGIC;
valid_in : in STD_LOGIC;
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
sine_cosine : out STD_LOGIC_VECTOR(31 downto 0);
ready_in : in STD_LOGIC;
valid_out : out STD_LOGIC;
poff_pinc : in STD_LOGIC_VECTOR(47 downto 0)
);
end component test_dds;
--! @brief Registro a parallelismo generico che opera sul fronte di salita del clock
component register_n_bit is
generic (
n : natural := 8
);
port (
I : in STD_LOGIC_VECTOR(n-1 downto 0);
clock : in STD_LOGIC;
load : in STD_LOGIC;
reset_n : in STD_LOGIC;
O : out STD_LOGIC_VECTOR(n-1 downto 0)
);
end component register_n_bit;
--! @brief Contatore modulo-n di tipo up-down con caricamento del valore di conteggio e
--! segnali di uscita indicanti valore e fine del conteggio
component counter_modulo_n
generic (
n : natural := 16
);
port (
clock : in STD_LOGIC;
count_en : in STD_LOGIC;
reset_n : in STD_LOGIC;
up_down : in STD_LOGIC;
load_conteggio : in STD_LOGIC;
conteggio_in : in STD_LOGIC_VECTOR(natural(ceil(log2(real(n))))-1 downto 0);
conteggio_out : out STD_LOGIC_VECTOR((natural(ceil(log2(real(n)))))-1 downto 0);
count_hit : out STD_LOGIC
);
end component counter_modulo_n;
--! @brief Parte di controllo del blocco
component fsm_dds_wrapper
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
count_hit : in STD_LOGIC;
valid_in_out : out STD_LOGIC;
reset_n_all : out STD_LOGIC;
done : out STD_LOGIC
);
end component fsm_dds_wrapper;
signal sine_cosine_sig : std_logic_vector(31 downto 0);
signal reset_n_all, counter_enable_sig, count_hit_sig, valid_out_sig, valid_in_sig, load_complex_value_reg : std_logic;
begin
valid_out <= valid_out_sig;
load_complex_value_reg <= counter_enable_sig and reset_n_all;
-- Il contatore si incrementa solo quando si è sicuri che il blocco a valle abbia
-- prelevato il dato in uscita. Questa situazione accade quando il blocco DDS ha
-- generato un'uscita valida ed il blocco a valle è pronto a ricevere il dato (asserendo ready_in).
counter_enable_sig <= valid_out_sig and ready_in;
--! @brief Il DDS genera dei campioni complessi campionati ad una frequenza di 20.46 Mhz
test_dds_i : component test_dds
port map (
clock => clock,
poff_pinc(47 downto 0) => poff_pinc(47 downto 0),
ready_in => ready_in,
ready_out => ready_out,
reset_n => reset_n_all,
sine_cosine(31 downto 0) => sine_cosine_sig(31 downto 0),
valid_in => valid_in_sig,
valid_out => valid_out_sig
);
--! @brief Il registro memorizza il valore complesso generato dal DDS
reg_complex_value_out : register_n_bit
generic map (
n => 32
)
port map (
I => sine_cosine_sig,
clock => clock,
load => load_complex_value_reg,
reset_n => reset_n,
O => sine_cosine
);
--! @brief Contatore che controlla il numero di campioni da generare
--! @details Una volta raggiunto il massimo conteggio, il contatore asserisce un segnale
--! (count_hit) che porta l'entità top-level a portarsi in uno stato di reset
counter_campioni : counter_modulo_n
generic map (
n => campioni
)
port map (
clock => clock,
count_en => counter_enable_sig,
reset_n => reset_n_all,
up_down => '0',
load_conteggio => '0',
conteggio_in => (others => '0'),
conteggio_out => open,
count_hit => count_hit_sig
);
--! @brief Automa a stati finiti per la gestione dei segnali di controllo del DDS.
--! @details Attende la terminazione del conteggio e resetta il DDS_compiler.
--! Questo componente è necessario per gestire opportunamente il segnale
--! di reset del blocco DDS, il quale deve mantenersi basso per almeno due periodi di clock.
fsm_dds_wrapper_i : fsm_dds_wrapper
port map (
clock => clock,
reset_n => reset_n,
valid_in => valid_in,
count_hit => count_hit_sig,
valid_in_out => valid_in_sig,
reset_n_all => reset_n_all,
done => done
);
end STRUCTURE;
| gpl-2.0 | 8c9d56744146f1a7bb676daecac1204a | 0.648564 | 3.370151 | false | true | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/compute_max/tb_wrapper_compute_max.vhd | 1 | 25,132 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2017 16:57:25
-- Design Name:
-- Module Name: tb_wrapper_compute_max - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.math_real.all;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_wrapper_compute_max is
end tb_wrapper_compute_max;
architecture Behavioral of tb_wrapper_compute_max is
component wrapper_compute_max is
Generic ( sample_width : natural := 32;
s : natural := 2;
d : natural := 2;
c : natural := 3);
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
ready_in : in STD_LOGIC;
sample_abs : in STD_LOGIC_VECTOR (sample_width-1 downto 0);
sample : in STD_LOGIC_VECTOR (sample_width-1 downto 0);
pos_campione : out STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0);
pos_doppler : out STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0);
pos_satellite : out STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0);
max : out STD_LOGIC_VECTOR (sample_width-1 downto 0);
sample_max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
valid_in : in STD_LOGIC;
ready_out : out STD_LOGIC;
valid_out : out STD_LOGIC);
end component wrapper_compute_max;
--Constants
constant clock_period : time := 10 ns;
constant sample_width : natural := 32;
constant s : natural := 5;
constant d: natural := 4;
constant c : natural := 5;
constant num_cicli : natural := s*c*d;
--Inputs
signal clock : std_logic := '0';
signal reset_n : std_logic := '1';
signal sample_abs : STD_LOGIC_VECTOR (sample_width-1 downto 0) := (others => '0');
signal sample : STD_LOGIC_VECTOR (sample_width-1 downto 0) := (others => '0');
signal valid_in : STD_LOGIC := '0';
signal ready_in : STD_LOGIC := '0';
--Outputs
signal pos_campione : STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0) := (others => '0');
signal pos_doppler : STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0) := (others => '0');
signal pos_satellite : STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0) := (others => '0');
signal max : STD_LOGIC_VECTOR (sample_width-1 downto 0) := (others => '0');
signal sample_max : STD_LOGIC_VECTOR(sample_width-1 downto 0) := (others => '0');
signal ready_out : STD_LOGIC := '0';
signal valid_out : STD_LOGIC := '0';
begin
uut : wrapper_compute_max
Generic map ( sample_width => sample_width,
s => s,
d => d,
c => c)
Port map(clock => clock,
reset_n => reset_n,
ready_in => ready_in,
valid_in => valid_in,
sample_abs => sample_abs,
sample => sample,
pos_campione => pos_campione,
pos_doppler => pos_doppler,
pos_satellite => pos_satellite,
max => max,
sample_max => sample_max,
ready_out => ready_out,
valid_out => valid_out );
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
stim_proc: process
variable valore_assoluto : std_logic_vector(sample_width-1 downto 0) := (others => '0');
variable sample_abs_variable : integer := 0;
begin
reset_n <= '0';
wait for 100 ns;
reset_n <='1';
ready_in <= '1';
-- for j in 0 to num_cicli-1 loop
-- if(j = 3) then
-- sample <= sample + 65537;
-- sample_abs_variable := 200;
-- sample_abs <= std_logic_vector(to_unsigned(sample_abs_variable * sample_abs_variable * 2, sample_width));
-- else
-- sample <= sample + 65537;
-- sample_abs_variable := 50;
-- sample_abs <= std_logic_vector(to_unsigned(sample_abs_variable * sample_abs_variable * 2, sample_width));
-- end if;
-- sample <= sample + 65537;
-- sample_abs_variable := sample_abs_variable + 1;
-- sample_abs <= std_logic_vector(to_unsigned(sample_abs_variable * sample_abs_variable * 2, sample_width));
-- wait for clock_period * 2;
-- valid_in <='1';
-- wait for clock_period * 2;
-- valid_in <= '0';
-- end loop;
--TEST Primo Assoluto
-- sample <= x"000a000a";
--sample_abs <= x"000000c8";
sample <= x"00010001";
sample_abs <= x"00000002";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
sample_abs <= x"00000020";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
sample_abs <= x"00000008";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
sample_abs <= x"00000012";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period;
reset_n <='1';
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
sample_abs <= x"00000048";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
sample_abs <= x"00000062";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
sample_abs <= x"00000002";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
sample_abs <= x"00000020";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
sample_abs <= x"00000008";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
sample_abs <= x"00000012";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period;
reset_n <='1';
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
sample_abs <= x"00000048";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
sample_abs <= x"00000062";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
sample_abs <= x"00000002";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
sample_abs <= x"00000020";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
sample_abs <= x"00000008";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
sample_abs <= x"00000012";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
sample_abs <= x"00000048";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
sample_abs <= x"00000062";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
sample_abs <= x"00000002";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
sample_abs <= x"00000020";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
sample_abs <= x"00000008";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
sample_abs <= x"00000012";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
sample_abs <= x"00000048";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
sample_abs <= x"00000062";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
--TEST Ultimo campione del secondo satellite
--sample <= x"000a000a";
--sample_abs <= x"000000c8";
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
--TEST Primo campione del terzo satellite
--sample <= x"000a000a";
--sample_abs <= x"000000c8";
sample <= x"00010001";
sample_abs <= x"00000002";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
sample_abs <= x"00000020";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
sample_abs <= x"00000008";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
sample_abs <= x"00000012";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
sample_abs <= x"00000048";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
--TEST in mezzo al terzo satellite
-- sample <= x"000a000a";
--sample_abs <= x"000000c8";
sample <= x"00070007";
sample_abs <= x"00000062";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
sample_abs <= x"00000002";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
sample_abs <= x"00000020";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
sample_abs <= x"00000008";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
sample_abs <= x"00000012";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
sample_abs <= x"00000048";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
sample_abs <= x"00000062";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
sample_abs <= x"00000002";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
sample_abs <= x"00000020";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
sample_abs <= x"00000008";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
sample_abs <= x"00000012";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
sample_abs <= x"00000048";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
sample_abs <= x"00000062";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
sample_abs <= x"00000002";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
sample_abs <= x"00000020";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
sample_abs <= x"00000008";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
sample_abs <= x"00000012";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
sample_abs <= x"00000048";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
sample_abs <= x"00000062";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
sample_abs <= x"00000002";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
sample_abs <= x"00000020";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
sample_abs <= x"00000008";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
sample_abs <= x"00000012";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
sample_abs <= x"00000048";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
sample_abs <= x"00000062";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
sample_abs <= x"00000002";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
sample_abs <= x"00000020";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
sample_abs <= x"00000008";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
sample_abs <= x"00000012";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
sample_abs <= x"00000048";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
sample_abs <= x"00000062";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
sample_abs <= x"00000080";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
--TEST Ultimo in assoluto
-- sample <= x"000a000a";
-- sample_abs <= x"000000c8";
sample <= x"00050005";
sample_abs <= x"00000032";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
--valid_in <= '0';
--TEST il blocco successivo al compute_max sarebbe pronto a ricevere il dato
--mentre quello prima non ha generato nuovi dati
ready_in <= '0';
wait until valid_out <= '1';
ready_in <= '1';
valid_in <= '0';
wait;
end process;
end Behavioral;
| gpl-2.0 | 176b434aa6a8d4fc83b7ec646ef239fd | 0.552125 | 3.282225 | false | false | false | false |
freecores/grain | src/VHDL/test_synth/hw2_grain128.vhd | 1 | 779 | --
-- synthesis test 2:
-- * without clock enable
-- * slow
--
--
-- Altera EP2C-8, Quartus 8.0: (same as hw1_grain128)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw2_grain128 is
port (
CLK_I : in std_logic;
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of hw2_grain128 is
begin
top: entity work.grain128
generic map (
DEBUG => false,
FAST => false
)
port map (
CLK_I => CLK_I,
CLKEN_I => '1',
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INIT_I=> INIT_I,
KEYSTREAM_O => KEYSTREAM_O,
KEYSTREAM_VALID_O => KEYSTREAM_VALID_O
);
end behav;
| lgpl-3.0 | 59c55f272a0c3c25922d405950395c9d | 0.620026 | 2.434375 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/tb_complex_max.vhd | 1 | 17,517 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.07.2017 14:40:20
-- Design Name:
-- Module Name: tb_complex_max - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_complex_max is
end tb_complex_max;
architecture Behavioral of tb_complex_max is
component complex_max is
Generic ( sample_width : natural := 32;
s : natural := 5;
d : natural := 4;
c : natural := 5 );
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
sample : in STD_LOGIC_VECTOR(sample_width-1 downto 0);
sample_max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
pos_campione : out STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0);
pos_doppler : out STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0);
pos_satellite : out STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0);
ready_out : out STD_LOGIC;
valid_out : out STD_LOGIC);
end component;
--Constants
constant clock_period : time := 10 ns;
constant sample_width : natural := 32;
constant s : natural := 5;
constant d : natural := 4;
constant c : natural := 5;
--Inputs
signal clock : std_logic := '0';
signal reset_n : std_logic := '1';
signal sample : std_logic_vector(sample_width-1 downto 0) := (others => '0');
signal valid_in : std_logic := '0';
signal ready_in : std_logic := '0';
-- Outputs
signal sample_max : std_logic_vector(sample_width-1 downto 0) := (others => '0');
signal max : std_logic_vector(sample_width-1 downto 0) := (others => '0');
signal pos_campione : STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0);
signal pos_doppler : STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0);
signal pos_satellite : STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0);
signal ready_out : std_logic := '0';
signal valid_out : std_logic := '0';
begin
uut: complex_max
Generic map ( sample_width => sample_width,
s => s,
d => d,
c => c )
Port map ( clock => clock,
reset_n => reset_n,
ready_in => ready_in,
valid_in => valid_in,
sample => sample,
sample_max => sample_max,
max => max,
pos_campione => pos_campione,
pos_doppler => pos_doppler,
pos_satellite => pos_satellite,
ready_out => ready_out,
valid_out => valid_out);
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
stim_proc: process
begin
reset_n <= '0';
wait for 100 ns;
reset_n <= '1';
ready_in <= '0';
--TEST Primo assoluto
-- sample <= x"000a000a";
sample <= x"00010001";
--TEST dato iniziale non pronto
--wait for clock_period * 20;
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00090009";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00090009";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
--TEST attesa simultanea dei blocchi
-- sample <= x"000b000b";
-- wait for clock_period * 50;
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
--TEST Ultimo campione del secondo satellite
-- sample <= x"000a000a";
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
--TEST Primo campione del terzo satellite
--sample <= x"000a000a";
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
--TEST in mezzo al terzo satellite
-- sample <= x"000a000a";
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00010001";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00040004";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00020002";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00060006";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00030003";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00070007";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
sample <= x"00080008";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
--TEST Ultimo in assoluto
-- sample <= x"000a000a";
sample <= x"00050005";
valid_in <= '1';
wait for clock_period * 3;
valid_in <= '0';
wait until ready_out = '1';
valid_in <= '1';
sample <=x"000c000c";
wait for clock_period * 20;
ready_in <= '0';
wait;
end process;
end Behavioral;
| gpl-2.0 | 7612e02154f53a764b57c76cf440b3b2 | 0.529314 | 3.188387 | false | false | false | false |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/RegisterDFlipFlop_x16.vhd | 1 | 538 | library ieee;
use ieee.std_logic_1164.all;
entity RegisterDFlipFlop_x16 is
port (
clock, reset, enable: in STD_LOGIC;
input: in STD_LOGIC_VECTOR(15 DOWNTO 0);
output: out STD_LOGIC_VECTOR(15 DOWNTO 0));
end RegisterDFlipFlop_x16;
architecture skeleton of RegisterDFlipFlop_x16 is
begin
process (clock, reset, enable, input) is
begin
if(reset = '1') then
output <= "0000000000000000";
elsif (clock'event AND clock = '1') then
if(enable = '1') then
output <= input;
end if;
end if;
end process;
end skeleton; | gpl-3.0 | d6c6da38254b17eb107ad6f0da192bfc | 0.700743 | 2.877005 | false | false | false | false |
freecores/grain | src/VHDL/test_sim/tb_grain.vhd | 1 | 3,610 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_grain is
generic (
DEBUG : boolean := false;
FAST : boolean := false
);
end entity;
architecture test of tb_grain is
-- some testvectors:
constant GRAIN_KEY1 : unsigned(79 downto 0) := (others => '0');
constant GRAIN_IV1 : unsigned(63 downto 0) := (others => '0');
constant GRAIN_KS1 : unsigned(79 downto 0) := x"7b978cf36846e5f4ee0b";
constant GRAIN_KEY2 : unsigned(79 downto 0) := x"0123456789abcdef1234";
constant GRAIN_IV2 : unsigned(63 downto 0) := x"0123456789abcdef";
constant GRAIN_KS2 : unsigned(79 downto 0) := x"42b567ccc65317680225";
-- DUT signal
signal clk, clken, areset : std_logic;
signal key_in, iv_in : std_logic;
signal key : unsigned(79 downto 0);
signal iv : unsigned(63 downto 0);
signal init, keystream, keystream_valid : std_logic;
-- monitor the output:
signal key_memory : unsigned(79 downto 0);
signal key_count : integer := 0;
begin
-- the one and only, the DUT
DUT: entity work.grain
generic map (
DEBUG => DEBUG,
FAST => FAST
)
port map (
CLK_I => clk,
CLKEN_I => clken,
ARESET_I => areset,
KEY_I => key_in,
IV_I => iv_in,
INIT_I => init,
KEYSTREAM_O => keystream,
KEYSTREAM_VALID_O => keystream_valid
);
-- clock generator:
clkgen_proc: process
begin
clk <= '0'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
end process;
-- dummy clock enable: every fourth cycle
clken_proc: process
begin
clken <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
clken <= '1';
wait until rising_edge(clk);
end process;
-- output monitor:
mon_proc: process(clk, areset)
begin
if areset = '1' then
key_memory <= (others => 'X');
key_count <= 0;
elsif rising_edge(clk) then
if clken = '1' then
if keystream_valid = '1' then
key_count <= key_count + 1;
key_memory <= key_memory(key_memory'high-1 downto 0) & keystream;
else
key_memory <= (others => 'X');
key_count <= 0;
end if;
end if;
end if;
end process;
-- this process will do all the testing
tester_proc: process
-- reset everything
procedure do_reset is
begin
key_in <= 'X';
iv_in <= 'X';
init <= '0';
areset <= '1';
wait for 100 ns;
areset <= '0';
end procedure;
-- initialize grain with key and IV
procedure do_init is
begin
wait until rising_edge(clk) and clken = '1';
init <= '1';
wait until rising_edge(clk) and clken = '1';
init <= '0';
for i in key'range loop
key_in <= key(key'high);
iv_in <= iv(iv'high);
key <= key rol 1;
iv <= iv rol 1;
wait until rising_edge(clk) and clken = '1';
end loop;
key_in <= 'X';
iv_in <= 'X';
end procedure;
begin
-- 1. start with a reset:
do_reset;
-- 2. inject key and IV
key <= GRAIN_KEY1;
iv <= GRAIN_IV1;
do_init;
-- 3. verify output:
wait on clk until key_count = 80;
assert key_memory = GRAIN_KS1
report "incorrect output with IV = 0 and KEY = 0"
severity failure;
-- 4. try the other testvector
key <= GRAIN_KEY2;
iv <= GRAIN_IV2;
do_init;
wait on clk until key_count = 80;
assert
key_memory = GRAIN_KS2
report "incorrect output with IV = 0123.. and KEY = 0123.."
severity failure;
-- done:
report "ALL DONE" severity failure;
wait;
end process;
end test;
-- asim -g/FAST=false tb_grain ; wave /DUT/* ; run 100 us
-- asim -g/FAST=true tb_grain ; wave /DUT/* ; run 100 us
| lgpl-3.0 | f04957b929b6d45fb2dd7737765610e3 | 0.606648 | 2.897271 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/integration_task/tb_integrazione_task.vhd | 1 | 9,687 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Scognamiglio, Riccio, Sorrentino
--
-- Create Date: 17.07.2017 16:56:47
-- Design Name:
-- Module Name: tb_integrazione_task - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
use std.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_integrazione_task is
end tb_integrazione_task;
architecture Behavioral of tb_integrazione_task is
component integrazione_task is
Generic ( campione : natural := 20460;
doppler : natural := 11;
satellite : natural := 10);
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
poff_pinc : in STD_LOGIC_VECTOR (47 downto 0);
dds_out : out STD_LOGIC_VECTOR (31 downto 0); --DA TOGLIERE
dds_done : out STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC;
fft1_in : in STD_LOGIC_VECTOR(31 downto 0);
fft1_ready_out : out STD_LOGIC;
fft1_valid_in : in STD_LOGIC;
ifft_out : out STD_LOGIC_VECTOR (31 downto 0); --DA TOGLIERE
fft1_out : out STD_LOGIC_VECTOR (31 downto 0); --DA TOGLIERE
fft2_out : out STD_LOGIC_VECTOR (31 downto 0); --DA TOGLIERE
pos_campione : out STD_LOGIC_VECTOR (natural(ceil(log2(real(campione))))-1 downto 0);
pos_doppler : out STD_LOGIC_VECTOR (natural(ceil(log2(real(doppler))))-1 downto 0);
pos_satellite : out STD_LOGIC_VECTOR (natural(ceil(log2(real(satellite))))-1 downto 0);
sample_max : out STD_LOGIC_VECTOR (31 downto 0);
max : out STD_LOGIC_VECTOR (31 downto 0));
end component integrazione_task;
--!Constants
constant campione : natural:= 8;
constant doppler : natural:= 11;
constant satellite : natural:= 10;
constant clock_period : time := 100 ns;
--!Signal
signal clock : std_logic := '0';
signal reset_n : std_logic := '0';
signal valid_in : std_logic := '0';
signal valid_out : std_logic := '0';
signal ready_in : std_logic := '0';
signal ready_out : std_logic := '0';
signal dds_done : std_logic := '0';
signal fft1_ready_out : std_logic := '0';
signal fft1_valid_in : std_logic := '0';
signal fft1_in : std_logic_vector(31 downto 0) := (others => '0');
signal ifft_out : std_logic_vector(31 downto 0) := (others => '0');
signal poff_pinc : std_logic_vector(47 downto 0) := (others => '0');
signal dds_out : std_logic_vector(31 downto 0) := (others => '0');
signal fft1_out : std_logic_vector(31 downto 0) := (others => '0');
signal fft2_out : std_logic_vector(31 downto 0) := (others => '0');
signal sample_max : std_logic_vector(31 downto 0) := (others => '0');
signal max : std_logic_vector(31 downto 0) := (others => '0');
signal pos_campione : std_logic_vector(natural(ceil(log2(real(campione))))-1 downto 0) := (others => '0');
signal pos_doppler : std_logic_vector(natural(ceil(log2(real(doppler))))-1 downto 0) := (others => '0');
signal pos_satellite : std_logic_vector(natural(ceil(log2(real(satellite))))-1 downto 0) := (others => '0');
--SEGNALI PER LA SCRITTURA SUL FILE
signal file_sig1_out : bit_vector(31 downto 0);
signal file_sig2_out : bit_vector(31 downto 0);
signal file_ifft_out : bit_vector(31 downto 0);
signal linenumber : integer:= 1;
signal endoffile : bit := '0';
signal fft1_out_sig : std_logic_vector(31 downto 0) := (others => '0');
signal fft2_out_sig : std_logic_vector(31 downto 0) := (others => '0');
signal ifft_out_sig : std_logic_vector(31 downto 0) := (others => '0');
begin
ifft_out <= ifft_out_sig;
fft1_out <= fft1_out_sig;
fft2_out <= fft2_out_sig;
uut: integrazione_task
Generic map ( campione => campione,
doppler => doppler,
satellite => satellite )
Port map ( clock => clock,
reset_n => reset_n,
poff_pinc => poff_pinc,
valid_in => valid_in,
ready_in => ready_in,
valid_out => valid_out,
ready_out => ready_out,
fft1_in => fft1_in,
fft1_ready_out => fft1_ready_out,
fft1_valid_in => fft1_valid_in,
dds_out => dds_out,
dds_done => dds_done,
fft1_out => fft1_out_sig,
fft2_out => fft2_out_sig,
ifft_out => ifft_out_sig,
pos_campione => pos_campione,
pos_doppler => pos_doppler,
pos_satellite => pos_satellite,
sample_max => sample_max,
max => max);
clock_process: process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
fft1_input_process: process(clock,fft1_ready_out)
begin
if(rising_edge(clock))then
if(fft1_ready_out = '1')then
fft1_in <= fft1_in + 1;
fft1_valid_in <= '1';
else
fft1_valid_in <= '0';
end if;
end if;
end process;
stimoli: process
begin
wait for clock_period*10;
reset_n <= '1';
ready_in <= '0';
for i in 0 to satellite-1 loop
--!PRIMA DOPPLER
valid_in <= '1';
poff_pinc <= x"A00000FFF597";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!SECONDA DOPPLER
valid_in <= '1';
poff_pinc <= x"500000FFF797";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!TERZA DOPPLER
valid_in <= '1';
poff_pinc <= x"000000FFF998";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!QUARTA DOPPLER
valid_in <= '1';
poff_pinc <= x"B00000FFFB98";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!QUINTA DOPPLER
valid_in <= '1';
poff_pinc <= x"600000FFFD99";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!SESTA DOPPLER
valid_in <= '1';
poff_pinc <= x"100000FFFF99";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!SETTIMA DOPPLER
valid_in <= '1';
poff_pinc <= x"C0000000019A";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!OTTAVA DOPPLER
valid_in <= '1';
poff_pinc <= x"70000000039B";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!NONA DOPPLER
valid_in <= '1';
poff_pinc <= x"20000000059B";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!DECIMA DOPPLER
valid_in <= '1';
poff_pinc <= x"D0000000079C";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
--!UNDICESIMA DOPPLER
valid_in <= '1';
poff_pinc <= x"80000000099C";
wait for clock_period;
valid_in <= '0';
wait until dds_done = '1';
wait for clock_period*10;
end loop;
wait;
end process;
--SCRITTURA SUL FILE
file_sig1_out <= to_bitvector(fft1_out_sig);
file_sig2_out <= to_bitvector(fft2_out_sig);
file_ifft_out <= to_bitvector(ifft_out_sig);
--write process
writing : process
file outfilesig1 : text is out "fft1_out.txt";
file outfilesig2 : text is out "fft2_out.txt";
file outfileifft : text is out "ifft_out.txt";
variable outlinesig1 : line;
variable outlinesig2 : line;
variable outlineifft : line;
begin
wait until falling_edge(clock);
if(endoffile='0') then --if the file end is not reached.
--write(linenumber,value(real type),justified(side),field(width),digits(natural));
write(outlinesig1,file_sig1_out,right,32);
writeline(outfilesig1, outlinesig1);
write(outlinesig2,file_sig2_out,right,32);
writeline(outfilesig2, outlinesig2);
write(outlineifft,file_ifft_out,right,32);
writeline(outfileifft, outlineifft);
linenumber <= linenumber + 1;
end if;
end process writing;
end Behavioral;
| gpl-2.0 | d67552c39ed2bdc553cd4c2fbcccdc4f | 0.545886 | 3.448558 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/moltiplicatore_booth/register_n_bit.vhd | 1 | 1,397 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:03:04 11/07/2015
-- Design Name:
-- Module Name: register_n_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity register_n_bit is
generic (n : natural := 8;
delay : time := 0 ns);
Port ( I : in STD_LOGIC_VECTOR (n-1 downto 0);
clock : in STD_LOGIC;
load : in STD_LOGIC;
reset_n : in STD_LOGIC;
O : out STD_LOGIC_VECTOR (n-1 downto 0));
end register_n_bit;
architecture Behavioral of register_n_bit is
begin
process (clock, load, reset_n)
begin
if (reset_n = '0') then
O <= (others => '0');
elsif (clock = '1' and rising_edge(clock)) then
if (load = '1') then
O <= I after delay;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | e0e8e2f781a8c7c300fa262925e41543 | 0.569792 | 3.59126 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/compute_max/wrapper_compute_max.vhd | 1 | 8,558 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2017 16:26:02
-- Design Name:
-- Module Name: wrapper_compute_max - Structural
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--! @file wrapper_compute_max.vhd
--! @author Antonio Riccio, Andrea Scognamiglio, Stefano Sorrentino
--! @brief Wrapper di @ref compute_max che fornisce funzioni di comunicazione
--! @anchor wrapper_compute_max
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--! @brief Wrapper per l'entità @ref compute_max
--! @details Questo componente arricchisce il modulo @ref compute_max con funzionalità
--! di comunicazione. Queste funzionalità sono necessarie per il collegamento del
--! blocco con altri componenti.
entity wrapper_compute_max is
Generic ( sample_width : natural := 32; --! Parallelismo in bit del campione
s : natural := 2; --! Numero di satelliti
d : natural := 2; --! Numero di intervalli doppler
c : natural := 3); --! Numero di campioni per intervallo doppler
Port ( clock : in STD_LOGIC; --! Segnale di temporizzazione
reset_n : in STD_LOGIC; --! Segnale di reset 0-attivo
valid_in : in STD_LOGIC; --! Indica che il dato sulla linea di ingresso è valido
ready_in : in STD_LOGIC; --! Indica che il componente a valle è pronto ad accettare valori in ingresso
sample_abs : in STD_LOGIC_VECTOR (sample_width-1 downto 0);
sample : in STD_LOGIC_VECTOR (sample_width-1 downto 0);
pos_campione : out STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0); --! Posizione del massimo nell'intervallo doppler
pos_doppler : out STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0); --! Intervallo di frequenze doppler al quale appartiene il massimo
pos_satellite : out STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0); --! Satellite associato al massimo
max : out STD_LOGIC_VECTOR (sample_width-1 downto 0); --! Modulo del massimo
sample_max : out STD_LOGIC_VECTOR(sample_width-1 downto 0); --! Valore complesso del massimo
valid_out : out STD_LOGIC; --! Indica che il dato sulla linea di uscita è valido
ready_out : out STD_LOGIC); --! Indica che questo componente è pronto ad accettare valori in ingresso
end wrapper_compute_max;
--! @brief Architettura del componente descritta nel dominio strutturale
architecture Structural of wrapper_compute_max is
--! @brief Registro a parallelismo generico che opera sul fronte di salita del clock
component register_n_bit is
generic (
n : natural := 8
);
port (
I : in STD_LOGIC_VECTOR (n-1 downto 0);
clock : in STD_LOGIC;
load : in STD_LOGIC;
reset_n : in STD_LOGIC;
O : out STD_LOGIC_VECTOR (n-1 downto 0)
);
end component register_n_bit;
--! @brief Calcola il massimo per un insieme di s*d*c campioni\
--! @see compute_max
component compute_max is
generic (
sample_width : natural := 32;
s : natural := 2;
d : natural := 2;
c : natural := 3
);
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
enable : in STD_LOGIC;
sample_abs : in STD_LOGIC_VECTOR (sample_width-1 downto 0);
sample : in STD_LOGIC_VECTOR(sample_width-1 downto 0);
pos_campione : out STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0);
pos_doppler : out STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0);
pos_satellite : out STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0);
max : out STD_LOGIC_VECTOR (sample_width-1 downto 0);
sample_max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
done : out STD_LOGIC
);
end component compute_max;
--! @brief Parte di controllo di questo blocco
component fsm_compute_max is
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
max_done : in STD_LOGIC;
start : out STD_LOGIC;
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC;
reset_n_all : out STD_LOGIC
);
end component fsm_compute_max;
-- for all : compute_max use entity work.compute_max(Behavioral);
for all : compute_max use entity work.compute_max(Structural_non_continous);
signal max_done, start, reset_n_all_sig : std_logic := '0';
signal max_sig : std_logic_vector(sample_width-1 downto 0) := (others => '0');
signal sample_max_sig : std_logic_vector(sample_width-1 downto 0) := (others => '0');
signal pos_campione_sig : std_logic_vector(natural(ceil(log2(real(c))))-1 downto 0) := (others => '0');
signal pos_doppler_sig : std_logic_vector(natural(ceil(log2(real(d))))-1 downto 0) := (others => '0');
signal pos_satellite_sig : std_logic_vector(natural(ceil(log2(real(s))))-1 downto 0) := (others => '0');
begin
--! @brief Componente che calcola il massimo sui moduli dei campioni in ingresso
compute_max_inst: compute_max
generic map (
sample_width => sample_width,
s => s,
d => d,
c => c
)
port map (
clock => clock,
reset_n => reset_n_all_sig,
enable => start,
sample_abs => sample_abs,
sample => sample,
pos_campione => pos_campione_sig,
pos_doppler => pos_doppler_sig,
pos_satellite => pos_satellite_sig,
max => max_sig,
sample_max => sample_max_sig,
done => max_done
);
--! @brief Automa a stati finiti per la gestione dei segnali di comunicazione
fsm_compute_max_inst: fsm_compute_max
port map (
clock => clock,
reset_n => reset_n,
valid_in => valid_in,
ready_in => ready_in,
max_done => max_done,
start => start,
valid_out => valid_out,
ready_out => ready_out,
reset_n_all => reset_n_all_sig
);
--! @brief Memorizza il massimo (in valore assoluto) ottenuto dal blocco compute_max
--! @details Questo registro è necessario per memorizzare il risultato(max) di compute_max
--! dato che il componente si resetta dopo che ha terminato l'elaborazione.
reg_max: register_n_bit
generic map (
n => sample_width
)
port map (
I => max_sig,
clock => clock,
load => max_done,
reset_n => reset_n,
O => max
);
--! @brief Memorizza il massimo campione ottenuto dal blocco compute_max
--! @details Questo registro è necessario per memorizzare il risultato(sample_max) di compute_max
--! dato che il componente si resetta dopo che ha terminato l'elaborazione.
reg_sample_max: register_n_bit
generic map (
n => sample_width
)
port map (
I => sample_max_sig,
clock => clock,
load => max_done,
reset_n => reset_n,
O => sample_max
);
--! @brief Memorizza la pos_campione del risultato ottenuto dal blocco compute_max
--! @details Questo registro è necessario per memorizzare pos_campione di compute_max
--! dato che il componente si resetta dopo che ha terminato l'elaborazione.
reg_pos_campione: register_n_bit
generic map (
n => natural(ceil(log2(real(c))))
)
port map (
I => pos_campione_sig,
clock => clock,
load => max_done,
reset_n => reset_n,
O => pos_campione
);
--! @brief Memorizza la pos_doppler del risultato ottenuto dal blocco compute_max
--! @details Questo registro è necessario per memorizzare pos_doppler di compute_max
--! dato che il componente si resetta dopo che ha terminato l'elaborazione.
reg_pos_doppler: register_n_bit
generic map (
n => natural(ceil(log2(real(d))))
)
port map (
I => pos_doppler_sig,
clock => clock,
load => max_done,
reset_n => reset_n,
O => pos_doppler
);
--! @brief Memorizza la pos_satellite del risultato ottenuto dal blocco compute_max
--! @details Questo registro è necessario per memorizzare pos_satellite di compute_max
--! dato che il componente si resetta dopo che ha terminato l'elaborazione.
reg_pos_satellite: register_n_bit
generic map (
n => natural(ceil(log2(real(s))))
)
port map (
I => pos_satellite_sig,
clock => clock,
load => max_done,
reset_n => reset_n,
O => pos_satellite
);
end Structural;
| gpl-2.0 | f94824cb343ab3df5a74727c27664a14 | 0.663351 | 3.235895 | false | false | false | false |
Subsets and Splits