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imr/Mandelbrot-VHDL | src/VGA.vhd | 1 | 1,917 | -- Ian Roth
-- ECE 8455
-- VGA module, final project
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY VGA IS
PORT(
VGA_CLK, VGA_BLANK_N, VGA_HS, VGA_VS, start :OUT STD_LOGIC;
clk, rst :IN STD_LOGIC
);
END ENTITY VGA;
ARCHITECTURE Behavior OF VGA IS
SIGNAL Hcount :UNSIGNED(10 downto 0);
SIGNAL Vcount :UNSIGNED(10 downto 0);
SIGNAL int_hs, int_vs :STD_LOGIC;
CONSTANT Hactive :UNSIGNED(10 downto 0) := "10000000000"; -- 1024
CONSTANT Hsyncs :UNSIGNED(10 downto 0) := "10000011001"; -- 1048 = 1024 + 24 (+1)
CONSTANT Hsynce :UNSIGNED(10 downto 0) := "10010100001"; -- 1184 = 1024 + 24 + 136 (+1)
CONSTANT Htotal :UNSIGNED(10 downto 0) := "10101000000"; -- 1344
CONSTANT Vactive :UNSIGNED(9 downto 0) := "1100000000"; -- 768
CONSTANT Vsysns :UNSIGNED(9 downto 0) := "1100000011"; -- 768 + 3 (+1)
CONSTANT Vsynce :UNSIGNED(9 downto 0) := "1100001001"; -- 768 + 3 + 6 (+1)
CONSTANT Vtotal :UNSIGNED(9 downto 0) := "1100100110"; -- 806
BEGIN
VGA_CLK <= NOT clk;
start <= (NOT int_hs) AND (NOT int_vs);
VGA_HS <= int_hs;
VGA_VS <= int_vs;
PROCESS(clk, rst)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (rst = '1') THEN
Hcount <= "00000000000";
Vcount <= "00000000000";
int_hs <= '1';
int_vs <= '1';
ELSE
IF (Hcount < Htotal) THEN
Hcount <= Hcount + 1;
ELSE
Hcount <= "00000000000";
END IF;
IF (Hcount = Hsyncs) THEN
int_hs <= '0';
END IF;
IF (Hcount = Hsynce) THEN
int_hs <= '1';
IF (Vcount < Vtotal) THEN
Vcount <= Vcount + 1;
ELSE
Vcount <= "00000000000";
END IF;
END IF;
IF (Vcount = Vsysns) THEN
int_vs <= '0';
END IF;
IF (Vcount = Vsynce) THEN
int_vs <= '1';
END IF;
IF ((Hcount < Hactive) AND (Vcount < Vactive)) THEN
VGA_BLANK_N <= '1';
ELSE
VGA_BLANK_N <= '0';
END IF;
END IF;
END IF;
END PROCESS;
END Behavior; | bsd-3-clause | 076420b1558566a6aaa7f38519da869c | 0.597809 | 2.79854 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/moltiplicatore_booth/shift_register_n_bit.vhd | 1 | 2,269 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:01:51 11/08/2015
-- Design Name:
-- Module Name: shift_register_n_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_register_n_bit is
generic (n : natural := 8;
delay : time := 0 ns);
Port ( D_IN : in STD_LOGIC_VECTOR (n-1 downto 0);
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
load : in STD_LOGIC;
shift : in STD_LOGIC;
lt_rt : in STD_LOGIC;
sh_in : in STD_LOGIC;
sh_out : out STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (n-1 downto 0));
end shift_register_n_bit;
architecture Behavioral of shift_register_n_bit is
signal pre_o : STD_LOGIC_VECTOR (n-1 downto 0);
begin
process (clock, reset_n)
--variable pre_o : STD_LOGIC_VECTOR (n-1 downto 0);
begin
if (reset_n = '0') then
pre_o <= (others => '0');
-- pre_o := (others => '0');
sh_out <= '0';
elsif (clock = '1' and clock'event) then
if (load = '1') then
pre_o <= D_IN;
-- pre_o := D_IN;
elsif(shift = '1') then
if (lt_rt = '0') then
pre_o <= pre_o (n-2 downto 0) & sh_in;
-- pre_o := pre_o (n-2 downto 0) & sh_in;
elsif(lt_rt = '1') then
pre_o <= sh_in & pre_o (n-1 downto 1);
-- pre_o := sh_in & pre_o (n-1 downto 1);
end if;
end if;
-- sia che faccio load che shift devo aggiornare sh_out al suo valore reale
if(lt_rt = '0') then
sh_out <= pre_o(n-1);
elsif(lt_rt = '1') then
sh_out <= pre_o(0);
end if;
end if;
--D_OUT <= pre_o;
end process;
-- MI ESCE X CON QSTA ASSEGNAZIONE
--sh_out <= pre_o(n-1) when (lt_rt = '0') else
-- pre_o(0);
D_OUT <= pre_o;
end Behavioral; | gpl-2.0 | e1a5cbb0e64225681dcce4bc4874bdb6 | 0.560159 | 2.8831 | false | false | false | false |
Xion345/fpga-projects | library/block_ram/block_ram.vhd | 1 | 1,633 | -- Single clock - Dual port block RAM
-- Heavily inspired from
-- http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity block_ram is
generic(
DATA_WIDTH: integer := 8;
ADDR_WIDTH: integer := 10
);
port(
clk: in std_logic;
-- Port A
wr_a: in std_logic;
addr_a: in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_in_a: in std_logic_vector(DATA_WIDTH-1 downto 0);
data_out_a: out std_logic_vector(DATA_WIDTH-1 downto 0);
-- Port B
wr_b: in std_logic;
addr_b: in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_in_b: in std_logic_vector(DATA_WIDTH-1 downto 0);
data_out_b: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end block_ram;
architecture block_ram_arch of block_ram is
-- Shared memory
type mem_type is array ((2**ADDR_WIDTH)-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
shared variable mem : mem_type;
begin
-- Port A
process(clk)
begin
if(rising_edge(clk)) then
if(wr_a = '1') then
mem(conv_integer(addr_a)) := data_in_a;
end if;
data_out_a <= mem(conv_integer(addr_a));
end if;
end process;
-- Port B
process(clk)
begin
if(rising_edge(clk)) then
if(wr_b = '1') then
mem(conv_integer(addr_b)) := data_in_b;
end if;
data_out_b <= mem(conv_integer(addr_b));
end if;
end process;
end block_ram_arch;
| mit | f9a4772e8d7d244cfa2272a2f5f62228 | 0.562156 | 3.246521 | false | false | false | false |
shio-phys/SPI-FLASH-Programmer | fpga/SPI_IF.vhd | 1 | 3,643 | --------------------------------------------------------------------------------
--! @file SPI_IF.vhd
--! @brief SPI interface to SPI Flash ROM
--! @author Takehiro Shiozaki
--! @date 2014-06-24
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SPI_IF is
port(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
START : in std_logic;
BUSY : out std_logic;
SPI_SCLK : out std_logic;
SPI_MISO : in std_logic;
SPI_MOSI : out std_logic
);
end SPI_IF;
architecture RTL of SPI_IF is
signal DinReg : std_logic_vector(7 downto 0);
signal BitSel : std_logic_vector(2 downto 0);
signal BitSelCountDown : std_logic;
signal BitSelCountClear : std_logic;
signal ShiftReg : std_logic_vector(7 downto 0);
signal ShiftRegEnable : std_logic;
signal SpiSclkPre : std_logic;
signal SpiMosiPre : std_logic;
type State is (IDLE, PREPARE, SCLK_LOW, SCLK_HIGH, PAUSE);
signal CurrentState, NextState : State;
begin
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(START = '1') then
DinReg <= DIN;
end if;
end if;
end process;
SpiMosiPre <= DinReg(conv_integer(BitSel));
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(ShiftRegEnable = '1') then
ShiftReg <= ShiftReg(6 downto 0) & SPI_MISO;
end if;
end if;
end process;
DOUT <= ShiftReg;
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(BitSelCountClear = '1') then
BitSel <= (others => '1');
elsif(BitSelCountDown = '1') then
BitSel <= BitSel - 1;
end if;
end if;
end process;
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(RESET = '1') then
CurrentState <= IDLE;
else
CurrentState <= NextState;
end if;
end if;
end process;
process(CurrentState, START, BitSel)
begin
case CurrentState is
when IDLE =>
if(START = '1') then
NextState <= PREPARE;
else
NextState <= CurrentState;
end if;
when PREPARE =>
NextState <= SCLK_LOW;
when SCLK_LOW =>
NextState <= SCLK_HIGH;
when SCLK_HIGH =>
if(BitSel = 0) then
NextState <= PAUSE;
else
NextState <= SCLK_LOW;
end if;
when PAUSE =>
NextState <= IDLE;
end case;
end process;
SpiSclkPre <= '1' when(CurrentState = SCLK_HIGH) else
'0';
ShiftRegEnable <= '1' when(CurrentState = SCLK_HIGH) else
'0';
BitSelCountDown <= '1' when(CurrentState = SCLK_HIGH) else
'0';
BitSelCountClear <= '1' when(CurrentState = IDLE) else
'0';
BUSY <= '1' when(CurrentState /= IDLE) else
'0';
process(CLK)
begin
if(CLK'event and CLK = '1') then
SPI_SCLK <= SpiSclkPre;
end if;
end process;
process(CLK)
begin
if(CLK'event and CLK = '1') then
SPI_MOSI <= SpiMosiPre;
end if;
end process;
end RTL;
| mit | 6e70d73387ea4b1e008ebccee0fa5daa | 0.482569 | 4.236047 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/tb_ipcore_uniti.vhd | 1 | 6,754 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03.07.2017 14:41:37
-- Design Name:
-- Module Name: tb_ipcore_uniti - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.math_real.all;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_ipcore_uniti is
end tb_ipcore_uniti;
architecture Behavioral of tb_ipcore_uniti is
component test_dds_wrapper
generic (
campioni : natural := 20460
);
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
poff_pinc : in STD_LOGIC_VECTOR(47 downto 0);
sine_cosine : out STD_LOGIC_VECTOR(31 downto 0);
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC;
done : out STD_LOGIC
);
end component test_dds_wrapper;
component complex_max
generic (
sample_width : natural := 32;
s : natural := 5;
d : natural := 4;
c : natural := 5
);
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
sample : in STD_LOGIC_VECTOR(sample_width-1 downto 0);
sample_max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
pos_campione : out STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0);
pos_doppler : out STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0);
pos_satellite : out STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0);
max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC
);
end component complex_max;
constant clock_period : time := 200 ns; -- 5 MHz
constant sample_width : natural:= 32;
constant s : natural:= 2;
constant d : natural:= 11;
constant c : natural:= 6;
--Inputs
signal clock : STD_LOGIC := '0';
signal reset_n : STD_LOGIC := '0';
signal valid_in : STD_LOGIC := '0';
signal poff_pinc : STD_LOGIC_VECTOR ( 47 downto 0 );
signal poff : STD_LOGIC_VECTOR (23 downto 0) := (others => '0');
signal pinc : STD_LOGIC_VECTOR (23 downto 0) := (others => '0');
--Outputs
signal sample_max : std_logic_vector(sample_width-1 downto 0);
signal ready_out : STD_LOGIC := '0';
signal done : std_logic;
signal pos_campione : std_logic_vector(natural(ceil(log2(real(c))))-1 downto 0);
signal pos_doppler : std_logic_vector(natural(ceil(log2(real(d))))-1 downto 0);
signal pos_satellite : std_logic_vector(natural(ceil(log2(real(s))))-1 downto 0);
signal max : std_logic_vector(sample_width-1 downto 0);
signal valid_out : STD_lOGIC := '0';
signal complex_max_ready_sig : std_logic;
signal dds_valid_out : std_logic;
signal sample_sig : std_logic_vector(sample_width-1 downto 0);
begin
poff_pinc(47 downto 24) <= poff;
poff_pinc(23 downto 0) <= pinc;
test_dds_wrapper_i : test_dds_wrapper
generic map (
campioni => c
)
port map (
clock => clock,
reset_n => reset_n,
valid_in => valid_in,
ready_in => complex_max_ready_sig,
poff_pinc => poff_pinc,
sine_cosine => sample_sig,
valid_out => dds_valid_out,
ready_out => ready_out,
done => done
);
complex_max_i : complex_max
generic map (
sample_width => sample_width,
s => s,
d => d,
c => c
)
port map (
clock => clock,
reset_n => reset_n,
valid_in => dds_valid_out,
ready_in => '0',
sample => sample_sig,
sample_max => sample_max,
pos_campione => pos_campione,
pos_doppler => pos_doppler,
pos_satellite => pos_satellite,
max => max,
valid_out => valid_out,
ready_out => complex_max_ready_sig
);
clock_process: process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
stimuli: process
begin
--LISTA DOPPLERS
--FFF597
--FFF797
--FFF998
--FFFB98
--FFFD99
--FFFF99
--19A
--39B
--59B
--79C
--99C
wait for clock_period*10;
reset_n <= '1';
ciclo_satelliti : for i in 0 to s-1 loop
--PRIMA DOPPLER
poff <= x"000000";
pinc <= x"FFF597";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--SECONDA DOPPLER
poff <= x"000000";
pinc <= x"FFF797";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--TERZA DOPPLER
poff <= x"000FFF";
pinc <= x"FFF998";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--QUARTA DOPPLER
poff <= x"FFF000";
pinc <= x"FFFB98";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--QUINTA DOPPLER
poff <= x"0F0F0F";
pinc <= x"FFFD99";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--SESTA DOPPLER (che presenta il massimo)
poff <= x"F0F0F0";
--poff <= x"00000F";
pinc <= x"FFFF99";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--SETTIMA DOPPLER
poff <= x"FF0000";
pinc <= x"00019A";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--OTTAVA DOPPLER
poff <= x"00FF00";
pinc <= x"00039B";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--NONA DOPPLER
poff <= x"0000DC";
pinc <= x"00059B";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--DECIMA DOPPLER
poff <= x"003400";
pinc <= x"00079C";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
--UNDICESIMA DOPPLER
poff <= x"220000";
pinc <= x"00099C";
valid_in <= '1';
wait for clock_period*2;
valid_in <= '0';
wait until done = '1';
end loop;
wait until valid_out = '1';
-- METTERE QUI L'ASSERT PER LA VERIFICA DEL MAX ASSOLUTO
wait;
end process;
end Behavioral;
| gpl-2.0 | 67963272f3944857d08d1ea4ea44ef70 | 0.579656 | 3.064428 | false | false | false | false |
shio-phys/SPI-FLASH-Programmer | fpga/SPI_FLASH_Programmer.vhd | 1 | 11,279 | --------------------------------------------------------------------------------
--! @file SPI_FLASH_Programmer.vhd
--! @brief Program SPI FLASH via RBCP bus
--! @author Takehiro Shiozaki
--! @date 2014-06-26
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SPI_FLASH_Programmer is
generic(
G_SPI_FLASH_PROGRAMMER_ADDRESS : std_logic_vector(31 downto 0)
:= (others => '0');
G_SITCP_CLK_FREQ : real := 25.0;
G_SPI_CLK_FREQ : real := 66.6
);
port(
SPI_CLK : in std_logic;
SITCP_CLK : in std_logic;
RESET : in std_logic;
RBCP_ACT : in std_logic;
RBCP_ADDR : in std_logic_vector(31 downto 0);
RBCP_WE : in std_logic;
RBCP_WD : in std_logic_vector(7 downto 0);
RBCP_RE : in std_logic;
RBCP_RD : out std_logic_vector(7 downto 0);
RBCP_ACK : out std_logic;
SPI_SCLK : out std_logic;
SPI_SS_N : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic
);
end SPI_FLASH_Programmer;
architecture RTL of SPI_FLASH_Programmer is
component SPI_CommandSender is
port(
CLK : in std_logic;
RESET : in std_logic;
START : in std_logic;
BUSY : out std_logic;
LENGTH : in std_logic_vector(12 downto 0);
WE : out std_logic;
DOUT : out std_logic_vector(7 downto 0);
WADDR : out std_logic_vector(12 downto 0);
DIN : in std_logic_vector(7 downto 0);
RADDR : out std_logic_vector(8 downto 0);
SPI_SCLK : out std_logic;
SPI_SS_N : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic
);
end component;
component RBCP_Sender is
generic(
G_ADDR : std_logic_vector(31 downto 0);
G_LEN : integer;
G_ADDR_WIDTH : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- RBCP interface
RBCP_ACT : in std_logic;
RBCP_ADDR : in std_logic_vector(31 downto 0);
RBCP_RE : in std_logic;
RBCP_RD : out std_logic_vector(7 downto 0);
RBCP_ACK : out std_logic;
-- SRAM interface
ADDR : out std_logic_vector(G_ADDR_WIDTH - 1 downto 0);
RD : in std_logic_vector(7 downto 0)
);
end component;
component RBCP_Receiver is
generic(
G_ADDR : std_logic_vector(31 downto 0);
G_LEN : integer;
G_ADDR_WIDTH : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- RBCP interface
RBCP_ACT : in std_logic;
RBCP_ADDR : in std_logic_vector(31 downto 0);
RBCP_WE : in std_logic;
RBCP_WD : in std_logic_vector(7 downto 0);
RBCP_ACK : out std_logic;
-- output
ADDR : out std_logic_vector(G_ADDR_WIDTH - 1 downto 0);
WE : out std_logic;
WD : out std_logic_vector(7 downto 0)
);
end component;
component DualPortRam is
generic(
G_WIDTH : integer;
G_DEPTH : integer
);
port(
-- write
WCLK : in std_logic;
DIN : in std_logic_vector(G_WIDTH - 1 downto 0);
WADDR : in std_logic_vector(G_DEPTH - 1 downto 0);
WE : in std_logic;
-- read
RCLK : in std_logic;
DOUT : out std_logic_vector(G_WIDTH - 1 downto 0);
RADDR : in std_logic_vector(G_DEPTH - 1 downto 0)
);
end component;
component Synchronizer is
port(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic;
DOUT : out std_logic
);
end component;
component SynchEdgeDetector is
port(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic;
DOUT : out std_logic
);
end component;
component SynchronizerNbit is
generic(
G_BITS : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(G_BITS - 1 downto 0);
DOUT : out std_logic_vector(G_BITS - 1 downto 0)
);
end component;
component PulseExtender is
generic(
G_WIDTH : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic;
DOUT : out std_logic
);
end component;
signal CommandSenderStart : std_logic;
signal CommandSenderBusy : std_logic;
signal CommandSenderLength : std_logic_vector(12 downto 0);
signal WriteBufDout : std_logic_vector(7 downto 0);
signal WriteBufRaddr : std_logic_vector(8 downto 0);
signal WriteBufDin : std_logic_vector(7 downto 0);
signal WriteBufWaddr : std_logic_vector(8 downto 0);
signal WriteBufWe : std_logic;
signal ReadBufDout : std_logic_vector(7 downto 0);
signal ReadBufRaddr : std_logic_vector(12 downto 0);
signal ReadBufDin : std_logic_vector(7 downto 0);
signal ReadBufWaddr : std_logic_vector(12 downto 0);
signal ReadBufWe : std_logic;
signal RbcpRdSender : std_logic_vector(7 downto 0);
signal RbcpRdStatusRegister : std_logic_vector(7 downto 0);
signal RbcpAckSender : std_logic;
signal RbcpAckReceiver : std_logic;
signal RbcpAckWriteStatusRegister : std_logic;
signal RbcpAckReadStatusRegister : std_logic;
signal RbcpAckLength : std_logic;
signal RbcpAddressLength : std_logic_vector(0 downto 0);
signal RbcpWeLength : std_logic;
signal RbcpWdLength : std_logic_vector(7 downto 0);
signal CommandSenderStartPre : std_logic;
signal CommandSenderStartPreExpanded : std_logic;
signal SynchCommandSenderBusy : std_logic;
signal RbcpAckReadStatusRegisterPre : std_logic;
signal LengthReg : std_logic_vector(12 downto 0);
begin
SPI_CommandSender_0: SPI_CommandSender
port map(
CLK => SPI_CLK,
RESET => RESET,
START => CommandSenderStart,
BUSY => CommandSenderBusy,
LENGTH => CommandSenderLength,
WE => ReadBufWe,
DOUT => ReadBufDin,
WADDR => ReadBufWaddr,
DIN => WriteBufDout,
RADDR => WriteBufRaddr,
SPI_SCLK => SPI_SCLK,
SPI_SS_N => SPI_SS_N,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO
);
RBCP_Sender_0: RBCP_Sender
generic map(
G_ADDR => G_SPI_FLASH_PROGRAMMER_ADDRESS + 3,
G_LEN => 8192,
G_ADDR_WIDTH => 13
)
port map(
CLK => SITCP_CLK,
RESET => RESET,
RBCP_ACT => RBCP_ACT,
RBCP_ADDR => RBCP_ADDR,
RBCP_RE => RBCP_RE,
RBCP_RD => RbcpRdSender,
RBCP_ACK => RbcpAckSender,
ADDR => ReadBufRaddr,
RD => ReadBufDout
);
RBCP_Receiver_0: RBCP_Receiver
generic map(
G_ADDR => G_SPI_FLASH_PROGRAMMER_ADDRESS + 3,
G_LEN => 512,
G_ADDR_WIDTH => 9
)
port map(
CLK => SITCP_CLK,
RESET => RESET,
RBCP_ACT => RBCP_ACT,
RBCP_ADDR => RBCP_ADDR,
RBCP_WE => RBCP_WE,
RBCP_WD => RBCP_WD,
RBCP_ACK => RbcpAckReceiver,
ADDR => WriteBufWaddr,
WE => WriteBufWe,
WD => WriteBufDin
);
ReadBuf: DualPortRam
generic map(
G_WIDTH => 8,
G_DEPTH => 13
)
port map(
WCLK => SPI_CLK,
DIN => ReadBufDin,
WADDR => ReadBufWaddr,
WE => ReadBufWe,
RCLK => SITCP_CLK,
DOUT => ReadBufDout,
RADDR => ReadBufRaddr
);
WriteBuf: DualPortRam
generic map(
G_WIDTH => 8,
G_DEPTH => 9
)
port map(
WCLK => SITCP_CLK,
DIN => WriteBufDin,
WADDR => WriteBufWaddr,
WE => WriteBufWe,
RCLK => SPI_CLK,
DOUT => WriteBufDout,
RADDR => WriteBufRaddr
);
CommandSenderStartPre <= '1' when(RBCP_ACT = '1' and RBCP_WE = '1' and
RBCP_WD = X"00" and
RBCP_ADDR = G_SPI_FLASH_PROGRAMMER_ADDRESS) else
'0';
process(SITCP_CLK)
begin
if(SITCP_CLK'event and SITCP_CLK = '1') then
RbcpAckWriteStatusRegister <= CommandSenderStartPre;
end if;
end process;
PulseExtender_CommandStart: PulseExtender
generic map(
G_WIDTH => integer(2.0 * G_SITCP_CLK_FREQ / G_SPI_CLK_FREQ + 1.0)
)
port map(
CLK => SITCP_CLK,
RESET => RESET,
DIN => CommandSenderStartPre,
DOUT => CommandSenderStartPreExpanded
);
SynchEdgeDetector_CommandSenderStart: SynchEdgeDetector
port map(
CLK => SPI_CLK,
RESET => RESET,
DIN => CommandSenderStartPreExpanded,
DOUT => CommandSenderStart
);
Synchronizer_CommandSenderBusy: Synchronizer
port map(
CLK => SITCP_CLK,
RESET => RESET,
DIN => CommandSenderBusy,
DOUT => SynchCommandSenderBusy
);
RbcpRdStatusRegister <= "0000000" & SynchCommandSenderBusy;
RbcpAckReadStatusRegisterPre <= '1' when(RBCP_ACT = '1' and RBCP_RE = '1' and
RBCP_ADDR = G_SPI_FLASH_PROGRAMMER_ADDRESS) else
'0';
process(SITCP_CLK)
begin
if(SITCP_CLK'event and SITCP_CLK = '1') then
RbcpAckReadStatusRegister <= RbcpAckReadStatusRegisterPre;
end if;
end process;
RBCP_Receiver_Length: RBCP_Receiver
generic map(
G_ADDR => G_SPI_FLASH_PROGRAMMER_ADDRESS + 1,
G_LEN => 2,
G_ADDR_WIDTH => 1
)
port map(
CLK => SITCP_CLK,
RESET => RESET,
RBCP_ACT => RBCP_ACT,
RBCP_ADDR => RBCP_ADDR,
RBCP_WE => RBCP_WE,
RBCP_WD => RBCP_WD,
RBCP_ACK => RbcpAckLength,
ADDR => RbcpAddressLength,
WE => RbcpWeLength,
WD => RbcpWdLength
);
process(SITCP_CLK)
begin
if(SITCP_CLK'event and SITCP_CLK = '1') then
if(RbcpWeLength = '1') then
if(RbcpAddressLength(0) = '0') then
LengthReg(12 downto 8) <= RbcpWdLength(4 downto 0);
else
LengthReg(7 downto 0) <= RbcpWdLength;
end if;
end if;
end if;
end process;
SynchronizerNbit_Length: SynchronizerNbit
generic map(
G_BITS => 13
)
port map(
CLK => SPI_CLK,
RESET => RESET,
DIN => LengthReg,
DOUT => CommandSenderLength
);
RBCP_RD <= RbcpRdSender when(RbcpAckSender = '1') else
RbcpRdStatusRegister;
RBCP_ACK <= RbcpAckReceiver or RbcpAckSender or
RbcpAckWriteStatusRegister or RbcpAckReadStatusRegister or
RbcpAckLength;
end RTL;
| mit | 87057648afec22f93efbf32c5c374f00 | 0.532228 | 3.717535 | false | false | false | false |
imr/Mandelbrot-VHDL | src/fixed_pkg_c.vhdl | 2 | 303,381 | -- --------------------------------------------------------------------
-- "fixed_pkg_c.vhdl" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers
-- synthesis tools. Please note the "%%%" comments. These are where we
-- diverge from the VHDL-200X LRM.
-- --------------------------------------------------------------------
-- Version : $Revision: 1.21 $
-- Date : $Date: 2007/09/26 18:08:53 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.fixed_float_types.all;
package fixed_pkg is
-- generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
constant fixed_round_style : fixed_round_style_type := fixed_round;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
constant fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
-- Extra bits used in divide routines
constant fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop ([email protected])
-- base Unsigned fixed point type, downto direction assumed
type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
-- base Signed fixed point type, downto direction assumed
type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
subtype U_ufixed is UNRESOLVED_ufixed;
subtype U_sfixed is UNRESOLVED_sfixed;
subtype ufixed is UNRESOLVED_ufixed;
subtype sfixed is UNRESOLVED_sfixed;
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Absolute value, 2's complement
-- abs sfixed(a downto b) = sfixed(a+1 downto b)
function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Negation, 2's complement
-- - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the binary point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED) return UNRESOLVED_sfixed;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "maximum(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "maximum(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
-- returns arg'low-1 if not found
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
-- returns arg'high+1 if not found
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is fixed_round, then the result will be rounded.
-- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
-- is a '1' or the lower bits of the remainder include a '1' then the result
-- will be increased by the smallest representable number for that type.
-- "overflow_style" can be fixed_saturate or fixed_wrap.
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- "size_res" functions create the size of the output from the indices
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Performs a conversion. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : UNRESOLVED_ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL;
-- Integer to UNRESOLVED_sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed;
-- Conversion from ufixed to sfixed
function to_sfixed (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_sfixed;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to real
function to_real (
arg : UNRESOLVED_sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
--
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_ufixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed;
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_sfixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed;
function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;
function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not convert these vectors because of their negative index.
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- rtl_synthesis off
-- pragma synthesis_off
--===========================================================================
-- string and textio Functions
--===========================================================================
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias bread is READ [LINE, UNRESOLVED_ufixed];
alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias bread is READ [LINE, UNRESOLVED_sfixed];
alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (value : UNRESOLVED_ufixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_ufixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
function to_ostring (value : UNRESOLVED_ufixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
function to_hstring (value : UNRESOLVED_ufixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
function to_string (value : UNRESOLVED_sfixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_sfixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
function to_ostring (value : UNRESOLVED_sfixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
function to_hstring (value : UNRESOLVED_sfixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
end package fixed_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT fixed_pkg package
-- (Fixed point math package)
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 1.21 $
-- Date : $Date: 2007/09/26 18:08:53 $
--
-- Created for VHDL-200X-ft, David Bishop ([email protected])
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
package body fixed_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');
constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
-- %%% Replicated functions
function maximum (
l, r : integer) -- inputs
return integer is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : integer) -- inputs
return integer is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\(LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- Id: M.3B
function \?=\ (L, R: SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function \?/=\ (L, R : SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition, silent
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report fixed_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_sfixed) -- input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_sfixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_ufixed) -- input
return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_ufixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type convert a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_ufixed(arg);
return result;
end function to_fixed;
-- Type convert a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_sfixed(arg);
return result;
end function to_fixed;
-- Type convert a "ufixed" into an "unsigned", used internally
function to_uns (
arg : UNRESOLVED_ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
return slv;
end function to_uns;
-- Type convert an "sfixed" into a "signed", used internally
function to_s (
arg : UNRESOLVED_sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
return slv;
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_ufixed;
result : out UNRESOLVED_ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0)
:= (others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_sfixed;
result : out UNRESOLVED_sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reduce (STD_ULOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : UNRESOLVED_ufixed;
remainder : UNRESOLVED_ufixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : UNRESOLVED_sfixed;
remainder : UNRESOLVED_sfixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- Sign bit not fixed when wrapping
end if;
end if;
return result;
end function round_fixed;
-- converts an sfixed into a ufixed. The output is the same length as the
-- input, because abs("1000") = "1000" = 8.
function to_ufixed (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_ufixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index);
variable result : UNRESOLVED_ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := UNRESOLVED_ufixed (xarg (left_index downto right_index));
return result;
end function to_ufixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- Conversion functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_UFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_SFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
-- Addition
function "+" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto
mine (l'low, l'low) - r'high -1);
variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);
variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto
mine (l'low, l'low) - r'high);
variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);
variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(sfixed) Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
constant one : UNRESOLVED_ufixed (0 downto 0) := "1";
begin
return divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
constant one : UNRESOLVED_sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return remainder (l, r);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return remainder (l, r);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto
mine(l'low, r'low));
variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto
mins(r'low, r'low)-guard_bits);
variable rresize : UNRESOLVED_ufixed (r'high downto r'low-guard_bits);
variable dresult : UNRESOLVED_ufixed (rresize'range);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (rresize'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rresize := resize (arg => r,
left_index => rresize'high,
right_index => rresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
rslv := to_uns (rresize);
if (rslv = 0) then
report fixed_pkg'instance_name
& "remainder(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- can't overflow
round_style => round_style);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto
mine(r'low, l'low));
variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
result := UNRESOLVED_sfixed (remainder (
l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return modulo (l, r);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return modulo(l, r);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style,
guard_bits => guard_bits);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (r'high downto
mine(r'low, l'low));
variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
dresult := "0" & UNRESOLVED_sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED)
return UNRESOLVED_ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED)
return UNRESOLVED_sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-- End reduction operator_reduces
function \?=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
function \?=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
-- compare functions
function "=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw);
variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : NATURAL; -- internal version of arg
begin
if (result'length < 1) then
return NAUF;
end if;
if arg /= 0 then
argx := arg;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := '0';
else
sresult(I) := '1';
end if;
argx := argx/2;
end loop;
if argx /= 0 then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_UFIXED(NATURAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
return saturate (left_index, right_index);
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw);
variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : INTEGER; -- internal version of arg
variable sign : STD_ULOGIC; -- sign of input
begin
if (result'length < 1) then -- null range
return NASF;
end if;
if arg /= 0 then
if (arg < 0) then
sign := '1';
argx := -(arg + 1);
else
sign := '0';
argx := arg;
end if;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := sign;
else
sresult(I) := not sign;
end if;
argx := argx/2;
end loop;
if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_saturate then -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_ufixed (left_index downto
fw-guard_bits) :=
(others => '0');
variable presult : REAL;
-- variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report fixed_pkg'instance_name
& "TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_UFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NAUF;
end if;
result := resize (arg => UNRESOLVED_ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- converted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return UNRESOLVED_ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NASF;
end if;
result := resize (arg => UNRESOLVED_sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- converted version
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return UNRESOLVED_sfixed(xarg);
end function to_sfixed;
function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function to_sfixed;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=
(others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=
(others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_UFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_SFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : UNRESOLVED_ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (ufixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : UNRESOLVED_sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (sfixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := to_ufixed (arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (left_index+1 downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (ufixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (left_index+1 downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (sfixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : UNRESOLVED_ufixed; -- ufixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (s'range); -- result
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(ufixed): null detected, returning NULL"
severity warning;
return NAUF;
end if;
return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);
end function to_01;
function to_01 (
s : UNRESOLVED_sfixed; -- sfixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (s'range);
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(sfixed): null detected, returning NULL"
severity warning;
return NASF;
end if;
return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);
end function to_01;
function Is_X (
arg : UNRESOLVED_ufixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function Is_X (
arg : UNRESOLVED_sfixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function To_X01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_ufixed (arghigh downto arglow);
variable result : UNRESOLVED_ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reduce(to_sulv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style = fixed_saturate and
or_reduce (to_sulv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_sfixed (arghigh downto arglow);
variable result : UNRESOLVED_sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) then
reduced := or_reduce (to_sulv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded math functions for real
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) + r);
end function "+";
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) - r);
end function "-";
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) * r);
end function "*";
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) mod r);
end function "mod";
-- Overloaded math functions for integers
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, 0));
end function "+";
function "+" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, 0));
end function "+";
function "+" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) + r);
end function "+";
-- Overloaded functions
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, 0));
end function "-";
function "-" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, 0));
end function "-";
function "-" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) - r);
end function "-";
-- Overloaded functions
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, 0));
end function "*";
function "*" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, 0));
end function "*";
function "*" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) * r);
end function "*";
-- Overloaded functions
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, 0));
end function "/";
function "/" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, 0));
end function "/";
function "/" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, 0));
end function "rem";
function "rem" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, 0));
end function "rem";
function "rem" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, 0));
end function "mod";
function "mod" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, 0));
end function "mod";
function "mod" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) mod r);
end function "mod";
-- overloaded ufixed compare functions with integer
function "=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- NATURAL to ufixed
function "=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded ufixed compare functions with real
function "=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- real and ufixed
function "=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with integer
function "=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- integer and sfixed
function "=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with real
function "=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- REAL and sfixed
function "=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- rtl_synthesis off
-- pragma synthesis_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- %%% Replicated Textio functions
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-- %%% END replicated textio functions
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : ufixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(ufixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(ufixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(ufixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(ufixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : ufixed (VALUE'range);
variable i : INTEGER; -- index variable
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := value'high;
GOOD := false;
while i >= VALUE'low loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
return;
elsif i /= -1 then -- Seperator in the wrong spot
return;
end if;
founddot := true;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then -- reading done
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : sfixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(sfixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(sfixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(sfixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(sfixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);
begin -- READ
READ (L => L, VALUE => value_ufixed, GOOD => GOOD);
VALUE := UNRESOLVED_sfixed (value_ufixed);
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
-- purpose: Routines common to the OREAD routines
procedure OREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "OREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "OREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2triBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-2) := nybble;
i := i - 3;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
igood := true; -- read into a null array
idex := -1;
end if;
end procedure OREAD_common;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD (L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => false);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: Routines common to the OREAD routines
procedure HREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "HREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "HREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2QuadBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-3) := nybble;
i := i - 4;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
idex := -1;
igood := true; -- read null string
end if;
end procedure HREAD_common;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if igood then
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_ufixed) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable subval : UNRESOLVED_ufixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_string (resize (sfixed(value), 0, value'low));
else
return to_string (resize (value, 0, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_string (value : UNRESOLVED_sfixed) return STRING is
variable s : STRING(1 to value'length + 1) := (others => ' ');
variable subval : UNRESOLVED_sfixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_ostring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_ufixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_ostring (resize (sfixed(value), 2, value'low));
else
return to_ostring (resize (value, 2, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value (value'low));
else
lpad := (others => '0');
end if;
return to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_ufixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_hstring (resize (sfixed(value), 3, value'low));
else
return to_hstring (resize (value, 3, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad);
end if;
end if;
end function to_hstring;
function to_ostring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_sfixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
pad := (others => value(value'high));
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_ostring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_sfixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
pad := (others => value(value'high));
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_hstring(hstring, size_res'high, size_res'low);
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_hstring (hstring, size_res'high, size_res'low);
end function from_hstring;
-- purpose: Calculate the string boundaries
procedure calculate_string_boundry (
arg : in STRING; -- input string
left_index : out INTEGER; -- left
right_index : out INTEGER) is -- right
-- examples "10001.111" would return +4, -3
-- "07X.44" would return +2, -2 (then the octal routine would multiply)
-- "A_B_._C" would return +1, -1 (then the hex routine would multiply)
alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range
variable l, r : INTEGER; -- internal indexes
variable founddot : BOOLEAN := false;
begin
if arg'length > 0 then
l := xarg'high - 1;
r := 0;
for i in xarg'range loop
if xarg(i) = '_' then
if r = 0 then
l := l - 1;
else
r := r + 1;
end if;
elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then
report fixed_pkg'instance_name
& "Found a space in the input STRING " & xarg
severity error;
elsif xarg(i) = '.' then
if founddot then
report fixed_pkg'instance_name
& "Found two binary points in input string " & xarg
severity error;
else
l := l - i;
r := -i + 1;
founddot := true;
end if;
end if;
end loop;
left_index := l;
right_index := r;
else
left_index := 0;
right_index := 0;
end if;
end procedure calculate_string_boundry;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
-- pragma synthesis_on
-- rtl_synthesis on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
begin
return to_UFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
begin
return to_SFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_SFix;
end package body fixed_pkg;
| bsd-3-clause | d5cce31662bca402c0943974c32008d3 | 0.568233 | 3.977672 | false | false | false | false |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/Altera_UP_SD_Card_48_bit_Command_Generator.vhd | 2 | 24,468 | -------------------------------------------------------------------------------------
-- This module takes a command ID and data, and generates a 48-bit message for it.
-- It will first check if the command is a valid 48-bit command and produce the
-- following outputs:
-- 1. o_dataout -> a single bit output that produces the message to be sent to the
-- SD card one bit at a time. Every time the i_message_bit_out input
-- is high and the i_clock has a positive edge, a new bit is produced.
-- 2. o_message_done -> a signal that is asserted high when the entire message has been
-- produced through the o_dataout output.
-- 3. o_valid -> is a signal that is asserted high if the specified message is valid.
-- 4. o_response_type -> indicates the command response type.
-- 5. o_returning_ocr -> the response from the SD card will contain the OCR register
-- 6. o_returning_cid -> the response from the SD card will contain the CID register
-- 7. o_returning_rca -> the response from the SD card will contain the RCA register
-- 8. o_returning_csd -> the response from the SD card will contain the CSD register
-- 9. o_data_read -> asserted when the command being sent is a data read command.
-- 10. o_data_write -> asserted when the command being sent is a data write command.
-- 11. o_wait_cmd_busy -> is set high when the response to this command will be
-- followed by a busy signal.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_48_bit_Command_Generator is
generic (
-- Basic commands
COMMAND_0_GO_IDLE : STD_LOGIC_VECTOR(5 downto 0) := "000000";
COMMAND_2_ALL_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "000010";
COMMAND_3_SEND_RCA : STD_LOGIC_VECTOR(5 downto 0) := "000011";
COMMAND_4_SET_DSR : STD_LOGIC_VECTOR(5 downto 0) := "000100";
COMMAND_6_SWITCH_FUNCTION : STD_LOGIC_VECTOR(5 downto 0) := "000110";
COMMAND_7_SELECT_CARD : STD_LOGIC_VECTOR(5 downto 0) := "000111";
COMMAND_9_SEND_CSD : STD_LOGIC_VECTOR(5 downto 0) := "001001";
COMMAND_10_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "001010";
COMMAND_12_STOP_TRANSMISSION : STD_LOGIC_VECTOR(5 downto 0) := "001100";
COMMAND_13_SEND_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
COMMAND_15_GO_INACTIVE : STD_LOGIC_VECTOR(5 downto 0) := "001111";
-- Block oriented read/write/lock commands
COMMAND_16_SET_BLOCK_LENGTH : STD_LOGIC_VECTOR(5 downto 0) := "010000";
-- Block oriented read commands
COMMAND_17_READ_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "010001";
COMMAND_18_READ_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010010";
-- Block oriented write commands
COMMAND_24_WRITE_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "011000";
COMMAND_25_WRITE_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "011001";
COMMAND_27_PROGRAM_CSD : STD_LOGIC_VECTOR(5 downto 0) := "011011";
-- Block oriented write-protection commands
COMMAND_28_SET_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011100";
COMMAND_29_CLEAR_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011101";
COMMAND_30_SEND_PROTECTED_GROUPS : STD_LOGIC_VECTOR(5 downto 0) := "011110";
-- Erase commands
COMMAND_32_ERASE_BLOCK_START : STD_LOGIC_VECTOR(5 downto 0) := "100000";
COMMAND_33_ERASE_BLOCK_END : STD_LOGIC_VECTOR(5 downto 0) := "100001";
COMMAND_38_ERASE_SELECTED_GROUPS: STD_LOGIC_VECTOR(5 downto 0) := "100110";
-- Block lock commands
COMMAND_42_LOCK_UNLOCK : STD_LOGIC_VECTOR(5 downto 0) := "101010";
-- Command Type Settings
COMMAND_55_APP_CMD : STD_LOGIC_VECTOR(5 downto 0) := "110111";
COMMAND_56_GEN_CMD : STD_LOGIC_VECTOR(5 downto 0) := "111000";
-- Application Specific commands - must be preceeded with command 55.
ACOMMAND_6_SET_BUS_WIDTH : STD_LOGIC_VECTOR(5 downto 0) := "000110";
ACOMMAND_13_SD_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
ACOMMAND_22_SEND_NUM_WR_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010100";
ACOMMAND_23_SET_BLK_ERASE_COUNT : STD_LOGIC_VECTOR(5 downto 0) := "010101";
ACOMMAND_41_SEND_OP_CONDITION : STD_LOGIC_VECTOR(5 downto 0) := "101001";
ACOMMAND_42_SET_CLR_CARD_DETECT : STD_LOGIC_VECTOR(5 downto 0) := "101010";
ACOMMAND_51_SEND_SCR : STD_LOGIC_VECTOR(5 downto 0) := "110011";
-- First custom_command
FIRST_NON_PREDEFINED_COMMAND : STD_LOGIC_VECTOR(3 downto 0) := "1010"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_message_bit_out : in std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_predefined_message : in std_logic_vector(3 downto 0);
i_generate : in std_logic;
i_DSR : in std_logic_vector(15 downto 0);
i_OCR : in std_logic_vector(31 downto 0);
i_RCA : in std_logic_vector(15 downto 0);
o_dataout : out std_logic;
o_message_done : out std_logic;
o_valid : out std_logic;
o_returning_ocr : out std_logic;
o_returning_cid : out std_logic;
o_returning_rca : out std_logic;
o_returning_csd : out std_logic;
o_returning_status : out std_logic;
o_data_read : out std_logic;
o_data_write : out std_logic;
o_wait_cmd_busy : out std_logic;
o_last_cmd_was_55 : out std_logic;
o_response_type : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_48_bit_Command_Generator is
component Altera_UP_SD_CRC7_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end component;
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal last_command_id : std_logic_vector(5 downto 0);
signal message_bits : std_logic_vector(39 downto 0);
signal last_command_sent_was_CMD55, valid : std_logic;
signal bit_to_send, sending_CRC, command_valid : std_logic;
signal returning_cid_reg, returning_rca_reg, returning_csd_reg, returning_dsr_reg, returning_ocr_reg, returning_status_reg : std_logic;
-- UNREGISTERED
signal temp_4_bits : std_logic_vector(3 downto 0);
signal message_done, CRC_generator_out, produce_next_bit : std_logic;
signal app_specific_valid, regular_command_valid : std_logic;
signal response_type, response_type_reg : std_logic_vector(2 downto 0);
signal cmd_argument : std_logic_vector(31 downto 0);
begin
-- This set of bits is necessary to allow the SD card to accept a VDD level for communication.
temp_4_bits <= "1111" when ((i_OCR(23) = '1') or (i_OCR(22) = '1') or (i_OCR(21) = '1') or (i_OCR(20) = '1')) else "0000";
-- Generate the bits to be sent to the SD card. These bits must pass through the CRC generator
-- to produce error checking code. The error checking code will follow the message. The message terminates with
-- a logic '1'. Total message length is 48 bits.
message_data_generator: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
message_bits <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
-- Store type of a response.
response_type_reg <= response_type;
-- Generate a message. Please note that the predefined messages are used for initialization.
-- If executed in sequence, they will initialize the SD card to work correctly. Only once these
-- instructions are completed can the data transfer begin.
case (i_predefined_message) is
when "0000" =>
-- Generate a predefined message - CMD0.
message_bits <= ("01" & COMMAND_0_GO_IDLE & "00000000000000000000000000000000");
when "0001" =>
-- Generate a predefined message - CMD55.
message_bits <= ("01" & COMMAND_55_APP_CMD & "0000000000000000" & "0000000000000000");
when "0010" =>
-- Generate a predefined message - ACMD41.
message_bits <= ("01" & ACOMMAND_41_SEND_OP_CONDITION & "0000" & temp_4_bits & "000" & i_OCR(20) & "00000000000000000000");
when "0011" =>
-- Generate a predefined message - CMD2.
message_bits <= ("01" & COMMAND_2_ALL_SEND_CID & "00000000000000000000000000000000");
when "0100" =>
-- Generate a predefined message - CMD3.
message_bits <= ("01" & COMMAND_3_SEND_RCA & "00000000000000000000000000000000");
when "0101" =>
-- Generate a predefined message - CMD9.
message_bits <= ("01" & COMMAND_9_SEND_CSD & i_RCA & "0000000000000000");
when "0110" =>
-- Generate a predefined message - CMD4.
message_bits <= ("01" & COMMAND_4_SET_DSR & i_DSR & "0000000000000000");
when "0111" =>
-- Generate a predefined message - CMD16. Set block length to 512.
message_bits <= ("01" & COMMAND_16_SET_BLOCK_LENGTH & "0000000000000000" & "0000001000000000" );
when "1000" =>
-- Generate a predefined message - CMD7. Select the card so we can access it's data.
message_bits <= ("01" & COMMAND_7_SELECT_CARD & i_RCA & "0000001000000000" );
when "1001" =>
-- Generate a predefined message - CMD13. Send SD card status.
message_bits <= ("01" & COMMAND_13_SEND_STATUS & i_RCA & "0000000000000000");
when others =>
-- Generate a custom message
message_bits <= ("01" & i_command_ID & cmd_argument);
end case;
else
-- Shift bits out as needed
if (produce_next_bit = '1') then
-- Shift message bits.
message_bits(39 downto 1) <= message_bits(38 downto 0);
message_bits(0) <= '0';
end if;
end if;
end if;
end if;
end process;
-- Generate command argument based on the command_ID. For most commands, the argument is user specified.
-- For some commands, it is necessary to send a particular SD Card register contents. Hence, these contents are
-- sent instead of the user data.
argument_generator: process (i_command_ID, last_command_sent_was_CMD55, i_generate, i_RCA, i_DSR, i_OCR, i_argument)
begin
cmd_argument <= i_argument;
if (i_generate = '1') then
case (i_command_ID) is
when COMMAND_4_SET_DSR =>
cmd_argument <= i_DSR & i_argument(15 downto 0);
when COMMAND_7_SELECT_CARD =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_9_SEND_CSD =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_10_SEND_CID =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_13_SEND_STATUS =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_15_GO_INACTIVE =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_55_APP_CMD =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when ACOMMAND_41_SEND_OP_CONDITION =>
if (last_command_sent_was_CMD55 = '1') then
cmd_argument <= i_OCR;
end if;
when others =>
cmd_argument <= i_argument;
end case;
end if;
end process;
-- Validate the message ID before sending it out.
command_validator: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
command_valid <= '0';
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
if (("0" & i_predefined_message) >= ("0" & FIRST_NON_PREDEFINED_COMMAND)) then
-- Check the custom message
if (last_command_sent_was_CMD55 = '1') then
-- Check the application specific messages
command_valid <= app_specific_valid;
else
-- Check the default messages.
command_valid <= regular_command_valid;
end if;
else
-- A command is valid if the message is predefined.
command_valid <= '1';
end if;
end if;
end if;
end if;
end process;
-- Registers that indicate that the command sent will return contents of a control register.
-- The contents of the response should therefore be stored in the appropriate register.
responses_with_control_regs: process(i_clock, i_reset_n, last_command_sent_was_CMD55, last_command_id, message_done)
begin
if (i_reset_n = '0') then
returning_ocr_reg <= '0';
returning_cid_reg <= '0';
returning_rca_reg <= '0';
returning_csd_reg <= '0';
returning_status_reg <= '0';
elsif (rising_edge(i_clock)) then
if (i_generate = '1') then
returning_ocr_reg <= '0';
returning_cid_reg <= '0';
returning_rca_reg <= '0';
returning_csd_reg <= '0';
returning_status_reg <= '0';
elsif (message_done = '1') then
-- OCR
if ((last_command_sent_was_CMD55 = '1') and (last_command_id = ACOMMAND_41_SEND_OP_CONDITION)) then
returning_ocr_reg <= '1';
end if;
-- CID
if (last_command_id = COMMAND_2_ALL_SEND_CID) then
returning_cid_reg <= '1';
end if;
-- RCA
if (last_command_id = COMMAND_3_SEND_RCA) then
returning_rca_reg <= '1';
end if;
-- CSD
if (last_command_id = COMMAND_9_SEND_CSD) then
returning_csd_reg <= '1';
end if;
-- Status
if ((last_command_sent_was_CMD55 = '0') and (last_command_id = COMMAND_13_SEND_STATUS)) then
returning_status_reg <= '1';
end if;
end if;
end if;
end process;
-- Count the number of bits sent using a counter.
sent_bit_counter: process(i_clock, i_reset_n, i_generate, produce_next_bit, counter)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
-- Reset the counter indicating the number of bits produced.
counter <= "0000000";
else
if (produce_next_bit = '1') then
-- Update the number of message bits sent.
counter <= counter + '1';
end if;
end if;
end if;
end if;
end process;
-- Select the source for the output data to be either the message data or the CRC bits.
source_selector: process(i_clock, i_reset_n, i_generate)
begin
if (i_reset_n = '0') then
sending_CRC <= '0';
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
-- Set sending CRC flag to 0.
sending_CRC <= '0';
else
-- If this is the last bit being sent, then bits that follow are the CRC bits.
if (counter = "0101000") then
sending_CRC <= '1';
end if;
end if;
end if;
end if;
end process;
-- When the message is sent, store its ID. In a special case when CMD55 is sent, the next command can be an application
-- specific command. We need to check those command IDs to verify the validity of the message.
CMD55_recognizer: process(i_clock, i_reset_n, i_generate, produce_next_bit, counter, message_done, last_command_id)
begin
if (i_reset_n = '0') then
last_command_sent_was_CMD55 <= '0';
else
if (rising_edge(i_clock)) then
if (i_generate = '0') then
-- Store the ID of the current command.
if (produce_next_bit = '1') then
if (counter = "0000000") then
last_command_id <= message_bits(37 downto 32);
end if;
end if;
-- When message has been sent then check if it was CMD55.
if (message_done = '1') then
if (last_command_id = COMMAND_55_APP_CMD) then
last_command_sent_was_CMD55 <= '1';
else
last_command_sent_was_CMD55 <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
-- Instantiate a CRC7 generator. Message bits will pass through it to create the CRC code for the message.
CRC7_Gen: Altera_UP_SD_CRC7_Generator PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_enable => i_message_bit_out,
i_shift => sending_CRC,
i_datain => message_bits(39),
o_dataout => CRC_generator_out
);
-- Define the source of the data produced by this module, depending on the counter value and the sending_CRC register state.
data_bit_register: process(i_clock, i_reset_n, i_generate, produce_next_bit, counter)
begin
if (i_reset_n = '0') then
bit_to_send <= '1';
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
bit_to_send <= '1';
elsif (produce_next_bit = '1') then
-- Send data to output.
if (sending_CRC = '0') then
-- Send message bits
bit_to_send <= message_bits(39);
else
-- Send CRC bits
if ((counter = "0101111") or (counter = "0110000")) then
-- At the end of CRC bits put a 1.
bit_to_send <= '1';
else
bit_to_send <= CRC_generator_out;
end if;
end if;
end if;
end if;
end if;
end process;
-- Define conditions to produce the next message bit on the module output port o_dataout.
produce_next_bit <= i_message_bit_out and (not message_done);
-- Message is done when the last bit appears at the output.
message_done <= '1' when (counter = "0110001") else '0';
-- Check the application specific messages
app_specific_valid <= '1' when (
--(i_command_ID = COMMAND_0_GO_IDLE) or
(i_command_ID = COMMAND_2_ALL_SEND_CID) or
(i_command_ID = COMMAND_3_SEND_RCA) or
(i_command_ID = COMMAND_4_SET_DSR) or
--(i_command_ID = ACOMMAND_6_SET_BUS_WIDTH) or
--(i_command_ID = COMMAND_7_SELECT_CARD) or
(i_command_ID = COMMAND_9_SEND_CSD) or
(i_command_ID = COMMAND_10_SEND_CID) or
--(i_command_ID = COMMAND_12_STOP_TRANSMISSION) or
(i_command_ID = ACOMMAND_13_SD_STATUS) or
--(i_command_ID = COMMAND_15_GO_INACTIVE) or
--(i_command_ID = COMMAND_16_SET_BLOCK_LENGTH) or
(i_command_ID = COMMAND_17_READ_BLOCK) or
--(i_command_ID = COMMAND_18_READ_MULTIPLE_BLOCKS) or
(i_command_ID = ACOMMAND_22_SEND_NUM_WR_BLOCKS) or
(i_command_ID = ACOMMAND_23_SET_BLK_ERASE_COUNT) or
(i_command_ID = COMMAND_24_WRITE_BLOCK) or
(i_command_ID = COMMAND_25_WRITE_MULTIPLE_BLOCKS) or
(i_command_ID = COMMAND_27_PROGRAM_CSD) or
(i_command_ID = COMMAND_28_SET_WRITE_PROTECT) or
(i_command_ID = COMMAND_29_CLEAR_WRITE_PROTECT) or
(i_command_ID = COMMAND_30_SEND_PROTECTED_GROUPS) or
(i_command_ID = COMMAND_32_ERASE_BLOCK_START) or
(i_command_ID = COMMAND_33_ERASE_BLOCK_END) or
(i_command_ID = COMMAND_38_ERASE_SELECTED_GROUPS) or
(i_command_ID = ACOMMAND_41_SEND_OP_CONDITION) or
(i_command_ID = ACOMMAND_42_SET_CLR_CARD_DETECT) or
(i_command_ID = ACOMMAND_51_SEND_SCR) or
(i_command_ID = COMMAND_55_APP_CMD) or
(i_command_ID = COMMAND_56_GEN_CMD)
)
else '0';
-- Check the default messages.
regular_command_valid <= '1' when (
-------------------------------------------------------
-- Disabled to prevent malfunction of the core
-------------------------------------------------------
--(i_command_ID = COMMAND_0_GO_IDLE) or
--(i_command_ID = COMMAND_6_SWITCH_FUNCTION) or
--(i_command_ID = COMMAND_7_SELECT_CARD) or
--(i_command_ID = COMMAND_15_GO_INACTIVE) or
--(i_command_ID = COMMAND_27_PROGRAM_CSD) or
--(i_command_ID = COMMAND_30_SEND_PROTECTED_GROUPS) or
--(i_command_ID = COMMAND_42_LOCK_UNLOCK) or
-------------------------------------------------------
(i_command_ID = COMMAND_2_ALL_SEND_CID) or
(i_command_ID = COMMAND_3_SEND_RCA) or
(i_command_ID = COMMAND_4_SET_DSR) or
(i_command_ID = COMMAND_9_SEND_CSD) or
(i_command_ID = COMMAND_10_SEND_CID) or
(i_command_ID = COMMAND_13_SEND_STATUS) or
-------------------------------------------------------
-- Disabled to simplify the circuit
-------------------------------------------------------
--(i_command_ID = COMMAND_12_STOP_TRANSMISSION) or
--(i_command_ID = COMMAND_16_SET_BLOCK_LENGTH) or
--(i_command_ID = COMMAND_18_READ_MULTIPLE_BLOCKS) or
--(i_command_ID = COMMAND_25_WRITE_MULTIPLE_BLOCKS) or
-------------------------------------------------------
(i_command_ID = COMMAND_17_READ_BLOCK) or
(i_command_ID = COMMAND_24_WRITE_BLOCK) or
(i_command_ID = COMMAND_28_SET_WRITE_PROTECT) or
(i_command_ID = COMMAND_29_CLEAR_WRITE_PROTECT) or
(i_command_ID = COMMAND_32_ERASE_BLOCK_START) or
(i_command_ID = COMMAND_33_ERASE_BLOCK_END) or
(i_command_ID = COMMAND_38_ERASE_SELECTED_GROUPS) or
(i_command_ID = COMMAND_55_APP_CMD) or
(i_command_ID = COMMAND_56_GEN_CMD)
)
else '0';
response_type <= "001" when -- Wait for type 1 response when
(
(i_predefined_message = "0001") or
(i_predefined_message = "0111") or
(i_predefined_message = "1000") or
(i_predefined_message = "1001") or
((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and
((i_command_ID = COMMAND_6_SWITCH_FUNCTION) or
(i_command_ID = COMMAND_7_SELECT_CARD) or
(i_command_ID = COMMAND_12_STOP_TRANSMISSION) or
(i_command_ID = COMMAND_13_SEND_STATUS) or
(i_command_ID = COMMAND_16_SET_BLOCK_LENGTH) or
(i_command_ID = COMMAND_17_READ_BLOCK) or
(i_command_ID = COMMAND_18_READ_MULTIPLE_BLOCKS) or
(i_command_ID = COMMAND_24_WRITE_BLOCK) or
(i_command_ID = COMMAND_25_WRITE_MULTIPLE_BLOCKS) or
(i_command_ID = COMMAND_27_PROGRAM_CSD) or
(i_command_ID = COMMAND_28_SET_WRITE_PROTECT) or
(i_command_ID = COMMAND_29_CLEAR_WRITE_PROTECT) or
(i_command_ID = COMMAND_30_SEND_PROTECTED_GROUPS) or
(i_command_ID = COMMAND_32_ERASE_BLOCK_START) or
(i_command_ID = COMMAND_33_ERASE_BLOCK_END) or
(i_command_ID = COMMAND_38_ERASE_SELECTED_GROUPS) or
(i_command_ID = COMMAND_42_LOCK_UNLOCK) or
(i_command_ID = COMMAND_55_APP_CMD) or
(i_command_ID = COMMAND_56_GEN_CMD) or
((last_command_sent_was_CMD55 = '1') and
((i_command_ID = ACOMMAND_6_SET_BUS_WIDTH) or
(i_command_ID = ACOMMAND_13_SD_STATUS) or
(i_command_ID = ACOMMAND_22_SEND_NUM_WR_BLOCKS) or
(i_command_ID = ACOMMAND_23_SET_BLK_ERASE_COUNT) or
(i_command_ID = ACOMMAND_42_SET_CLR_CARD_DETECT) or
(i_command_ID = ACOMMAND_51_SEND_SCR)))))
) else
"010" when -- Wait for type 2 response when
(
((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and
((i_command_ID = COMMAND_2_ALL_SEND_CID) or
(i_command_ID = COMMAND_9_SEND_CSD) or
(i_command_ID = COMMAND_10_SEND_CID))) or
(i_predefined_message = "0011") or
(i_predefined_message = "0101")
) else
"011" when -- Wait for type 3 response when
(
((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and (last_command_sent_was_CMD55 = '1') and (i_command_ID = ACOMMAND_41_SEND_OP_CONDITION)) or
(i_predefined_message = "0010")
) else
"110" when -- Wait for type 6 response when
(((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and (i_command_ID = COMMAND_3_SEND_RCA)) or
(i_predefined_message = "0100"))
else "000"; -- Otherwise there is no response pending.
-- Define circuit outputs
o_message_done <= message_done;
o_response_type <= response_type_reg;
o_valid <= command_valid;
o_dataout <= bit_to_send;
o_returning_ocr <= returning_ocr_reg;
o_returning_cid <= returning_cid_reg;
o_returning_rca <= returning_rca_reg;
o_returning_csd <= returning_csd_reg;
o_returning_status <= returning_status_reg;
o_data_read <= '1' when (last_command_id = COMMAND_17_READ_BLOCK) else '0';
o_data_write <= '1' when (last_command_id = COMMAND_24_WRITE_BLOCK) else '0';
o_last_cmd_was_55 <= last_command_sent_was_CMD55;
o_wait_cmd_busy <= '1' when (
(last_command_id = COMMAND_7_SELECT_CARD) or
(last_command_id = COMMAND_12_STOP_TRANSMISSION) or
(last_command_id = COMMAND_28_SET_WRITE_PROTECT) or
(last_command_id = COMMAND_29_CLEAR_WRITE_PROTECT) or
(last_command_id = COMMAND_38_ERASE_SELECTED_GROUPS))
else '0';
end rtl; | mit | d0e111873257af9bafc2ee27915741c9 | 0.614108 | 3.088224 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_auto_pc_0/zqynq_lab_1_design_auto_pc_0_sim_netlist.vhdl | 1 | 531,562 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:12:07 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top zqynq_lab_1_design_auto_pc_0 -prefix
-- zqynq_lab_1_design_auto_pc_0_ zqynq_lab_1_design_auto_pc_2_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_auto_pc_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_auto_pc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_auto_pc_0 : entity is "zqynq_lab_1_design_auto_pc_2,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_auto_pc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zqynq_lab_1_design_auto_pc_0 : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end zqynq_lab_1_design_auto_pc_0;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0 is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 9599d9bbed84d0b6a1822b59e5063e31 | 0.530745 | 2.536163 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/inpad_ddr.vhd | 1 | 3,704 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad_ddr, inpad_ddrv
-- File: inpad_ddr.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Wrapper that instantiates an input pad connected to a DDR_IREG.
-- The generic tech wrappers are not used for nextreme since this
-- technology is not wrapped by ddr_ireg.
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.all;
entity inpad_ddr is
generic (
tech : integer := 0;
level : integer := 0;
voltage : integer := x33v;
filter : integer := 0;
strength : integer := 0
);
port (
pad : in std_ulogic;
o1, o2 : out std_ulogic;
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of inpad_ddr is
signal d : std_ulogic;
begin
def: if (tech /= easic90) and (tech /= easic45) generate
p : inpad generic map (tech, level, voltage, filter, strength)
port map (pad, d);
ddrreg : ddr_ireg generic map (tech)
port map (o1, o2, c1, c2, ce, d, r, s);
end generate def;
nex : if (tech = easic90) generate
p : nextreme_inpad generic map (level, voltage)
port map(pad, d);
ddrreg : nextreme_iddr_reg
port map (ck => c1, d => d, qh => o1, ql => o2, rstb => r);
end generate;
n2x : if (tech = easic45) generate
p : n2x_inpad_ddr generic map (level, voltage)
port map (pad, o1, o2, c1, c2, ce, r, s);
d <= '0';
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad_ddrv is
generic (
tech : integer := 0;
level : integer := 0;
voltage : integer := 0;
filter : integer := 0;
strength : integer := 0;
width : integer := 1
);
port (
pad : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic;
ce : in std_ulogic;
r : in std_ulogic;
s : in std_ulogic
);
end;
architecture rtl of inpad_ddrv is
begin
n2x : if (tech = easic45) generate
p : n2x_inpad_ddrv generic map (level, voltage, width)
port map (pad, o1, o2, c1, c2, ce, r, s);
end generate;
base : if (tech /= easic45) generate
v : for i in width-1 downto 0 generate
x0 : inpad_ddr generic map (tech, level, voltage, filter, strength)
port map (pad(i), o1(i), o2(i), c1, c2, ce, r, s);
end generate;
end generate;
end;
| gpl-2.0 | 748ccf8276b1336142c68845534b1060 | 0.588823 | 3.5109 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ipshared/0177/hdl/ip/convolve_kernel_ap_fadd_7_full_dsp_32.vhd | 4 | 14,048 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_5;
USE floating_point_v7_1_5.floating_point_v7_1_5;
ENTITY convolve_kernel_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fadd_7_full_dsp_32;
ARCHITECTURE convolve_kernel_ap_fadd_7_full_dsp_32_arch OF convolve_kernel_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_5 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_5,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_7_full_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_H" &
"AS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESE" &
"TN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNE" &
"D=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_result_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclken: SIGNAL IS "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : floating_point_v7_1_5
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fadd_7_full_dsp_32_arch;
| mit | 06305391ba9596f4d9470d676c83ff2b | 0.661233 | 3.026282 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/spi/spimctrl.vhd | 1 | 38,341 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spimctrl
-- File: spimctrl.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: SPI flash memory controller. Supports a wide range of SPI
-- memory devices with the data read instruction configurable via
-- generics. Also has limited support for initializing and reading
-- SD Cards in SPI mode.
--
-- The controller has two memory areas. The flash area where the flash memory
-- is directly mapped and the I/O area where core registers are mapped.
--
-- Revision 1 added support for burst reads when sdcard = 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.spi.all;
entity spimctrl is
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
faddr : integer := 16#000#; -- Flash map base address
fmask : integer := 16#fff#; -- Flash area mask
ioaddr : integer := 16#000#; -- I/O base address
iomask : integer := 16#fff#; -- I/O mask
spliten : integer := 0; -- AMBA SPLIT support
oepol : integer := 0; -- Output enable polarity
sdcard : integer range 0 to 1 := 0; -- Core is connected to SD card
readcmd : integer range 0 to 255 := 16#0B#; -- Mem. dev. READ command
dummybyte : integer range 0 to 1 := 1; -- Dummy byte after cmd
dualoutput : integer range 0 to 1 := 0; -- Enable dual output
scaler : integer range 1 to 512 := 1; -- SCK scaler
altscaler : integer range 1 to 512 := 1; -- Alternate SCK scaler
pwrupcnt : integer := 0; -- System clock cycles to init
maxahbaccsz : integer range 0 to 256 := AHBDW; -- Max AHB access size
offset : integer := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
spii : in spimctrl_in_type;
spio : out spimctrl_out_type
);
end spimctrl;
architecture rtl of spimctrl is
constant REVISION : amba_version_type := 1;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPIMCTRL, 0, REVISION, hirq),
4 => ahb_iobar(ioaddr, iomask),
5 => ahb_membar(faddr, '1', '1', fmask),
others => zero32);
-- BANKs
constant CTRL_BANK : integer := 0;
constant FLASH_BANK : integer := 1;
constant MAXDW : integer := maxahbaccsz;
-----------------------------------------------------------------------------
-- SD card constants
-----------------------------------------------------------------------------
constant SD_BLEN : integer := 4;
constant SD_CRC_BYTE : std_logic_vector(7 downto 0) := X"95";
constant SD_BLOCKLEN : std_logic_vector(31 downto 0) :=
conv_std_logic_vector(SD_BLEN, 32);
-- Commands
constant SD_CMD0 : std_logic_vector(5 downto 0) := "000000";
constant SD_CMD16 : std_logic_vector(5 downto 0) := "010000";
constant SD_CMD17 : std_logic_vector(5 downto 0) := "010001";
constant SD_CMD55 : std_logic_vector(5 downto 0) := "110111";
constant SD_ACMD41 : std_logic_vector(5 downto 0) := "101001";
-- Command timeout
constant SD_CMD_TIMEOUT : integer := 100;
-- Data token timeout
constant SD_DATATOK_TIMEOUT : integer := 312500;
-----------------------------------------------------------------------------
-- SPI device constants
-----------------------------------------------------------------------------
-- Length of read instruction argument-1
constant SPI_ARG_LEN : integer := 2 + dummybyte;
-----------------------------------------------------------------------------
-- Core constants
-----------------------------------------------------------------------------
-- OEN
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1); -- Enable outputs
constant INPUT : std_ulogic := not OUTPUT; -- Tri-state outputs
-- Register offsets
constant CONF_REG_OFF : std_logic_vector(7 downto 2) := "000000";
constant CTRL_REG_OFF : std_logic_vector(7 downto 2) := "000001";
constant STAT_REG_OFF : std_logic_vector(7 downto 2) := "000010";
constant RX_REG_OFF : std_logic_vector(7 downto 2) := "000011";
constant TX_REG_OFF : std_logic_vector(7 downto 2) := "000100";
-----------------------------------------------------------------------------
-- Subprograms
-----------------------------------------------------------------------------
-- Description: Determines required size of timer used for clock scaling
function timer_size
return integer is
begin -- timer_size
if altscaler > scaler then
return altscaler;
end if;
return scaler;
end timer_size;
-- Description: Returns the number of bits required for the haddr vector to
-- be able to save the Flash area address.
function req_addr_bits
return integer is
begin -- req_addr_bits
case fmask is
when 16#fff# => return 20;
when 16#ffe# => return 21;
when 16#ffc# => return 22;
when 16#ff8# => return 23;
when 16#ff0# => return 24;
when 16#fe0# => return 25;
when 16#fc0# => return 26;
when 16#f80# => return 27;
when 16#f00# => return 28;
when 16#e00# => return 29;
when 16#c00# => return 30;
when others => return 31;
end case;
end req_addr_bits;
-- Description: Returns true if SCK clock should transition
function sck_toggle (
curr : std_logic_vector((timer_size-1) downto 0);
last : std_logic_vector((timer_size-1) downto 0);
usealtscaler : boolean)
return boolean is
begin -- sck_toggle
if usealtscaler then
return (curr(altscaler-1) xor last(altscaler-1)) = '1';
end if;
return (curr(scaler-1) xor last(scaler-1)) = '1';
end sck_toggle;
-- Description: Short for conv_std_logic_vector, avoiding an alias
function cslv (
i : integer;
w : integer)
return std_logic_vector is
begin -- cslv
return conv_std_logic_vector(i,w);
end cslv;
-- Description: Calculates value for spi.cnt based on AMBA HSIZE
function calc_spi_cnt (
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable cnt : std_logic_vector(4 downto 0) := (others => '0');
begin -- calc_spi_cnt
for i in 0 to 4 loop
if i < conv_integer(hsize) then
cnt(i) := '1';
end if;
end loop; -- i
return cnt;
end calc_spi_cnt;
-----------------------------------------------------------------------------
-- States
-----------------------------------------------------------------------------
-- Main FSM states
type spimstate_type is (IDLE, AHB_RESPOND, USER_SPI, BUSY);
-- SPI device FSM states
type spistate_type is (SPI_PWRUP, SPI_READY, SPI_READ, SPI_ADDR, SPI_DATA);
-- SD FSM states
type sdstate_type is (SD_CHECK_PRES, SD_PWRUP0, SD_PWRUP1, SD_INIT_IDLE,
SD_ISS_ACMD41, SD_CHECK_CMD16, SD_READY,
SD_CHECK_CMD17, SD_CHECK_TOKEN, SD_HANDLE_DATA,
SD_SEND_CMD, SD_GET_RESP);
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type spim_ctrl_reg_type is record -- Control register
eas : std_ulogic; -- Enable alternate scaler
ien : std_ulogic; -- Interrupt enable
usrc : std_ulogic; -- User mode
end record;
type spim_stat_reg_type is record -- Status register
busy : std_ulogic; -- Core busy
done : std_ulogic; -- User operation done
end record;
type spim_regif_type is record -- Register bank
ctrl : spim_ctrl_reg_type; -- Control register
stat : spim_stat_reg_type; -- Status register
end record;
type sdcard_type is record -- Present when SD card
state : sdstate_type; -- SD state
tcnt : std_logic_vector(2 downto 0); -- Transmit count
rcnt : std_logic_vector(3 downto 0); -- Receive count
cmd : std_logic_vector(5 downto 0); -- SD command
rstate : sdstate_type; -- Return state
htb : std_ulogic; -- Handle trailing byte
vresp : std_ulogic; -- Valid response
cd : std_ulogic; -- Synchronized card detect
timeout : std_ulogic; -- Timeout status bit
dtocnt : std_logic_vector(18 downto 0); -- Data token timeout counter
ctocnt : std_logic_vector(6 downto 0); -- CMD resp. timeout counter
end record;
type spiflash_type is record -- Present when !SD card
state : spistate_type; -- Mem. device comm. state
cnt : std_logic_vector(4 downto 0); -- Generic counter
hsize : std_logic_vector(2 downto 0); -- Size of access
hburst : std_logic_vector(0 downto 0); -- Incremental burst
end record;
type spimctrl_in_array is array (1 downto 0) of spimctrl_in_type;
type spim_reg_type is record
-- Common
spimstate : spimstate_type; -- Main FSM
rst : std_ulogic; -- Reset
reg : spim_regif_type; -- Register bank
timer : std_logic_vector((timer_size-1) downto 0);
sample : std_logic_vector(1 downto 0); -- Sample data line
bd : std_ulogic;
sreg : std_logic_vector(7 downto 0); -- Shiftreg
bcnt : std_logic_vector(2 downto 0); -- Bit counter
go : std_ulogic; -- SPI comm. active
stop : std_ulogic; -- Stop SPI comm.
ar : std_logic_vector(MAXDW-1 downto 0); -- argument/response
hold : std_ulogic; -- Do not shift ar
insplit : std_ulogic; -- SPLIT response issued
unsplit : std_ulogic; -- SPLIT complete not issued
-- SPI flash device
spi : spiflash_type; -- Used when !SD card
-- SD
sd : sdcard_type; -- Used when SD card
-- AHB
irq : std_ulogic; -- Interrupt request
hsize : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 1);
haddr : std_logic_vector((req_addr_bits-1) downto 0);
hready : std_ulogic;
frdata : std_logic_vector(MAXDW-1 downto 0); -- Flash response data
rrdata : std_logic_vector(7 downto 0); -- Register response data
hresp : std_logic_vector(1 downto 0);
splmst : std_logic_vector(log2(NAHBMST)-1 downto 0); -- SPLIT:ed master
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- Other SPLIT:ed masters
ahbcancel : std_ulogic; -- Locked access cancels ongoing SPLIT
-- response
hburst : std_logic_vector(0 downto 0);
seq : std_ulogic; -- Sequential burst
-- Inputs and outputs
spii : spimctrl_in_array;
spio : spimctrl_out_type;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : spim_reg_type;
begin -- rtl
comb: process (r, rstn, ahbsi, spii)
variable v : spim_reg_type;
variable change : std_ulogic;
variable regaddr : std_logic_vector(7 downto 2);
variable hsplit : std_logic_vector(NAHBMST-1 downto 0);
variable ahbirq : std_logic_vector((NAHBIRQ-1) downto 0);
variable lastbit : std_ulogic;
variable enable_altscaler : boolean;
variable disable_flash : boolean;
variable read_flash : boolean;
variable hrdata : std_logic_vector(MAXDW-1 downto 0);
variable hwdata : std_logic_vector(7 downto 0);
begin -- process comb
v := r; v.spii := r.spii(0) & spii; v.sample := r.sample(0) & '0';
change := '0'; v.irq := '0'; v.hresp := HRESP_OKAY; v.hready := '1';
regaddr := r.haddr(7 downto 2); hsplit := (others => '0');
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2))(7 downto 0);
ahbirq := (others => '0'); ahbirq(hirq) := r.irq;
if sdcard = 1 then v.sd.cd := r.spii(0).cd; else v.sd.cd := '0'; end if;
read_flash := false;
enable_altscaler := (not r.spio.initialized or r.reg.ctrl.eas) = '1';
disable_flash := (r.spio.errorn = '0' or r.reg.ctrl.usrc = '1' or
r.spio.initialized = '0' or r.spimstate = USER_SPI);
if dualoutput = 1 and sdcard = 0 then
lastbit := andv(r.bcnt(1 downto 0)) and
((r.spio.mosioen xnor INPUT) or r.bcnt(2));
else
lastbit := andv(r.bcnt);
end if;
v.bd := lastbit and r.sample(0);
---------------------------------------------------------------------------
-- AHB communication
---------------------------------------------------------------------------
if ahbsi.hready = '1' then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hmbsel := ahbsi.hmbsel(r.hmbsel'range);
if (spliten = 0 or r.spimstate /= AHB_RESPOND or
ahbsi.hmbsel(CTRL_BANK) = '1' or ahbsi.hmastlock = '1') then
-- Writes to register space have no wait state
v.hready := ahbsi.hmbsel(CTRL_BANK) and ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr(r.haddr'range);
v.hsel := '1';
if ahbsi.hmbsel(FLASH_BANK) = '1' then
if sdcard = 0 then
v.hburst(r.hburst'range) := ahbsi.hburst(r.hburst'range);
v.seq := ahbsi.htrans(0);
end if;
if ahbsi.hwrite = '1' or disable_flash then
v.hresp := HRESP_ERROR;
v.hsel := '0';
else
if spliten /= 0 then
if ahbsi.hmastlock = '0' then
v.hresp := HRESP_SPLIT;
v.splmst := ahbsi.hmaster;
v.unsplit := '1';
else
v.ahbcancel := r.insplit;
end if;
v.insplit := not ahbsi.hmastlock;
end if;
end if;
end if;
else
-- Core is busy, transfer is not locked and access was to flash
-- area. Respond with SPLIT or insert wait states
v.hready := '0';
if spliten /= 0 then
v.hresp := HRESP_SPLIT;
v.hsplit(conv_integer(ahbsi.hmaster)) := '1';
end if;
end if;
else
v.hsel := '0';
end if;
end if;
if (r.hready = '0') then
if (r.hresp = HRESP_OKAY) then v.hready := '0';
else v.hresp := r.hresp; end if;
end if;
-- Read access to core registers
if (r.hsel and r.hmbsel(CTRL_BANK) and not r.hwrite) = '1' then
v.rrdata := (others => '0');
v.hready := '1';
v.hsel := '0';
case regaddr is
when CONF_REG_OFF =>
if sdcard = 1 then
v.rrdata := (others => '0');
else
v.rrdata := cslv(readcmd, 8);
end if;
when CTRL_REG_OFF =>
v.rrdata(3) := r.spio.csn;
v.rrdata(2) := r.reg.ctrl.eas;
v.rrdata(1) := r.reg.ctrl.ien;
v.rrdata(0) := r.reg.ctrl.usrc;
when STAT_REG_OFF =>
v.rrdata(5) := r.sd.cd;
v.rrdata(4) := r.sd.timeout;
v.rrdata(3) := not r.spio.errorn;
v.rrdata(2) := r.spio.initialized;
v.rrdata(1) := r.reg.stat.busy;
v.rrdata(0) := r.reg.stat.done;
when RX_REG_OFF => v.rrdata := r.ar(7 downto 0);
when others => null;
end case;
end if;
-- Write access to core registers
if (r.hsel and r.hmbsel(CTRL_BANK) and r.hwrite) = '1' then
case regaddr is
when CTRL_REG_OFF =>
v.rst := hwdata(4);
if (r.reg.ctrl.usrc and not hwdata(0)) = '1' then
v.spio.csn := '1';
elsif hwdata(0) = '1' then
v.spio.csn := hwdata(3);
end if;
v.reg.ctrl.eas := hwdata(2);
v.reg.ctrl.ien := hwdata(1);
v.reg.ctrl.usrc := hwdata(0);
when STAT_REG_OFF =>
v.spio.errorn := r.spio.errorn or hwdata(3);
v.reg.stat.done := r.reg.stat.done and not hwdata(0);
when RX_REG_OFF => null;
when TX_REG_OFF =>
if r.reg.ctrl.usrc = '1' then
v.sreg := hwdata(7 downto 0);
end if;
when others => null;
end case;
end if;
---------------------------------------------------------------------------
-- SPIMCTRL control FSM
---------------------------------------------------------------------------
v.reg.stat.busy := '1';
case r.spimstate is
when BUSY =>
-- Wait for core to finish user mode access
if (r.go or r.spio.sck) = '0' then
v.spimstate := IDLE;
v.reg.stat.done:= '1';
v.irq := r.reg.ctrl.ien;
end if;
when AHB_RESPOND =>
if r.spio.ready = '1' then
if spliten /= 0 and r.unsplit = '1' then
hsplit(conv_integer(r.splmst)) := '1';
v.unsplit := '0';
end if;
if ((spliten = 0 or v.ahbcancel = '0') and
(spliten = 0 or ahbsi.hmaster = r.splmst or r.insplit = '0') and
(((ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1') or
((spliten = 0 or r.insplit = '0') and r.hready = '0' and r.hresp = HRESP_OKAY))) then
v.spimstate := IDLE;
v.hresp := HRESP_OKAY;
if spliten /= 0 then
v.insplit := '0';
v.hsplit := r.hsplit;
end if;
v.hready := '1';
v.hsel := '0';
if r.spio.errorn = '0' then
v.hready := '0';
v.hresp := HRESP_ERROR;
end if;
elsif spliten /= 0 and v.ahbcancel = '1' then
v.spimstate := IDLE;
v.ahbcancel := '0';
end if;
end if;
when USER_SPI =>
if r.bd = '1' then
v.spimstate := BUSY;
v.hold := '1';
end if;
when others => -- IDLE
if spliten /= 0 and r.hresp /= HRESP_SPLIT then
hsplit := r.hsplit;
v.hsplit := (others => '0');
end if;
v.reg.stat.busy := '0';
if r.hsel = '1' then
if r.hmbsel(FLASH_BANK) = '1' then
-- Access to memory mapped flash area
v.spimstate := AHB_RESPOND;
read_flash := true;
elsif regaddr = TX_REG_OFF and (r.hwrite and r.reg.ctrl.usrc) = '1' then
-- Access to core transmit register
v.spimstate := USER_SPI;
v.go := '1';
v.stop := '1';
change := '1';
v.hold := '0';
if sdcard = 0 and dualoutput = 1 then
v.spio.mosioen := OUTPUT;
end if;
end if;
end if;
end case;
---------------------------------------------------------------------------
-- SD Card specific code
---------------------------------------------------------------------------
-- SD card initialization sequence:
-- * Check if card is present
-- * Perform power-up initialization sequence
-- * Issue CMD0 GO_IDLE_STATE
-- * Issue CMD55 APP_CMD
-- * Issue ACMD41 SEND_OP_COND
-- * Issue CMD16 SET_BLOCKLEN
if sdcard = 1 then
case r.sd.state is
when SD_PWRUP0 =>
v.go := '1';
v.sd.vresp := '1';
v.sd.state := SD_GET_RESP;
v.sd.rstate := SD_PWRUP1;
v.sd.rcnt := cslv(2, r.sd.rcnt'length);
when SD_PWRUP1 =>
v.sd.state := SD_SEND_CMD;
v.sd.rstate := SD_INIT_IDLE;
v.sd.cmd := SD_CMD0;
v.sd.rcnt := (others => '0');
v.ar := (others => '0');
when SD_INIT_IDLE =>
v.sd.state := SD_SEND_CMD;
v.sd.rcnt := (others => '0');
if r.ar(0) = '0' and r.sd.cmd /= SD_CMD0 then
v.sd.cmd := SD_CMD16;
v.ar := SD_BLOCKLEN;
v.sd.rstate := SD_CHECK_CMD16;
else
v.sd.cmd := SD_CMD55;
v.ar := (others => '0');
v.sd.rstate := SD_ISS_ACMD41;
end if;
when SD_ISS_ACMD41 =>
v.sd.state := SD_SEND_CMD;
v.sd.cmd := SD_ACMD41;
v.sd.rcnt := (others => '0');
v.ar := (others => '0');
v.sd.rstate := SD_INIT_IDLE;
when SD_CHECK_CMD16 =>
if r.ar(7 downto 0) /= zero32(7 downto 0) then
v.spio.errorn := '0';
else
v.spio.errorn := '1';
v.spio.initialized := '1';
v.sd.timeout := '0';
end if;
v.sd.state := SD_READY;
when SD_READY =>
v.spio.ready := '1';
v.sd.cmd := SD_CMD17;
v.sd.rstate := SD_CHECK_CMD17;
if read_flash then
v.sd.state := SD_SEND_CMD;
v.spio.ready := '0';
v.ar := (others => '0');
v.ar(r.haddr'left downto 2) := r.haddr(r.haddr'left downto 2);
end if;
when SD_CHECK_CMD17 =>
if r.ar(7 downto 0) /= X"00" then
v.sd.state := SD_READY;
v.spio.errorn := '0';
else
v.sd.rstate := SD_CHECK_TOKEN;
v.spio.csn := '0';
v.go := '1';
change := '1';
end if;
v.sd.dtocnt := cslv(SD_DATATOK_TIMEOUT, r.sd.dtocnt'length);
v.sd.state := SD_GET_RESP;
v.sd.vresp := '1';
v.hold := '0';
when SD_CHECK_TOKEN =>
if (r.ar(7 downto 5) = "111" and
r.sd.dtocnt /= zero32(r.sd.dtocnt'range)) then
v.sd.dtocnt := r.sd.dtocnt - 1;
v.sd.state := SD_GET_RESP;
if r.ar(0) = '0' then
v.sd.rstate := SD_HANDLE_DATA;
v.sd.rcnt := cslv(SD_BLEN-1, r.sd.rcnt'length);
end if;
v.spio.csn := '0';
v.go := '1';
change := '1';
else
v.spio.errorn := '0';
v.sd.state := SD_READY;
end if;
v.sd.timeout := not orv(r.sd.dtocnt);
v.sd.ctocnt := cslv(SD_CMD_TIMEOUT, r.sd.ctocnt'length);
v.hold := '0';
when SD_HANDLE_DATA =>
v.frdata := r.ar;
-- Receive and discard CRC
v.sd.state := SD_GET_RESP;
v.sd.rstate := SD_READY;
v.sd.htb := '1';
v.spio.csn := '0';
v.go := '1';
change := '1';
v.sd.vresp := '1';
v.spio.errorn := '1';
when SD_SEND_CMD =>
v.sd.htb := '1';
v.sd.vresp := '0';
v.spio.csn := '0';
v.sd.ctocnt := cslv(SD_CMD_TIMEOUT, r.sd.ctocnt'length);
if (v.bd or not r.go) = '1'then
v.hold := '0';
case r.sd.tcnt is
when "000" => v.sreg := "01" & r.sd.cmd;
v.hold := '1'; change := '1';
when "001" => v.sreg := r.ar(31 downto 24);
when "010" => v.sreg := r.ar(30 downto 23);
when "011" => v.sreg := r.ar(30 downto 23);
when "100" => v.sreg := r.ar(30 downto 23);
when "101" => v.sreg := SD_CRC_BYTE;
when others => v.sd.state := SD_GET_RESP;
end case;
v.go := '1';
v.sd.tcnt := r.sd.tcnt + 1;
end if;
when SD_GET_RESP =>
if v.bd = '1' then
if r.sd.vresp = '1' or r.sd.ctocnt = zero32(r.sd.ctocnt'range) then
if r.sd.rcnt = zero32(r.sd.rcnt'range) then
if r.sd.htb = '0' then
v.spio.csn := '1';
end if;
v.sd.htb := '0';
v.hold := '1';
else
v.sd.rcnt := r.sd.rcnt - 1;
end if;
else
v.sd.ctocnt := r.sd.ctocnt - 1;
end if;
end if;
if lastbit = '1' then
v.sd.vresp := r.sd.vresp or not r.ar(6);
if r.sd.rcnt = zero32(r.sd.rcnt'range) then
v.stop := r.sd.vresp and r.go and not r.sd.htb;
end if;
end if;
if r.sd.ctocnt = zero32(r.sd.ctocnt'range) then
v.stop := r.go;
end if;
if (r.go or r.spio.sck) = '0' then
v.sd.state := r.sd.rstate;
if r.sd.ctocnt = zero32(r.sd.ctocnt'range) then
if r.spio.initialized = '1' then
v.sd.state := SD_READY;
else
-- Try to initialize again
v.sd.state := SD_CHECK_PRES;
end if;
v.spio.errorn := '0';
v.sd.timeout := '1';
end if;
v.spio.csn := '1';
end if;
v.sd.tcnt := (others => '0');
when others => -- SD_CHECK_PRES
if r.sd.cd = '1' then
v.go := '1';
v.spio.csn := '0';
v.sd.state := SD_GET_RESP;
v.spio.cdcsnoen := OUTPUT;
end if;
v.sd.htb := '0';
v.sd.vresp := '1';
v.sd.rstate := SD_PWRUP0;
v.sd.rcnt := cslv(10, r.sd.rcnt'length);
v.sd.ctocnt := cslv(SD_CMD_TIMEOUT, r.sd.ctocnt'length);
end case;
end if;
---------------------------------------------------------------------------
-- SPI Flash (non SD) specific code
---------------------------------------------------------------------------
if sdcard = 0 then
case r.spi.state is
when SPI_READ =>
if r.go = '0' then
v.go := '1';
change := '1';
end if;
v.spi.cnt := cslv(SPI_ARG_LEN, r.spi.cnt'length);
if v.bd = '1' then
v.sreg := r.ar(23 downto 16);
end if;
if r.bd = '1' then
v.hold := '0';
v.spi.state := SPI_ADDR;
end if;
when SPI_ADDR =>
if v.bd = '1' then
v.sreg := r.ar(22 downto 15);
if dualoutput = 1 then
if r.spi.cnt = zero32(r.spi.cnt'range) then
v.spio.mosioen := INPUT;
end if;
end if;
end if;
if r.bd = '1' then
if r.spi.cnt = zero32(r.spi.cnt'range) then
v.spi.state := SPI_DATA;
v.spi.cnt := calc_spi_cnt(r.spi.hsize);
else
v.spi.cnt := r.spi.cnt - 1;
end if;
end if;
when SPI_DATA =>
if v.bd = '1' then
v.spi.cnt := r.spi.cnt - 1;
end if;
if lastbit = '1' and r.spi.cnt = zero32(r.spi.cnt'range) then
v.stop := r.go;
end if;
if (r.go or r.spio.sck) = '0' then
if r.spi.hburst(0) = '0' then -- not an incrementing burst
v.spi.state := SPI_PWRUP; -- CSN wait
v.spio.csn := '1';
v.go := '1';
v.stop := '1';
v.seq := '1'; -- Make right choice in SPI_PWRUP
v.bcnt := "110";
else
v.spi.state := SPI_READY;
end if;
v.hold := '1';
end if;
when SPI_READY =>
v.spio.ready := '1';
if read_flash then
v.go := '1';
if dualoutput = 1 then
v.bcnt(2) := '0';
end if;
if r.spio.csn = '1' then
-- New access, command and address
v.go := '0';
v.spio.csn := '0';
v.spi.state := SPI_READ;
elsif r.seq = '1' then
-- Continuation of burst
v.spi.state := SPI_DATA;
v.hold := '0';
else
-- Burst ended and new access
v.stop := '1';
v.spio.csn := '1';
v.spi.state := SPI_PWRUP;
v.bcnt := "011";
end if;
v.ar := (others => '0');
if offset /= 0 then
v.ar(r.haddr'range) := r.haddr + cslv(offset, req_addr_bits);
else
v.ar(r.haddr'range) := r.haddr;
end if;
v.spio.ready := '0';
v.sreg := cslv(readcmd, 8);
end if;
if r.spio.ready = '0' then
case r.spi.hsize is
when HSIZE_BYTE =>
for i in 0 to (MAXDW/8-1) loop
v.frdata(7+8*i downto 8*i):= r.ar(7 downto 0);
end loop; -- i
when HSIZE_HWORD =>
for i in 0 to (MAXDW/16-1) loop
v.frdata(15+16*i downto 16*i) := r.ar(15 downto 0);
end loop; -- i
when HSIZE_WORD =>
for i in 0 to (MAXDW/32-1) loop
v.frdata(31+32*i downto 32*i) := r.ar(31 downto 0);
end loop; -- i
when HSIZE_DWORD =>
if MAXDW > 32 and AHBDW > 32 then
for i in 0 to (MAXDW/64-1) loop
if MAXDW = 64 then
v.frdata(MAXDW-1+MAXDW*i downto MAXDW*i) :=
r.ar(MAXDW-1 downto 0);
elsif MAXDW = 128 then
v.frdata(MAXDW/2-1+MAXDW/2*i downto MAXDW/2*i) :=
r.ar(MAXDW/2-1 downto 0);
else
v.frdata(MAXDW/4-1+MAXDW/4*i downto MAXDW/4*i) :=
r.ar(MAXDW/4-1 downto 0);
end if;
end loop; -- i
else
null;
end if;
when HSIZE_4WORD =>
if MAXDW > 64 and AHBDW > 64 then
for i in 0 to (MAXDW/128-1) loop
if MAXDW = 128 then
v.frdata(MAXDW-1+MAXDW*i downto MAXDW*i) :=
r.ar(MAXDW-1 downto 0);
else
v.frdata(MAXDW/2-1+MAXDW/2*i downto MAXDW/2*i) :=
r.ar(MAXDW/2-1 downto 0);
end if;
end loop; -- i
else
null;
end if;
when others =>
if MAXDW > 128 and AHBDW > 128 then
v.frdata := r.ar;
else
null;
end if;
end case;
end if;
v.spi.hsize := r.hsize;
v.spi.hburst(0) := r.hburst(0);
v.spi.cnt := calc_spi_cnt(r.spi.hsize);
when others => -- SPI_PWRUP
v.hold := '1';
if r.spio.initialized = '1' then
-- Chip select wait
if (r.go or r.spio.sck) = '0' then
if r.seq = '1' then
v.spi.state := SPI_READY;
else
v.spi.state := SPI_READ;
v.spio.csn := '0';
end if;
if dualoutput = 1 then
v.spio.mosioen := OUTPUT;
v.bcnt(2) := '0';
end if;
end if;
else
-- Power up wait
if pwrupcnt /= 0 then
v.frdata := r.frdata - 1;
if r.frdata = zahbdw(r.frdata'range) then
v.spio.initialized := '1';
v.spi.state := SPI_READY;
end if;
else
v.spio.initialized := '1';
v.spi.state := SPI_READY;
end if;
end if;
end case;
end if;
---------------------------------------------------------------------------
-- SPI communication
---------------------------------------------------------------------------
-- Clock generation
if (r.go or r.spio.sck) = '1' then
v.timer := r.timer - 1;
if sck_toggle(v.timer, r.timer, enable_altscaler) then
v.spio.sck := not r.spio.sck;
v.sample(0) := not r.spio.sck;
change := r.spio.sck and r.go;
if (v.stop and lastbit and not r.spio.sck) = '1' then
v.go := '0';
v.stop := '0';
end if;
end if;
else
v.timer := (others => '1');
end if;
if r.sample(0) = '1' then
v.bcnt := r.bcnt + 1;
end if;
if r.sample(1-sdcard) = '1' then
if r.hold = '0' then
if sdcard = 0 and dualoutput = 1 and r.spio.mosioen = INPUT then
v.ar := r.ar(r.ar'left-2 downto 0) & r.spii(1-sdcard).miso & r.spii(1-sdcard).mosi;
else
v.ar := r.ar(r.ar'left-1 downto 0) & r.spii(1-sdcard).miso;
end if;
end if;
end if;
if change = '1' then
v.spio.mosi := v.sreg(7);
if sdcard = 1 or r.spi.state /= SPI_PWRUP then
v.sreg(7 downto 0) := v.sreg(6 downto 0) & '1';
end if;
end if;
---------------------------------------------------------------------------
-- System and core reset
---------------------------------------------------------------------------
if (not rstn or r.rst) = '1' then
if sdcard = 1 then
v.sd.state := SD_CHECK_PRES;
v.spio.cdcsnoen := INPUT;
v.sd.timeout := '0';
else
v.spi.state := SPI_PWRUP;
v.frdata := cslv(pwrupcnt, r.frdata'length);
v.spio.cdcsnoen := OUTPUT;
end if;
v.spimstate := IDLE;
v.rst := '0';
--
v.reg.ctrl := ('0', '0', '0');
v.reg.stat.done := '0';
--
v.sample := (others => '0');
v.sreg := (others => '1');
v.bcnt := (others => '0');
v.go := '0';
v.stop := '0';
v.hold := '0';
v.unsplit := '0';
--
v.hready := '1';
v.hwrite := '0';
v.hsel := '0';
v.hmbsel := (others => '0');
v.ahbcancel := '0';
--
v.spio.sck := '0';
v.spio.mosi := '1';
v.spio.mosioen := OUTPUT;
v.spio.csn := '1';
v.spio.errorn := '1';
v.spio.initialized := '0';
v.spio.ready := '0';
end if;
---------------------------------------------------------------------------
-- Drive unused signals
---------------------------------------------------------------------------
if sdcard = 1 then
v.spi.state := SPI_PWRUP;
v.spi.cnt := (others => '0');
v.spi.hsize := (others => '0');
v.spi.hburst := (others => '0');
v.hburst := (others => '0');
v.seq := '0';
else
v.sd.state := SD_CHECK_PRES;
v.sd.tcnt := (others => '0');
v.sd.rcnt := (others => '0');
v.sd.cmd := (others => '0');
v.sd.rstate := SD_CHECK_PRES;
v.sd.htb := '0';
v.sd.vresp := '0';
v.sd.timeout := '0';
v.sd.dtocnt := (others => '0');
v.sd.ctocnt := (others => '0');
end if;
if spliten = 0 then
v.insplit := '0';
v.unsplit := '0';
v.splmst := (others => '0');
v.hsplit := (others => '0');
v.ahbcancel := '0';
end if;
---------------------------------------------------------------------------
-- Signal assignments
---------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB slave output
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
if r.hmbsel(CTRL_BANK) = '1' then
for i in 0 to (MAXDW/32-1) loop
hrdata(31 + 32*i downto 32*i) := zero32(31 downto 8) & r.rrdata;
end loop;
else
hrdata := r.frdata;
end if;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hconfig <= HCONFIG;
ahbso.hirq <= ahbirq;
ahbso.hindex <= hindex;
ahbso.hsplit <= hsplit;
-- SPI signals
spio <= r.spio;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"spimctrl" & tost(hindex) & ": SPI memory controller rev " &
tost(REVISION) & ", irq " & tost(hirq));
-- pragma translate_on
end rtl;
| gpl-2.0 | 346d583d549e856f7ef59916af5feb64 | 0.45064 | 3.836786 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/micron/sdram/components.vhd | 2 | 13,707 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declaration of Micron SDRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package components is
component mt48lc16m16a2
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
component mt46v16m16
GENERIC ( -- Timing for -75Z CL2
tCK : TIME := 7.500 ns;
tCH : TIME := 3.375 ns; -- 0.45*tCK
tCL : TIME := 3.375 ns; -- 0.45*tCK
tDH : TIME := 0.500 ns;
tDS : TIME := 0.500 ns;
tIH : TIME := 0.900 ns;
tIS : TIME := 0.900 ns;
tMRD : TIME := 15.000 ns;
tRAS : TIME := 40.000 ns;
tRAP : TIME := 20.000 ns;
tRC : TIME := 65.000 ns;
tRFC : TIME := 75.000 ns;
tRCD : TIME := 20.000 ns;
tRP : TIME := 20.000 ns;
tRRD : TIME := 15.000 ns;
tWR : TIME := 15.000 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
cols_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec"; -- File to read from
bbits : INTEGER := 16;
fdelay : INTEGER := 0;
chktiming : boolean := true
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END component;
component ftmt48lc16m16a2
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec"; -- File to read from
err : INTEGER := 0
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
component ddr2 is
generic(
DM_BITS : integer := 2;
ADDR_BITS : integer := 13;
ROW_BITS : integer := 13;
COL_BITS : integer := 9;
DQ_BITS : integer := 16;
DQS_BITS : integer := 2;
TRRD : integer := 10000;
TFAW : integer := 50000;
DEBUG : integer := 0
);
port (
ck : in std_ulogic;
ck_n : in std_ulogic;
cke : in std_ulogic;
cs_n : in std_ulogic;
ras_n : in std_ulogic;
cas_n : in std_ulogic;
we_n : in std_ulogic;
dm_rdqs : inout std_logic_vector(DQS_BITS-1 downto 0);
ba : in std_logic_vector(1 downto 0);
addr : in std_logic_vector(ADDR_BITS-1 downto 0);
dq : inout std_logic_vector(DQ_BITS-1 downto 0);
dqs : inout std_logic_vector(DQS_BITS-1 downto 0);
dqs_n : inout std_logic_vector(DQS_BITS-1 downto 0);
rdqs_n : out std_logic_vector(DQS_BITS-1 downto 0);
odt : in std_ulogic
);
end component;
component mobile_ddr
--GENERIC ( -- Timing for -75Z CL2
-- tCK : TIME := 7.500 ns;
-- tCH : TIME := 3.375 ns; -- 0.45*tCK
-- tCL : TIME := 3.375 ns; -- 0.45*tCK
-- tDH : TIME := 0.500 ns;
-- tDS : TIME := 0.500 ns;
-- tIH : TIME := 0.900 ns;
-- tIS : TIME := 0.900 ns;
-- tMRD : TIME := 15.000 ns;
-- tRAS : TIME := 40.000 ns;
-- tRAP : TIME := 20.000 ns;
-- tRC : TIME := 65.000 ns;
-- tRFC : TIME := 75.000 ns;
-- tRCD : TIME := 20.000 ns;
-- tRP : TIME := 20.000 ns;
-- tRRD : TIME := 15.000 ns;
-- tWR : TIME := 15.000 ns;
-- addr_bits : INTEGER := 13;
-- data_bits : INTEGER := 16;
-- cols_bits : INTEGER := 9;
-- index : INTEGER := 0;
-- fname : string := "ram.srec"; -- File to read from
-- bbits : INTEGER := 32
--);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
----Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'Z');
----Dqs : INOUT STD_LOGIC_VECTOR (data_bits/8 - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
----Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
----Dm : IN STD_LOGIC_VECTOR (data_bits/8 - 1 DOWNTO 0)
);
END component;
component mobile_ddr_fe
port (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
BEaddr: out std_logic_vector (24 downto 0);
BEwr : out std_logic_vector(1 downto 0);
BEdin : out std_logic_vector(15 downto 0);
BEdout: in std_logic_vector(15 downto 0);
BEclear: out std_logic;
BEclrpart: out std_logic;
BEsynco: out std_logic;
BEsynci: in std_logic
);
end component;
component mobile_ddr_febe
generic (
dbits: integer := 32;
rampad: integer := 0;
fname: string := "dummy";
autoload: integer := 1;
rstmode: integer := 0;
rstdatah: integer := 16#DEAD#;
rstdatal: integer := 16#BEEF#
);
port (
Dq : INOUT STD_LOGIC_VECTOR (dbits-1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (dbits/8-1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (dbits/8-1 DOWNTO 0)
);
end component;
component mobile_ddr2_fe
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ca : in std_logic_vector( 9 downto 0);
dm : in std_logic_vector( 1 downto 0);
dq : inout std_logic_vector(15 downto 0) := (OTHERS => 'Z');
dqs : inout std_logic_vector( 1 downto 0) := (OTHERS => 'Z');
dqs_n : inout std_logic_vector( 1 downto 0) := (OTHERS => 'Z');
BEaddr : out std_logic_vector(27 downto 0);
BEwr_h : out std_logic_vector( 1 downto 0);
BEwr_l : out std_logic_vector( 1 downto 0);
BEdin_h : out std_logic_vector(15 downto 0);
BEdin_l : out std_logic_vector(15 downto 0);
BEdout_h: in std_logic_vector(15 downto 0);
BEdout_l: in std_logic_vector(15 downto 0);
BEclear : out std_logic;
BEreload: out std_logic;
BEsynco : out std_logic;
BEsynci : in std_logic
);
end component;
component mobile_ddr2_febe
generic (
dbits: integer := 32;
rampad: integer := 0;
fname: string := "dummy";
autoload: integer := 1;
rstmode: integer := 0;
rstdatah: integer := 16#DEAD#;
rstdatal: integer := 16#BEEF#
);
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ca : in std_logic_vector( 9 downto 0);
dm : in std_logic_vector(dbits/8-1 downto 0);
dq : inout std_logic_vector( dbits-1 downto 0) := (OTHERS => 'Z');
dqs : inout std_logic_vector(dbits/8-1 downto 0) := (OTHERS => 'Z');
dqs_n : inout std_logic_vector(dbits/8-1 downto 0) := (OTHERS => 'Z')
);
end component;
component mobile_sdr
--GENERIC (
-- DEBUG : INTEGER := 1;
-- addr_bits : INTEGER := 13;
-- data_bits : INTEGER := 16
--);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
end component;
end;
-- pragma translate_on
| gpl-2.0 | 522abf15ddd220bb2ae9439e03a0f4aa | 0.452105 | 3.318083 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml501/config.vhd | 1 | 7,221 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex5;
constant CFG_MEMTECH : integer := virtex5;
constant CFG_PADTECH : integer := virtex5;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex5;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 8;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000030#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (140);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (15);
constant CFG_DDR2SP_DELAY1 : integer := (15);
constant CFG_DDR2SP_DELAY2 : integer := (15);
constant CFG_DDR2SP_DELAY3 : integer := (15);
constant CFG_DDR2SP_DELAY4 : integer := (15);
constant CFG_DDR2SP_DELAY5 : integer := (15);
constant CFG_DDR2SP_DELAY6 : integer := (15);
constant CFG_DDR2SP_DELAY7 : integer := (15);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (14);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- AMBA Wrapper for Xilinx System Monitor
constant CFG_GRSYSMON : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | d8bf0b3e8c28e9cf3001a047438ceef9 | 0.649633 | 3.553642 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Stack/src/TestBench/ctrl1_TB.vhd | 1 | 3,757 | library stack;
use stack.OneHotStack.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity ctrl1_tb is
end ctrl1_tb;
architecture TB_ARCHITECTURE of ctrl1_tb is
component MROM is
port (
RE: in std_logic;
ADDR: in mem_addr;
DOUT: out command
);
end component;
component MRAM is
port (
CLK: in std_logic;
RW: in std_logic;
ADDR: in mem_addr;
DIN: in operand;
DOUT: out operand
);
end component;
component DPATH is
port(
EN: in std_logic;
CLK: in std_logic;
OT: in operation;
OP: in operand;
RES: out operand;
ZF: out std_logic;
Stop: out std_logic
);
end component;
-- Component declaration of the tested unit
component ctrl1
port(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Start : in STD_LOGIC;
Stop : out STD_LOGIC;
ROM_re : out STD_LOGIC;
ROM_addr : out mem_addr;
ROM_dout : in command;
RAM_rw : out STD_LOGIC;
RAM_addr : out mem_addr;
RAM_din : out operand;
RAM_dout : in operand;
DP_op : out operand;
DP_ot : out operation;
DP_en : out STD_LOGIC;
DP_res : in operand;
DP_zf : in STD_LOGIC;
DP_stop : in STD_LOGIC );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal CLK : STD_LOGIC;
signal RST : STD_LOGIC;
signal Start : STD_LOGIC;
signal ROM_dout : command;
signal RAM_dout : operand;
signal DP_res : operand;
signal DP_zf : STD_LOGIC;
signal DP_stop : STD_LOGIC;
-- Observed signals - signals mapped to the output ports of tested entity
signal Stop : STD_LOGIC;
signal ROM_re : STD_LOGIC;
signal ROM_addr : mem_addr;
signal RAM_rw : STD_LOGIC;
signal RAM_addr : mem_addr;
signal RAM_din : operand;
signal DP_op : operand;
signal DP_ot : operation;
signal DP_en : STD_LOGIC;
constant CLK_period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : ctrl1
port map (
CLK => CLK,
RST => RST,
Start => Start,
Stop => Stop,
ROM_re => ROM_re,
ROM_addr => ROM_addr,
ROM_dout => ROM_dout,
RAM_rw => RAM_rw,
RAM_addr => RAM_addr,
RAM_din => RAM_din,
RAM_dout => RAM_dout,
DP_op => DP_op,
DP_ot => DP_ot,
DP_en => DP_en,
DP_res => DP_res,
DP_zf => DP_zf,
DP_stop => DP_stop
);
UMRAM: MRAM
port map(
CLK => CLK,
RW => ram_rw,
ADDR => ram_addr,
DIN => ram_din,
DOUT => ram_dout
);
UMROM: entity MROM (Beh_Stack)
port map (
RE => rom_re,
ADDR => rom_addr,
DOUT => rom_dout
);
UDPATH: DPATH
port map(
EN => dp_en,
CLK => CLK,
OT => dp_ot,
OP => dp_op,
RES => dp_res,
ZF => dp_zf,
STOP => dp_stop
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
main: process
begin
rst <= '1';
wait for 1 * CLK_PERIOD;
rst <= '0';
start <= '1';
wait for 100 * CLK_PERIOD;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_ctrl1 of ctrl1_tb is
for TB_ARCHITECTURE
for UUT : ctrl1
use entity work.ctrl1(beh_stack);
end for;
end for;
end TESTBENCH_FOR_ctrl1;
| mit | 2630155c8b26f7116ea55db16ee97c48 | 0.523556 | 3.369507 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/misc.vhd | 1 | 45,771 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: misc
-- File: misc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Misc models
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package misc is
-- reset generator with filter
component rstgen
generic (acthigh : integer := 0; syncrst : integer := 0;
scanen : integer := 0; syncin : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0');
end component;
type gptimer_in_type is record
dhalt : std_ulogic;
extclk : std_ulogic;
wdogen : std_ulogic;
end record;
type gptimer_in_vector is array (natural range <>) of gptimer_in_type;
type gptimer_out_type is record
tick : std_logic_vector(0 to 7);
timer1 : std_logic_vector(31 downto 0);
wdogn : std_ulogic;
wdog : std_ulogic;
end record;
type gptimer_out_vector is array (natural range <>) of gptimer_out_type;
constant gptimer_in_none : gptimer_in_type := ('0', '0', '0');
constant gptimer_out_none : gptimer_out_type :=
((others => '0'), (others => '0'), '1', '0');
component gptimer
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0;
ewdogen : integer := 0;
glatch : integer := 0;
gextclk : integer := 0;
gset : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end component;
-- 32-bit ram with AHB interface
component ahbram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
end component;
type ahbram_out_type is record
ce : std_ulogic;
end record;
component ftahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer := 1;
autoscrub : integer := 0;
errcnten : integer := 0;
cntbits : integer range 1 to 8 := 1;
ahbpipe : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ftahbram2 is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
testen : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ahbdpram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := 2;
abits : integer range 8 to 19 := 8;
bytewrite : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
clkdp : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
enable : in std_ulogic; -- active high chip select
write : in std_logic_vector(0 to 3) -- active high byte write enable
); -- big-endian write: bwrite(0) => data(31:24)
end component;
component ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type
);
end component;
component ahbtrace_mmb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
ntrace : integer range 1 to 8 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmiv : in ahb_mst_in_vector_type(0 to ntrace-1); -- Trace
tahbsiv : in ahb_slv_in_vector_type(0 to ntrace-1)
);
end component;
type ahbmst2_request is record
req: std_logic; -- Request enable bit
wr: std_logic;
hsize: std_logic_vector(2 downto 0);
hburst: std_logic_vector(2 downto 0);
hprot: std_logic_vector(3 downto 0);
addr: std_logic_vector(32-1 downto 0);
burst_cont: std_logic; -- Set for all except the first request in a burst
burst_wrap: std_logic; -- High for the request where wrap occurs
end record;
constant ahbmst2_request_none: ahbmst2_request := (
req => '0', wr => '0', hsize => "010", hburst => "000", burst_cont => '0',
burst_wrap => '0', addr => (others => '0'), hprot => "0011");
type ahbmst2_in_type is record
request: ahbmst2_request;
wrdata: std_logic_vector(AHBDW-1 downto 0);
-- For back-to-back transfers or bursts, this must be set when done is high
-- and then copied over to request after the rising edge of clk.
next_request: ahbmst2_request;
-- Insert busy cycle, must only be asserted when request and next_request
-- are both part of the same burst.
busy: std_logic;
hlock: std_logic; -- Lock signal, passed through directly to AMBA.
keepreq: std_logic; -- Keep bus request high even when no request needs it.
end record;
type ahbmst2_out_type is record
done: std_logic;
flip: std_logic;
fail: std_logic;
rddata: std_logic_vector(AHBDW-1 downto 0);
end record;
component ahbmst2 is
generic (
hindex: integer := 0;
venid: integer;
devid: integer;
version: integer;
dmastyle: integer range 1 to 3 := 3;
syncrst: integer range 0 to 1 := 1
);
port (
clk: in std_logic;
rst: in std_logic;
ahbi: in ahb_mst_in_type;
ahbo: out ahb_mst_out_type;
m2i: in ahbmst2_in_type;
m2o: out ahbmst2_out_type
);
end component;
type gpio_in_type is record
din : std_logic_vector(31 downto 0);
sig_in : std_logic_vector(31 downto 0);
sig_en : std_logic_vector(31 downto 0);
end record;
type gpio_in_vector is array (natural range <>) of gpio_in_type;
type gpio_out_type is record
dout : std_logic_vector(31 downto 0);
oen : std_logic_vector(31 downto 0);
val : std_logic_vector(31 downto 0);
sig_out : std_logic_vector(31 downto 0);
end record;
type gpio_out_vector is array (natural range <>) of gpio_out_type;
component grgpio
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0;
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#;
pirq : integer := 0;
irqgen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end component;
type ahb2ahb_ctrl_type is record
slck : std_ulogic;
blck : std_ulogic;
mlck : std_ulogic;
end record;
constant ahb2ahb_ctrl_none : ahb2ahb_ctrl_type := ('0', '0', '0');
type ahb2ahb_ifctrl_type is record
mstifen : std_ulogic;
slvifen : std_ulogic;
end record;
constant ahb2ahb_ifctrl_none : ahb2ahb_ifctrl_type := ('1', '1');
component ahb2ahb
generic(
memtech : integer := 0;
hsindex : integer := 0;
hmindex : integer := 0;
slv : integer range 0 to 1 := 0;
dir : integer range 0 to 1 := 0; -- 0 - down, 1 - up
ffact : integer range 0 to 15:= 2;
pfen : integer range 0 to 1 := 0;
wburst : integer range 2 to 32 := 8;
iburst : integer range 4 to 8 := 8;
rburst : integer range 2 to 32 := 8;
irqsync : integer range 0 to 2 := 0;
bar0 : integer range 0 to 1073741823 := 0;
bar1 : integer range 0 to 1073741823 := 0;
bar2 : integer range 0 to 1073741823 := 0;
bar3 : integer range 0 to 1073741823 := 0;
sbus : integer := 0;
mbus : integer := 0;
ioarea : integer := 0;
ibrsten : integer := 0;
lckdac : integer range 0 to 2 := 0;
slvmaccsz : integer range 32 to 256 := 32;
mstmaccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
ifctrlen : integer range 0 to 1 := 0;
fcfs : integer range 0 to NAHBMST := 0;
fcfsmtech : integer range 0 to NTECH := inferred;
scantest : integer range 0 to 1 := 0;
split : integer range 0 to 1 := 1;
pipe : integer range 0 to 128 := 0);
port (
rstn : in std_ulogic;
hclkm : in std_ulogic;
hclks : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbso2 : in ahb_slv_out_vector;
lcki : in ahb2ahb_ctrl_type;
lcko : out ahb2ahb_ctrl_type;
ifctrl : in ahb2ahb_ifctrl_type := ahb2ahb_ifctrl_none
);
end component;
component ahbbridge
generic(
memtech : integer := 0;
ffact : integer range 0 to 15 := 2;
-- high-speed bus
hsb_hsindex : integer := 0;
hsb_hmindex : integer := 0;
hsb_iclsize : integer range 4 to 8 := 8;
hsb_bank0 : integer range 0 to 1073741823 := 0;
hsb_bank1 : integer range 0 to 1073741823 := 0;
hsb_bank2 : integer range 0 to 1073741823 := 0;
hsb_bank3 : integer range 0 to 1073741823 := 0;
hsb_ioarea : integer := 0;
-- low-speed bus
lsb_hsindex : integer := 0;
lsb_hmindex : integer := 0;
lsb_rburst : integer range 16 to 32 := 16;
lsb_wburst : integer range 2 to 32 := 8;
lsb_bank0 : integer range 0 to 1073741823 := 0;
lsb_bank1 : integer range 0 to 1073741823 := 0;
lsb_bank2 : integer range 0 to 1073741823 := 0;
lsb_bank3 : integer range 0 to 1073741823 := 0;
lsb_ioarea : integer := 0;
--
lckdac : integer range 0 to 2 := 2;
maccsz : integer range 32 to 256 := 32;
rdcomb : integer range 0 to 2 := 0;
wrcomb : integer range 0 to 2 := 0;
combmask : integer := 16#ffff#;
allbrst : integer range 0 to 2 := 0;
fcfs : integer range 0 to NAHBMST := 0;
scantest : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
hsb_clk : in std_ulogic;
lsb_clk : in std_ulogic;
hsb_ahbsi : in ahb_slv_in_type;
hsb_ahbso : out ahb_slv_out_type;
hsb_ahbsov : in ahb_slv_out_vector;
hsb_ahbmi : in ahb_mst_in_type;
hsb_ahbmo : out ahb_mst_out_type;
lsb_ahbsi : in ahb_slv_in_type;
lsb_ahbso : out ahb_slv_out_type;
lsb_ahbsov : in ahb_slv_out_vector;
lsb_ahbmi : in ahb_mst_in_type;
lsb_ahbmo : out ahb_mst_out_type);
end component;
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer;
type ahbstat_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
end record;
component ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
type nuhosp3_in_type is record
flash_d : std_logic_vector(15 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_ardy : std_ulogic;
smsc_intr : std_ulogic;
smsc_nldev : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
end record;
type nuhosp3_out_type is record
flash_a : std_logic_vector(20 downto 0);
flash_d : std_logic_vector(15 downto 0);
flash_oen : std_ulogic;
flash_wen : std_ulogic;
flash_cen : std_ulogic;
smsc_addr : std_logic_vector(14 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_nbe : std_logic_vector(3 downto 0);
smsc_resetn : std_ulogic;
smsc_nrd : std_ulogic;
smsc_nwr : std_ulogic;
smsc_ncs : std_ulogic;
smsc_aen : std_ulogic;
smsc_lclk : std_ulogic;
smsc_wnr : std_ulogic;
smsc_rdyrtn : std_ulogic;
smsc_cycle : std_ulogic;
smsc_nads : std_ulogic;
smsc_ben : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
lcd_rs : std_ulogic;
lcd_rw : std_ulogic;
lcd_en : std_ulogic;
lcd_backl : std_ulogic;
lcd_ben : std_ulogic;
end record;
component nuhosp3
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
ioaddr : integer := 16#200#;
iomask : integer := 16#fff#);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
nui : in nuhosp3_in_type;
nuo : out nuhosp3_out_type
);
end component;
-- On-chip Logic Analyzer
component logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0;
usediv : integer range 0 to 1 := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic;
clk : in std_logic;
tclk : in std_logic;
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end component;
type ps2_in_type is record
ps2_clk_i : std_ulogic;
ps2_data_i : std_ulogic;
end record;
type ps2_out_type is record
ps2_clk_o : std_ulogic;
ps2_clk_oe : std_ulogic;
ps2_data_o : std_ulogic;
ps2_data_oe : std_ulogic;
end record;
component apbps2
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 0;
oepol : integer range 0 to 1 := 0);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end component;
type apbvga_out_type is record
hsync : std_ulogic; -- horizontal sync
vsync : std_ulogic; -- vertical sync
comp_sync : std_ulogic; -- composite sync
blank : std_ulogic; -- blank signal
video_out_r : std_logic_vector(7 downto 0); -- red channel
video_out_g : std_logic_vector(7 downto 0); -- green channel
video_out_b : std_logic_vector(7 downto 0); -- blue channel
bitdepth : std_logic_vector(1 downto 0); -- Bith depth
end record;
component apbvga
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end component;
component svgactrl
generic(
length : integer := 384; -- Fifo-length
part : integer := 128; -- Fifo-part lenght
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8;
ahbaccsz : integer := 32;
asyncrst : integer range 0 to 1 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0);
arst : in std_ulogic := '1'
);
end component;
constant vgao_none : apbvga_out_type :=
('0', '0', '0', '0', "00000000", "00000000", "00000000", "00");
constant ps2o_none : ps2_out_type := ('1', '1', '1', '1');
-- component ahbrom
-- generic (
-- hindex : integer := 0;
-- haddr : integer := 0;
-- hmask : integer := 16#fff#;
-- pipe : integer := 0;
-- tech : integer := 0;
-- kbytes : integer := 1);
-- port (
-- rst : in std_ulogic;
-- clk : in std_ulogic;
-- ahbsi : in ahb_slv_in_type;
-- ahbso : out ahb_slv_out_type
-- );
-- end component;
component ahbdma
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
dbuf : integer := 0);
port (
rst : in std_logic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for FIFO controller
-----------------------------------------------------------------------------
type FIFO_In_Type is record
Din: Std_Logic_Vector(31 downto 0); -- data input
Pin: Std_Logic_Vector( 3 downto 0); -- parity input
EFn: Std_ULogic; -- empty flag
FFn: Std_ULogic; -- full flag
HFn: Std_ULogic; -- half flag
end record;
type FIFO_Out_Type is record
Dout: Std_Logic_Vector(31 downto 0); -- data output
Den: Std_Logic_Vector(31 downto 0); -- data enable
Pout: Std_Logic_Vector( 3 downto 0); -- parity output
Pen: Std_Logic_Vector( 3 downto 0); -- parity enable
WEn: Std_ULogic; -- write enable
REn: Std_ULogic; -- read enable
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR FIFO Interface
-----------------------------------------------------------------------------
component grfifo is
generic (
hindex: Integer := 0;
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
dwidth: Integer := 16; -- data width
ptrwidth: Integer range 16 to 16 := 16; -- 16 to 64k bytes
-- 128 to 512k bits
singleirq: Integer range 0 to 1 := 0; -- single irq output
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
ahbi: in AHB_Mst_In_Type;
ahbo: out AHB_Mst_Out_Type;
fifoi: in FIFO_In_Type;
fifoo: out FIFO_Out_Type);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for CAN controllers
-----------------------------------------------------------------------------
type Analog_In_Type is record
Ain: Std_Logic_Vector(31 downto 0); -- address input
Din: Std_Logic_Vector(31 downto 0); -- data input
Rdy: Std_ULogic; -- adc ready input
Trig: Std_Logic_Vector( 2 downto 0); -- adc trigger inputs
end record;
type Analog_Out_Type is record
Aout: Std_Logic_Vector(31 downto 0); -- address output
Aen: Std_Logic_Vector(31 downto 0); -- address enable
Dout: Std_Logic_Vector(31 downto 0); -- dac data output
Den: Std_Logic_Vector(31 downto 0); -- dac data enable
Wr: Std_ULogic; -- dac write strobe
CS: Std_ULogic; -- adc chip select
RC: Std_ULogic; -- adc read/convert
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR ADC/DAC Interface
-----------------------------------------------------------------------------
component gradcdac is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
awidth: Integer := 8; -- address width
dwidth: Integer := 16; -- data width
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
adi: in Analog_In_Type;
ado: out Analog_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AMBA wrapper for System Monitor
-----------------------------------------------------------------------------
type grsysmon_in_type is record
convst : std_ulogic;
convstclk : std_ulogic;
vauxn : std_logic_vector(15 downto 0);
vauxp : std_logic_vector(15 downto 0);
vn : std_ulogic;
vp : std_ulogic;
end record;
type grsysmon_out_type is record
alm : std_logic_vector(2 downto 0);
ot : std_ulogic;
eoc : std_ulogic;
eos : std_ulogic;
channel : std_logic_vector(4 downto 0);
end record;
constant grsysmon_in_gnd : grsysmon_in_type :=
('0', '0', (others => '0'), (others => '0'), '0', '0');
component grsysmon
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
caddr : integer := 16#000#; -- Base address for configuration area
cmask : integer := 16#fff#; -- Area mask
saddr : integer := 16#001#; -- Base address for sysmon register area
smask : integer := 16#fff#; -- Area mask
split : integer := 0; -- Enable AMBA SPLIT support
extconvst : integer := 0; -- Use external CONVST signal
wrdalign : integer := 0; -- Word align System Monitor registers
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "sysmon.txt");
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sysmoni : in grsysmon_in_type;
sysmono : out grsysmon_out_type
);
end component;
-----------------------------------------------------------------------------
-- AMBA System ACE Interface Controller
-----------------------------------------------------------------------------
type gracectrl_in_type is record
di : std_logic_vector(15 downto 0);
-- brdy : std_ulogic;
irq : std_ulogic;
end record;
type gracectrl_out_type is record
addr : std_logic_vector(6 downto 0);
do : std_logic_vector(15 downto 0);
cen : std_ulogic;
wen : std_ulogic;
oen : std_ulogic;
doen : std_ulogic; -- Data output enable to pad
end record;
constant gracectrl_none : gracectrl_out_type :=
((others => '1'), (others => '1'), '1', '1', '1', '1');
component gracectrl
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
haddr : integer := 16#000#; -- Base address
hmask : integer := 16#fff#; -- Area mask
split : integer range 0 to 1 := 0; -- Enable AMBA SPLIT support
swap : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0; -- Output enable polarity
mode : integer range 0 to 2 := 0 -- 16/8-bit mode
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
clkace : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
acei : in gracectrl_in_type;
aceo : out gracectrl_out_type
);
end component;
-----------------------------------------------------------------------------
-- General purpose register
-----------------------------------------------------------------------------
component grgpreg is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer range 1 to 64 := 16;
rstval : integer := 0;
rstval2 : integer := 0;
extrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gprego : out std_logic_vector(nbits-1 downto 0);
resval : in std_logic_vector(nbits-1 downto 0) := (others => '0')
);
end component;
component grgprbank is
generic (
pindex: integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
regbits: integer range 1 to 32 := 32;
nregs : integer range 1 to 32 := 1;
rstval: integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
rego : out std_logic_vector(nregs*regbits-1 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- EDAC Memory scrubber
-----------------------------------------------------------------------------
type memscrub_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
clrcount: std_logic;
start : std_logic;
end record;
component memscrub is
generic(
hmindex : integer := 0;
hsindex : integer := 0;
ioaddr : integer := 0;
iomask : integer := 16#FFF#;
hirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3;
memwidth: integer := AHBDW;
-- Read block (cache line) burst size, must be even mult of 2
burstlen: integer := 2;
countlen: integer := 8
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
scrubi: in memscrub_in_type
);
end component;
type ahb_mst_iface_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type ahb_mst_iface_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
component ahb_mst_iface is
generic(
hindex : integer;
vendor : integer;
device : integer;
revision : integer);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
msti : in ahb_mst_iface_in_type;
msto : out ahb_mst_iface_out_type
);
end component;
-----------------------------------------------------------------------------
-- Clock gate unit
-----------------------------------------------------------------------------
component grclkgate
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
ungateen : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0); -- Only used with shared FPU
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2)*(ncpu/2-1) downto 0); -- Only used with shared FPU
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic);
end component;
component grclkgate2x
generic (
tech : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
nclks : integer := 8;
emask : integer := 0;
extemask : integer := 0;
scantest : integer := 0;
edges : integer := 0;
noinv : integer := 0; -- Do not use inverted clock on gate enable
fpush : integer range 0 to 2 := 0;
clk2xen : integer := 0; -- Enable double clocking
ungateen : integer := 0
);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2x : in std_ulogic;
pwd : in std_logic_vector(ncpu-1 downto 0);
fpen : in std_logic_vector(ncpu-1 downto 0); -- Only used with shared FPU
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gclk : out std_logic_vector(nclks-1 downto 0);
reset : out std_logic_vector(nclks-1 downto 0);
clkahb : out std_ulogic;
clkahb2x : out std_ulogic;
clkcpu : out std_logic_vector(ncpu-1 downto 0);
enable : out std_logic_vector(nclks-1 downto 0);
clkfpu : out std_logic_vector((fpush/2)*(ncpu/2-1) downto 0); -- Only used with shared FPU
epwen : in std_logic_vector(nclks-1 downto 0);
ungate : in std_ulogic
);
end component;
component ahbwbax is
generic (
ahbbits: integer;
blocksz: integer := 16;
mstmode: integer := 0
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
-- Wide-side slave inputs
wi_hready: in std_ulogic;
wi_hsel: in std_ulogic;
wi_htrans: in std_logic_vector(1 downto 0);
wi_hsize: in std_logic_vector(2 downto 0);
wi_hburst: in std_logic_vector(2 downto 0);
wi_hwrite: in std_ulogic;
wi_haddr: in std_logic_vector(31 downto 0);
wi_hwdata: in std_logic_vector(AHBDW-1 downto 0);
wi_hmbsel: in std_logic_vector(0 to NAHBAMR-1);
wi_hmaster: in std_logic_vector(3 downto 0);
wi_hprot: in std_logic_vector(3 downto 0);
wi_hmastlock: in std_ulogic;
-- Wide-side slave outputs
wo_hready: out std_ulogic;
wo_hresp : out std_logic_vector(1 downto 0);
wo_hrdata: out std_logic_vector(AHBDW-1 downto 0);
-- Narrow-side slave inputs
ni_hready: out std_ulogic;
ni_htrans: out std_logic_vector(1 downto 0);
ni_hsize: out std_logic_vector(2 downto 0);
ni_hburst: out std_logic_vector(2 downto 0);
ni_hwrite: out std_ulogic;
ni_haddr: out std_logic_vector(31 downto 0);
ni_hwdata: out std_logic_vector(31 downto 0);
ni_hmbsel: out std_logic_vector(0 to NAHBAMR-1);
ni_hmaster: out std_logic_vector(3 downto 0);
ni_hprot : out std_logic_vector(3 downto 0);
ni_hmastlock: out std_ulogic;
-- Narrow-side slave outputs
no_hready: in std_ulogic;
no_hresp: in std_logic_vector(1 downto 0);
no_hrdata: in std_logic_vector(31 downto 0)
);
end component;
component ahbswba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_type;
ahbsi_slv: out ahb_slv_in_type;
ahbso_slv: in ahb_slv_out_type
);
end component;
component ahbswbav is
generic (
slvmask: integer;
ahbbits: integer;
blocksz: integer
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbsi_bus: in ahb_slv_in_type;
ahbso_bus: out ahb_slv_out_vector;
ahbsi_slv: out ahb_slv_in_vector_type(NAHBSLV-1 downto 0);
ahbso_slv: in ahb_slv_out_vector
);
end component;
component ahbmwba is
generic (
hindex: integer;
ahbbits: integer;
blocksz: integer := 16
);
port (
clk: in std_ulogic;
rst: in std_ulogic;
ahbmo_mst : in ahb_mst_out_type;
ahbmi_mst: out ahb_mst_in_type;
ahbmo_bus: out ahb_mst_out_type;
ahbmi_bus: in ahb_mst_in_type
);
end component;
-----------------------------------------------------------------------------
-- GRPULSE
-----------------------------------------------------------------------------
component grpulse
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1; -- Interrupt index
nchannel: Integer := 24; -- Number of channels
npulse: Integer := 8; -- Channels with pulses
imask: Integer := 16#ff0000#; -- Interrupt mask
ioffset: Integer := 8; -- Interrupt offset
invertpulse: Integer := 0; -- Invert pulses
cntrwidth: Integer := 10; -- Width of counter
syncrst: Integer := 1; -- Only synchronous reset
oepol: Integer := 1); -- Output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpioi: in gpio_in_type;
gpioo: out gpio_out_type);
end component;
-----------------------------------------------------------------------------
-- GRTIMER
-----------------------------------------------------------------------------
component grtimer is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
pirq: Integer := 1;
sepirq: Integer := 1; -- separate interrupts
sbits: Integer := 10; -- scaler bits
ntimers: Integer range 1 to 7 := 2; -- number of timers
nbits: Integer := 32; -- timer bits
wdog: Integer := 0;
glatch: Integer := 0;
gextclk: Integer := 0;
gset: Integer := 0);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
gpti: in gptimer_in_type;
gpto: out gptimer_out_type);
end component;
-----------------------------------------------------------------------------
-- GRVERSION
-----------------------------------------------------------------------------
component grversion
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#fff#;
versionnr: Integer := 16#0123#;
revisionnr: Integer := 16#4567#);
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type);
end component;
-----------------------------------------------------------------------------
-- AHBFROM - Microsemi/Actel Flash ROM
-----------------------------------------------------------------------------
component ahbfrom is
generic (
tech: integer := 0;
hindex: integer := 0;
haddr: integer := 0;
hmask: integer := 16#fff#;
width8: integer := 0;
memoryfile: string := "from.mem";
progfile: string := "from.ufc");
port (
rstn: in std_ulogic;
clk: in std_ulogic;
ahbi: in ahb_slv_in_type;
ahbo: out ahb_slv_out_type);
end component;
-----------------------------------------------------------------------------
-- Interrupt generator
-----------------------------------------------------------------------------
component irqgen
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ngen : integer range 1 to 15 := 1
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
-- function nandtree(v : std_logic_vector) return std_ulogic;
end;
package body misc is
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_membar(memaddr, prefetch, cache, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_iobar(memaddr, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
-- function nandtree(v : std_logic_vector) return std_ulogic is
-- variable a : std_logic_vector(v'length-1 downto 0);
-- variable b : std_logic_vector(v'length downto 0);
-- begin
--
-- a := v; b(0) := '1';
--
-- for i in 0 to v'length-1 loop
-- b(i+1) := a(i) nand b(i);
-- end loop;
--
-- return b(v'length);
--
-- end;
end;
| gpl-2.0 | 3c3d18f3620eea9beabc4bffecc5d075 | 0.507505 | 3.739155 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/stdlib/stdio.vhd | 1 | 9,020 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--------------------------------------------------------------------------------
-- Package: StdIO
-- File: stdio.vhd
-- Author: Gaisler Research
-- Description: Package for common I/O functions
--------------------------------------------------------------------------------
-- pragma translate_off
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library IEEE;
use IEEE.Std_Logic_1164.all;
-- pragma translate_on
package StdIO is
-- pragma translate_off
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector);
procedure HRead(
variable L: inout Line;
variable VALUE: out bit_vector);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector;
variable GOOD: out Boolean);
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector);
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_Logic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
procedure Write(
variable L: inout Line;
constant VALUE: in Std_ULogic;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0);
-- pragma translate_on
end package StdIO;
package body StdIO is
-- pragma translate_off
function ToChar(N: Std_ULogic_Vector(0 to 3)) return Character is
begin
case N is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('A');
when "1011" => return('B');
when "1100" => return('C');
when "1101" => return('D');
when "1110" => return('E');
when "1111" => return('F');
when others => return('X');
end case;
end ToChar;
function FromChar(C: Character) return Std_ULogic_Vector is
variable R: Std_ULogic_Vector(0 to 3);
begin
case C is
when '0' => R := "0000";
when '1' => R := "0001";
when '2' => R := "0010";
when '3' => R := "0011";
when '4' => R := "0100";
when '5' => R := "0101";
when '6' => R := "0110";
when '7' => R := "0111";
when '8' => R := "1000";
when '9' => R := "1001";
when 'A' => R := "1010";
when 'B' => R := "1011";
when 'C' => R := "1100";
when 'D' => R := "1101";
when 'E' => R := "1110";
when 'F' => R := "1111";
when 'a' => R := "1010";
when 'b' => R := "1011";
when 'c' => R := "1100";
when 'd' => R := "1101";
when 'e' => R := "1110";
when 'f' => R := "1111";
when others => R := "XXXX";
end case;
return R;
end FromChar;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector;
variable GOOD: out Boolean) is
variable B: Boolean;
variable C: Character;
constant SL: Integer := VALUE'Length;
variable SV: Std_ULogic_Vector(0 to SL-1);
variable S: String(1 to SL/4-1);
begin
if VALUE'Length mod 4 /= 0 then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
loop
Read(L, C, B);
exit when ((C /= ' ') and (C /= CR) and (C /= HT)) or (not B);
end loop;
SV(0 to 3) := FromChar(C);
if Is_X(SV(0 to 3)) or (not B) then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
Read(L, S, B);
if not B then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
for i in 1 to SL/4-1 loop
SV(4*i to 4*i+3) := FromChar(S(i));
if Is_X(SV(4*i to 4*i+3)) then
GOOD := False;
SV := (others => 'X');
VALUE := SV;
return;
end if;
end loop;
GOOD := True;
VALUE := SV;
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_ULogic_Vector) is
variable GOOD: Boolean;
begin
HRead(L, VALUE, GOOD);
--assert GOOD
-- report "HREAD: access incorrect";
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out bit_vector) is
variable GOOD: Boolean;
variable V: Std_ULogic_Vector(0 to Value'Length-1);
begin
HRead(L, V, GOOD);
--assert GOOD
-- report "HREAD: access incorrect";
VALUE := to_bitvector(V);
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector;
variable GOOD: out Boolean) is
variable V: Std_ULogic_Vector(0 to Value'Length-1);
begin
HRead(L, V, GOOD);
VALUE := Std_Logic_Vector(V);
end HRead;
procedure HRead(
variable L: inout Line;
variable VALUE: out Std_Logic_Vector) is
variable GOOD: Boolean;
variable V: Std_ULogic_Vector(0 to Value'Length-1);
begin
HRead(L, V, GOOD);
VALUE := Std_Logic_Vector(V);
--assert GOOD
-- report "HREAD: access incorrect";
end HRead;
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_ULogic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
constant PL: Integer := 4-(VALUE'Length mod 4);
constant PV: Std_ULogic_Vector(1 to PL) := (others => '0');
constant TL: Integer := PL + VALUE'Length;
constant TV: Std_ULogic_Vector(0 to TL-1) := PV & Value;
variable S: String(1 to TL/4);
begin
if PL /= 4 then
for i in 0 to TL/4 -1 loop
S(i+1) := ToChar(TV(4*i to 4*i+3));
end loop;
Write(L, S(1 to TL/4), JUSTIFIED, FIELD);
else
for i in 1 to TL/4 -1 loop
S(i+1) := ToChar(TV(4*i to 4*i+3));
end loop;
Write(L, S(2 to TL/4), JUSTIFIED, FIELD);
end if;
end HWrite;
procedure HWrite(
variable L: inout Line;
constant VALUE: in Std_Logic_Vector;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
begin
HWrite(L, Std_ULogic_Vector(VALUE), JUSTIFIED, FIELD);
end HWrite;
procedure Write(
variable L: inout Line;
constant VALUE: in Std_ULogic;
constant JUSTIFIED: in SIDE := RIGHT;
constant FIELD: in WIDTH := 0) is
type Char_Array is array (Std_ULogic) of Character;
constant ToChar: Char_Array := "UX01ZWLH-";
begin
Write(L, ToChar(VALUE), JUSTIFIED, FIELD);
end Write;
-- pragma translate_on
end package body StdIO;
| gpl-2.0 | 6e8c6b81f6d3ff5d82dc797fb7d467f6 | 0.491796 | 3.87457 | false | false | false | false |
dsaves/dsaves-hdl | dft/tap_controller.vhd | 1 | 6,346 | --MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
library ieee, dsaves;
use ieee.std_logic_1164.all;
entity TAP_CONTROLLER is
port(
tclk : in std_logic;
tms : in std_logic;
tdi : in std_logic;
trst : in std_logic;
tdo : out std_logic
);
end entity;
architecture IEEE_STD_1149_1_2013 of TAP_CONTROLLER is
type TAP_STATE is ( RESET, IDLE,
SELECT_DR_SCAN, CAPTURE_DR, SHIFT_DR, EXIT1_DR, PAUSE_DR, EXIT2_DR, UPDATE_DR,
SELECT_IR_SCAN, CAPTURE_IR, SHIFT_IR, EXIT1_IR, PAUSE_IR, EXIT2_IR, UPDATE_IR );
signal CURRENT_STATE, NEXT_STATE : TAP_STATE;
begin
--CURRENT_STATE assignment
process(tclk, trst)
begin
if(trst = '1') then
CURRENT_STATE <= RESET;
end if;
if(tclk'event and tclk='1') then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
--NEXT STATE logic
process(tclk, trst)
begin
if(trst = '1') then
NEXT_STATE <= RESET;
end if;
if(tclk'event and tclk = '1') then
case CURRENT_STATE is
when RESET =>
if(tms = '1') then
NEXT_STATE <= RESET;
else
NEXT_STATE <= IDLE;
end if;
when IDLE =>
if(tms = '1') then
NEXT_STATE <= SELECT_DR_SCAN;
else
NEXT_STATE <= IDLE;
end if;
when SELECT_DR_SCAN =>
if(tms = '1') then
NEXT_STATE <= SELECT_IR_SCAN;
else
NEXT_STATE <= CAPTURE_DR;
end if;
when CAPTURE_DR =>
if(tms = '1') then
NEXT_STATE <= EXIT1_DR;
else
NEXT_STATE <= SHIFT_DR;
end if;
when SHIFT_DR =>
if(tms = '1') then
NEXT_STATE <= EXIT1_DR;
else
NEXT_STATE <= SHIFT_DR;
end if;
when EXIT1_DR =>
if(tms = '1') then
NEXT_STATE <= UPDATE_DR;
else
NEXT_STATE <= PAUSE_DR;
end if;
when PAUSE_DR =>
if(tms = '1') then
NEXT_STATE <= EXIT2_DR;
else
NEXT_STATE <= PAUSE_DR;
end if;
when EXIT2_DR =>
if(tms = '1') then
NEXT_STATE <= UPDATE_DR;
else
NEXT_STATE <= SHIFT_DR;
end if;
when UPDATE_DR =>
if(tms = '1') then
NEXT_STATE <= SELECT_DR_SCAN;
else
NEXT_STATE <= IDLE;
end if;
when SELECT_IR_SCAN =>
if(tms = '1') then
NEXT_STATE <= RESET;
else
NEXT_STATE <= CAPTURE_IR;
end if;
when CAPTURE_IR =>
if(tms = '1') then
NEXT_STATE <= EXIT1_IR;
else
NEXT_STATE <= SHIFT_IR;
end if;
when SHIFT_IR =>
if(tms = '1') then
NEXT_STATE <= EXIT1_IR;
else
NEXT_STATE <= SHIFT_IR;
end if;
when EXIT1_IR =>
if(tms = '1') then
NEXT_STATE <= UPDATE_IR;
else
NEXT_STATE <= PAUSE_IR;
end if;
when PAUSE_IR =>
if(tms = '1') then
NEXT_STATE <= EXIT2_IR;
else
NEXT_STATE <= PAUSE_IR;
end if;
when EXIT2_IR =>
if(tms = '1') then
NEXT_STATE <= UPDATE_IR;
else
NEXT_STATE <= SHIFT_IR;
end if;
when UPDATE_IR =>
if(tms = '1') then
NEXT_STATE <= SELECT_DR_SCAN;
else
NEXT_STATE <= IDLE;
end if;
end case;
end if;
end process;
end architecture;
| mit | 0587fe9153da67a21558557749382d3b | 0.396313 | 5.197379 | false | false | false | false |
a4a881d4/ringbus4xilinx | src/cbus/CSlave.vhd | 1 | 2,957 | ---------------------------------------------------------------------------------------------------
--
-- Title : Control Bus Slave
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : CSlave.vhd
-- Generated : 2013/9/13
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Control bus Slave
--
-- Rev: 3.1
-- rd signal ahead data one clock
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.rb_config.all;
use work.contr_config.all;
entity CSlave is
generic(
Bwidth : natural := 16
);
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- send to bus
tx: out std_logic_vector( Bwidth-1 downto 0 );
Req : out std_logic;
tx_sop : in std_logic;
en : in std_logic;
-- read from bus
rx_sop : in std_logic;
rx: in std_logic_vector( Bwidth-1 downto 0 );
-- Local Bus
addr : out std_logic_vector( Bwidth-1 downto 0 );
Din : out STD_LOGIC_VECTOR( Bwidth-1 downto 0 );
Dout : in STD_LOGIC_VECTOR( Bwidth-1 downto 0 ) := (others => '0');
wr : out std_logic;
rd : out std_logic := '0'
--
);
end CSlave;
architecture behave of CSlave is
signal req_i : std_logic := '0';
signal command : std_logic_vector( command_end downto command_start ) := (others => '0');
signal state : natural := 0;
signal tx_i : std_logic_vector( Bwidth-1 downto 0 ) := (others => '0');
begin
req<=req_i;
tx<=tx_i;
FSM:process(clk,rst)
begin
if rst='1' then
state<=state_IDLE;
command<=(others=>'0');
addr<=(others=>'0');
Din<=(others=>'0');
req_i<='0';
wr<='0';
tx_i<=(others=>'0');
elsif rising_edge(clk) then
case state is
when state_IDLE =>
if rx_sop='1' then
command<=rx( command_end downto command_start );
state<=state_ADDR;
end if;
wr<='0';
when state_ADDR =>
addr<=rx;
state<=state_DATA;
when state_DATA =>
if command=command_read then
state<=state_pending;
req_i<='1';
tx_i<=rx;
elsif command=command_write then
wr<='1';
Din<=rx;
state<=state_idle;
else
state<=state_idle;
end if;
when state_pending =>
if en='1' and tx_sop='1' then
req_i<='0';
state<=state_SENDING;
end if;
when state_SENDING =>
tx_i<=Dout;
state<=state_IDLE;
when others =>
state<=state_IDLE;
end case;
end if;
end process;
rd<= '1' when state=state_pending and en='1' and tx_sop='1' else '0';
end behave;
| gpl-2.0 | 395a400910820fe661e495a6df245e60 | 0.481231 | 3.245884 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/unisim/ise/unisim_VPKG.vhd | 4 | 13,609 | ----------------------------------------------------------------------------
-- Simple simulation models for some Xilinx blocks
----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library STD;
use STD.TEXTIO.all;
package vpkg is
signal GTS : std_logic := '0';
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN STRING := "";
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN INTEGER;
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN BOOLEAN;
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN REAL;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
procedure detect_resolution ( constant model_name : in string);
function slv_to_int (slv : in std_logic_vector) return integer;
function addr_is_valid (slv : in std_logic_vector) return boolean ;
function DECODE_ADDR4 (
ADDRESS : in std_logic_vector(3 downto 0)
) return integer;
function DECODE_ADDR5 (
ADDRESS : in std_logic_vector(4 downto 0)
) return integer;
function SLV_TO_STR (
SLV : in std_logic_vector
) return string;
end;
package body vpkg is
function SLV_TO_STR (
SLV : in std_logic_vector
) return string is
variable j : integer := SLV'length;
variable STR : string (SLV'length downto 1);
begin
for I in SLV'high downto SLV'low loop
case SLV(I) is
when '0' => STR(J) := '0';
when '1' => STR(J) := '1';
when 'X' => STR(J) := 'X';
when 'U' => STR(J) := 'U';
when others => STR(J) := 'X';
end case;
J := J - 1;
end loop;
return STR;
end SLV_TO_STR;
function DECODE_ADDR4 (
ADDRESS : in std_logic_vector(3 downto 0)
) return integer is
variable I : integer;
begin
case ADDRESS is
when "0000" => I := 0;
when "0001" => I := 1;
when "0010" => I := 2;
when "0011" => I := 3;
when "0100" => I := 4;
when "0101" => I := 5;
when "0110" => I := 6;
when "0111" => I := 7;
when "1000" => I := 8;
when "1001" => I := 9;
when "1010" => I := 10;
when "1011" => I := 11;
when "1100" => I := 12;
when "1101" => I := 13;
when "1110" => I := 14;
when "1111" => I := 15;
when others => I := 16;
end case;
return I;
end DECODE_ADDR4;
function ADDR_IS_VALID (
SLV : in std_logic_vector
) return boolean is
variable IS_VALID : boolean := TRUE;
begin
for I in SLV'high downto SLV'low loop
if (SLV(I) /= '0' AND SLV(I) /= '1') then
IS_VALID := FALSE;
end if;
end loop;
return IS_VALID;
end ADDR_IS_VALID;
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
procedure detect_resolution (
constant model_name : in string
) IS
variable test_value : time;
variable Message : LINE;
BEGIN
test_value := 1 ps;
if (test_value = 0 ps) then
Write (Message, STRING'(" Simulator Resolution Error : "));
Write (Message, STRING'(" Simulator resolution is set to a value greater than 1 ps. "));
Write (Message, STRING'(" In order to simulate the "));
Write (Message, model_name);
Write (Message, STRING'(", the simulator resolution must be set to 1ps or smaller "));
ASSERT FALSE REPORT Message.ALL SEVERITY ERROR;
DEALLOCATE (Message);
end if;
END detect_resolution;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN STRING := "";
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN INTEGER;
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN BOOLEAN;
Constant Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN REAL;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
function DECODE_ADDR5 (
ADDRESS : in std_logic_vector(4 downto 0)
) return integer is
variable I : integer;
begin
case ADDRESS is
when "00000" => I := 0;
when "00001" => I := 1;
when "00010" => I := 2;
when "00011" => I := 3;
when "00100" => I := 4;
when "00101" => I := 5;
when "00110" => I := 6;
when "00111" => I := 7;
when "01000" => I := 8;
when "01001" => I := 9;
when "01010" => I := 10;
when "01011" => I := 11;
when "01100" => I := 12;
when "01101" => I := 13;
when "01110" => I := 14;
when "01111" => I := 15;
when "10000" => I := 16;
when "10001" => I := 17;
when "10010" => I := 18;
when "10011" => I := 19;
when "10100" => I := 20;
when "10101" => I := 21;
when "10110" => I := 22;
when "10111" => I := 23;
when "11000" => I := 24;
when "11001" => I := 25;
when "11010" => I := 26;
when "11011" => I := 27;
when "11100" => I := 28;
when "11101" => I := 29;
when "11110" => I := 30;
when "11111" => I := 31;
when others => I := 32;
end case;
return I;
end DECODE_ADDR5;
end;
| gpl-2.0 | fa58cadcfda72c8cf5c32372d3b44ffa | 0.58814 | 4.164321 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2s60-ddr/config.vhd | 1 | 5,446 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 1413e7628889c77dfbe400188d91af2a | 0.642857 | 3.657488 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_processing_system7_0_0/zynq_design_1_processing_system7_0_0_sim_netlist.vhdl | 1 | 197,262 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:31 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_processing_system7_0_0/zynq_design_1_processing_system7_0_0_sim_netlist.vhdl
-- Design : zynq_design_1_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "zynq_design_1_processing_system7_0_0.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_processing_system7_0_0 : entity is "zynq_design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.2";
end zynq_design_1_processing_system7_0_0;
architecture STRUCTURE of zynq_design_1_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "zynq_design_1_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.zynq_design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => FTMT_F2P_TRIG_0,
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => FTMT_P2F_TRIG_0,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | c326a0fb38ed8e5757169c486c7da669 | 0.634273 | 2.753748 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/dbg/fmsp_dbg_i2c.vhd | 1 | 24,688 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_dbg_i2c.vhd
--!
--! @brief fpgaMSP430 Debug I2C Slave communication interface
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use work.fmsp_misc_package.all;
entity fmsp_dbg_i2c is
generic (
DBG_I2C_BROADCAST_EN : boolean := false --! Enable the I2C broadcast address
);
port (
dbg_clk : in std_logic; --! Debug unit clock
dbg_rst : in std_logic; --! Debug unit reset
--! INPUTs
dbg_dout : in std_logic_vector(15 downto 0); --! Debug register data output
dbg_i2c_addr : in std_logic_vector(6 downto 0); --! Debug interface: I2C ADDRESS
dbg_i2c_broadcast : in std_logic_vector(6 downto 0); --! Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl : in std_logic; --! Debug interface: I2C SCL
dbg_i2c_sda_in : in std_logic; --! Debug interface: I2C SDA IN
mem_burst : in std_logic; --! Burst on going
mem_burst_end : in std_logic; --! End TX/RX burst
mem_burst_rd : in std_logic; --! Start TX burst
mem_burst_wr : in std_logic; --! Start RX burst
mem_bw : in std_logic; --! Burst byte width
--! OUTPUTs
dbg_addr : out std_logic_vector(5 downto 0); --! Debug register address
dbg_din : out std_logic_vector(15 downto 0); --! Debug register data input
dbg_i2c_sda_out : out std_logic; --! Debug interface: I2C SDA OUT
dbg_rd : out std_logic; --! Debug register data read
dbg_wr : out std_logic --! Debug register data write
);
end entity fmsp_dbg_i2c;
architecture RTL of fmsp_dbg_i2c is
--! 3) I2C STATE MACHINE
--! State machine definition
-- constant RX_ADDR : integer := 0;
-- constant RX_ADDR_ACK : integer := 1;
-- constant RX_DATA : integer := 2;
-- constant RX_DATA_ACK : integer := 3;
-- constant TX_DATA : integer := 4;
-- constant TX_DATA_ACK : integer := 5;
type I2C_STATE_TYPE is ( RX_ADDR,
RX_ADDR_ACK,
RX_DATA,
RX_DATA_ACK,
TX_DATA,
TX_DATA_ACK
); --type of state machine.
--! 6) DEBUG INTERFACE STATE MACHINE
--! State machine definition
-- constant RX_CMD : integer := 0;
-- constant RX_BYTE_LO : integer := 1;
-- constant RX_BYTE_HI : integer := 2;
-- constant TX_BYTE_LO : integer := 3;
-- constant TX_BYTE_HI : integer := 4;
type DBG_STATE_TYPE is ( RX_CMD,
RX_BYTE_LO,
RX_BYTE_HI,
TX_BYTE_LO,
TX_BYTE_HI
); --type of state machine.
--! 7) REGISTER READ/WRITE ACCESS
constant MEM_DATA : std_logic_vector(5 downto 0) := "000110";
type fmsp_dbg_i2c_in_type is record
dbg_dout : std_logic_vector(15 downto 0); --! Debug register data output
dbg_i2c_addr : std_logic_vector(6 downto 0); --! Debug interface: I2C ADDRESS
dbg_i2c_broadcast : std_logic_vector(6 downto 0); --! Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl : std_logic; --! Debug interface: I2C SCL
dbg_i2c_sda_in : std_logic; --! Debug interface: I2C SDA IN
mem_burst : std_logic; --! Burst on going
mem_burst_end : std_logic; --! End TX/RX burst
mem_burst_rd : std_logic; --! Start TX burst
mem_burst_wr : std_logic; --! Start RX burst
mem_bw : std_logic; --! Burst byte width
scl_sync_n : std_logic;
sda_in_sync_n : std_logic;
end record;
type reg_type is record
scl_buf : std_logic_vector(1 downto 0); --! SCL/SDA input buffers
sda_in_buf : std_logic_vector(1 downto 0); --! SCL/SDA input buffers
sda_in_dly : std_logic; --! SDA Edge detection
scl_dly : std_logic; --! SCL Edge detection
scl_re_dly : std_logic_vector(1 downto 0); --! Delayed SCL Rising-Edge for SDA data sampling
i2c_active_seq : std_logic; --! I2C Slave Active
i2c_state : I2C_STATE_TYPE; --! State register/wires
-- i2c_state_nxt : I2C_STATE_TYPE; --! State register/wires
shift_buf : std_logic_vector(8 downto 0); --! Utility signals
dbg_rd : std_logic; --! Utility signals
dbg_i2c_sda_out : std_logic; --! 5) I2C TRANSMIT BUFFER
dbg_state : DBG_STATE_TYPE; --! State register/wires
dbg_addr : std_logic_vector(5 downto 0);
dbg_din_lo : std_logic_vector(7 downto 0);
dbg_din_hi : std_logic_vector(7 downto 0);
dbg_bw : std_logic; --! Utility signals
dbg_wr : std_logic; --! Debug register data write command
end record;
signal d : fmsp_dbg_i2c_in_type;
signal r : reg_type := ( scl_buf => "00", --! SCL/SDA input buffers
sda_in_buf => "00", --! SCL/SDA input buffers
sda_in_dly => '0', --! SDA Edge detection
scl_dly => '0', --! SCL Edge detection
scl_re_dly => "00", --! Delayed SCL Rising-Edge for SDA data sampling
i2c_active_seq => '0', --! I2C Slave Active
i2c_state => RX_ADDR, --! State register/wires
shift_buf => "000000000",--! Utility signals
dbg_rd => '0', --! Utility signals
dbg_i2c_sda_out => '0', --! I2C TRANSMIT BUFFER
dbg_state => RX_CMD, --! State register/wires
dbg_addr => "000000",
dbg_din_lo => "00000000",
dbg_din_hi => "00000000",
dbg_bw => '0', --! Utility signals
dbg_wr => '0' --! Debug register data write command
);
signal rin : reg_type;
begin
d.dbg_dout <= dbg_dout;
d.dbg_i2c_addr <= dbg_i2c_addr;
d.dbg_i2c_broadcast <= dbg_i2c_broadcast;
d.dbg_i2c_scl <= dbg_i2c_scl;
d.dbg_i2c_sda_in <= dbg_i2c_sda_in;
d.mem_burst <= mem_burst;
d.mem_burst_end <= mem_burst_end;
d.mem_burst_rd <= mem_burst_rd;
d.mem_burst_wr <= mem_burst_wr;
d.mem_bw <= mem_bw;
COMB : process (d, r)
variable v : reg_type;
--! 1) I2C RECEIVE LINE SYNCHRONIZTION & FILTERING
--! Synchronize SCL/SDA inputs
variable v_scl_sync_n : std_logic;
variable v_scl_sync : std_logic;
variable v_sda_in_sync_n : std_logic;
variable v_sda_in_sync : std_logic;
--! SCL/SDA Majority decision
variable v_scl : std_logic;
variable v_sda_in : std_logic;
--! SDA Edge detection
variable v_sda_in_fe : std_logic;
variable v_sda_in_re : std_logic;
-- variable v_sda_in_edge : std_logic;
--! SCL Edge detection
variable v_scl_fe : std_logic;
variable v_scl_re : std_logic;
-- variable v_scl_edge : std_logic;
--! Delayed SCL Rising-Edge for SDA data sampling
variable v_scl_sample : std_logic;
--! 2) I2C START & STOP CONDITION DETECTION
--! Start condition
variable v_start_detect : std_logic;
--! Stop condition
variable v_stop_detect : std_logic;
--! I2C Slave Active
variable v_i2c_addr_not_valid : std_logic;
variable v_i2c_active : std_logic;
variable v_i2c_init : std_logic;
--! State machine
variable v_i2c_state_nxt : I2C_STATE_TYPE;
--! 4) I2C SHIFT REGISTER (FOR RECEIVING & TRANSMITING)
variable v_shift_rx_en : std_logic;
variable v_shift_tx_en : std_logic;
variable v_shift_tx_en_pre : std_logic;
variable v_shift_rx_done : std_logic;
variable v_shift_tx_done : std_logic;
variable v_shift_buf_rx_init : std_logic;
variable v_shift_buf_rx_en : std_logic;
variable v_shift_buf_tx_init : std_logic;
variable v_shift_buf_tx_en : std_logic;
variable v_shift_tx_val : std_logic_vector(7 downto 0);
variable v_shift_buf_nxt : std_logic_vector(8 downto 0);
variable v_shift_buf : std_logic;
--! Detect when the received I2C device address is not valid
-- variable v_i2c_addr_not_valid : std_logic;
variable UNUSED_dbg_i2c_broadcast : std_logic_vector(6 downto 0);
--! Utility signals
variable v_shift_rx_data_done : std_logic;
variable v_shift_tx_data_done : std_logic;
--! State machine
variable v_dbg_state_nxt : DBG_STATE_TYPE;
--! Utility signals
variable v_cmd_valid : std_logic;
variable v_rx_lo_valid : std_logic;
variable v_rx_hi_valid : std_logic;
--! Debug register address & bit width
variable v_dbg_addr : std_logic_vector(5 downto 0);
--! Debug register data input
variable v_dbg_din : std_logic_vector(15 downto 0);
--! Debug register data read command
-- variable v_dbg_rd : std_logic;
--! Debug register data read value
-- variable v_shift_tx_val : std_logic;
begin
--! default assignment
v := r;
--! overriding assignments
v_scl_sync := not(d.scl_sync_n);
v_sda_in_sync := not(d.sda_in_sync_n);
--! SCL/SDA input buffers
v.scl_buf := r.scl_buf(0) & v_scl_sync;
v.sda_in_buf := r.sda_in_buf(0) & v_sda_in_sync;
--! SCL/SDA Majority decision
v_scl := (v_scl_sync and r.scl_buf(0))
or (v_scl_sync and r.scl_buf(0))
or (r.scl_buf(0) and r.scl_buf(1));
v_sda_in := (v_sda_in_sync and r.sda_in_buf(0))
or (v_sda_in_sync and r.sda_in_buf(1))
or (r.sda_in_buf(0) and r.sda_in_buf(1));
--! SCL/SDA Edge detection
--------------------------------
--! SDA Edge detection
v.sda_in_dly := v_sda_in;
v_sda_in_fe := r.sda_in_dly and not( v_sda_in);
v_sda_in_re := not( r.sda_in_dly) and v_sda_in;
-- v_sda_in_edge := r.sda_in_dly xor v_sda_in;
--! SCL Edge detection
v.scl_dly := v_scl;
v_scl_fe := r.scl_dly and not( v_scl);
v_scl_re := not( r.scl_dly) and v_scl;
-- v_scl_edge := r.scl_dly xor v_scl;
--! Delayed SCL Rising-Edge for SDA data sampling
v.scl_re_dly := r.scl_re_dly(0) & v_scl_re;
v_scl_sample := r.scl_re_dly(1);
--=============================================================================
--! 4) I2C SHIFT REGISTER (FOR RECEIVING)
--=============================================================================
v_shift_rx_en := '0';
if ( (r.i2c_state = RX_ADDR)
or (r.i2c_state = RX_DATA)
or (r.i2c_state = RX_DATA_ACK)
) then
v_shift_rx_en := '1';
end if;
v_shift_rx_done := v_shift_rx_en and v_scl_fe and r.shift_buf(8);
v_shift_buf_rx_init := '0';
if ( (v_i2c_init = '1')
or ( (r.i2c_state = RX_ADDR_ACK)
and (v_scl_fe = '1')
and (not(r.shift_buf(8)) = '1')
)
or ( (r.i2c_state = RX_DATA_ACK)
and (v_scl_fe = '1')
)
) then
v_shift_buf_rx_init := '1';
end if;
v_shift_buf_rx_en := v_shift_rx_en and v_scl_sample;
--! Detect when the received I2C device address is not valid
v_i2c_addr_not_valid := '0';
if (DBG_I2C_BROADCAST_EN = true) then
if ( (r.i2c_state = RX_ADDR)
and (v_shift_rx_done = '1')
and (r.shift_buf(7 downto 1) /= d.dbg_i2c_broadcast(6 downto 0))
and (r.shift_buf(7 downto 1) /= d.dbg_i2c_addr(6 downto 0))
) then
v_i2c_addr_not_valid := '1';
end if;
else
if ( (r.i2c_state = RX_ADDR)
and (v_shift_rx_done = '1')
and (r.shift_buf(7 downto 1) /= d.dbg_i2c_addr(6 downto 0))
) then
v_i2c_addr_not_valid := '1';
end if;
end if;
--=============================================================================
--! 4) I2C SHIFT REGISTER (FOR RECEIVING & TRANSMITING)
--=============================================================================
v_shift_tx_en := '0';
if ( (r.i2c_state = TX_DATA)
or (r.i2c_state = TX_DATA_ACK)
) then
v_shift_tx_en := '1';
end if;
if (r.shift_buf = "100000000") then
v_shift_tx_done := v_shift_tx_en and v_scl_fe;
else
v_shift_tx_done := '0';
end if;
--=============================================================================
--! 2) I2C START & STOP CONDITION DETECTION
--=============================================================================
--! Start condition
v_start_detect := v_sda_in_fe and v_scl;
--! Stop condition
v_stop_detect := v_sda_in_re and v_scl;
-------------------
--! I2C Slave Active
-------------------
--! The I2C logic will be activated whenever a start condition
--! is detected and will be disactivated if the slave address
--! doesn't match or if a stop condition is detected.
if (v_start_detect = '1') then
v.i2c_active_seq := '1';
elsif ((v_stop_detect = '1') or (v_i2c_addr_not_valid = '1')) then
v.i2c_active_seq := '0';
end if;
v_i2c_active := r.i2c_active_seq and not(v_stop_detect);
v_i2c_init := not(v_i2c_active) or v_start_detect;
--=============================================================================
--! 3) I2C STATE MACHINE
--=============================================================================
--! State transition
case (r.i2c_state) is
when RX_ADDR =>
if (v_i2c_init = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_shift_rx_done) = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_i2c_addr_not_valid) = '1') then
v_i2c_state_nxt := RX_ADDR;
else
v_i2c_state_nxt := RX_ADDR_ACK;
end if;
when RX_ADDR_ACK =>
if (v_i2c_init = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_scl_fe) = '1') then
v_i2c_state_nxt := RX_ADDR_ACK;
elsif (r.shift_buf(0) = '1') then
v_i2c_state_nxt := TX_DATA;
else
v_i2c_state_nxt := RX_DATA;
end if;
when RX_DATA =>
if (v_i2c_init = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_shift_rx_done) = '1') then
v_i2c_state_nxt := RX_DATA;
else
v_i2c_state_nxt := RX_DATA_ACK;
end if;
when RX_DATA_ACK =>
if (v_i2c_init = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_scl_fe) = '1') then
v_i2c_state_nxt := RX_DATA_ACK;
else
v_i2c_state_nxt := RX_DATA;
end if;
when TX_DATA =>
if (v_i2c_init = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_shift_tx_done) = '1') then
v_i2c_state_nxt := TX_DATA;
else
v_i2c_state_nxt := TX_DATA_ACK;
end if;
when TX_DATA_ACK =>
if (v_i2c_init = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_scl_fe) = '1') then
v_i2c_state_nxt := TX_DATA_ACK;
elsif (not(v_sda_in) = '1') then
v_i2c_state_nxt := TX_DATA;
else
v_i2c_state_nxt := RX_ADDR;
end if;
when Others =>
v_i2c_state_nxt := RX_ADDR;
end case;
--! State machine
v.i2c_state := v_i2c_state_nxt;
--=============================================================================
--! 4) I2C SHIFT REGISTER (FOR RECEIVING & TRANSMITING)
--=============================================================================
v_shift_tx_en_pre := '0';
if ( (v_i2c_state_nxt = TX_DATA)
or (v_i2c_state_nxt = TX_DATA_ACK)
) then
v_shift_tx_en_pre := '1';
end if;
v_shift_buf_tx_init := '0';
if ( ( (r.i2c_state = RX_ADDR_ACK)
and (v_scl_re = '1')
and (not(r.shift_buf(0)) = '1')
)
or ( (r.i2c_state = TX_DATA_ACK)
and (v_scl_re = '1')
)
) then
v_shift_buf_tx_init := '1';
end if;
if (r.shift_buf /= "100000000") then
v_shift_buf_tx_en := v_shift_tx_en_pre and v_scl_fe;
else
v_shift_buf_tx_en := '0';
end if;
--! Debug register data read value
if (r.dbg_state = TX_BYTE_HI) then
v_shift_tx_val := d.dbg_dout(15 downto 8);
else
v_shift_tx_val := d.dbg_dout(7 downto 0);
end if;
if (v_shift_buf_rx_init = '1') then --! RX Init
v_shift_buf_nxt := "000000001";
elsif (v_shift_buf_tx_init = '1') then --! TX Init
v_shift_buf_nxt := v_shift_tx_val & '1';
elsif (v_shift_buf_rx_en = '1') then --! RX Shift
v_shift_buf_nxt := r.shift_buf(7 downto 0) & v_sda_in;
elsif (v_shift_buf_tx_en = '1') then --! TX Shift
v_shift_buf_nxt := r.shift_buf(7 downto 0) & '0';
else --! Hold
v_shift_buf_nxt := r.shift_buf(8 downto 0);
end if;
v.shift_buf := v_shift_buf_nxt;
UNUSED_dbg_i2c_broadcast := d.dbg_i2c_broadcast;
--! Utility signals
v_shift_rx_data_done := '0';
if ( (r.i2c_state = RX_DATA)
and (v_shift_rx_done = '1')
) then
v_shift_rx_data_done := '1';
end if;
v_shift_tx_data_done := v_shift_tx_done;
--=============================================================================
--! 5) I2C TRANSMIT BUFFER
--=============================================================================
if (v_scl_fe) then
if ( (v_i2c_state_nxt = RX_ADDR_ACK)
or (v_i2c_state_nxt = RX_ADDR_ACK)
or ( (v_shift_buf_tx_en = '1')
and (not(r.shift_buf(8)) = '1')
)
) then
v.dbg_i2c_sda_out := '1';
else
v.dbg_i2c_sda_out := '1';
end if;
end if;
--=============================================================================
--! 6) DEBUG INTERFACE STATE MACHINE
--=============================================================================
--! State transition
case (r.dbg_state) is
when RX_CMD =>
if (d.mem_burst_wr = '1') then
v_dbg_state_nxt := RX_BYTE_LO;
elsif (d.mem_burst_rd = '1') then
v_dbg_state_nxt := TX_BYTE_LO;
elsif (not(v_shift_rx_data_done) = '1') then
v_dbg_state_nxt := RX_CMD;
elsif (r.shift_buf(7) = '1') then
v_dbg_state_nxt := RX_BYTE_LO;
else
v_dbg_state_nxt := TX_BYTE_LO;
end if;
when RX_BYTE_LO =>
if ( (d.mem_burst = '1') and (d.mem_burst_end = '1') ) then
v_dbg_state_nxt := RX_CMD;
elsif (not(v_shift_rx_data_done) = '1') then
v_dbg_state_nxt := RX_BYTE_LO;
elsif ( (d.mem_burst = '1') and (not(d.mem_burst_end) = '1') ) then
if (not(d.mem_bw) = '1') then
v_dbg_state_nxt := RX_BYTE_LO;
else
v_dbg_state_nxt := RX_BYTE_HI;
end if;
elsif (not(r.dbg_bw) = '1') then
v_dbg_state_nxt := RX_CMD;
else
v_dbg_state_nxt := RX_BYTE_HI;
end if;
when RX_BYTE_HI =>
if (not(v_shift_rx_data_done) = '1') then
v_dbg_state_nxt := RX_BYTE_HI;
elsif ( (d.mem_burst_wr = '1') and (not(d.mem_burst_end) = '1') ) then
v_dbg_state_nxt := RX_BYTE_LO;
else
v_dbg_state_nxt := RX_CMD;
end if;
when TX_BYTE_LO =>
if (not(v_shift_tx_data_done) = '1') then
v_dbg_state_nxt := TX_BYTE_LO;
elsif ( (d.mem_burst = '1') and (d.mem_bw = '1') ) then
v_dbg_state_nxt := TX_BYTE_LO;
elsif ( (d.mem_burst = '1') and (not(d.mem_bw) = '1') ) then
v_dbg_state_nxt := TX_BYTE_HI;
elsif (not(r.dbg_bw) = '1') then
v_dbg_state_nxt := TX_BYTE_HI;
else
v_dbg_state_nxt := RX_CMD;
end if;
when TX_BYTE_HI =>
if (not(v_shift_rx_data_done) = '1') then
v_dbg_state_nxt := TX_BYTE_HI;
elsif (d.mem_burst = '1') then
v_dbg_state_nxt := TX_BYTE_LO;
else
v_dbg_state_nxt := RX_CMD;
end if;
when Others =>
v_dbg_state_nxt := RX_CMD;
end case;
--! State machine
v.dbg_state := v_dbg_state_nxt;
--! Utility signals
if ( (r.dbg_state = RX_CMD)
and (v_shift_rx_data_done = '1')
) then
v_cmd_valid := '1';
else
v_cmd_valid := '0';
end if;
if ( (r.dbg_state = RX_BYTE_LO)
and (v_shift_rx_data_done = '1')
) then
v_rx_lo_valid := '1';
else
v_rx_lo_valid := '0';
end if;
if ( (r.dbg_state = RX_BYTE_HI)
and (v_shift_rx_data_done = '1')
) then
v_rx_hi_valid := '1';
else
v_rx_hi_valid := '0';
end if;
--=============================================================================
--! 7) REGISTER READ/WRITE ACCESS
--=============================================================================
if (v_cmd_valid = '1') then
v.dbg_bw := r.shift_buf(6);
v.dbg_addr := r.shift_buf(5 downto 0);
elsif (d.mem_burst = '1') then
v.dbg_bw := d.mem_bw;
v.dbg_addr := MEM_DATA;
end if;
--! Debug register data input
if (v_rx_lo_valid = '1') then
v.dbg_din_lo := r.shift_buf(7 downto 0);
end if;
if (v_rx_lo_valid = '1') then
v.dbg_din_hi := x"00";
elsif (v_rx_hi_valid = '1') then
v.dbg_din_hi := r.shift_buf(7 downto 0);
end if;
v_dbg_din := r.dbg_din_hi & r.dbg_din_lo;
--! Debug register data write command
if ((d.mem_burst and d.mem_bw) = '1') then
v.dbg_wr := v_rx_lo_valid;
elsif ((d.mem_burst and not(d.mem_bw)) = '1') then
v.dbg_wr := v_rx_hi_valid;
elsif (r.dbg_bw = '1') then
v.dbg_wr := v_rx_lo_valid;
else
v.dbg_wr := v_rx_hi_valid;
end if;
--! Debug register data read command
if ((d.mem_burst and d.mem_bw) = '1') then
if ( (r.dbg_state = TX_BYTE_LO)
and (v_shift_tx_data_done = '1')
) then
v.dbg_rd := '1';
else
v.dbg_rd := '0';
end if;
elsif ((d.mem_burst and not(d.mem_bw)) = '1') then
if ( (r.dbg_state = TX_BYTE_HI)
and (v_shift_tx_data_done = '1')
) then
v.dbg_rd := '1';
else
v.dbg_rd := '0';
end if;
elsif (v_cmd_valid = '1') then
v.dbg_rd := not(r.shift_buf(7));
else
v.dbg_rd := '0';
end if;
--! drive register inputs
rin <= v;
--! drive module outputs
dbg_addr <= r.dbg_addr; --! Debug register address
dbg_din <= v_dbg_din; --! Debug register data input
dbg_i2c_sda_out <= r.dbg_i2c_sda_out; --! Debug interface: I2C SDA OUT
dbg_rd <= r.dbg_rd; --! Debug register data read
dbg_wr <= r.dbg_wr; --! Debug register data write
end process COMB;
REGS : process (dbg_clk,dbg_rst)
begin
if (dbg_rst = '1') then
r <= ( scl_buf => "11", --! SCL input buffer
sda_in_buf => "11", --! SDA input buffer
sda_in_dly => '0', --! SDA Edge detection
scl_dly => '0', --! SCL Edge detection
scl_re_dly => "00", --! Delayed SCL Rising-Edge for SDA data sampling
i2c_active_seq => '0', --! I2C Slave Active
i2c_state => RX_ADDR, --! State register/wires
shift_buf => "000000000",--! Utility signals
dbg_rd => '0', --! Utility signals
dbg_i2c_sda_out => '0', --! I2C TRANSMIT BUFFER
dbg_state => RX_CMD, --! State register/wires
dbg_addr => "000000",
dbg_din_lo => "00000000",
dbg_din_hi => "00000000",
dbg_bw => '0', --! Utility signals
dbg_wr => '0' --! Debug register data write command
);
elsif rising_edge(dbg_clk) then
r <= rin;
end if;
end process REGS;
sync_cell_i2c_scl : fmsp_sync_cell
port map(
clk => dbg_clk,
rst => dbg_rst,
data_in => not(dbg_i2c_scl),
data_out => d.scl_sync_n
);
sync_cell_i2c_sda : fmsp_sync_cell
port map(
clk => dbg_clk,
rst => dbg_rst,
data_in => not(dbg_i2c_sda_in),
data_out => d.sda_in_sync_n
);
end RTL;
| bsd-3-clause | 2bb374c96a84d11f12f89ce27c36349d | 0.54249 | 2.594913 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_7_full_dsp_32/synth/convolve_kernel_ap_fadd_7_full_dsp_32.vhd | 1 | 14,042 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_5;
USE floating_point_v7_1_5.floating_point_v7_1_5;
ENTITY convolve_kernel_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fadd_7_full_dsp_32;
ARCHITECTURE convolve_kernel_ap_fadd_7_full_dsp_32_arch OF convolve_kernel_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_5 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_5,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_7_full_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_5,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_" &
"FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=" &
"0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0" &
"}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_result_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclken: SIGNAL IS "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : floating_point_v7_1_5
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fadd_7_full_dsp_32_arch;
| mit | 1929159361b637ee72333ca47bfb5be5 | 0.661088 | 3.03152 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ambatest/ahbtbm.vhd | 1 | 14,241 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtbm
-- File: ahbtbm.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: AHB Testbench master
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.ahbtbp.all;
entity ahbtbm is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in ahbtbm_ctrl_in_type;
ctrlo : out ahbtbm_ctrl_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end;
architecture rtl of ahbtbm is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
-- new /*
grant : std_logic;
grant2 : std_logic;
retry : std_logic_vector(1 downto 0);
read : std_logic; -- indicate
dbgl : integer;
use128 : integer;
hsize : std_logic_vector(2 downto 0);
ac : ahbtbm_access_array_type;
retryac : ahbtbm_access_type;
curac : ahbtbm_access_type;
haddr : std_logic_vector(31 downto 0); -- addr current access
hdata : std_logic_vector(31 downto 0); -- data currnet access
hdata128 : std_logic_vector(127 downto 0); -- data currnet access
hwrite : std_logic; -- write current access
hrdata : std_logic_vector(31 downto 0);
hrdata128 : std_logic_vector(127 downto 0);
status : ahbtbm_status_type;
dvalid : std_logic;
oldhtrans : std_logic_vector(1 downto 0);
-- new */
start : std_ulogic;
active : std_ulogic;
end record;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal r, rin : reg_type;
begin
ctrlo.rst <= rst;
ctrlo.clk <= clk;
comb : process(ahbmi, ctrli, rst, r)
-- new /*
variable v : reg_type;
variable update : std_logic;
variable hbusreq : std_ulogic; -- bus request
variable kblimit : std_logic; -- 1 kB limit indicator
-- new */
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(3 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(31 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(10 downto 0); -- next sequential address
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
-- new /*
v := r; update := '0'; hbusreq := '0';--v.retry := '0';
v.dvalid := '0'; xhirq := (others => '0');
hprot := "1110";
--v.hrdata := ahbmi.hrdata;
--v.hrdata128 := ahbmi.hrdata128;
v.hrdata := ahbmi.hrdata(31 downto 0);
v.hrdata128 := ahbread4word(ahbmi.hrdata);
-- pragma translate_off
if ahbmi.hready = '1' and ahbmi.hresp = HRESP_ERROR then
v.hrdata := (others => 'X');
v.hrdata128 := (others => 'X');
end if;
-- pragma translate_on
v.status.err := '0';
--v.oldhtrans := r.ac(1).htrans;
kblimit := '0';
-- Sample grant when hready
if ahbmi.hready = '1' then
v.grant := ahbmi.hgrant(hindex);
v.grant2 := r.grant;
v.oldhtrans := r.ac(1).htrans;
end if;
-- 1k limit
if (r.ac(0).htrans = HTRANS_SEQ
and (r.ac(0).haddr(10) xor r.ac(1).haddr(10)) = '1')
or (r.retryac.htrans = HTRANS_SEQ
and (r.retryac.haddr(10) xor r.ac(1).haddr(10)) = '1' and r.retry = "10") then
kblimit := '1';
end if;
-- Read in new access
--if ((ahbmi.hready = '1' and ahbmi.hresp = HRESP_OKAY and r.grant = '1')
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = '0' then
--if ahbmi.hready = '1' and ((ahbmi.hresp = HRESP_OKAY and r.grant = '1')
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
if ahbmi.hready = '0' and (ahbmi.hresp = HRESP_RETRY or ahbmi.hresp = HRESP_SPLIT) and r.grant2 = '1' then
if r.retry = "00" then
v.retryac := r.ac(1);
v.ac(1) := r.curac;
v.ac(1).htrans := HTRANS_IDLE;
v.ac(1).hburst := "000";
v.retry := "01";
elsif r.retry = "10" then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
end if;
elsif ahbmi.hready = '1' and ( r.grant = '1'
or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
-- elsif ahbmi.hready = '1' and (( r.grant = '1' and
-- (ahbmi.hresp = HRESP_OKAY or ahbmi.hresp = HRESP_ERROR))
-- or r.ac(1).htrans = HTRANS_IDLE) and r.retry = "00" then
v.ac(1) := r.ac(0); v.ac(0) := ctrli.ac;
v.curac := r.ac(1);
v.hdata := r.ac(1).hdata; v.haddr := r.ac(1).haddr;
v.hwrite := r.ac(1).hwrite; v.dbgl := r.ac(1).ctrl.dbgl;
v.use128 := r.ac(1).ctrl.use128;
if v.use128 = 0 then
v.hdata128 := r.ac(1).hdata & r.ac(1).hdata & r.ac(1).hdata & r.ac(1).hdata;
else
v.hdata128 := r.ac(1).hdata128;
end if;
v.hsize := r.ac(1).hsize;
v.read := (not r.ac(1).hwrite) and r.ac(1).htrans(1);
update := '1';
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
elsif ahbmi.hready = '0' and (ahbmi.hresp = HRESP_RETRY or ahbmi.hresp = HRESP_SPLIT) and r.grant2 = '1' then
if r.retry = "00" then
v.retryac := r.ac(1);
v.ac(1) := r.curac;
v.ac(1).htrans := HTRANS_IDLE;
v.ac(1).hburst := "000";
v.retry := "01";
elsif r.retry = "10" then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
end if;
elsif r.retry = "01" then
v.ac(1).htrans := HTRANS_NONSEQ;
v.ac(1).hburst := r.curac.hburst;
v.read := '0';
v.retry := "10";
elsif ahbmi.hready = '1' and r.grant = '1' and r.retry = "10" then
v.read := (not r.ac(1).hwrite) and r.ac(1).htrans(1);
--if ahbmi.hresp = HRESP_OKAY then
--if ahbmi.hresp = HRESP_OKAY or ahbmi.hresp = HRESP_ERROR then
v.ac(1) := r.retryac;
if kblimit = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
v.retry := "00";
--end if;
end if;
-- NONSEQ in retry
--if r.retry = '1' then v.ac(1).htrans := HTRANS_NONSEQ; end if;
-- NONSEQ if burst is interrupted
if r.grant = '0' and r.ac(1).htrans = HTRANS_SEQ then
v.ac(1).htrans := HTRANS_NONSEQ;
end if;
--if r.ac(1).htrans /= HTRANS_IDLE or r.ac(0).htrans /= HTRANS_IDLE then
-- hbusreq := '1';
--end if;
if r.ac(1).htrans = HTRANS_NONSEQ
or (r.ac(1).htrans = HTRANS_SEQ
and r.ac(0).htrans /= HTRANS_NONSEQ and kblimit = '0') then
hbusreq := '1';
end if;
--if r.grant = '0' then -- fix dvalid if grant deasserted *** ???
if r.grant = '0' and ahbmi.hready = '1' then
v.read := '0';
end if;
-- Check read data
if r.read = '1' and ahbmi.hresp = HRESP_OKAY and ahbmi.hready = '1' then
v.dvalid := '1';
if r.use128 = 0 then
--if r.hdata /= ahbmi.hrdata then
if r.hdata /= ahbmi.hrdata(31 downto 0) then
v.status.err := '1';
end if;
else
if r.hsize = "100" then
--if r.hdata128 /= ahbmi.hrdata128 then
if r.hdata128 /= ahbread4word(ahbmi.hrdata) then
v.status.err := '1';
end if;
else
--if r.hdata128(63 downto 0) /= ahbmi.hrdata128(63 downto 0) then
--if r.hdata128(63 downto 0) /= ahbmi.hrdata(63 downto 0) then
if r.hdata128(63 downto 0) /= ahbreaddword(ahbmi.hrdata) then
v.status.err := '1';
end if;
end if;
end if;
elsif r.read = '1' and ahbmi.hresp = HRESP_ERROR and ahbmi.hready = '1' then
v.status.err := '1';
end if;
-- new */
if rst = '0' then
v.ac(0).htrans := (others => '0');
v.ac(1).htrans := (others => '0');
v.retry := (others => '0');
v.read := '0';
v.ac(1).haddr := (others => '0');
v.ac(1).htrans := (others => '0');
v.ac(1).hwrite := '0';
v.ac(1).hsize := (others => '0');
v.ac(1).hburst := (others =>'0');
end if;
rin <= v;
ctrlo.update <= update;
ctrlo.status <= r.status;
ctrlo.hrdata <= r.hrdata;
ctrlo.hrdata128 <= r.hrdata128;
ctrlo.dvalid <= r.dvalid;
ahbmo.haddr <= r.ac(1).haddr;
ahbmo.htrans <= r.ac(1).htrans;
ahbmo.hbusreq <= hbusreq;
--ahbmo.hwdata <= r.hdata;
--ahbmo.hwdata128 <= r.hdata128;
ahbmo.hwdata <= ahbdrivedata(r.hdata128);
ahbmo.hconfig <= hconfig;
ahbmo.hlock <= '0';
ahbmo.hwrite <= r.ac(1).hwrite;
ahbmo.hsize <= r.ac(1).hsize;
ahbmo.hburst <= r.ac(1).hburst;
ahbmo.hprot <= r.ac(1).hprot;
ahbmo.hirq <= xhirq;
ahbmo.hindex <= hindex;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
-- pragma translate_off
if r.read = '1' and ahbmi.hready = '1' then --and r.oldhtrans /= HTRANS_IDLE then
if ahbmi.hresp = HRESP_OKAY then
if rin.status.err = '0' then
if r.dbgl >= 2 then
if r.use128 = 0 then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata(31 downto 0)));
else
if r.hsize = "100" then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata));
else print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbreaddword(ahbmi.hrdata))); end if;
end if;
end if;
else
if r.dbgl >= 1 then
if r.use128 = 0 then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata(31 downto 0))
& " != " & tost(r.hdata));
else
if r.hsize = "100" then print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbmi.hrdata)
& " != " & tost(r.hdata128));
else print(ptime & "Read[" & tost(r.haddr) & "]: " & tost(ahbreaddword(ahbmi.hrdata))
& " != " & tost(r.hdata128(63 downto 0)));
end if;
end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_RETRY then
if r.dbgl >= 3 then
print(ptime & "Read[" & tost(r.haddr) & "]: [RETRY]");
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Read[" & tost(r.haddr) & "]: [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_ERROR then
if r.dbgl >= 1 then
print(ptime & "Read[" & tost(r.haddr) & "]: [ERROR]");
end if;
end if;
end if;
if r.hwrite = '1' and ahbmi.hready = '1' and r.oldhtrans /= HTRANS_IDLE then
if ahbmi.hresp = HRESP_OKAY then
if r.dbgl >= 2 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata));
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128));
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0))); end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_RETRY then
if r.dbgl >= 3 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata) & " [RETRY]");
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128) & " [RETRY]");
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0)) & " [RETRY]"); end if;
end if;
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata)
& " [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_SPLIT then
if r.dbgl >= 3 then
print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata)
& " [SPLIT]");
end if;
elsif ahbmi.hresp = HRESP_ERROR then
if r.dbgl >= 1 then
if r.use128 = 0 then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata) & " [ERROR]");
else
if r.hsize = "100" then print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128) & " [ERROR]");
else print(ptime & "Write[" & tost(r.haddr) & "]: " & tost(r.hdata128(63 downto 0)) & " [ERROR]"); end if;
end if;
end if;
end if;
end if;
-- pragma translate_on
end if;
end process;
end;
| gpl-2.0 | 06e8d335d97a67aef1226288605e4e32 | 0.533811 | 3.301113 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/dbg/fmsp_dbg.vhd | 1 | 44,946 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_dbg.vhd
--!
--! @brief fpgaMSP430 Debug interface
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use work.fmsp_functions.all;
use work.fmsp_dbg_package.all;
entity fmsp_dbg is
generic (
DBG_UART : boolean := false; --! Enable UART (8N1) debug interface
DBG_I2C : boolean := true; --! Enable I2C debug interface
DBG_I2C_BROADCAST_EN : boolean := false; --! Enable the I2C broadcast address
DBG_RST_BRK_EN : boolean := false; --! CPU break on PUC reset
DBG_HWBRK_0_EN : boolean := false; --! Include hardware breakpoints unit
DBG_HWBRK_1_EN : boolean := false; --! Include hardware breakpoints unit
DBG_HWBRK_2_EN : boolean := false; --! Include hardware breakpoints unit
DBG_HWBRK_3_EN : boolean := false; --! Include hardware breakpoints unit
DBG_HWBRK_RANGE : boolean := true; --! Enable/Disable the hardware breakpoint RANGE mode
DBG_UART_AUTO_SYNC : boolean := true; --! Debug UART interface auto data synchronization
DBG_UART_BAUD : integer := 9600; --! Debug UART interface data rate
DBG_DCO_FREQ : integer := 20000000; --! Debug DCO_CLK frequency
SYNC_DBG_UART_RXD : boolean := true --! Synchronize RXD inputs
);
port (
dbg_clk : in std_logic; --! Debug unit clock
dbg_rst : in std_logic; --! Debug unit reset
--! INPUTs
cpu_en_s : in std_logic; --! Enable CPU code execution (synchronous)
cpu_id : in std_logic_vector(31 downto 0); --! CPU ID
cpu_nr_inst : in std_logic_vector(7 downto 0); --! Current fmsp instance number
cpu_nr_total : in std_logic_vector(7 downto 0); --! Total number of fmsp instances-1
dbg_en_s : in std_logic; --! Debug interface enable (synchronous)
dbg_halt_st : in std_logic; --! Halt/Run status from CPU
dbg_i2c_addr : in std_logic_vector(6 downto 0); --! Debug interface: I2C Address
dbg_i2c_broadcast : in std_logic_vector(6 downto 0); --! Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl : in std_logic; --! Debug interface: I2C SCL
dbg_i2c_sda_in : in std_logic; --! Debug interface: I2C SDA IN
dbg_mem_din : in std_logic_vector(15 downto 0); --! Debug unit Memory data input
dbg_reg_din : in std_logic_vector(15 downto 0); --! Debug unit CPU register data input
dbg_uart_rxd : in std_logic; --! Debug interface: UART RXD (asynchronous)
decode_noirq : in std_logic; --! Frontend decode instruction
eu_mab : in std_logic_vector(15 downto 0); --! Execution-Unit Memory address bus
eu_mb_en : in std_logic; --! Execution-Unit Memory bus enable
eu_mb_wr : in std_logic_vector(1 downto 0); --! Execution-Unit Memory bus write transfer
fe_mdb_in : in std_logic_vector(15 downto 0); --! Frontend Memory data bus input
pc : in std_logic_vector(15 downto 0); --! Program counter
puc_pnd_set : in std_logic; --! PUC pending set for the serial debug interface
--! OUTPUTs
dbg_cpu_reset : out std_logic; --! Reset CPU from debug interface
dbg_freeze : out std_logic; --! Freeze peripherals
dbg_halt_cmd : out std_logic; --! Halt CPU command
dbg_i2c_sda_out : out std_logic := '1'; --! Debug interface: I2C SDA OUT
dbg_mem_addr : out std_logic_vector(15 downto 0); --! Debug address for rd/wr access
dbg_mem_dout : out std_logic_vector(15 downto 0); --! Debug unit data output
dbg_mem_en : out std_logic; --! Debug unit memory enable
dbg_mem_wr : out std_logic_vector(1 downto 0); --! Debug unit memory write
dbg_reg_wr : out std_logic; --! Debug unit CPU register write
dbg_uart_txd : out std_logic := '1' --! Debug interface: UART TXD
);
end entity fmsp_dbg;
architecture RTL of fmsp_dbg is
--! Debug interface: Software breakpoint opcode
constant DBG_SWBRK_OP : std_logic_vector(15 downto 0) :=x"4343";
----! State machine definition
constant M_IDLE : std_logic_vector(1 downto 0) := "00";
constant M_SET_BRK : std_logic_vector(1 downto 0) := "01";
constant M_ACCESS_BRK : std_logic_vector(1 downto 0) := "10";
constant M_ACCESS : std_logic_vector(1 downto 0) := "11";
--! Debug interface
constant DBG_UART_WR : integer := 18;
constant DBG_UART_BW : integer := 17;
-- constant DBG_UART_ADDR 16:11
--! Debug interface CPU_CTL register
constant HALT : integer := 0;
constant RUN : integer := 1;
constant ISTEP : integer := 2;
constant SW_BRK_EN : integer := 3;
constant FRZ_BRK_EN : integer := 4;
constant RST_BRK_EN : integer := 5;
constant CPU_RST : integer := 6;
--! Debug interface CPU_STAT register
constant HALT_RUN : integer := 0;
constant PUC_PND : integer := 1;
constant SWBRK_PND : integer := 3;
constant HWBRK0_PND : integer := 4;
constant HWBRK1_PND : integer := 5;
--! Debug interface BRKx_CTL register
constant BRK_MODE_RD : integer := 0;
constant BRK_MODE_WR : integer := 1;
-- constant BRK_MODE 1:0
constant BRK_EN : integer := 2;
constant BRK_I_EN : integer := 3;
constant BRK_RANGE : integer := 4;
--! Number of registers
constant NR_REG : integer := 25;
--! Register addresses
constant CPU_ID_LO : integer := 00;
constant CPU_ID_HI : integer := 01;
constant CPU_CTL : integer := 02;
constant CPU_STAT : integer := 03;
constant MEM_CTL : integer := 04;
constant MEM_ADDR : integer := 05;
constant C_MEM_DATA : integer := 06;
constant MEM_CNT : integer := 07;
constant BRK0_CTL : integer := 08;
constant BRK0_STAT : integer := 09;
constant BRK0_ADDR0 : integer := 10;
constant BRK0_ADDR1 : integer := 11;
constant BRK1_CTL : integer := 12;
constant BRK1_STAT : integer := 13;
constant BRK1_ADDR0 : integer := 14;
constant BRK1_ADDR1 : integer := 15;
constant BRK2_CTL : integer := 16;
constant BRK2_STAT : integer := 17;
constant BRK2_ADDR0 : integer := 18;
constant BRK2_ADDR1 : integer := 19;
constant BRK3_CTL : integer := 20;
constant BRK3_STAT : integer := 21;
constant BRK3_ADDR0 : integer := 22;
constant BRK3_ADDR1 : integer := 23;
constant CPU_NR : integer := 24;
type fmsp_dbg_in_type is record
cpu_en_s : std_logic; --! Enable CPU code execution (synchronous)
cpu_id : std_logic_vector(31 downto 0); --! CPU ID
cpu_nr_inst : std_logic_vector(7 downto 0); --! Current fmsp instance number
cpu_nr_total : std_logic_vector(7 downto 0); --! Total number of fmsp instances-1
dbg_en_s : std_logic; --! Debug interface enable (synchronous)
dbg_halt_st : std_logic; --! Halt/Run status from CPU
dbg_i2c_addr : std_logic_vector(6 downto 0); --! Debug interface: I2C Address
dbg_i2c_broadcast : std_logic_vector(6 downto 0); --! Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl : std_logic; --! Debug interface: I2C SCL
dbg_i2c_sda_in : std_logic; --! Debug interface: I2C SDA IN
dbg_mem_din : std_logic_vector(15 downto 0); --! Debug unit Memory data input
dbg_reg_din : std_logic_vector(15 downto 0); --! Debug unit CPU register data input
dbg_uart_rxd : std_logic; --! Debug interface: UART RXD (asynchronous)
decode_noirq : std_logic; --! Frontend decode instruction
eu_mab : std_logic_vector(15 downto 0); --! Execution-Unit Memory address bus
eu_mb_en : std_logic; --! Execution-Unit Memory bus enable
eu_mb_wr : std_logic_vector(1 downto 0); --! Execution-Unit Memory bus write transfer
fe_mdb_in : std_logic_vector(15 downto 0); --! Frontend Memory data bus input
pc : std_logic_vector(15 downto 0); --! Program counter
puc_pnd_set : std_logic; --! PUC pending set for the serial debug interface
--! frome Sub modules
brk0_halt : std_logic;
brk0_pnd : std_logic;
brk0_dout : std_logic_vector(15 downto 0);
brk1_halt : std_logic;
brk1_pnd : std_logic;
brk1_dout : std_logic_vector(15 downto 0);
brk2_halt : std_logic;
brk2_pnd : std_logic;
brk2_dout : std_logic_vector(15 downto 0);
brk3_halt : std_logic;
brk3_pnd : std_logic;
brk3_dout : std_logic_vector(15 downto 0);
dbg_addr_rs232 : std_logic_vector(5 downto 0);
dbg_din_rs232 : std_logic_vector(15 downto 0);
dbg_wr_rs232 : std_logic;
dbg_rd_rs232 : std_logic;
dbg_addr_i2c : std_logic_vector(5 downto 0);
dbg_din_i2c : std_logic_vector(15 downto 0);
dbg_wr_i2c : std_logic;
dbg_rd_i2c : std_logic;
end record;
type reg_type is record
mem_burst : std_logic;
dbg_mem_rd_dly : std_logic;
dbg_rd_rdy : std_logic;
--! Register address decode
reg_dec : std_logic_vector(NR_REG-1 downto 0);
cpu_ctl : std_logic_vector(6 downto 3);
cpu_stat : std_logic_vector(3 downto 2);
mem_ctl : std_logic_vector(3 downto 1);
mem_start : std_logic;
mem_data : std_logic_vector(15 downto 0);
mem_addr : std_logic_vector(15 downto 0);
mem_cnt : std_logic_vector(15 downto 0);
--! Single step
inc_step : std_logic_vector(1 downto 0);
--! Run / Halt
halt_flag : std_logic;
--! Memory access state machine
mem_state : std_logic_vector(1 downto 0);
mem_state_nxt : std_logic_vector(1 downto 0);
--! Trigger CPU Register or memory access during a burst
mem_startb : std_logic;
end record;
signal d : fmsp_dbg_in_type;
signal r : reg_type := ( mem_burst => '0',
dbg_mem_rd_dly => '0',
dbg_rd_rdy => '0',
reg_dec => (Others => '0'),
cpu_ctl => "0000",
cpu_stat => "00",
mem_ctl => "000",
mem_start => '0',
mem_data => x"0000",
mem_addr => x"0000",
mem_cnt => x"0000",
inc_step => "00",
halt_flag => '0',
mem_state => "00",
mem_state_nxt => "00",
mem_startb => '0'
);
signal rin : reg_type;
signal mem_bw : std_logic;
--! Hardware Breakpoint/Watchpoint Register read select
signal brk0_reg_rd : std_logic_vector(3 downto 0) := "0000";
signal brk1_reg_rd : std_logic_vector(3 downto 0) := "0000";
signal brk2_reg_rd : std_logic_vector(3 downto 0) := "0000";
signal brk3_reg_rd : std_logic_vector(3 downto 0) := "0000";
--! Hardware Breakpoint/Watchpoint Register write select
signal brk0_reg_wr : std_logic_vector(3 downto 0) := "0000";
signal brk1_reg_wr : std_logic_vector(3 downto 0) := "0000";
signal brk2_reg_wr : std_logic_vector(3 downto 0) := "0000";
signal brk3_reg_wr : std_logic_vector(3 downto 0) := "0000";
signal dbg_addr : std_logic_vector(5 downto 0);
signal dbg_din : std_logic_vector(15 downto 0);
signal dbg_wr : std_logic;
signal dbg_rd : std_logic;
signal dbg_dout : std_logic_vector(15 downto 0);
signal mem_burst_end : std_logic;
signal mem_burst_rd : std_logic;
signal mem_burst_wr : std_logic;
begin
d.cpu_en_s <= cpu_en_s; --! Enable CPU code execution (synchronous)
d.cpu_id <= cpu_id; --! CPU ID
d.cpu_nr_inst <= cpu_nr_inst; --! Current fmsp instance number
d.cpu_nr_total <= cpu_nr_total; --! Total number of fmsp instances-1
d.dbg_en_s <= dbg_en_s; --! Debug interface enable (synchronous)
d.dbg_halt_st <= dbg_halt_st; --! Halt/Run status from CPU
d.dbg_i2c_addr <= dbg_i2c_addr; --! Debug interface: I2C Address
d.dbg_i2c_broadcast <= dbg_i2c_broadcast; --! Debug interface: I2C Broadcast Address (for multicore systems)
d.dbg_i2c_scl <= dbg_i2c_scl; --! Debug interface: I2C SCL
d.dbg_i2c_sda_in <= dbg_i2c_sda_in; --! Debug interface: I2C SDA IN
d.dbg_mem_din <= dbg_mem_din; --! Debug unit Memory data input
d.dbg_reg_din <= dbg_reg_din; --! Debug unit CPU register data input
d.dbg_uart_rxd <= dbg_uart_rxd; --! Debug interface: UART RXD (asynchronous)
d.decode_noirq <= decode_noirq; --! Frontend decode instruction
d.eu_mab <= eu_mab; --! Execution-Unit Memory address bus
d.eu_mb_en <= eu_mb_en; --! Execution-Unit Memory bus enable
d.eu_mb_wr <= eu_mb_wr; --! Execution-Unit Memory bus write transfer
d.fe_mdb_in <= fe_mdb_in; --! Frontend Memory data bus input
d.pc <= pc; --! Program counter
d.puc_pnd_set <= puc_pnd_set; --! PUC pending set for the serial debug interface
COMB : process (d, r)
variable v : reg_type;
--============================================================================
--! 2) REGISTER DECODER
--============================================================================
--=============================================================================
--! 1) variable v_& PARAMETER DECLARATION
--=============================================================================
--! Diverse wires and registers
variable v_dbg_addr : std_logic_vector(5 downto 0);
variable v_dbg_din : std_logic_vector(15 downto 0);
variable v_dbg_wr : std_logic;
variable v_dbg_rd : std_logic;
--! Select Data register during a burst
variable v_dbg_addr_in : std_logic_vector(5 downto 0);
--! Register address decode
variable v_reg_dec : std_logic_vector(63 downto 0);
--! Read/Write probes
variable v_reg_write : std_logic;
variable v_reg_read : std_logic;
--! Read/Write vectors
variable v_reg_wr : std_logic_vector(NR_REG-1 downto 0);
variable v_reg_rd : std_logic_vector(NR_REG-1 downto 0);
--! 3) REGISTER: CORE INTERFACE
--! CPU_NR Register
variable v_cpu_nr : std_logic_vector(15 downto 0);
--! CPU_CTL Register
variable v_cpu_ctl_wr : std_logic;
variable v_cpu_ctl_full : std_logic_vector(7 downto 0);
variable v_halt_cpu : std_logic;
variable v_run_cpu : std_logic;
variable v_istep : std_logic;
--! CPU_STAT Register
variable v_cpu_stat_wr : std_logic;
variable v_cpu_stat_set : std_logic_vector(3 downto 2);
variable v_cpu_stat_clr : std_logic_vector(3 downto 2);
variable v_cpu_stat_full : std_logic_vector(7 downto 0);
--! 4) REGISTER: MEMORY INTERFACE
--! MEM_CTL Register
variable v_mem_ctl_wr : std_logic;
variable v_mem_ctl_full : std_logic_vector(7 downto 0);
variable v_mem_bw : std_logic;
--! C_MEM_DATA Register
variable v_mem_access : std_logic;
variable v_mem_data_wr : std_logic;
variable v_dbg_mem_din_bw : std_logic_vector(15 downto 0);
--! MEM_ADDR Register
variable v_mem_addr_wr : std_logic;
variable v_dbg_mem_acc : std_logic;
variable v_dbg_reg_acc : std_logic;
variable v_mem_addr_inc : std_logic_vector(15 downto 0);
--! MEM_CNT Register
variable v_mem_cnt_wr : std_logic;
variable v_mem_cnt_dec : std_logic_vector(15 downto 0);
--! 6) DATA OUTPUT GENERATION
variable v_cpu_id_lo_rd : std_logic_vector(15 downto 0);
variable v_cpu_id_hi_rd : std_logic_vector(15 downto 0);
variable v_cpu_ctl_rd : std_logic_vector(15 downto 0);
variable v_cpu_stat_rd : std_logic_vector(15 downto 0);
variable v_mem_ctl_rd : std_logic_vector(15 downto 0);
variable v_mem_data_rd : std_logic_vector(15 downto 0);
variable v_mem_addr_rd : std_logic_vector(15 downto 0);
variable v_mem_cnt_rd : std_logic_vector(15 downto 0);
variable v_cpu_nr_rd : std_logic_vector(15 downto 0);
variable v_dbg_dout : std_logic_vector(15 downto 0);
--! 7) CPU CONTROL
--! Reset CPU
variable v_dbg_cpu_reset : std_logic;
--! Break after reset
variable v_halt_rst : std_logic;
--! Freeze peripherals
variable v_dbg_freeze : std_logic;
--! Software break
variable v_dbg_swbrk : std_logic;
variable v_mem_halt_cpu : std_logic;
variable v_mem_run_cpu : std_logic;
variable v_halt_flag_clr : std_logic;
variable v_halt_flag_set : std_logic;
variable v_dbg_halt_cmd : std_logic;
--! 8) MEMORY CONTROL
variable v_mem_state_nxt : std_logic_vector(1 downto 0);
--! Control Memory bursts
variable v_mem_burst_start : std_logic;
variable v_mem_burst_end : std_logic;
--! Control signals for UART/I2C interface
variable v_mem_burst_rd : std_logic;
variable v_mem_burst_wr : std_logic;
--! Combine single and burst memory start of sequence
variable v_mem_seq_start : std_logic;
--! Interface to CPU Registers and Memory bacbkone
variable v_dbg_mem_addr : std_logic_vector(15 downto 0);
variable v_dbg_mem_dout : std_logic_vector(15 downto 0);
variable v_dbg_reg_wr : std_logic;
variable v_dbg_reg_rd : std_logic;
variable v_dbg_mem_en : std_logic;
variable v_dbg_mem_rd : std_logic;
variable v_dbg_mem_wr_msk : std_logic_vector(1 downto 0);
variable v_dbg_mem_wr : std_logic_vector(1 downto 0);
--! UNUSED UART COMMUNICATION
variable UNUSED_dbg_uart_rxd : std_logic;
--! UNUSED I2C COMMUNICATION
variable UNUSED_dbg_i2c_addr : std_logic_vector(6 downto 0);
variable UNUSED_dbg_i2c_broadcast : std_logic_vector(6 downto 0);
variable UNUSED_dbg_i2c_scl : std_logic;
variable UNUSED_dbg_i2c_sda_in : std_logic;
variable UNUSED_dbg_rd_rdy : std_logic;
begin
--! default assignment
v := r;
--! overriding assignments
if (DBG_UART = true) then
v_dbg_addr := d.dbg_addr_rs232; --! Debug register address
v_dbg_din := d.dbg_din_rs232; --! Debug register data input
v_dbg_rd := d.dbg_rd_rs232; --! Debug register data read
v_dbg_wr := d.dbg_wr_rs232; --! Debug register data write
elsif (DBG_I2C = true) then
v_dbg_addr := d.dbg_addr_i2c; --! Debug register address
v_dbg_din := d.dbg_din_i2c; --! Debug register data input
v_dbg_rd := d.dbg_rd_i2c; --! Debug register data read
v_dbg_wr := d.dbg_wr_i2c; --! Debug register data write
else
v_dbg_addr := "000000"; --! Debug register address
v_dbg_din := x"0000"; --! Debug register data input
v_dbg_rd := '0'; --! Debug register data read
v_dbg_wr := '0'; --! Debug register data writ
end if;
--============================================================================
--! 2) REGISTER DECODER
--============================================================================
--! Select Data register during a burst
if (r.mem_burst = '1') then
v_dbg_addr_in := STD_LOGIC_VECTOR(TO_UNSIGNED(C_MEM_DATA,6));
else
v_dbg_addr_in := v_dbg_addr;
end if;
--! Register address decode
v_reg_dec := onehot(v_dbg_addr_in);
--! Read/Write probes
v_reg_write := v_dbg_wr;
v_reg_read := '1';
--! Read/Write vectors
if (v_reg_write = '1') then
v_reg_wr := v_reg_dec(NR_REG-1 downto 0);
else
v_reg_wr := (Others => '0');
end if;
if (v_reg_read = '1') then
v_reg_rd := v_reg_dec(NR_REG-1 downto 0);
else
v_reg_rd := (Others => '0');
end if;
--=============================================================================
--! 3) REGISTER: CORE INTERFACE
--=============================================================================
--! CPU_ID Register
-------------------
--! -------------------------------------------------------------------
--! CPU_ID_LO: | 15 14 13 12 11 10 9 | 8 7 6 5 4 | 3 | 2 1 0 |
--! |----------------------------+-----------------+------+-------------|
--! | PER_SPACE | USER_VERSION | ASIC | CPU_VERSION |
--! --------------------------------------------------------------------
--! CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 |
--! |----------------------------+-------------------------------+------|
--! | PMEM_SIZE | DMEM_SIZE | MPY |
--! -------------------------------------------------------------------
--! This register is assigned in the SFR module
--! CPU_NR Register
-------------------
--! -------------------------------------------------------------------
--! | 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
--! |---------------------------------+---------------------------------|
--! | CPU_TOTAL_NR | CPU_INST_NR |
--! -------------------------------------------------------------------
v_cpu_nr := d.cpu_nr_total & d.cpu_nr_inst;
--! CPU_CTL Register
-------------------------------------------------------------------------------
--! 7 6 5 4 3 2 1 0
--! Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT
-------------------------------------------------------------------------------
v_cpu_ctl_wr := v_reg_wr(CPU_CTL);
if (v_cpu_ctl_wr = '1') then
v.cpu_ctl := v_dbg_din(6 downto 3);
end if;
v_cpu_ctl_full := '0' & r.cpu_ctl & "000";
v_halt_cpu := v_cpu_ctl_wr and v_dbg_din(HALT) and not( d.dbg_halt_st);
v_run_cpu := v_cpu_ctl_wr and v_dbg_din(RUN) and d.dbg_halt_st;
v_istep := v_cpu_ctl_wr and v_dbg_din(ISTEP) and d.dbg_halt_st;
--! Reset CPU
v_dbg_cpu_reset := r.cpu_ctl(CPU_RST);
--! Break after reset
v_halt_rst := r.cpu_ctl(RST_BRK_EN) and d.dbg_en_s and d.puc_pnd_set;
--! Freeze peripherals
v_dbg_freeze := d.dbg_halt_st and ( r.cpu_ctl(FRZ_BRK_EN) or not(d.cpu_en_s) );
--! Software break
v_dbg_swbrk := '0';
if (d.fe_mdb_in = DBG_SWBRK_OP) then
v_dbg_swbrk := d.decode_noirq and r.cpu_ctl(SW_BRK_EN);
end if;
--! Single step
if (v_istep = '1') then
v.inc_step := "11";
else
v.inc_step := r.inc_step(0) & '0';
end if;
--============================================================================
--! 7) CPU CONTROL
--============================================================================
--! Run / Halt
v_halt_flag_clr := v_run_cpu or v_mem_run_cpu;
v_halt_flag_set := v_halt_cpu or v_halt_rst or v_dbg_swbrk or v_mem_halt_cpu or d.brk0_halt or d.brk1_halt or d.brk2_halt or d.brk3_halt;
if (v_halt_flag_clr = '1') then
v.halt_flag := '0';
elsif (v_halt_flag_set = '1') then
v.halt_flag := '1';
end if;
v_dbg_halt_cmd := (r.halt_flag or v_halt_flag_set) and not(r.inc_step(1));
--! CPU_STAT Register
--------------------------------------------------------------------------------------
--! 7 6 5 4 3 2 1 0
--! HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
--------------------------------------------------------------------------------------
v_cpu_stat_wr := v_reg_wr(CPU_STAT);
v_cpu_stat_set := v_dbg_swbrk & d.puc_pnd_set;
v_cpu_stat_clr := not(v_dbg_din(3 downto 2));
if (v_cpu_stat_wr = '1') then
v.cpu_stat := v_cpu_stat_set or (r.cpu_stat and v_cpu_stat_clr);
else
v.cpu_stat := v_cpu_stat_set or r.cpu_stat;
end if;
v_cpu_stat_full := d.brk3_pnd & d.brk2_pnd & d.brk1_pnd & d.brk0_pnd & r.cpu_stat & '0' & d.dbg_halt_st;
-- UNUSED_eu_mab := eu_mab;
-- UNUSED_eu_mb_en := eu_mb_en;
-- UNUSED_eu_mb_wr := eu_mb_wr;
-- UNUSED_pc := pc;
--============================================================================
--! 8) MEMORY CONTROL
--============================================================================
--! Control Memory bursts
if ( (r.mem_cnt /= x"0000") and (r.mem_start = '1') ) then
v_mem_burst_start := '1';
else
v_mem_burst_start := '0';
end if;
if ( (r.mem_cnt = x"0000") and ((v_dbg_wr or r.dbg_rd_rdy) = '1') ) then
v_mem_burst_end := '1';
else
v_mem_burst_end := '0';
end if;
--! Detect when burst is on going
if (v_mem_burst_start = '1') then
v.mem_burst := '1';
elsif (v_mem_burst_end = '1') then
v.mem_burst := '0';
end if;
--! Control signals for UART/I2C interface
v_mem_burst_rd := v_mem_burst_start and not(r.mem_ctl(1));
v_mem_burst_wr := v_mem_burst_start and r.mem_ctl(1);
--! Trigger CPU Register or memory access during a burst
v.mem_startb := (r.mem_burst and (v_dbg_wr or v_dbg_rd)) or v_mem_burst_rd;
--! Combine single and burst memory start of sequence
if ( ( (r.mem_cnt = x"0000")
and (r.mem_start = '1') )
or (r.mem_startb = '1') )then
v_mem_seq_start := '1';
else
v_mem_seq_start := '0';
end if;
--! Memory access state machine
--------------------------------
--! State transition
case (r.mem_state) is
when M_IDLE =>
if (not(v_mem_seq_start) = '1') then
v_mem_state_nxt := M_IDLE;
elsif (d.dbg_halt_st = '1') then
v_mem_state_nxt := M_ACCESS;
else
v_mem_state_nxt := M_SET_BRK;
end if;
when M_SET_BRK =>
if (d.dbg_halt_st = '1') then
v_mem_state_nxt := M_ACCESS_BRK;
else
v_mem_state_nxt := M_SET_BRK;
end if;
when M_ACCESS_BRK =>
v_mem_state_nxt := M_IDLE;
when M_ACCESS =>
v_mem_state_nxt := M_IDLE;
when others =>
v_mem_state_nxt := M_IDLE;
end case;
--! State machine
v.mem_state := v_mem_state_nxt;
--! Utility signals
v_mem_halt_cpu := '0';
v_mem_run_cpu := '0';
v_mem_access := '0';
if ( (r.mem_state = M_IDLE)
and (v_mem_state_nxt = M_SET_BRK) ) then
v_mem_halt_cpu := '1';
end if;
if ( (r.mem_state = M_ACCESS_BRK)
and (v_mem_state_nxt = M_IDLE) ) then
v_mem_run_cpu := '1';
end if;
if ( (r.mem_state = M_ACCESS)
or (r.mem_state = M_ACCESS_BRK) ) then
v_mem_access := '1';
end if;
--! Interface to CPU Registers and Memory bacbkone
--------------------------------------------------
v_dbg_mem_addr := r.mem_addr;
if (not(v_mem_bw) = '1') then
v_dbg_mem_dout := r.mem_data;
elsif (r.mem_addr(0) = '1') then
v_dbg_mem_dout := r.mem_data(7 downto 0) & x"00";
else
v_dbg_mem_dout := x"00" & r.mem_data(7 downto 0);
end if;
v_dbg_reg_wr := v_mem_access and r.mem_ctl(1) and r.mem_ctl(2);
v_dbg_reg_rd := v_mem_access and not(r.mem_ctl(1)) and r.mem_ctl(2);
v_dbg_mem_en := v_mem_access and not(r.mem_ctl(2));
v_dbg_mem_rd := dbg_mem_en and not(r.mem_ctl(1));
if (not(v_mem_bw) = '1') then
v_dbg_mem_wr_msk := "11";
elsif (r.mem_addr(0) = '1') then
v_dbg_mem_wr_msk := "10";
else
v_dbg_mem_wr_msk := "01";
end if;
v_dbg_mem_wr := "00";
if ( (dbg_mem_en = '1')
and (r.mem_ctl(1) = '1') ) then
v_dbg_mem_wr := v_dbg_mem_wr_msk;
end if;
--! It takes one additional cycle to read from Memory as from registers
v.dbg_mem_rd_dly := v_dbg_mem_rd;
--=============================================================================
--! 4) REGISTER: MEMORY INTERFACE
--=============================================================================
--! MEM_CTL Register
-------------------------------------------------------------------------------
--! 7 6 5 4 3 2 1 0
--! Reserved B/W MEM/REG RD/WR START
--
--! START : - 0 : Do nothing.
--! - 1 : Initiate memory transfer.
--
--! RD/WR : - 0 : Read access.
--! - 1 : Write access.
--
--! MEM/REG: - 0 : Memory access.
--! - 1 : CPU Register access.
--
--! B/W : - 0 : 16 bit access.
--! - 1 : 8 bit access (not valid for CPU Registers).
--
-------------------------------------------------------------------------------
v_mem_ctl_wr := v_reg_wr(MEM_CTL);
if (v_mem_ctl_wr = '1') then
v.mem_ctl := v_dbg_din(3 downto 1);
end if;
v_mem_ctl_full := "0000" & r.mem_ctl & '0';
v.mem_start := v_mem_ctl_wr and v_dbg_din(0);
v_mem_bw := r.mem_ctl(3);
--! C_MEM_DATA Register
--------------------
v_mem_data_wr := v_reg_wr(C_MEM_DATA);
if (not(v_mem_bw) = '1') then
v_dbg_mem_din_bw := d.dbg_mem_din;
elsif (r.mem_addr(0) = '1') then
v_dbg_mem_din_bw := x"00" & d.dbg_mem_din(15 downto 8);
else
v_dbg_mem_din_bw := x"00" & d.dbg_mem_din(7 downto 0);
end if;
if (v_mem_data_wr = '1') then
v.mem_data := v_dbg_din;
elsif (v_dbg_reg_rd = '1') then
v.mem_data := d.dbg_reg_din;
elsif (r.dbg_mem_rd_dly = '1') then
v.mem_data := v_dbg_mem_din_bw;
end if;
--! MEM_ADDR Register
--------------------
v_mem_addr_wr := v_reg_wr(MEM_ADDR);
v_dbg_mem_acc := ( v_dbg_mem_wr(0) or v_dbg_mem_wr(1) or ( r.dbg_rd_rdy and not(r.mem_ctl(2)) ) );
v_dbg_reg_acc := ( dbg_reg_wr or ( r.dbg_rd_rdy and r.mem_ctl(2) ) );
if (r.mem_cnt = x"0000") then
v_mem_addr_inc := x"0000";
elsif ((r.mem_burst and v_dbg_mem_acc and not(v_mem_bw)) = '1') then
v_mem_addr_inc := x"0000";
elsif ((r.mem_burst and (v_dbg_mem_acc or v_dbg_reg_acc)) = '1') then
v_mem_addr_inc := x"0001";
else
v_mem_addr_inc := x"0000";
end if;
if (v_mem_addr_wr = '1') then
v.mem_addr := v_dbg_din;
else
v.mem_addr := STD_LOGIC_VECTOR( UNSIGNED(r.mem_addr) + UNSIGNED(v_mem_addr_inc) );
end if;
--! MEM_CNT Register
--------------------
v_mem_cnt_wr := v_reg_wr(MEM_CNT);
if (r.mem_cnt = x"0000") then
v_mem_cnt_dec := x"0000";
elsif ((r.mem_burst and (v_dbg_mem_acc or v_dbg_reg_acc)) = '1') then
v_mem_cnt_dec := x"FFFF";
else
v_mem_cnt_dec := x"0000";
end if;
if (v_mem_cnt_wr = '1') then
v.mem_cnt := v_dbg_din;
else
v.mem_cnt := STD_LOGIC_VECTOR( UNSIGNED(r.mem_cnt) + UNSIGNED(v_mem_cnt_dec) );
end if;
--=============================================================================
--! 9) UART COMMUNICATION
--=============================================================================
if (DBG_UART = false) then
UNUSED_dbg_uart_rxd := d.dbg_uart_rxd;
end if;
--=============================================================================
--! 10) I2C COMMUNICATION
--=============================================================================
if (DBG_I2C = false) then
UNUSED_dbg_i2c_addr := d.dbg_i2c_addr;
UNUSED_dbg_i2c_broadcast := d.dbg_i2c_broadcast;
UNUSED_dbg_i2c_scl := d.dbg_i2c_scl;
UNUSED_dbg_i2c_sda_in := d.dbg_i2c_sda_in;
--v_UNUSED_dbg_rd_rdy := d.dbg_rd_rdy;
end if;
--============================================================================
--! 6) DATA OUTPUT GENERATION
--============================================================================
-- v_cpu_id_lo_rd := word_per_select_dout( CPU_ID_LO, v_reg_rd, d.cpu_id(15 downto 0) );
-- v_cpu_id_hi_rd := word_per_select_dout( CPU_ID_HI, v_reg_rd, d.cpu_id(31 downto 16) );
-- v_cpu_ctl_rd := word_per_select_dout( CPU_CTL, v_reg_rd, (x"00" & v_cpu_ctl_full) );
-- v_cpu_stat_rd := word_per_select_dout( CPU_STAT, v_reg_rd, (x"00" & v_cpu_stat_full) );
-- v_mem_ctl_rd := word_per_select_dout( MEM_CTL, v_reg_rd, (x"00" & v_mem_ctl_full) );
-- v_mem_data_rd := word_per_select_dout( C_MEM_DATA, v_reg_rd, r.mem_data );
-- v_mem_addr_rd := word_per_select_dout( MEM_ADDR, v_reg_rd, r.mem_addr );
-- v_mem_cnt_rd := word_per_select_dout( MEM_CNT, v_reg_rd, r.mem_cnt );
-- v_cpu_nr_rd := word_per_select_dout( CPU_NR, v_reg_rd, v_cpu_nr );
if ( v_reg_rd(CPU_ID_LO) = '1' ) then
v_cpu_id_lo_rd := d.cpu_id(15 downto 0);
else
v_cpu_id_lo_rd := x"0000";
end if;
if ( v_reg_rd(CPU_ID_HI) = '1' ) then
v_cpu_id_hi_rd := d.cpu_id(31 downto 16);
else
v_cpu_id_hi_rd := x"0000";
end if;
if ( v_reg_rd(CPU_CTL) = '1' ) then
v_cpu_ctl_rd := x"00" & v_cpu_ctl_full;
else
v_cpu_ctl_rd := x"0000";
end if;
if ( v_reg_rd(CPU_STAT) = '1' ) then
v_cpu_stat_rd := x"00" & v_cpu_stat_full;
else
v_cpu_stat_rd := x"0000";
end if;
if ( v_reg_rd(MEM_CTL) = '1' ) then
v_mem_ctl_rd := x"00" & v_mem_ctl_full;
else
v_mem_ctl_rd := x"0000";
end if;
if ( v_reg_rd(C_MEM_DATA) = '1' ) then
v_mem_data_rd := r.mem_data;
else
v_mem_data_rd := x"0000";
end if;
if ( v_reg_rd(MEM_ADDR) = '1' ) then
v_mem_addr_rd := r.mem_addr;
else
v_mem_addr_rd := x"0000";
end if;
if ( v_reg_rd(MEM_CNT) = '1' ) then
v_mem_cnt_rd := r.mem_cnt;
else
v_mem_cnt_rd := x"0000";
end if;
if ( v_reg_rd(CPU_NR) = '1' ) then
v_cpu_nr_rd := v_cpu_nr;
else
v_cpu_nr_rd := x"0000";
end if;
v_dbg_dout := v_cpu_id_lo_rd or
v_cpu_id_hi_rd or
v_cpu_ctl_rd or
v_cpu_stat_rd or
v_mem_ctl_rd or
v_mem_data_rd or
v_mem_addr_rd or
v_mem_cnt_rd or
d.brk0_dout or
d.brk1_dout or
d.brk2_dout or
d.brk3_dout or
v_cpu_nr_rd;
--! Tell UART/I2C interface that the data is ready to be read
if ( (r.mem_burst = '1') or (v_mem_burst_rd = '1') ) then
v.dbg_rd_rdy := v_dbg_reg_rd or r.dbg_mem_rd_dly;
else
v.dbg_rd_rdy := v_dbg_rd;
end if;
-- if ( v_brk_stat_set /= "000000" ) then
-- v_brk_halt := r.brk_ctl(C_BRK_EN);
-- end if;
--! drive register inputs
rin <= v;
--! drive module outputs
-- brk_halt <= v_brk_halt; --! Hardware breakpoint command
-- brk_pnd <= v_brk_pnd; --! Hardware break/watch-point pending
-- brk_dout <= v_brk_dout; --! Hardware break/watch-point register data input
dbg_cpu_reset <= v_dbg_cpu_reset; --! Reset CPU from debug interface
dbg_freeze <= v_dbg_freeze; --! Freeze peripherals
dbg_halt_cmd <= v_dbg_halt_cmd; --! Halt CPU command
-- dbg_i2c_sda_out <= v_dbg_i2c_sda_out; --! Debug interface: I2C SDA OUT
dbg_mem_addr <= v_dbg_mem_addr; --! Debug address for rd/wr access
dbg_mem_dout <= v_dbg_mem_dout; --! Debug unit data output
dbg_mem_en <= v_dbg_mem_en; --! Debug unit memory enable
dbg_mem_wr <= v_dbg_mem_wr; --! Debug unit memory write
dbg_reg_wr <= v_dbg_reg_wr; --! Debug unit CPU register write
-- dbg_uart_txd <= v_dbg_uart_txd; --! Debug interface: UART TXD
--! Hardware Breakpoint/Watchpoint Register read select
brk0_reg_rd <= v_reg_rd(BRK0_ADDR1) & v_reg_rd(BRK0_ADDR0) & v_reg_rd(BRK0_STAT) & v_reg_rd(BRK0_CTL);
brk1_reg_rd <= v_reg_rd(BRK1_ADDR1) & v_reg_rd(BRK1_ADDR0) & v_reg_rd(BRK1_STAT) & v_reg_rd(BRK1_CTL);
brk2_reg_rd <= v_reg_rd(BRK2_ADDR1) & v_reg_rd(BRK2_ADDR0) & v_reg_rd(BRK2_STAT) & v_reg_rd(BRK2_CTL);
brk3_reg_rd <= v_reg_rd(BRK3_ADDR1) & v_reg_rd(BRK3_ADDR0) & v_reg_rd(BRK3_STAT) & v_reg_rd(BRK3_CTL);
--! Hardware Breakpoint/Watchpoint Register write select
brk0_reg_wr <= v_reg_wr(BRK0_ADDR1) & v_reg_wr(BRK0_ADDR0) & v_reg_wr(BRK0_STAT) & v_reg_wr(BRK0_CTL);
brk1_reg_wr <= v_reg_wr(BRK1_ADDR1) & v_reg_wr(BRK1_ADDR0) & v_reg_wr(BRK1_STAT) & v_reg_wr(BRK1_CTL);
brk2_reg_wr <= v_reg_wr(BRK2_ADDR1) & v_reg_wr(BRK2_ADDR0) & v_reg_wr(BRK2_STAT) & v_reg_wr(BRK2_CTL);
brk3_reg_wr <= v_reg_wr(BRK3_ADDR1) & v_reg_wr(BRK3_ADDR0) & v_reg_wr(BRK3_STAT) & v_reg_wr(BRK3_CTL);
dbg_din <= v_dbg_din; --! Debug register data input
dbg_dout <= v_dbg_dout; --! Debug register data output
mem_burst_end <= v_mem_burst_end;
mem_burst_rd <= v_mem_burst_rd;
mem_burst_wr <= v_mem_burst_wr;
mem_bw <= v_mem_bw;
end process COMB;
REGS : process (dbg_clk,dbg_rst)
begin
if (dbg_rst = '1') then
if (DBG_RST_BRK_EN = true) then
r.cpu_ctl <= x"6";
else
r.cpu_ctl <= x"2";
end if;
r.mem_burst <= '0';
r.dbg_mem_rd_dly <= '0';
r.dbg_rd_rdy <= '0';
r.reg_dec <= (Others => '0');
--r.cpu_ctl : std_logic_vector(6 downto 3);
r.cpu_stat <= "00";
r.mem_ctl <= "000";
r.mem_start <= '0';
r.mem_data <= x"0000";
r.mem_addr <= x"0000";
r.mem_cnt <= x"0000";
r.inc_step <= "00";
r.halt_flag <= '0';
r.mem_state <= "00";
r.mem_startb <= '0';
elsif rising_edge(dbg_clk) then
r <= rin;
end if;
end process REGS;
-- DBG_HWBRK_0 : if DBG_HWBRK_0_EN generate
dbg_hwbr_0 : fmsp_dbg_hwbrk
generic map (
DBG_HWBRK_EN => DBG_HWBRK_0_EN -- Include hardware breakpoints unit
)
port map (
dbg_clk => dbg_clk, --! Debug unit clock
dbg_rst => dbg_rst, --! Debug unit reset
--! INPUTs
brk_reg_rd => brk0_reg_rd, --! Hardware break/watch-point register read select
brk_reg_wr => brk0_reg_wr, --! Hardware break/watch-point register write select
dbg_din => dbg_din, --! Debug register data input
decode_noirq => decode_noirq, --! Frontend decode instruction
eu_mab => eu_mab, --! Execution-Unit Memory address bus
eu_mb_en => eu_mb_en, --! Execution-Unit Memory bus enable
eu_mb_wr => eu_mb_wr, --! Execution-Unit Memory bus write transfer
pc => pc, --! Program counter
--! OUTPUTs
brk_halt => d.brk0_halt, --! Hardware breakpoint command
brk_pnd => d.brk0_pnd, --! Hardware break/watch-point pending
brk_dout => d.brk0_dout --! Hardware break/watch-point register data input
);
-- end generate DBG_HWBRK_0;
-- DBG_HWBRK_1 : if DBG_HWBRK_1_EN generate
dbg_hwbr_1 : fmsp_dbg_hwbrk
generic map (
DBG_HWBRK_EN => DBG_HWBRK_1_EN -- Include hardware breakpoints unit
)
port map (
dbg_clk => dbg_clk, --! Debug unit clock
dbg_rst => dbg_rst, --! Debug unit reset
--! INPUTs
brk_reg_rd => brk1_reg_rd, --! Hardware break/watch-point register read select
brk_reg_wr => brk1_reg_wr, --! Hardware break/watch-point register write select
dbg_din => dbg_din, --! Debug register data input
decode_noirq => decode_noirq, --! Frontend decode instruction
eu_mab => eu_mab, --! Execution-Unit Memory address bus
eu_mb_en => eu_mb_en, --! Execution-Unit Memory bus enable
eu_mb_wr => eu_mb_wr, --! Execution-Unit Memory bus write transfer
pc => pc, --! Program counter
--! OUTPUTs
brk_halt => d.brk1_halt, --! Hardware breakpoint command
brk_pnd => d.brk1_pnd, --! Hardware break/watch-point pending
brk_dout => d.brk1_dout --! Hardware break/watch-point register data input
);
-- end generate DBG_HWBRK_1;
-- DBG_HWBRK_2 : if DBG_HWBRK_2_EN generate
dbg_hwbr_2 : fmsp_dbg_hwbrk
generic map (
DBG_HWBRK_EN => DBG_HWBRK_2_EN -- Include hardware breakpoints unit
)
port map (
dbg_clk => dbg_clk, --! Debug unit clock
dbg_rst => dbg_rst, --! Debug unit reset
--! INPUTs
brk_reg_rd => brk2_reg_rd, --! Hardware break/watch-point register read select
brk_reg_wr => brk2_reg_wr, --! Hardware break/watch-point register write select
dbg_din => dbg_din, --! Debug register data input
decode_noirq => decode_noirq, --! Frontend decode instruction
eu_mab => eu_mab, --! Execution-Unit Memory address bus
eu_mb_en => eu_mb_en, --! Execution-Unit Memory bus enable
eu_mb_wr => eu_mb_wr, --! Execution-Unit Memory bus write transfer
pc => pc, --! Program counter
--! OUTPUTs
brk_halt => d.brk2_halt, --! Hardware breakpoint command
brk_pnd => d.brk2_pnd, --! Hardware break/watch-point pending
brk_dout => d.brk2_dout --! Hardware break/watch-point register data input
);
-- end generate DBG_HWBRK_2;
-- DBG_HWBRK_3 : if DBG_HWBRK_3_EN generate
dbg_hwbr_3 : fmsp_dbg_hwbrk
generic map (
DBG_HWBRK_EN => DBG_HWBRK_3_EN -- Include hardware breakpoints unit
)
port map (
dbg_clk => dbg_clk, --! Debug unit clock
dbg_rst => dbg_rst, --! Debug unit reset
--! INPUTs
brk_reg_rd => brk3_reg_rd, --! Hardware break/watch-point register read select
brk_reg_wr => brk3_reg_wr, --! Hardware break/watch-point register write select
dbg_din => dbg_din, --! Debug register data input
decode_noirq => decode_noirq, --! Frontend decode instruction
eu_mab => eu_mab, --! Execution-Unit Memory address bus
eu_mb_en => eu_mb_en, --! Execution-Unit Memory bus enable
eu_mb_wr => eu_mb_wr, --! Execution-Unit Memory bus write transfer
pc => pc, --! Program counter
--! OUTPUTs
brk_halt => d.brk3_halt, --! Hardware breakpoint command
brk_pnd => d.brk3_pnd, --! Hardware break/watch-point pending
brk_dout => d.brk3_dout --! Hardware break/watch-point register data input
);
-- end generate DBG_HWBRK_3;
ADD_DEBUG_I2C : if DBG_I2C generate
dbg_i2c_0 : fmsp_dbg_i2c
generic map(
DBG_I2C_BROADCAST_EN => DBG_I2C_BROADCAST_EN --! Enable the I2C broadcast address
)
port map(
dbg_clk => dbg_clk, --! Debug unit clock
dbg_rst => dbg_rst, --! Debug unit reset
--! INPUTs
dbg_dout => dbg_dout, --! Debug register data output
dbg_i2c_addr => dbg_i2c_addr, --! Debug interface: I2C Address
dbg_i2c_broadcast => dbg_i2c_broadcast, --! Debug interface: I2C Broadcast Address (for multicore systems)
mem_burst => r.mem_burst, --! Burst on going
mem_burst_end => mem_burst_end, --! End TX/RX burst
mem_burst_rd => mem_burst_rd, --! Start TX burst
mem_burst_wr => mem_burst_wr, --! Start RX burst
mem_bw => mem_bw, --! Burst byte width
--! OUTPUTs
dbg_addr => d.dbg_addr_i2c, --! Debug register address
dbg_din => d.dbg_din_i2c, --! Debug register data input
dbg_rd => d.dbg_rd_i2c, --! Debug register data read
dbg_wr => d.dbg_wr_i2c, --! Debug register data write
--! I2C Interface
dbg_i2c_scl => dbg_i2c_scl, --! Debug interface: I2C SCL
dbg_i2c_sda_in => dbg_i2c_sda_in, --! Debug interface: I2C SDA IN
dbg_i2c_sda_out => dbg_i2c_sda_out --! Debug interface: I2C SDA OUT
);
end generate ADD_DEBUG_I2C;
ADD_DEBUG_UART : if DBG_UART generate
dbg_uart_0 : fmsp_dbg_uart
generic map(
DBG_UART_AUTO_SYNC => DBG_UART_AUTO_SYNC, --! Debug UART interface auto data synchronization
DBG_UART_BAUD => DBG_UART_BAUD, --! Debug UART interface data rate
DBG_DCO_FREQ => DBG_DCO_FREQ, --! Debug DCO_CLK frequency
DBG_HWBRK_RANGE => DBG_HWBRK_RANGE, --! Enable/Disable the hardware breakpoint RANGE mode
SYNC_DBG_UART_RXD => SYNC_DBG_UART_RXD --! Synchronize RXD inputs
)
port map(
dbg_clk => dbg_clk, --! Debug unit clock
dbg_rst => dbg_rst, --! Debug unit reset
--! INPUTs
dbg_dout => dbg_dout, --! Debug register data output
dbg_rd_rdy => r.dbg_rd_rdy, --! Debug register data is ready for read
mem_burst => r.mem_burst, --! Burst on going
mem_burst_end => mem_burst_end, --! End TX/RX burst
mem_burst_rd => mem_burst_rd, --! Start TX burst
mem_burst_wr => mem_burst_wr, --! Start RX burst
mem_bw => mem_bw, --! Burst byte width
--! OUTPUTs
dbg_addr => d.dbg_addr_rs232, --! Debug register address
dbg_din => d.dbg_din_rs232, --! Debug register data input
dbg_rd => d.dbg_rd_rs232, --! Debug register data read
dbg_wr => d.dbg_wr_rs232, --! Debug register data write
--! RS232 Interface
dbg_uart_rxd => dbg_uart_rxd, --! Debug interface: UART RXD
dbg_uart_txd => dbg_uart_txd --! Debug interface: UART TXD
);
end generate ADD_DEBUG_UART;
end RTL; --! fmsp_dbg
| bsd-3-clause | 9a1736366ea6d36270b0984dedc594ed | 0.564655 | 2.657011 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-gr-xc3s-1500/leon3mp.vhd | 1 | 38,591 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.grusb.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
clk3 : in std_ulogic; -- 25 MHz ethernet clock
pllref : in std_ulogic;
errorn : out std_ulogic;
wdogn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
bexcn : in std_ulogic; -- DSU rx data
brdyn : in std_ulogic; -- DSU rx data
romsn : out std_logic_vector (1 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 rx data
rtsn1 : out std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART1 rx data
rtsn2 : out std_ulogic; -- UART1 rx data
pio : inout std_logic_vector(17 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
usb_clkout : in std_ulogic;
usb_d : inout std_logic_vector(15 downto 0);
usb_linestate : in std_logic_vector(1 downto 0);
usb_opmode : out std_logic_vector(1 downto 0);
usb_reset : out std_ulogic;
usb_rxactive : in std_ulogic;
usb_rxerror : in std_ulogic;
usb_rxvalid : in std_ulogic;
usb_suspend : out std_ulogic;
usb_termsel : out std_ulogic;
usb_txready : in std_ulogic;
usb_txvalid : out std_ulogic;
usb_validh : inout std_ulogic;
usb_xcvrsel : out std_ulogic;
usb_vbus : in std_ulogic
);
end;
architecture rtl of leon3mp is
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
CFG_GRUSBDC;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, rst, ndsuact, wdogl : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_GRUSBDC;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_clkl : std_ulogic;
signal spw_clkln : std_ulogic;
signal stati : ahbstat_in_type;
signal uclk : std_ulogic;
signal usbi : grusb_in_type;
signal usbo : grusb_out_type;
constant SPW_LOOP_BACK : integer := 0;
signal dac_clk, video_clk, clk50 : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk50 : signal is true;
attribute syn_preserve of clk50 : signal is true;
attribute keep of clk50 : signal is true;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
ethclk_pad : inpad generic map (tech => padtech) port map(clk3, ethclk);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
end generate;
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
rxd2_pad : inpad generic map (tech => padtech) port map (rxd2, u2i.rxd);
txd2_pad : outpad generic map (tech => padtech) port map (txd2, u2o.txd);
cts2_pad : inpad generic map (tech => padtech) port map (ctsn2, u2i.ctsn);
rts2_pad : outpad generic map (tech => padtech) port map (rtsn2, u2o.rtsn);
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate
apbo(9) <= apb_none; rtsn2 <= '0';
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
wden : if CFG_GPT_WDOGEN /= 0 generate
wdogl <= gpto.wdogn or not rstn;
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
end generate;
wddis : if CFG_GPT_WDOGEN = 0 generate
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc(0));
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, video_clk);
video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 20000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
vgaclk0 : entity work.vga_clkgen
port map (rstn, clk_sel, ethclk, clkm, clk50, video_clk);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
video_clk <= not clkm;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, video_clk);
end generate;
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
pio_pads : for i in 1 to 2 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
p1 : if (CFG_CAN = 0) generate
pio_pads : for i in 4 to 5 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
pio_pad0 : iopad generic map (tech => padtech)
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
pio_pad1 : iopad generic map (tech => padtech)
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
pio_pads : for i in 6 to 17 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 13, paddr => 13, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Multi-core CAN ---------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
can_tx_pad1 : iopad generic map (tech => padtech)
port map (pio(5), can_ltx(0), gnd(0), gpioi.din(5));
can_rx_pad1 : iopad generic map (tech => padtech)
port map (pio(4), gnd(0), vcc(0), can_lrx(0));
canpas : if CFG_CAN_NUM = 2 generate
can_tx_pad2 : iopad generic map (tech => padtech)
port map (pio(2), can_ltx(1), gnd(0), gpioi.din(2));
can_rx_pad2 : iopad generic map (tech => padtech)
port map (pio(1), gnd(0), vcc(0), can_lrx(1));
end generate;
end generate;
-- standby controlled by pio(3) and pio(0)
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
core0: if CFG_SPW_GRSPW = 1 generate
spw_clkl <= clkm;
spw_rxclkn <= not spw_rxtxclk;
end generate;
core1 : if CFG_SPW_GRSPW = 2 generate
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen_spw_rx : clkgen -- clock generator
generic map (clktech, 12, 2, 0,
1, 0, 0, 0, 25000)
port map (ethclk, ethclk, spw_clkl, spw_clkln, open, open, open, cgi2, cgo2, open, open);
spw_rxclkn <= spw_clkln;
end generate;
spw_rxtxclk <= spw_clkl;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j*2+1 downto j*2),
dov => spwi(i).dv(j*2+1 downto j*2),
dconnect => spwi(i).dconnect(j*2+1 downto j*2),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dv(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j),
ndo => spwi(i).nd(j*5+4 downto j*5),
dconnect => spwi(i).dconnect(j*2+1 downto j*2));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(1) <= '0'; -- For second port
spwi(i).d(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
end generate spw1_input;
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+i,
sysfreq => CPU_FREQ, usegen => 1,
pindex => 10+i, paddr => 10+i, pirq => 10+i,
nsync => 1, rmap => CFG_SPW_RMAP, rxunaligned => CFG_SPW_RXUNAL,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 2, dmachan => CFG_SPW_DMACHAN,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, ports => CFG_SPW_PORTS,
spwcore => CFG_SPW_GRSPW, netlist => CFG_SPW_NETLIST,
rxtx_sameclk => CFG_SPW_RTSAME, input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT)
port map(rstn, clkm, spw_rxclk(i*CFG_SPW_PORTS), spw_rxclk(i*CFG_SPW_PORTS+1),
spw_rxtxclk, spw_rxtxclk, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8) when CFG_SPW_GRSPW = 1
else conv_std_logic_vector((25*12/20)-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
swportloop1: for j in 0 to CFG_SPW_PORTS-1 generate
spwlb0 : if SPW_LOOP_BACK = 1 generate
dtmp(CFG_SPW_PORTS*i+j) <= spwo(i).d(j);
stmp(CFG_SPW_PORTS*i+j) <= spwo(i).s(j);
end generate;
nospwlb0 : if SPW_LOOP_BACK = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(CFG_SPW_PORTS*i+j), spw_rxdn(CFG_SPW_PORTS*i+j),
dtmp(CFG_SPW_PORTS*i+j));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(CFG_SPW_PORTS*i+j), spw_rxsn(CFG_SPW_PORTS*i+j),
stmp(CFG_SPW_PORTS*i+j));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(CFG_SPW_PORTS*i+j), spw_txdn(CFG_SPW_PORTS*i+j),
spwo(i).d(j), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(CFG_SPW_PORTS*i+j), spw_txsn(CFG_SPW_PORTS*i+j),
spwo(i).s(j), gnd(0));
end generate;
end generate;
end generate;
end generate;
-------------------------------------------------------------------------------
--- USB -----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Note that the GRUSBDC and GRUSB_DCL can not be instantiated at the same
-- time (board has only one USB transceiver), therefore they share AHB
-- master/slave indexes
-----------------------------------------------------------------------------
-- Shared pads
-----------------------------------------------------------------------------
usbpads: if (CFG_GRUSBDC + CFG_GRUSB_DCL) = 0 generate
usbo.oen <= '1'; usbo.reset <= '1';
end generate;
usb_clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (usb_clkout, uclk);
usb_d_pad: iopadv generic map(tech => padtech, width => 16, slew => 1)
port map (usb_d, usbo.dataout, usbo.oen, usbi.datain);
usb_txready_pad : inpad generic map (tech => padtech)
port map (usb_txready,usbi.txready);
usb_rxvalid_pad : inpad generic map (tech => padtech)
port map (usb_rxvalid,usbi.rxvalid);
usb_rxerror_pad : inpad generic map (tech => padtech)
port map (usb_rxerror,usbi.rxerror);
usb_rxactive_pad : inpad generic map (tech => padtech)
port map (usb_rxactive,usbi.rxactive);
usb_linestate_pad : inpadv generic map (tech => padtech, width => 2)
port map (usb_linestate,usbi.linestate);
usb_vbus_pad : inpad generic map (tech => padtech)
port map (usb_vbus, usbi.vbusvalid);
usb_reset_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_reset,usbo.reset);
usb_suspend_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_suspend,usbo.suspendm);
usb_termsel_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_termsel,usbo.termselect);
usb_xcvrsel_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_xcvrsel,usbo.xcvrselect(0));
usb_txvalid_pad : outpad generic map (tech => padtech, slew => 1)
port map (usb_txvalid,usbo.txvalid);
usb_opmode_pad : outpadv generic map (tech =>padtech ,width =>2, slew =>1)
port map (usb_opmode,usbo.opmode);
usb_validh_pad:iopad generic map(tech => padtech, slew => 1)
port map (usb_validh, usbo.txvalidh, usbo.oen, usbi.rxvalidh);
-----------------------------------------------------------------------------
-- USB 2.0 Device Controller
-----------------------------------------------------------------------------
usbdc0: if CFG_GRUSBDC = 1 generate
usbdc0: grusbdc
generic map(
hsindex => 5, hirq => 7, haddr => 16#004#, hmask => 16#FFC#,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
aiface => CFG_GRUSBDC_AIFACE, uiface => 0, dwidth => CFG_GRUSBDC_DW,
nepi => CFG_GRUSBDC_NEPI, nepo => CFG_GRUSBDC_NEPO,
i0 => CFG_GRUSBDC_I0, i1 => CFG_GRUSBDC_I1,
i2 => CFG_GRUSBDC_I2, i3 => CFG_GRUSBDC_I3,
i4 => CFG_GRUSBDC_I4, i5 => CFG_GRUSBDC_I5,
i6 => CFG_GRUSBDC_I6, i7 => CFG_GRUSBDC_I7,
i8 => CFG_GRUSBDC_I8, i9 => CFG_GRUSBDC_I9,
i10 => CFG_GRUSBDC_I10, i11 => CFG_GRUSBDC_I11,
i12 => CFG_GRUSBDC_I12, i13 => CFG_GRUSBDC_I13,
i14 => CFG_GRUSBDC_I14, i15 => CFG_GRUSBDC_I15,
o0 => CFG_GRUSBDC_O0, o1 => CFG_GRUSBDC_O1,
o2 => CFG_GRUSBDC_O2, o3 => CFG_GRUSBDC_O3,
o4 => CFG_GRUSBDC_O4, o5 => CFG_GRUSBDC_O5,
o6 => CFG_GRUSBDC_O6, o7 => CFG_GRUSBDC_O7,
o8 => CFG_GRUSBDC_O8, o9 => CFG_GRUSBDC_O9,
o10 => CFG_GRUSBDC_O10, o11 => CFG_GRUSBDC_O11,
o12 => CFG_GRUSBDC_O12, o13 => CFG_GRUSBDC_O13,
o14 => CFG_GRUSBDC_O14, o15 => CFG_GRUSBDC_O15,
memtech => memtech)
port map(
uclk => uclk,
usbi => usbi,
usbo => usbo,
hclk => clkm,
hrst => rstn,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN),
ahbsi => ahbsi,
ahbso => ahbso(5)
);
end generate usbdc0;
-----------------------------------------------------------------------------
-- USB DCL
-----------------------------------------------------------------------------
usb_dcl0: if CFG_GRUSB_DCL = 1 generate
usb_dcl0: grusb_dcl
generic map (
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN,
memtech => memtech, uiface => 0, dwidth => CFG_GRUSB_DCL_DW)
port map (
uclk, usbi, usbo, clkm, rstn, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+
CFG_SPW_NUM*CFG_SPW_EN));
end generate usb_dcl0;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-XC3S-1500 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 9be03c27d8a00f93e8b6d5e074d2eff0 | 0.556995 | 3.493347 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/dbg/fmsp_dbg_uart.vhd | 1 | 17,739 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_dbg_uart.vhd
--!
--! @brief fpgaMSP430 Debug UART communication interface (8N1, Half-duplex)
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use work.fmsp_misc_package.all;
entity fmsp_dbg_uart is
generic (
DBG_UART_AUTO_SYNC : boolean := true; --! Debug UART interface auto data synchronization
DBG_UART_BAUD : integer := 9600; --! Debug UART interface data rate
DBG_DCO_FREQ : integer := 20000000; --! Debug DCO_CLK frequency
DBG_HWBRK_RANGE : boolean := true; --! Enable/Disable the hardware breakpoint RANGE mode
SYNC_DBG_UART_RXD : boolean := true --! Synchronize RXD inputs
);
port (
dbg_clk : in std_logic; --! Debug unit clock
dbg_rst : in std_logic; --! Debug unit reset
--! INPUTs
dbg_dout : in std_logic_vector(15 downto 0); --! Debug register data output
dbg_rd_rdy : in std_logic; --! Debug register data is ready for read
dbg_uart_rxd : in std_logic; --! Debug interface: UART RXD
mem_burst : in std_logic; --! Burst on going
mem_burst_end : in std_logic; --! End TX/RX burst
mem_burst_rd : in std_logic; --! Start TX burst
mem_burst_wr : in std_logic; --! Start RX burst
mem_bw : in std_logic; --! Burst byte width
--! OUTPUTs
dbg_addr : out std_logic_vector(5 downto 0); --! Debug register address
dbg_din : out std_logic_vector(15 downto 0); --! Debug register data input
dbg_rd : out std_logic; --! Debug register data read
dbg_uart_txd : out std_logic; --! Debug interface: UART TXD
dbg_wr : out std_logic --! Debug register data write
);
end entity fmsp_dbg_uart;
architecture RTL of fmsp_dbg_uart is
--! Debug interface
constant DBG_UART_WR : integer := 18;
constant DBG_UART_BW : integer := 17;
--define 16 downto 11 16:11
constant DBG_UART_CNT_INT : integer := ((DBG_DCO_FREQ/DBG_UART_BAUD)-1);
--! Counter width for the debug interface UART
constant DBG_UART_XFER_CNT_W : integer := 16;
constant DBG_UART_CNT : std_logic_vector(DBG_UART_XFER_CNT_W+2 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(DBG_UART_CNT_INT,DBG_UART_XFER_CNT_W+2));
--! State machine definition
constant RX_SYNC : std_logic_vector(2 downto 0) := "000";
constant RX_CMD : std_logic_vector(2 downto 0) := "001";
constant RX_DATA1 : std_logic_vector(2 downto 0) := "010";
constant RX_DATA2 : std_logic_vector(2 downto 0) := "011";
constant TX_DATA1 : std_logic_vector(2 downto 0) := "100";
constant TX_DATA2 : std_logic_vector(2 downto 0) := "101";
type fmsp_dbg_uart_in_type is record
dbg_dout : std_logic_vector(15 downto 0); --! Debug register data output
dbg_rd_rdy : std_logic; --! Debug register data is ready for read
dbg_uart_rxd : std_logic; --! Debug interface: UART RXD
mem_burst : std_logic; --! Burst on going
mem_burst_end : std_logic; --! End TX/RX burst
mem_burst_rd : std_logic; --! Start TX burst
mem_burst_wr : std_logic; --! Start RX burst
mem_bw : std_logic; --! Burst byte width
uart_rxd_n : std_logic;
end record;
type reg_type is record
rxd_buf : std_logic_vector(1 downto 0); --! RXD input buffer
rxd_maj : std_logic; --! Majority decision
uart_state : std_logic_vector(2 downto 0); --! Receive state
xfer_buf : std_logic_vector(19 downto 0);
sync_busy : std_logic;
sync_cnt : std_logic_vector(DBG_UART_XFER_CNT_W+2 downto 0);
xfer_bit : std_logic_vector(3 downto 0);
xfer_cnt : std_logic_vector(DBG_UART_XFER_CNT_W-1 downto 0); --! Transfer counter
dbg_uart_txd : std_logic; --! Generate TXD output
dbg_addr : std_logic_vector(5 downto 0);
dbg_bw : std_logic;
end record;
signal d : fmsp_dbg_uart_in_type;
signal r : reg_type := ( rxd_buf => "00", --! RXD input buffer
rxd_maj => '0', --! Majority decision
uart_state => "000", --! Receive state
xfer_buf => (Others => '0'),
sync_busy => '0',
sync_cnt => (Others => '0'),
xfer_bit => "0000",
xfer_cnt => (Others => '0'), --! Transfer counter
dbg_uart_txd => '0', --! Generate TXD output
dbg_addr => "000000",
dbg_bw => '0'
);
signal rin : reg_type;
begin
d.dbg_dout <= dbg_dout;
d.dbg_rd_rdy <= dbg_rd_rdy;
d.dbg_uart_rxd <= dbg_uart_rxd;
d.mem_burst <= mem_burst;
d.mem_burst_end <= mem_burst_end;
d.mem_burst_rd <= mem_burst_rd;
d.mem_burst_wr <= mem_burst_wr;
d.mem_bw <= mem_bw;
COMB : process (d, r)
variable v : reg_type;
--=============================================================================
--! 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
--=============================================================================
variable v_uart_rxd : std_logic;
--! Majority decision
variable v_rxd_maj_nxt : std_logic;
variable v_rxd_s : std_logic;
variable v_rxd_fe : std_logic;
variable v_rxd_re : std_logic;
variable v_rxd_edge : std_logic;
--=============================================================================
--! 2) UART STATE MACHINE
--=============================================================================
--! Receive state
variable v_uart_state_nxt : std_logic_vector(19 downto 0);
variable v_sync_done : std_logic;
variable v_xfer_done : std_logic;
variable v_xfer_buf_nxt : std_logic_vector(19 downto 0);
--! Utility signals
variable v_cmd_valid : std_logic;
variable v_rx_active : std_logic;
variable v_tx_active : std_logic;
--=============================================================================
--! 3) UART SYNCHRONIZATION
--=============================================================================
--! After DBG_RST, the host needs to fist send a synchronization character (0x80)
--! If this feature doesn't work properly, it is possible to disable it by
--! commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
variable v_bit_cnt_max : std_logic_vector(DBG_UART_XFER_CNT_W-1 downto 0);
--=============================================================================
--! 4) UART RECEIVE / TRANSMIT
--=============================================================================
--! Transfer counter
variable v_txd_start : std_logic;
variable v_rxd_start : std_logic;
variable v_xfer_bit_inc : std_logic;
--=============================================================================
--! 5) INTERFACE TO DEBUG REGISTERS
--=============================================================================
variable v_dbg_din_bw : std_logic;
variable v_dbg_din : std_logic_vector(15 downto 0);
variable v_dbg_wr : std_logic;
variable v_dbg_rd : std_logic;
begin
--! default assignment
v := r;
--! overriding assignments
--=============================================================================
--! 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
--=============================================================================
--! Synchronize RXD input
if (SYNC_DBG_UART_RXD = true) then
v_uart_rxd := not(d.uart_rxd_n);
else
v_uart_rxd := d.dbg_uart_rxd;
end if;
--! RXD input buffer
v.rxd_buf := r.rxd_buf(0) & v_uart_rxd;
--! Majority decision
v_rxd_maj_nxt := (v_uart_rxd and r.rxd_buf(0))
or (v_uart_rxd and r.rxd_buf(1))
or (r.rxd_buf(0) and r.rxd_buf(1));
v.rxd_maj := v_rxd_maj_nxt;
v_rxd_s := r.rxd_maj;
v_rxd_fe := r.rxd_maj and not( v_rxd_maj_nxt);
v_rxd_re := not( r.rxd_maj) and v_rxd_maj_nxt;
v_rxd_edge := r.rxd_maj xor v_rxd_maj_nxt;
--=============================================================================
--! 2) UART STATE MACHINE
--=============================================================================
case (r.uart_state) is
when RX_SYNC =>
v_uart_state_nxt := RX_CMD;
when RX_CMD =>
if (d.mem_burst_wr = '1') then
if (d.mem_bw = '1') then
v_uart_state_nxt := RX_DATA2;
else
v_uart_state_nxt := RX_DATA1;
end if;
elsif (d.mem_burst_rd = '1') then
if (d.mem_bw = '1') then
v_uart_state_nxt := RX_DATA2;
else
v_uart_state_nxt := RX_DATA1;
end if;
elsif (v_xfer_buf_nxt(DBG_UART_WR) = '1') then
if (v_xfer_buf_nxt(DBG_UART_BW) = '1') then
v_uart_state_nxt := RX_DATA2;
else
v_uart_state_nxt := RX_DATA1;
end if;
else
if (v_xfer_buf_nxt(DBG_UART_BW) = '1') then
v_uart_state_nxt := TX_DATA2;
else
v_uart_state_nxt := TX_DATA1;
end if;
end if;
when RX_DATA1 =>
v_uart_state_nxt := RX_DATA2;
when RX_DATA2 =>
if ( (d.mem_burst and not(d.mem_burst_end)) = '1' ) then
if (d.mem_bw = '1') then
v_uart_state_nxt := RX_DATA2;
else
v_uart_state_nxt := RX_DATA1;
end if;
else
v_uart_state_nxt := RX_CMD;
end if;
when TX_DATA1 =>
v_uart_state_nxt := TX_DATA2;
when TX_DATA2 =>
if ( (d.mem_burst and not(d.mem_burst_end)) = '1' ) then
if (d.mem_bw = '1') then
v_uart_state_nxt := TX_DATA2;
else
v_uart_state_nxt := TX_DATA1;
end if;
else
v_uart_state_nxt := RX_CMD;
end if;
when Others =>
v_uart_state_nxt := RX_CMD;
end case;
--! State machine
if ( (v_xfer_done or v_sync_done or d.mem_burst_wr or d.mem_burst_rd) = '1' ) then
v.uart_state := v_uart_state_nxt;
end if;
--! Utility signals
if (r.uart_state = RX_CMD) then
v_cmd_valid := v_xfer_done;
else
v_cmd_valid := '0';
end if;
if ( (r.uart_state = RX_DATA1)
or (r.uart_state = RX_DATA2)
or (r.uart_state = RX_CMD) ) then
v_rx_active := '1';
else
v_rx_active := '0';
end if;
if ( (r.uart_state = TX_DATA1)
or (r.uart_state = TX_DATA2) ) then
v_tx_active := '1';
else
v_tx_active := '0';
end if;
--=============================================================================
--! 3) UART SYNCHRONIZATION
--=============================================================================
--! After DBG_RST, the host needs to fist send a synchronization character (0x80)
--! If this feature doesn't work properly, it is possible to disable it by
--! commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
if ( (r.uart_state = RX_SYNC)
and (v_rxd_fe = '1') ) then
v.sync_busy := '1';
elsif ( (r.uart_state = RX_SYNC)
and (v_rxd_re = '1') ) then
v.sync_busy := '0';
end if;
v_sync_done := '0';
if ( (r.uart_state = RX_SYNC)
and (v_rxd_re = '1')
and (r.sync_busy = '1') ) then
v_sync_done := '1';
end if;
if (DBG_UART_AUTO_SYNC = true) then
if ( (r.sync_busy or (not(r.sync_busy) and r.sync_cnt(2))) = '1') then
v.sync_cnt := STD_LOGIC_VECTOR( UNSIGNED(r.sync_cnt) + TO_UNSIGNED(1,DBG_UART_XFER_CNT_W+3) );
end if;
v_bit_cnt_max := r.sync_cnt(DBG_UART_XFER_CNT_W+2 downto 3);
else
v_bit_cnt_max := DBG_UART_CNT;
end if;
--=============================================================================
--! 4) UART RECEIVE / TRANSMIT
--=============================================================================
--! Transfer counter
if ( (r.uart_state = TX_DATA1)
and (v_xfer_done = '1') ) then
v_txd_start := '1';
elsif (dbg_rd_rdy = '1') then
v_txd_start := '1';
else
v_txd_start := '0';
end if;
if ( (r.xfer_bit = "0000")
and (r.uart_state /= RX_SYNC)
and (v_rxd_fe = '1') ) then
v_rxd_start := '1';
else
v_rxd_start := '0';
end if;
if ( (r.xfer_bit /= "0000")
and (r.xfer_cnt = STD_LOGIC_VECTOR(TO_UNSIGNED(0,DBG_UART_XFER_CNT_W))) ) then
v_xfer_bit_inc := '1';
else
v_xfer_bit_inc := '0';
end if;
v_xfer_done := '0';
if (v_rx_active = '1') then
if (r.xfer_bit = "1010") then
v_xfer_done := '1';
end if;
else
if (r.xfer_bit = "1011") then
v_xfer_done := '1';
end if;
end if;
if ( (v_txd_start or v_rxd_start) = '1') then
v.xfer_bit := "0001";
elsif (v_xfer_done = '1') then
v.xfer_bit := "0000";
elsif (v_xfer_bit_inc = '1') then
v.xfer_bit := STD_LOGIC_VECTOR( UNSIGNED(r.xfer_bit) + TO_UNSIGNED(1,4) );
end if;
if ( (v_rx_active and v_rxd_edge) = '1' ) then
v.xfer_cnt := '0' & v_bit_cnt_max(DBG_UART_XFER_CNT_W-1 downto 1);
elsif ( (v_txd_start or v_xfer_bit_inc) = '1' ) then
v.xfer_cnt := v_bit_cnt_max;
elsif ( r.xfer_cnt /= STD_LOGIC_VECTOR( TO_UNSIGNED(0,DBG_UART_XFER_CNT_W) ) ) then
v.xfer_cnt := STD_LOGIC_VECTOR( UNSIGNED(r.xfer_cnt) - TO_UNSIGNED(1,DBG_UART_XFER_CNT_W) );
end if;
--! Receive/Transmit buffer
v_xfer_buf_nxt := v_rxd_s & r.xfer_buf(19 downto 1);
if (dbg_rd_rdy = '1') then
v.xfer_buf := '1' & d.dbg_dout(15 downto 8) & "01" & dbg_dout(7 downto 0) & '0';
elsif (v_xfer_bit_inc = '1') then
v.xfer_buf := v_xfer_buf_nxt;
end if;
--! Generate TXD output
if ( (v_xfer_bit_inc and v_tx_active) = '1' ) then
v.dbg_uart_txd := r.xfer_buf(0);
end if;
--=============================================================================
--! 5) INTERFACE TO DEBUG REGISTERS
--=============================================================================
if (v_cmd_valid = '1') then
v.dbg_addr := v_xfer_buf_nxt(16 downto 11);
end if;
if (v_cmd_valid = '1') then
v.dbg_bw := v_xfer_buf_nxt(DBG_UART_BW);
end if;
if (d.mem_burst = '1') then
v_dbg_din_bw := d.mem_bw;
else
v_dbg_din_bw := r.dbg_bw;
end if;
if (v_dbg_din_bw = '1') then
v_dbg_din := x"00" & v_xfer_buf_nxt(18 downto 11);
else
v_dbg_din := v_xfer_buf_nxt(18 downto 11) & v_xfer_buf_nxt(9 downto 2);
end if;
v_dbg_wr := '0';
if ( (r.uart_state = RX_DATA2)
and (v_xfer_done = '1') ) then
v_dbg_wr := '1';
end if;
if (d.mem_burst = '1') then
if ( (r.uart_state = TX_DATA2)
and (v_xfer_done = '1') ) then
v_dbg_rd := '1';
else
v_dbg_rd := '0';
end if;
else
v_dbg_rd := ( v_cmd_valid and not(v_xfer_buf_nxt(DBG_UART_WR)) ) or d.mem_burst_rd;
end if;
--! drive register inputs
rin <= v;
--! drive module outputs
dbg_addr <= r.dbg_addr; --! Debug register address
dbg_din <= v_dbg_din; --! Debug register data input
dbg_rd <= v_dbg_rd; --! Debug register data read
dbg_wr <= v_dbg_wr; --! Debug register data write
dbg_uart_txd <= r.dbg_uart_txd; --! Debug interface: UART TXD
end process COMB;
REGS : process (dbg_clk,dbg_rst)
begin
if (dbg_rst = '1') then
r <= ( rxd_buf => "11", --! RXD input buffer
rxd_maj => '1', --! Majority decision
uart_state => "000", --! Receive state
xfer_buf => (Others => '0'),
sync_busy => '0',
sync_cnt => (0 => '0', 1 => '0', 2 => '0', Others => '1'),
xfer_bit => "0000",
xfer_cnt => (Others => '0'), --! Transfer counter
dbg_uart_txd => '1', --! Generate TXD output
dbg_addr => "000000",
dbg_bw => '0'
);
elsif rising_edge(dbg_clk) then
r <= rin;
end if;
end process REGS;
sync_cell_uart_rxd : fmsp_sync_cell
port map(
clk => dbg_clk,
rst => dbg_rst,
data_in => not(dbg_uart_rxd),
data_out => d.uart_rxd_n
);
end RTL;
| bsd-3-clause | f0c49d36982bc99dfcb856b9af379c32 | 0.527256 | 2.876906 | false | false | false | false |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/dac_interface.vhd | 3 | 4,707 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dac_interface is
generic(
width : integer := 32
);
port(
clk : in std_logic;
rst : in std_logic;
input_0 : in std_logic_vector(width - 1 downto 0);
input_1 : in std_logic_vector(width - 1 downto 0);
input_2 : in std_logic_vector(width - 1 downto 0);
input_3 : in std_logic_vector(width - 1 downto 0);
input_4 : in std_logic_vector(width - 1 downto 0);
input_5 : in std_logic_vector(width - 1 downto 0);
input_6 : in std_logic_vector(width - 1 downto 0);
input_7 : in std_logic_vector(width - 1 downto 0);
dithering : in std_logic;
output : out std_logic
);
end entity dac_interface;
architecture rtl of dac_interface is
function to_std(x : boolean) return std_logic is
begin
if x then
return '1';
else
return '0';
end if;
end function;
component serdes is
port(
clk : in std_logic;
rst : in std_logic;
input_0 : in std_logic;
input_1 : in std_logic;
input_2 : in std_logic;
input_3 : in std_logic;
input_4 : in std_logic;
input_5 : in std_logic;
input_6 : in std_logic;
input_7 : in std_logic;
output : out std_logic
);
end component serdes;
component lfsr is
generic(
init : in std_logic_vector(63 downto 0) := X"0000000000000001"
);
port(
clk : in std_logic;
rand : out std_logic_vector(31 downto 0)
);
end component lfsr;
signal rand_0 : std_logic_vector(31 downto 0) := X"A000b001";
signal rand_1 : std_logic_vector(31 downto 0) := X"B0000002";
signal rand_2 : std_logic_vector(31 downto 0) := X"C000e003";
signal rand_3 : std_logic_vector(31 downto 0) := X"D0000004";
signal rand_4 : std_logic_vector(31 downto 0) := X"E0004005";
signal rand_5 : std_logic_vector(31 downto 0) := X"F0000006";
signal rand_6 : std_logic_vector(31 downto 0) := X"00f00007";
signal rand_7 : std_logic_vector(31 downto 0) := X"0000e008";
signal dithered_0 : std_logic;
signal dithered_1 : std_logic;
signal dithered_2 : std_logic;
signal dithered_3 : std_logic;
signal dithered_4 : std_logic;
signal dithered_5 : std_logic;
signal dithered_6 : std_logic;
signal dithered_7 : std_logic;
signal dac_0 : std_logic;
signal dac_1 : std_logic;
signal dac_2 : std_logic;
signal dac_3 : std_logic;
signal dac_4 : std_logic;
signal dac_5 : std_logic;
signal dac_6 : std_logic;
signal dac_7 : std_logic;
begin
lfsr_0 : lfsr generic map(init => X"0000004000800001") port map(clk, rand_0);
lfsr_1 : lfsr generic map(init => X"000e000600000004") port map(clk, rand_1);
lfsr_2 : lfsr generic map(init => X"0000005000400001") port map(clk, rand_2);
lfsr_3 : lfsr generic map(init => X"0000500000000001") port map(clk, rand_3);
lfsr_4 : lfsr generic map(init => X"000000000c000005") port map(clk, rand_4);
lfsr_5 : lfsr generic map(init => X"00000a00d0000001") port map(clk, rand_5);
lfsr_6 : lfsr generic map(init => X"000000000f000007") port map(clk, rand_6);
lfsr_7 : lfsr generic map(init => X"00000a0000000001") port map(clk, rand_7);
process
begin
wait until rising_edge(clk);
dithered_0 <= to_std(signed(input_0) > signed(rand_0(width-1 downto 0)));
dithered_1 <= to_std(signed(input_1) > signed(rand_1(width-1 downto 0)));
dithered_2 <= to_std(signed(input_2) > signed(rand_2(width-1 downto 0)));
dithered_3 <= to_std(signed(input_3) > signed(rand_3(width-1 downto 0)));
dithered_4 <= to_std(signed(input_4) > signed(rand_4(width-1 downto 0)));
dithered_5 <= to_std(signed(input_5) > signed(rand_5(width-1 downto 0)));
dithered_6 <= to_std(signed(input_6) > signed(rand_6(width-1 downto 0)));
dithered_7 <= to_std(signed(input_7) > signed(rand_7(width-1 downto 0)));
if dithering = '1' then
dac_0 <= dithered_0;
dac_1 <= dithered_1;
dac_2 <= dithered_2;
dac_3 <= dithered_3;
dac_4 <= dithered_4;
dac_5 <= dithered_5;
dac_6 <= dithered_6;
dac_7 <= dithered_7;
else
dac_0 <= input_0(width -1);
dac_1 <= input_1(width -1);
dac_2 <= input_2(width -1);
dac_3 <= input_3(width -1);
dac_4 <= input_4(width -1);
dac_5 <= input_5(width -1);
dac_6 <= input_6(width -1);
dac_7 <= input_7(width -1);
end if;
end process;
serdes_inst_1 : serdes port map(
clk => clk,
rst => rst,
input_0 => dac_0,
input_1 => dac_1,
input_2 => dac_2,
input_3 => dac_3,
input_4 => dac_4,
input_5 => dac_5,
input_6 => dac_6,
input_7 => dac_7,
output => output
);
end rtl;
| mit | 6a3c85fae350dcb02ff4c914498550e5 | 0.609305 | 2.938202 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ac701/leon3mp.vhd | 1 | 35,718 | -----------------------------------------------------------------------------
-- LEON3 Xilinx KC705 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
-- spi_sel_n : inout std_ulogic;
-- spi_clk : out std_ulogic;
-- spi_miso : in std_ulogic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(3 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_txclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
sfp_clock_mux : out std_logic_vector(1 downto 0)
);
end;
architecture rtl of leon3mp is
component ahb2mig_series7
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
component ddr_dummy
port (
ddr_dq : inout std_logic_vector(63 downto 0);
ddr_dqs : inout std_logic_vector(7 downto 0);
ddr_dqs_n : inout std_logic_vector(7 downto 0);
ddr_addr : out std_logic_vector(13 downto 0);
ddr_ba : out std_logic_vector(2 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_cke : out std_logic_vector(0 downto 0);
ddr_cs_n : out std_logic_vector(0 downto 0);
ddr_dm : out std_logic_vector(7 downto 0);
ddr_odt : out std_logic_vector(0 downto 0)
);
end component ;
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IDELAYCTRL
port (
RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic
);
end component;
component IODELAYE1
generic (
DELAY_SRC : string := "I";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CLKIN : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
--constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbm : integer := 16;
constant maxahbs : integer := 16;
constant maxapbs : integer := CFG_IRQ3_ENABLE+CFG_GPT_ENABLE+CFG_GRGPIO_ENABLE+CFG_AHBSTAT+CFG_AHBSTAT;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal ui_clk : std_ulogic;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii : eth_in_type;
signal gmiio : eth_out_type;
signal rgmiii,rgmiii_buf : eth_in_type;
signal rgmiio : eth_out_type;
signal sgmiii : eth_sgmii_in_type;
signal sgmiio : eth_sgmii_out_type;
signal sgmiirst : std_logic;
signal ethernet_phy_int : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gtx_clk,gtx_clk_nobuf,gtx_clk90 : std_ulogic;
signal rstgtxn : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ : integer := 200000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal dsurx_int : std_logic;
signal dsutx_int : std_logic;
signal dsuctsn_int : std_logic;
signal dsurtsn_int : std_logic;
signal dsu_sel : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal io_ref : std_logic;
signal clkref : std_logic;
signal migrstn : std_logic;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_gen0 : if (CFG_MIG_SERIES7 = 0) generate
clk_pad_ds : clkpad_ds generic map (tech => padtech, level => sstl, voltage => x15v) port map (clk200p, clk200n, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, open, open);
end generate;
reset_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1, syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_SERIES7 = 1 else cgo.clklock;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, '1', migrstn, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(1), dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui_break_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (button(0), dsui.break);
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.extclk <= '0';
end generate;
nouah : if CFG_AHB_UART = 0 generate
apbo(7) <= apb_none;
duo.txd <= '0';
duo.rtsn <= '0';
dui.extclk <= '0';
end generate;
sw4_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(3), '0', '1', dsu_sel);
dsutx_int <= duo.txd when dsu_sel = '1' else u1o.txd;
dui.rxd <= dsurx_int when dsu_sel = '1' else '1';
u1i.rxd <= dsurx_int when dsu_sel = '0' else '1';
dsurtsn_int <= duo.rtsn when dsu_sel = '1' else u1o.rtsn;
dui.ctsn <= dsuctsn_int when dsu_sel = '1' else '1';
u1i.ctsn <= dsuctsn_int when dsu_sel = '0' else '1';
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dsurx_int);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, dsutx_int);
dsuctsn_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsuctsn, dsuctsn_int);
dsurtsn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurtsn, dsurtsn_int);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+1)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+1),
open, open, open, open, open, open, open, gnd);
end generate;
nojtag : if CFG_AHB_JTAG = 0 generate apbo(CFG_NCPU+1) <= apb_none; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
-- mctrl_gen : if CFG_MCTRL_LEON2 /= 0 generate
-- mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
-- paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
-- ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
-- invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
-- pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
-- port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
-- spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
-- spimctrl0 : spimctrl -- SPI Memory Controller
-- generic map (hindex => 0, hirq => 0, faddr => 16#000#, fmask => 16#ff8#,
-- ioaddr => 16#002#, iomask => 16#fff#,
-- spliten => CFG_SPLIT, oepol => 0,
-- sdcard => CFG_SPIMCTRL_SDCARD,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
-- scaler => CFG_SPIMCTRL_SCALER,
-- altscaler => CFG_SPIMCTRL_ASCALER,
-- pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
-- port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo);
--
--
-- miso_pad : inpad generic map (tech => padtech)
-- port map (spi_miso, spmi.miso);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spmo.sck);
-- slvsel0_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, spmo.csn);
-- end generate;
--
-- nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
-- (CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
-- (CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
-- miso_pad : inpad generic map (tech => padtech)
-- port map (spi_miso, spmi.miso);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, '0');
-- slvsel0_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, '1');
-- end generate;
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_SERIES7 = 1) generate
ddrc : ahb2mig_series7 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#C00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => rstraw,
clk_amba => clkm,
sys_clk_p => clk200p,
sys_clk_n => clk200n,
clk_ref_i => clkref,
ui_clk => clkm,
ui_clk_sync_rst => open
);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
end generate;
no_mig_gen : if (CFG_MIG_SERIES7 = 0) generate
ahbram0 : ahbram
generic map (hindex => 4, haddr => 16#400#, tech => CFG_MEMTECH, kbytes => 32)
port map ( rstn, clkm, ahbsi, ahbso(4));
ddrdummy0 : ddr_dummy
port map (
ddr_dq => ddr3_dq,
ddr_dqs => ddr3_dqs_p,
ddr_dqs_n => ddr3_dqs_n,
ddr_addr => ddr3_addr,
ddr_ba => ddr3_ba,
ddr_ras_n => ddr3_ras_n,
ddr_cas_n => ddr3_cas_n,
ddr_we_n => ddr3_we_n,
ddr_reset_n => ddr3_reset_n,
ddr_ck_p => ddr3_ck_p,
ddr_ck_n => ddr3_ck_n,
ddr_cke => ddr3_cke,
ddr_cs_n => ddr3_cs_n,
ddr_dm => ddr3_dm,
ddr_odt => ddr3_odt
);
calib_done <= '1';
end generate;
led2_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(2), calib_done);
led3_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(3), lock);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 16#C00#, pmask => 16#C00#, pirq => 14, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G, ramdebug => 2)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
-----------------------------------------------------------------------------
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
-- All IDELAYs in Fixed Tap Delay mode and the IDELAYCTRL primitives have
-- to be LOC'ed in the UCF file.
-----------------------------------------------------------------------------
dlyctrl0 : IDELAYCTRL port map (
RDY => OPEN,
REFCLK => io_ref,
RST => idelayctrl_reset
);
delay_rgmii_rx_ctl0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
ODATAIN => '0',
DATAOUT => rgmiii.rx_dv,
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
ODATAIN => '0',
DATAOUT => rgmiii.rxd(i),
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
end generate;
-- Generate a synchron delayed reset for Xilinx IO delay
rst1 : rstgen
generic map (acthigh => 1)
port map (rst, io_ref, lock, rstgtxn, OPEN);
process (io_ref,rstgtxn)
begin
if (rstgtxn = '0') then
idelay_reset_cnt <= (others => '0');
idelayctrl_reset <= '1';
elsif rising_edge(io_ref) then
if (idelay_reset_cnt > "1110") then
idelay_reset_cnt <= (others => '1');
idelayctrl_reset <= '0';
else
idelay_reset_cnt <= idelay_reset_cnt + 1;
idelayctrl_reset <= '1';
end if;
end if;
end process;
-- RGMII Interface
rgmii0 : rgmii generic map (pindex => 11, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 1,
pirq => 11, use90degtxclk => 1)
port map (rstn, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11));
egtxc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txclk, rgmiio.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v, arch => 4)
port map (phy_rxclk, rgmiii.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 4)
port map (phy_rxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_rxctl_rxdv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1, width => 4)
port map (phy_txd, rgmiio.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txctl_txen, rgmiio.tx_en);
emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdc, rgmiio.mdc);
rgmiii.mdint <= '0'; -- No interrupt on Marvell 88E1116R PHY
erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_reset, rstraw);
sfp_clock_mux_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 2)
port map (sfp_clock_mux, "00");
-- GTX Clock
rgmiii.gtx_clk <= gtx_clk;
-- 125MHz input clock
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => gtrefclk_p,
IB => gtrefclk_n,
CEB => '0',
O => gtx_clk_nobuf,
ODIV2 => open
);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen_gtrefclk : clkgen
generic map (clktech, 8, 8, 0, 0, 0, 0, 0, 125000)
port map (gtx_clk_nobuf, gtx_clk_nobuf, gtx_clk, gtx_clk90, io_ref, open, open, cgi2, cgo2, open, open, open);
end generate;
noeth0 : if CFG_GRETH = 0 generate
-- TODO:
end generate;
----------------------------------------------------------------------
--- I2C Controller --------------------------------------------------
----------------------------------------------------------------------
--i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 11, filter => 9)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
--end generate i2cm;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16, debug => 2)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 2 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 3 to 5 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (button(i-2), gpioi.din(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 3, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
-- pragma translate_on
test1_gen : if (testahb = false) generate
ahbram0 : ahbram generic map (hindex => 3, haddr => 16#200#,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(3));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx AC701 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | b696892c54e4dbeb02844a3f59168f1d | 0.533904 | 3.520402 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_sim_netlist.vhdl | 1 | 533,674 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:33 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_sim_netlist.vhdl
-- Design : zynq_design_1_auto_pc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm : entity is "axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm : entity is "axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel : entity is "axi_protocol_converter_v2_1_13_b2s_b_channel";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel : entity is "axi_protocol_converter_v2_1_13_b2s_r_channel";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel : entity is "axi_protocol_converter_v2_1_13_b2s_ar_channel";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel : entity is "axi_protocol_converter_v2_1_13_b2s_aw_channel";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s : entity is "axi_protocol_converter_v2_1_13_b2s";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter";
attribute P_AXI3 : integer;
attribute P_AXI3 of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_auto_pc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_auto_pc_0 : entity is "zynq_design_1_auto_pc_0,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_auto_pc_0 : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end zynq_design_1_auto_pc_0;
architecture STRUCTURE of zynq_design_1_auto_pc_0 is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 338761467da0e73ea9db203594cc5eb8 | 0.531581 | 2.538331 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-kc705/testbench.vhd | 1 | 18,864 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := true;
USE_MIG_INTERFACE_MODEL : boolean := false
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- ram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal adv : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1 , rxd1 , dsurx : std_logic;
signal txd2 , rxd2 , dsutx : std_logic;
signal ctsn1 , rtsn1 , dsuctsn : std_ulogic;
signal ctsn2 , rtsn2 , dsurtsn : std_ulogic;
signal phy_gtxclk : std_logic := '0';
signal phy_txer : std_ulogic;
signal phy_txd : std_logic_vector(7 downto 0);
signal phy_txctl_txen : std_ulogic;
signal phy_txclk : std_ulogic;
signal phy_rxer : std_ulogic;
signal phy_rxd : std_logic_vector(7 downto 0);
signal phy_rxctl_rxdv : std_ulogic;
signal phy_rxclk : std_ulogic;
signal phy_reset : std_ulogic;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_col : std_ulogic;
signal phy_int : std_ulogic;
signal phy_rxdl : std_logic_vector(7 downto 0);
signal phy_txdl : std_logic_vector(7 downto 0);
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal clkethp : std_ulogic := '0';
signal clkethn : std_ulogic := '1';
signal txp1 : std_logic;
signal txn : std_logic;
signal rxp : std_logic := '1';
signal rxn : std_logic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(63 downto 0);
signal ddr3_dqs_p : std_logic_vector(7 downto 0);
signal ddr3_dqs_n : std_logic_vector(7 downto 0);
signal ddr3_addr : std_logic_vector(13 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_cs_n : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(7 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(6 downto 0); -- I/O port
constant lresp : boolean := false;
signal tdqs_n : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_rx_clk : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_gtxclk : out std_logic;
--phy_txer : out std_ulogic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
--phy_txclk : in std_ulogic;
--phy_rxer : in std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
phy_int : in std_ulogic
);
end component;
begin
-- clock and reset
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
clkethp <= not clkethp after 4 ns;
clkethn <= not clkethp after 4 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch(2 downto 0) <= "000";
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
testahb => testahb,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL
)
port map (
reset => rst,
clk200p => clk200p,
clk200n => clk200n,
address => address,
data => data,
oen => oen,
writen => writen,
romsn => romsn,
adv => adv,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
dsurx => dsurx,
dsutx => dsutx,
dsuctsn => dsuctsn,
dsurtsn => dsurtsn,
button => button,
switch => switch,
led => led,
iic_scl => iic_scl,
iic_sda => iic_sda,
gtrefclk_p => clkethp,
gtrefclk_n => clkethn,
phy_gtxclk => phy_gtxclk,
--phy_txer => phy_txer,
phy_txd => phy_txd(3 downto 0),
phy_txctl_txen => phy_txctl_txen,
--phy_txclk => phy_txclk,
--phy_rxer => phy_rxer,
phy_rxd => phy_rxd(3 downto 0),
phy_rxctl_rxdv => phy_rxctl_rxdv,
phy_rxclk => phy_rxclk'delayed(1 ns),
phy_reset => phy_reset,
phy_mdio => phy_mdio,
phy_mdc => phy_mdc,
phy_int => phy_int
);
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 22, fname => promfile)
port map (address(21 downto 0), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
-- Memory Models instantiations
gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddr3mem : if (CFG_MIG_SERIES7 = 1) generate
u1 : ddr3ram
generic map (
width => 64,
abits => 14,
colbits => 10,
rowbits => 10,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 8)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
end generate ddr3mem;
end generate gen_mem_model;
mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
end generate mig_mem_model;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
phy_int <= '0';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd,
phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd,
phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk);
end generate;
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
wait on led(3); -- DDR3 Memory Init ready
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ; -- this should be a failure
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
switch(3) <= '0';
wait for 2500 ns;
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
dsurst <= '1';
switch(3) <= '1';
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- Wait for DDR3 Memory Init ready
end if;
report "Start DSU transfer";
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- Reads from memory and DSU register to mimic GRMON during simulation
l1 : loop
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU read memory " & tost(w32);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU Break and Single Step register" & tost(w32);
end loop l1;
wait;
-- ** This is only kept for reference --
-- do test read and writes to DDR3 to check status
-- Write
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
report "* Read " & tost(w32);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
-- Register 0x90000000 (DSU Control Register)
-- Data 0x0000202e (b0010 0000 0010 1110)
-- [0] - Trace Enable
-- [1] - Break On Error
-- [2] - Break on IU watchpoint
-- [3] - Break on s/w break points
--
-- [4] - (Break on trap)
-- [5] - Break on error traps
-- [6] - Debug mode (Read mode only)
-- [7] - DSUEN (read mode)
--
-- [8] - DSUBRE (read mode)
-- [9] - Processor mode error (clears error)
-- [10] - processor halt (returns 1 if processor halted)
-- [11] - power down mode (return 1 if processor in power down mode)
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
end;
begin
dsuctsn <= '0';
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 29ad32b45004893443194e15b2f35eff | 0.526983 | 3.341718 | false | false | false | false |
freecores/mdct | source/testbench/MDCTTB_PKG.vhd | 1 | 18,986 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : MDCTTB_PKG
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : MDCTTB_PKG.VHD
-- Created : Sat Mar 5 2006
--
--------------------------------------------------------------------------------
--
-- Description : Package for testbench simulation
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
library STD;
use STD.TEXTIO.all;
library WORK;
use WORK.MDCT_PKG.all;
package MDCTTB_PKG is
----------------------------------------------
-- constant section 1
----------------------------------------------
constant MAX_IMAGE_SIZE_X : INTEGER := 1024;
constant MAX_IMAGE_SIZE_Y : INTEGER := 1024;
----------------------------------------------
-- type section
----------------------------------------------
type MATRIX_TYPE is array (0 to N-1,0 TO N-1) of REAL;
type I_MATRIX_TYPE is array (0 to N-1,0 TO N-1) of INTEGER;
type COEM_TYPE is array (0 to N/2-1, 0 to N/2-1)
of SIGNED(ROMDATA_W-1 downto 0);
type VECTOR4 is array (0 to N/2-1) of REAL;
type N_LINES_TYPE is array (0 to N-1)
of STD_LOGIC_VECTOR(0 to MAX_IMAGE_SIZE_X*IP_W-1);
type IMAGE_TYPE is array (0 to MAX_IMAGE_SIZE_Y-1,
0 to MAX_IMAGE_SIZE_X-1) of INTEGER;
----------------------------------------------
-- function section
----------------------------------------------
procedure CMP_MATRIX(ref_matrix : in I_MATRIX_TYPE;
dcto_matrix : in I_MATRIX_TYPE;
max_error : in INTEGER;
error_matrix : out I_MATRIX_TYPE;
error_cnt : inout INTEGER);
function STR(int: INTEGER; base: INTEGER) return STRING;
function COMPUTE_REF_DCT1D(input_matrix : I_MATRIX_TYPE; shift : BOOLEAN
) return I_MATRIX_TYPE;
function COMPUTE_REF_IDCT(X : I_MATRIX_TYPE) return I_MATRIX_TYPE;
function COMPUTE_PSNR(ref_input : I_MATRIX_TYPE;
reconstr_input : I_MATRIX_TYPE) return REAL;
function COMPUTE_PSNR(ref_input : IMAGE_TYPE;
reconstr_input : IMAGE_TYPE;
ysize : INTEGER;
xsize : INTEGER
) return REAL;
----------------------------------------------
-- constant section 2
----------------------------------------------
-- set below to true to enable quantization in testbench
constant CLK_FREQ_C : INTEGER := 50;
constant HOLD_TIME : TIME := 1 ns;
constant ENABLE_QUANTIZATION_C : BOOLEAN := FALSE;
constant HEX_BASE : INTEGER := 16;
constant DEC_BASE : INTEGER := 10;
constant RUN_FULL_IMAGE : BOOLEAN := FALSE;
constant FILEIN_NAME_C : STRING := "SOURCE\TESTBENCH\lena512.txt";
constant FILEERROR_NAME_C : STRING := "SOURCE\TESTBENCH\imagee.txt";
constant FILEIMAGEO_NAME_C : STRING := "SOURCE\TESTBENCH\imageo.txt";
constant MAX_ERROR_1D : INTEGER := 1;
constant MAX_ERROR_2D : INTEGER := 4;
constant MAX_PIX_VAL : INTEGER := 2**IP_W-1;
constant null_data_r : MATRIX_TYPE :=
(
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0),
(000.0,000.0,000.0,000.0,000.0,000.0,000.0,000.0)
);
constant input_data0 : I_MATRIX_TYPE :=
(
(139,144,149,153,155,155,155,155),
(144,151,153,156,159,156,156,156),
(150,155,160,163,158,156,156,156),
(159,161,162,160,160,159,159,159),
(159,160,161,162,162,155,155,155),
(161,161,161,161,160,157,157,157),
(162,162,161,163,162,157,157,157),
(162,162,161,161,163,158,158,158)
);
constant input_data1 : I_MATRIX_TYPE :=
(
(255,255,255,000,000,255,254,255),
(255,255,255,000,000,255,254,000),
(255,255,255,000,000,255,254,255),
(255,255,255,000,000,255,254,000),
(254,000,255,255,000,255,254,255),
(254,000,255,255,000,255,254,000),
(254,000,255,255,000,255,254,255),
(254,000,255,255,000,255,254,000)
);
constant input_data2 : I_MATRIX_TYPE :=
(
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000),
(000,000,000,000,000,000,000,000)
);
constant input_data3 : I_MATRIX_TYPE :=
(
(55,89,0,2,35,34,100,255),
(144,151,153,151,159,156,156,156),
(150,155,165,163,158,126,156,156),
(254,000,255,255,000,245,254,255),
(159,199,161,162,162,133,155,165),
(231,000,255,235,000,255,254,253),
(162,162,161,163,162,157,157,157),
(11,12,167,165,166,167,101,108)
);
constant input_data4 : I_MATRIX_TYPE :=
(
(135,14,145,15,155,15,155,15),
(140,15,151,15,152,15,153,15),
(154,15,165,16,156,15,157,15),
(158,16,168,16,169,15,150,15),
(15,161,16,162,16,153,15,154),
(165,16,166,16,167,15,158,15),
(16,169,16,160,16,152,15,153),
(164,16,165,16,165,15,156,15)
);
-- from JPEG standard (but not in standard itself!)
constant Q_JPEG_STD : I_MATRIX_TYPE :=
(
(16,11,10,16,24,40,51,61),
(12,12,14,19,26,58,60,55),
(14,13,16,24,40,57,69,56),
(14,17,22,29,51,87,80,62),
(18,22,37,56,68,109,103,77),
(24,35,55,64,81,104,113,92),
(49,64,78,87,103,121,120,101),
(72,92,95,98,112,100,103,99)
);
-- CANON EOS10D super fine quality
constant Q_CANON10D : I_MATRIX_TYPE :=
(
(1, 1, 1, 1, 1, 1, 2, 2),
(1, 1, 1, 1, 1, 2, 4, 4),
(1, 1, 1, 1, 1, 3, 3, 5),
(1, 1, 1, 2, 3, 3, 5, 5),
(1, 1, 3, 3, 4, 4, 5, 5),
(1, 3, 3, 3, 4, 5, 6, 6),
(2, 3, 3, 5, 3, 6, 5, 5),
(3, 3, 4, 3, 6, 4, 5, 5)
);
-- quantization matrix used in testbench
constant Q_MATRIX_USED : I_MATRIX_TYPE := Q_CANON10D;
constant Ce : COEM_TYPE :=
(
(AP,AP,AP,AP),
(BP,CP,CM,BM),
(AP,AM,AM,AP),
(CP,BM,BP,CM)
);
constant Co : COEM_TYPE :=
(
(DP,EP,FP,GP),
(EP,GM,DM,FM),
(FP,DM,GP,EP),
(GP,FM,EP,DM)
);
end MDCTTB_PKG;
--------------------------------------------------
-- PACKAGE BODY
--------------------------------------------------
package body MDCTTB_PKG is
--------------------------------------------------------------------------
-- converts an INTEGER into a CHARACTER
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the CHARACTERs A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
--------------------------------------------------------------------------
function CHR(int: INTEGER) return CHARACTER is
variable c: CHARACTER;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end CHR;
--------------------------------------------------------------------------
-- convert INTEGER to STRING using specified base
--------------------------------------------------------------------------
function STR(int: INTEGER; base: INTEGER) return STRING is
variable temp: STRING(1 to 10);
variable num: INTEGER;
variable abs_int: INTEGER;
variable len: INTEGER := 1;
variable power: INTEGER := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop
len := len + 1;
num := num / base;
end loop ;
for i in len downto 1 loop
temp(i) := chr(abs_int/power mod base);
power := power * base;
end loop ;
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end STR;
------------------------------------------------
-- computes DCT1D
------------------------------------------------
function COMPUTE_REF_DCT1D(input_matrix : I_MATRIX_TYPE; shift : BOOLEAN)
return I_MATRIX_TYPE is
variable fXm : VECTOR4 := (0.0,0.0,0.0,0.0);
variable fXs : VECTOR4 := (0.0,0.0,0.0,0.0);
variable fYe : VECTOR4 := (0.0,0.0,0.0,0.0);
variable fYo : VECTOR4 := (0.0,0.0,0.0,0.0);
variable ref_dct_matrix : I_MATRIX_TYPE;
variable norma_input : MATRIX_TYPE;
begin
-- compute reference coefficients
for x in 0 to N-1 loop
for s in 0 to 7 loop
if shift = TRUE then
norma_input(x,s) := (REAL(input_matrix(x,s))- REAL(LEVEL_SHIFT))/2.0;
else
norma_input(x,s) := REAL(input_matrix(x,s))/2.0;
end if;
end loop;
fXs(0) := norma_input(x,0)+norma_input(x,7);
fXs(1) := norma_input(x,1)+norma_input(x,6);
fXs(2) := norma_input(x,2)+norma_input(x,5);
fXs(3) := norma_input(x,3)+norma_input(x,4);
fXm(0) := norma_input(x,0)-norma_input(x,7);
fXm(1) := norma_input(x,1)-norma_input(x,6);
fXm(2) := norma_input(x,2)-norma_input(x,5);
fXm(3) := norma_input(x,3)-norma_input(x,4);
for k in 0 to N/2-1 loop
fYe(k) := REAL(TO_INTEGER(Ce(k,0)))*fXs(0) +
REAL(TO_INTEGER(Ce(k,1)))*fXs(1) +
REAL(TO_INTEGER(Ce(k,2)))*fXs(2) +
REAL(TO_INTEGER(Ce(k,3)))*fXs(3);
fYo(k) := REAL(TO_INTEGER(Co(k,0)))*fXm(0) +
REAL(TO_INTEGER(Co(k,1)))*fXm(1) +
REAL(TO_INTEGER(Co(k,2)))*fXm(2) +
REAL(TO_INTEGER(Co(k,3)))*fXm(3);
end loop;
-- transpose matrix by writing in row order
ref_dct_matrix(0,x) := INTEGER(fYe(0)/REAL((2**(COE_W-1))));
ref_dct_matrix(1,x) := INTEGER(fYo(0)/REAL((2**(COE_W-1))));
ref_dct_matrix(2,x) := INTEGER(fYe(1)/REAL((2**(COE_W-1))));
ref_dct_matrix(3,x) := INTEGER(fYo(1)/REAL((2**(COE_W-1))));
ref_dct_matrix(4,x) := INTEGER(fYe(2)/REAL((2**(COE_W-1))));
ref_dct_matrix(5,x) := INTEGER(fYo(2)/REAL((2**(COE_W-1))));
ref_dct_matrix(6,x) := INTEGER(fYe(3)/REAL((2**(COE_W-1))));
ref_dct_matrix(7,x) := INTEGER(fYo(3)/REAL((2**(COE_W-1))));
end loop;
return ref_dct_matrix;
end COMPUTE_REF_DCT1D;
-----------------------------------------------
-- compares NxN matrices, logs failure if difference
-- greater than maximum error specified
-----------------------------------------------
procedure CMP_MATRIX(ref_matrix : in I_MATRIX_TYPE;
dcto_matrix : in I_MATRIX_TYPE;
max_error : in INTEGER;
error_matrix : out I_MATRIX_TYPE;
error_cnt : inout INTEGER
) is
variable error_matrix_v : I_MATRIX_TYPE;
begin
for a in 0 to N - 1 loop
for b in 0 to N - 1 loop
error_matrix_v(a,b) := ref_matrix(a,b) - dcto_matrix(a,b);
if abs(error_matrix_v(a,b)) > max_error then
error_cnt := error_cnt + 1;
assert false
report "E01: DCT max error violated!"
severity Error;
end if;
end loop;
end loop;
error_matrix := error_matrix_v;
end CMP_MATRIX;
------------------------------------------------
-- computes IDCT on NxN matrix
------------------------------------------------
function COMPUTE_REF_IDCT(X : I_MATRIX_TYPE)
return I_MATRIX_TYPE is
variable i : INTEGER := 0;
variable j : INTEGER := 0;
variable u : INTEGER := 0;
variable v : INTEGER := 0;
variable Cu : REAL;
variable Cv : REAL;
variable xi : MATRIX_TYPE := null_data_r;
variable xr : I_MATRIX_TYPE;
begin
-- idct
for i in 0 to N-1 loop
for j in 0 to N-1 loop
for u in 0 to N-1 loop
if u = 0 then
Cu := 1.0/sqrt(2.0);
else
Cu := 1.0;
end if;
for v in 0 to N-1 loop
if v = 0 then
Cv := 1.0/sqrt(2.0);
else
Cv := 1.0;
end if;
xi(i,j) := xi(i,j) +
2.0/REAL(N)*Cu*Cv*REAL(X(u,v))*
cos( ( (2.0*REAL(i)+1.0)*REAL(u)*MATH_PI ) / (2.0*REAL(N)) )*
cos( ( (2.0*REAL(j)+1.0)*REAL(v)*MATH_PI ) / (2.0*REAL(N)) );
xr(i,j) := INTEGER(ROUND(xi(i,j)))+LEVEL_SHIFT;
end loop;
end loop;
end loop;
end loop;
return xr;
end COMPUTE_REF_IDCT;
------------------------------------------------
-- computes peak signal to noise ratio
-- for reconstruced and input image data
------------------------------------------------
function COMPUTE_PSNR(ref_input : I_MATRIX_TYPE;
reconstr_input : I_MATRIX_TYPE) return REAL is
variable psnr_tmp : REAL := 0.0;
begin
for i in 0 to N-1 loop
for j in 0 to N-1 loop
psnr_tmp := psnr_tmp + (REAL(ref_input(i,j))-REAL(reconstr_input(i,j)))**2;
end loop;
end loop;
psnr_tmp := psnr_tmp / (REAL(N)*REAL(N));
psnr_tmp := 10.0*LOG10( (REAL(MAX_PIX_VAL)**2) / psnr_tmp );
return psnr_tmp;
end COMPUTE_PSNR;
------------------------------------------------
-- computes peak signal to noise ratio
-- for reconstruced and input image data
------------------------------------------------
function COMPUTE_PSNR(ref_input : IMAGE_TYPE;
reconstr_input : IMAGE_TYPE;
ysize : INTEGER;
xsize : INTEGER
) return REAL is
variable psnr_tmp : REAL := 0.0;
variable lineb : LINE;
begin
for i in 0 to ysize-1 loop
for j in 0 to xsize-1 loop
psnr_tmp := psnr_tmp +
(REAL(ref_input(i,j))-REAL(reconstr_input(i,j)))**2;
end loop;
end loop;
psnr_tmp := psnr_tmp / (REAL(ysize)*REAL(xsize));
--WRITE(lineb,STRING'("MSE Mean Squared Error is "));
--WRITE(lineb,psnr_tmp);
--assert false
-- report lineb.all
-- severity Note;
psnr_tmp := 10.0*LOG10( (REAL(MAX_PIX_VAL)**2) / psnr_tmp );
return psnr_tmp;
end COMPUTE_PSNR;
end MDCTTB_PKG; | lgpl-3.0 | e0b8e5d0e19bfbab8e934f8e46eada91 | 0.394712 | 3.67234 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/GPR/src/CTRL1.vhd | 1 | 6,631 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library gpr;
use gpr.OneHotGPR.all;
entity CTRL1 is
port(
CLK, RST, Start: in std_logic;
Stop: out std_logic;
-- ROM
ROM_re: out std_logic;
ROM_addr: out mem_addr;
ROM_dout: in command;
-- RAM
RAM_rw: out std_logic;
RAM_addr1: out mem_addr;
RAM_addr2: out mem_addr;
RAM_addrw: out mem_addr;
RAM_dwin: out operand;
RAM_d1out: in operand;
RAM_d2out: in operand;
--datapath
DP_op1: out operand;
DP_op2: out operand;
DP_ot: out operation;
DP_en: out std_logic;
DP_res: in operand;
DP_zf: in std_logic
);
end CTRL1;
architecture Beh_GPR of CTRL1 is
type states is (I, F, D, R, W, A, SB, SH, H, M, CP, CPR, JNOTZ);
-- I - idle
-- F - fetch
-- D - decode
-- R - read
-- W - write
-- A - add
-- SB - sub
-- SH - shift
-- H - halt
-- M - move the value from RD_1 to RD_W
-- CP - copy to indirect, CP addr1, [addrw], empty - load ra_2 from rd_2
-- CPR - copy to indirect, read - RA_W = RA_2
-- JNOTZ - jump if zero bit not set
signal nxt_state, cur_state: states;
-- instruction register
signal RI: std_logic_vector(17 downto 0);
-- instruction counter
signal IC: mem_addr;
-- operation type register
signal RO: std_logic_vector(2 downto 0);
-- memory address register for the first operand
signal RA_1: mem_addr;
-- memory address register for the second operand
signal RA_2: mem_addr;
-- memory address register for the result
signal RA_W: mem_addr;
-- data register for the first operand
signal RD_1: operand;
-- data register for the second operand
signal RD_2: operand;
-- data register for the result
signal RD_W: operand;
begin
-- synchronous memory
FSM: process(CLK, RST, nxt_state)
begin
if (RST = '1') then
cur_state <= I;
elsif rising_edge(CLK) then
cur_state <= nxt_state;
end if;
end process;
-- Next state
COMB: process(cur_state, start, RO)
begin
case cur_state is
when I =>
if (start = '1') then
nxt_state <= F;
else
nxt_state <= I;
end if;
when F => nxt_state <= D;
when D =>
if (RO = HALT) then
nxt_state <= H;
elsif (RO = JNZ) then
nxt_state <= JNOTZ;
else
nxt_state <= R;
end if;
when R =>
if (RO = ADD) then
nxt_state <= A;
elsif (RO = SUBT) then
nxt_state <= SB;
elsif (RO = SHIFT) then
nxt_state <= SH;
elsif (RO = COPY) then
nxt_state <= CP;
else
nxt_state <= I;
end if;
when CP => nxt_state <= CPR;
when CPR => nxt_state <= M;
when A | SB | SH | M => nxt_state <= W;
when W | JNOTZ => nxt_state <= F;
when H => nxt_state <= H;
when others => nxt_state <= I;
end case;
end process;
-- stop signal handler
PSTOP: process (cur_state)
begin
if (cur_state = H) then
stop <= '1';
else
stop <= '0';
end if;
end process;
-- instruction counter
PMC: process (CLK, RST, cur_state)
begin
if (RST = '1') then
IC <= (others => '0');
elsif falling_edge(CLK) then
if (cur_state = D) then
IC <= IC + 1;
elsif (cur_state = JNOTZ and DP_ZF = '0') then
IC <= RA_1;
end if;
end if;
end process;
ROM_addr <= IC;
-- reading from ROM
PROMREAD: process (nxt_state, cur_state)
begin
if (nxt_state = F or cur_state = F) then
ROM_re <= '1';
else
ROM_re <= '0';
end if;
end process;
-- reading the instruction from ROM and put it into RI
PROMDAT: process (RST, cur_state, ROM_dout)
begin
if (RST = '1') then
RI <= (others => '0');
elsif (cur_state = F) then
RI <= ROM_dout;
end if;
end process;
-- fill RO and RA_1, RA_2, RA_W registers
PRORA: process (RST, nxt_state, RI)
begin
if (RST = '1') then
RO <= (others => '0');
RA_1 <= (others => '0');
RA_2 <= (others => '0');
RA_W <= (others => '0');
elsif (nxt_state = D) then
RO <= RI (17 downto 15);
RA_1 <= RI (14 downto 10);
RA_2 <= RI (9 downto 5);
RA_W <= RI (4 downto 0);
elsif (nxt_state = CP) then
RA_2 <= RD_2 (4 downto 0);
elsif (nxt_state = CPR) then
RA_W <= RA_2;
end if;
end process;
PRAMST: process (RA_1, RA_2, RA_W)
begin
if (cur_state /= JNOTZ) then
RAM_addr1 <= RA_1;
RAM_addr2 <= RA_2;
RAM_addrw <= RA_W;
end if;
end process;
-- control read/write signal for RAM
PRAMREAD: process (cur_state)
begin
if (cur_state = W) then
RAM_rw <= '0';
else
RAM_rw <= '1';
end if;
end process;
-- read values from RAM and store them in RD_1 and RD_2 registers
PRAMDAR: process (cur_state)
begin
if (cur_state = R) then
RD_1 <= RAM_d1out;
RD_2 <= RAM_d2out;
end if;
end process;
-- pass the value from data path to RAM data bus
RAM_dwin <= DP_res;
-- pass the value from RD_1 register to the data path first operand
DP_op1 <= RD_1;
-- pass the value from RD_2 register to the data path second operand
DP_op2 <= RD_2;
-- pass the value from RO register to the data path operation type
DP_ot <= RO;
paddsuben: process (cur_state)
begin
if (cur_state = A or cur_state = SB or cur_state = SH or cur_state = M) then
DP_en <= '1';
else
DP_en <= '0';
end if;
end process;
end Beh_GPR; | mit | 70f37805e7c4f6ebb094e9c91744bcb6 | 0.464937 | 3.776196 | false | false | false | false |
dsaves/dsaves-hdl | crypto/sha_512/sha_512_core.vhdl | 1 | 15,504 | --MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
-- ############################################################################
-- The official specifications of the SHA-256 algorithm can be found here:
-- http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf
-- ##################################################################
-- This SHA_512_CORE module reads in PADDED message blocks (from
-- an external source) and hashes the resulting message
-- ##################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha_512_pkg.all;
entity sha_512_core is
generic(
RESET_VALUE : std_logic := '0' --reset enable value
);
port(
clk : in std_logic;
rst : in std_logic;
data_ready : in std_logic; --the edge of this signal triggers the capturing of input data and hashing it.
n_blocks : in natural; --N, the number of (padded) message blocks
msg_block_in : in std_logic_vector(0 to (16 * WORD_SIZE)-1);
--mode_in : in std_logic;
finished : out std_logic;
data_out : out std_logic_vector((WORD_SIZE * 8)-1 downto 0) --SHA-512 results in a 512-bit hash value
);
end entity;
architecture sha_512_core_ARCH of sha_512_core is
signal HASH_ROUND_COUNTER : natural := 0;
signal MSG_BLOCK_COUNTER : natural := 0;
signal HASH_02_COUNTER : natural := 0;
constant HASH_02_COUNT_LIMIT : natural := 80;
--Temporary words
signal T1 : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal T2 : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
--Working variables, 8 64-bit words
signal a : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal b : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal c : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal d : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal e : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal f : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal g : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
signal h : std_logic_vector(WORD_SIZE-1 downto 0) := (others => '0');
constant K : K_DATA := (
--address 0
X"428a2f98d728ae22", X"7137449123ef65cd", X"b5c0fbcfec4d3b2f", X"e9b5dba58189dbbc",
X"3956c25bf348b538", X"59f111f1b605d019", X"923f82a4af194f9b", X"ab1c5ed5da6d8118",
X"d807aa98a3030242", X"12835b0145706fbe", X"243185be4ee4b28c", X"550c7dc3d5ffb4e2",
X"72be5d74f27b896f", X"80deb1fe3b1696b1", X"9bdc06a725c71235", X"c19bf174cf692694",
X"e49b69c19ef14ad2", X"efbe4786384f25e3", X"0fc19dc68b8cd5b5", X"240ca1cc77ac9c65",
X"2de92c6f592b0275", X"4a7484aa6ea6e483", X"5cb0a9dcbd41fbd4", X"76f988da831153b5",
X"983e5152ee66dfab", X"a831c66d2db43210", X"b00327c898fb213f", X"bf597fc7beef0ee4",
X"c6e00bf33da88fc2", X"d5a79147930aa725", X"06ca6351e003826f", X"142929670a0e6e70",
X"27b70a8546d22ffc", X"2e1b21385c26c926", X"4d2c6dfc5ac42aed", X"53380d139d95b3df",
X"650a73548baf63de", X"766a0abb3c77b2a8", X"81c2c92e47edaee6", X"92722c851482353b",
X"a2bfe8a14cf10364", X"a81a664bbc423001", X"c24b8b70d0f89791", X"c76c51a30654be30",
X"d192e819d6ef5218", X"d69906245565a910", X"f40e35855771202a", X"106aa07032bbd1b8",
X"19a4c116b8d2d0c8", X"1e376c085141ab53", X"2748774cdf8eeb99", X"34b0bcb5e19b48a8",
X"391c0cb3c5c95a63", X"4ed8aa4ae3418acb", X"5b9cca4f7763e373", X"682e6ff3d6b2b8a3",
X"748f82ee5defb2fc", X"78a5636f43172f60", X"84c87814a1f0ab72", X"8cc702081a6439ec",
X"90befffa23631e28", X"a4506cebde82bde9", X"bef9a3f7b2c67915", X"c67178f2e372532b",
X"ca273eceea26619c", X"d186b8c721c0c207", X"eada7dd6cde0eb1e", X"f57d4f7fee6ed178",
X"06f067aa72176fba", X"0a637dc5a2c898a6", X"113f9804bef90dae", X"1b710b35131c471b",
X"28db77f523047d84", X"32caab7b40c72493", X"3c9ebe0a15c9bebc", X"431d67c49c100d4c",
X"4cc5d4becb3e42b6", X"597f299cfc657e2a", X"5fcb6fab3ad6faec", X"6c44198c4a475817"
);
--Message schedule, W(00), W(01), ...W(63) (80 64-bit words)
signal W : K_DATA := (
--address 0
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000",
X"0000000000000000", X"0000000000000000", X"0000000000000000", X"0000000000000000"
);
--Hash values w/ initial hash values; 8 64-bit words
signal HV : H_DATA;
signal HV_INITIAL_VALUES : H_DATA := ( X"6a09e667f3bcc908", X"bb67ae8584caa73b",
X"3c6ef372fe94f82b", X"a54ff53a5f1d36f1",
X"510e527fade682d1", X"9b05688c2b3e6c1f",
X"1f83d9abfb41bd6b", X"5be0cd19137e2179");
--intermediate Message block values; for use with a for-generate loop;
signal M_INT : M_DATA;
--intermediate Message Schedule values; for use with a for-generate loop;
signal W_INT : K_DATA;
type SHA_512_HASH_CORE_STATE is ( RESET, IDLE, READ_MSG_BLOCK, PREP_MSG_SCHEDULE_00, PREP_MSG_SCHEDULE_01, PREP_MSG_SCHEDULE_02, PREP_MSG_SCHEDULE_03, PREP_MSG_SCHEDULE_04, HASH_01, HASH_02, HASH_02b, HASH_02c, HASH_03, DONE );
signal CURRENT_STATE, NEXT_STATE : SHA_512_HASH_CORE_STATE;
signal PREVIOUS_STATE : SHA_512_HASH_CORE_STATE := READ_MSG_BLOCK;
begin
--current state logic
process(clk, rst)
begin
if(rst=RESET_VALUE) then
CURRENT_STATE <= RESET;
elsif(clk'event and clk='1') then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
--next state logic
process(CURRENT_STATE, HASH_ROUND_COUNTER, HASH_02_COUNTER, rst, data_ready)
begin
case CURRENT_STATE is
when RESET =>
if(rst=RESET_VALUE) then
NEXT_STATE <= RESET;
else
NEXT_STATE <= IDLE;
end if;
when IDLE =>
if(data_ready='1') then
NEXT_STATE <= READ_MSG_BLOCK;
else
NEXT_STATE <= IDLE;
end if;
when READ_MSG_BLOCK =>
NEXT_STATE <= PREP_MSG_SCHEDULE_00;
when PREP_MSG_SCHEDULE_00 =>
NEXT_STATE <= PREP_MSG_SCHEDULE_01;
when PREP_MSG_SCHEDULE_01 =>
NEXT_STATE <= PREP_MSG_SCHEDULE_02;
when PREP_MSG_SCHEDULE_02 =>
NEXT_STATE <= PREP_MSG_SCHEDULE_03;
when PREP_MSG_SCHEDULE_03 =>
NEXT_STATE <= PREP_MSG_SCHEDULE_04;
when PREP_MSG_SCHEDULE_04 =>
NEXT_STATE <= HASH_01;
when HASH_01 =>
NEXT_STATE <= HASH_02;
when HASH_02 =>
if(HASH_02_COUNTER = HASH_02_COUNT_LIMIT) then
NEXT_STATE <= HASH_03;
else
NEXT_STATE <= HASH_02b;
end if;
when HASH_02b =>
NEXT_STATE <= HASH_02c;
when HASH_02c =>
NEXT_STATE <= HASH_02;
when HASH_03 =>
if(HASH_ROUND_COUNTER = n_blocks-1) then
NEXT_STATE <= DONE;
else
NEXT_STATE <= IDLE;
end if;
when DONE =>
NEXT_STATE <= DONE; --stay in done state unless reset
end case;
end process;
--hash logic
process(clk, rst, CURRENT_STATE)
begin
if(rst=RESET_VALUE) then
HASH_ROUND_COUNTER <= 0;
MSG_BLOCK_COUNTER <= 0;
elsif(clk'event and clk='1') then
a <= a; b <= b; c <= c; d <= d;
e <= e; f <= f; g <= g; h <= h;
T1 <= T1; T2 <= T2;
W <= W; M <= M; HV <= HV;
HASH_02_COUNTER <= HASH_02_COUNTER;
HASH_ROUND_COUNTER <= HASH_ROUND_COUNTER;
case CURRENT_STATE is
when RESET =>
HV <= HV_INITIAL_VALUES;
HASH_02_COUNTER <= 0;
HASH_ROUND_COUNTER <= 0;
when IDLE => --the IDLE stage is a stall stage, perhaps waiting for new message block to arrive.
when READ_MSG_BLOCK =>
if(HASH_ROUND_COUNTER = 0) then
HV <= HV_INITIAL_VALUES;
end if;
M <= M_INT;
when PREP_MSG_SCHEDULE_00 =>
W(0 to 15) <= W_INT(0 to 15);
when PREP_MSG_SCHEDULE_01 =>
W(16 to 31) <= W_INT(16 to 31);
when PREP_MSG_SCHEDULE_02 =>
W(32 to 47) <= W_INT(32 to 47);
when PREP_MSG_SCHEDULE_03 =>
W(48 to 63) <= W_INT(48 to 63);
when PREP_MSG_SCHEDULE_04 =>
W(64 to 79) <= W_INT(64 to 79);
when HASH_01 =>
a <= HV(0);
b <= HV(1);
c <= HV(2);
d <= HV(3);
e <= HV(4);
f <= HV(5);
g <= HV(6);
h <= HV(7);
when HASH_02 =>
if(HASH_02_COUNTER = HASH_02_COUNT_LIMIT) then
HASH_02_COUNTER <= 0;
else
--you have to set T1 and T2 in a different state, due to how
--VHDL sequential/process statements are evaluated.
T1 <= std_logic_vector(unsigned(h) + unsigned(SIGMA_UCASE_1(e)) + unsigned(CH(e, f, g)) + unsigned(K(HASH_02_COUNTER)) + unsigned(W(HASH_02_COUNTER)));
T2 <= std_logic_vector(unsigned(SIGMA_UCASE_0(a)) + unsigned(MAJ(a, b, c)));
end if;
when HASH_02b =>
h <= g;
g <= f;
f <= e;
e <= std_logic_vector(unsigned(d) + unsigned(T1));
d <= c;
c <= b;
b <= a;
a <= std_logic_vector(unsigned(T1) + unsigned(T2));
when HASH_02c =>
HASH_02_COUNTER <= HASH_02_COUNTER + 1; --increment counter
when HASH_03 =>
HV(0) <= std_logic_vector(unsigned(a) + unsigned(HV(0)));
HV(1) <= std_logic_vector(unsigned(b) + unsigned(HV(1)));
HV(2) <= std_logic_vector(unsigned(c) + unsigned(HV(2)));
HV(3) <= std_logic_vector(unsigned(d) + unsigned(HV(3)));
HV(4) <= std_logic_vector(unsigned(e) + unsigned(HV(4)));
HV(5) <= std_logic_vector(unsigned(f) + unsigned(HV(5)));
HV(6) <= std_logic_vector(unsigned(g) + unsigned(HV(6)));
HV(7) <= std_logic_vector(unsigned(h) + unsigned(HV(7)));
if(HASH_ROUND_COUNTER = n_blocks-1) then
HASH_ROUND_COUNTER <= 0;
else
HASH_ROUND_COUNTER <= HASH_ROUND_COUNTER + 1; --increment counter, read in next message block
end if;
when DONE =>
end case;
end if;
end process;
MESSAGE_BLOCK_INTERMEDIATE :
for i in 0 to 15 generate
begin
--M_INT(i) <= msg_block_in((WORD_SIZE * (i+1))-1 downto WORD_SIZE * i);
M_INT(i) <= msg_block_in((WORD_SIZE * i) to WORD_SIZE * (i+1)-1);
end generate;
MESSAGE_SCHEDULE_INTERMEDIATE_00:
for i in 0 to 15 generate
begin
W_INT(i) <= M(i);
end generate;
MESSAGE_SCHEDULE_INTERMEDIATE_01:
for i in 16 to 79 generate
begin
W_INT(i) <= std_logic_vector(unsigned(SIGMA_LCASE_1(W_INT(i-2))) + unsigned(W_INT(i-7)) + unsigned(SIGMA_LCASE_0(W_INT(i-15))) + unsigned(W_INT(i-16)));
end generate;
--FINISHED signal asserts when hashing is done
finished <= '1' when CURRENT_STATE = DONE else
'0';
data_out <= HV(0) & HV(1) & HV(2) & HV(3) & HV(4) & HV(5) & HV(6) & HV(7);
end architecture;
| mit | f2d3231214a8c9523e386135d96413ef | 0.551729 | 3.542962 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/93e5591f9289143f/zqynq_lab_1_design_axi_gpio_0_0_sim_netlist.vhdl | 1 | 51,884 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:07:50 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_gpio_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair4";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_io_o(7 downto 0) <= \^gpio_io_o\(7 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(7),
Q => D(7),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(6),
Q => D(6),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(5),
Q => D(5),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(4),
Q => D(4),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(3),
Q => D(3),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[5].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(2),
Q => D(2),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[6].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(1),
Q => D(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(0),
Q => D(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7),
Q => \^gpio_io_o\(7),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6),
Q => \^gpio_io_o\(6),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5),
Q => \^gpio_io_o\(5),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => \^gpio_io_o\(4),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => \^gpio_io_o\(3),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => \^gpio_io_o\(2),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => \^gpio_io_o\(1),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => \^gpio_io_o\(0),
R => SS(0)
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7),
Q => gpio_io_t(7),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6),
Q => gpio_io_t(6),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5),
Q => gpio_io_t(5),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => gpio_io_t(4),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => gpio_io_t(3),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => gpio_io_t(2),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => gpio_io_t(1),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => gpio_io_t(0),
S => SS(0)
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
rst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
start2_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => start2_reg,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => gpio_xferAck_Reg,
I3 => GPIO_xferAck_i,
O => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAABAAAA"
)
port map (
I0 => rst_reg,
I1 => Q(1),
I2 => bus2ip_rnw_i_reg,
I3 => Q(0),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => Q(2),
O => E(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(15),
O => D(7)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(14),
O => D(6)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(13),
O => D(5)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(12),
O => D(4)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(11),
O => D(3)
);
\Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(10),
O => D(2)
);
\Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(9),
O => D(1)
);
\Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(8),
O => D(0)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => rst_reg,
I1 => Q(0),
I2 => Q(1),
I3 => bus2ip_rnw_i_reg,
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => Q(2),
O => \Not_Dual.gpio_OE_reg[0]\(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
SR : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_data_out_reg[0]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair1";
begin
\Not_Dual.gpio_Data_Out_reg[0]\ <= \^not_dual.gpio_data_out_reg[0]\;
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(7 downto 0) => D(7 downto 0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(2) => bus2ip_addr(0),
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^not_dual.gpio_data_out_reg[0]\,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
rst_reg => \^sr\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
s_axi_wready => \^s_axi_wready\,
start2_reg => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(5),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_data_out_reg[0]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_in,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[7]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(0),
Q => s_axi_rdata(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(1),
Q => s_axi_rdata(1),
R => \^sr\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(2),
Q => s_axi_rdata(2),
R => \^sr\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(3),
Q => s_axi_rdata(3),
R => \^sr\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(4),
Q => s_axi_rdata(4),
R => \^sr\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(5),
Q => s_axi_rdata(5),
R => \^sr\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(6),
Q => s_axi_rdata(6),
R => \^sr\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(7),
Q => s_axi_rdata(7),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => p_0_out(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
D(7 downto 0) => D(7 downto 0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => bus2ip_rnw,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(7 downto 0) => Q(7 downto 0),
SR => bus2ip_reset,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => s_axi_rdata(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "LOGICORE";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_6 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 7 );
signal GPIO_xferAck_i : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_core_1_n_19 : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 24 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 24 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
D(7) => DBus_Reg(0),
D(6) => DBus_Reg(1),
D(5) => DBus_Reg(2),
D(4) => DBus_Reg(3),
D(3) => DBus_Reg(4),
D(2) => DBus_Reg(5),
D(1) => DBus_Reg(6),
D(0) => DBus_Reg(7),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_17,
\Not_Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_7,
Q(7) => ip2bus_data_i_D1(24),
Q(6) => ip2bus_data_i_D1(25),
Q(5) => ip2bus_data_i_D1(26),
Q(4) => ip2bus_data_i_D1(27),
Q(3) => ip2bus_data_i_D1(28),
Q(2) => ip2bus_data_i_D1(29),
Q(1) => ip2bus_data_i_D1(30),
Q(0) => ip2bus_data_i_D1(31),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(15 downto 8) => s_axi_wdata(31 downto 24),
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
gpio_core_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
port map (
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7) => DBus_Reg(0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6) => DBus_Reg(1),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5) => DBus_Reg(2),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4) => DBus_Reg(3),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3) => DBus_Reg(4),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2) => DBus_Reg(5),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1) => DBus_Reg(6),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0) => DBus_Reg(7),
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_17,
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => gpio_io_t(7 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_19,
rst_reg(0) => AXI_LITE_IPIF_I_n_7,
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_19,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_gpio_0_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_gpio,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 1;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(7 downto 0) => B"00000000",
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(7 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 21ee6fffe12ee6de7efb7fc7685f987b | 0.553812 | 2.66893 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-ztex-ufm-115/leon3mp.vhd | 1 | 16,905 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Patched for ZTEX: Oleg Belousov <[email protected]>
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
library unisim;
use unisim.vcomponents.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk48 : in std_ulogic;
errorn : out std_logic;
-- DDR SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n: inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
dsuact : out std_ulogic; -- Debug Unit break (connect to button)
-- AHB UART (debug link)
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- UART
rxd1 : in std_ulogic;
txd1 : out std_ulogic;
-- SD card
sd_dat : inout std_logic;
sd_cmd : inout std_logic;
sd_sck : inout std_logic;
sd_dat3 : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal clk200 : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal cgo_ddr : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 48000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk48_pad : clkpad generic map (tech => padtech) port map (clk48, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_DDR2 = 1) generate
clkgen_ddr : clkgen
generic map (fabtech, 25, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clk200, open, open, open, open, cgi, cgo_ddr, open, open, open);
ddrc : entity work.ahb2mig_ztex generic map(
hindex => 4, haddr => 16#400#, hmask => CFG_MIG_HMASK,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udm => mcb3_dram_udm,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem => clk200,
test_error => open
);
end generate;
noddr : if CFG_MIG_DDR2 = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- General purpose timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
-- NOTE:
-- GPIO pads are not instantiated here. If you want to use
-- GPIO then add a top-level port, update the UCF and
-- instantiate pads for the GPIO lines as is done in other
-- template designs.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 9, paddr => 9, pmask => 16#fff#, pirq => 10,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => CFG_SPICTRL_ODMODE,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(9), spii, spio, slvsel);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat, spio.miso, spio.misooen, spii.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_sck, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel(0));
spii.spisel <= '1'; -- Master only
end generate spic;
nospic: if CFG_SPICTRL_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for ZTEX USB-FPGA Module 1.15",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 | 04e881b0ef745483e0bcecdbea6eca91 | 0.532742 | 3.769231 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/inferred/ddr_inferred.vhd | 1 | 2,631 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gen_iddr_reg
-- File: gen_iddr_reg.vhd
-- Author: David Lindh, Jiri Gaisler - Gaisler Research
-- Description: Generic DDR input reg
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity gen_iddr_reg is
port(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end;
architecture rtl of gen_iddr_reg is
signal preQ2 : std_ulogic;
begin
ddrregp : process(R,C1)
begin
if R = '1' then Q1 <= '0'; Q2 <= '0';
elsif rising_edge(C1) then Q1 <= D; Q2 <= preQ2; end if;
end process;
ddrregn : process(R,C2)
begin
if R = '1' then preQ2 <= '0';
-- elsif falling_edge(C1) then preQ2 <= D; end if;
elsif rising_edge(C2) then preQ2 <= D; end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity gen_oddr_reg is
port (
Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of gen_oddr_reg is
signal Q1,Q2: std_ulogic;
begin
Q <= Q1 when C1='1' else Q2;
ddrregp: process(C1,R,S)
begin
if rising_edge(C1) then Q1 <= D1; Q2 <= D2; end if;
if S='1' then Q1 <= '1'; Q2 <= '1'; end if;
if R='1' then Q1 <= '0'; Q2 <= '0'; end if;
end process;
end;
| gpl-2.0 | 2028c924839fc4112b3da8b8efd90ec1 | 0.566705 | 3.461842 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_0_1/synth/design_1_axi_bram_ctrl_0_1.vhd | 1 | 17,300 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_12;
USE axi_bram_ctrl_v4_0_12.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_0_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_0_1;
ARCHITECTURE design_1_axi_bram_ctrl_0_1_arch OF design_1_axi_bram_ctrl_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_bram_ctrl_0_1_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_bram_ctrl_0_1_arch : ARCHITECTURE IS "design_1_axi_bram_ctrl_0_1,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_bram_ctrl_0_1_arch: ARCHITECTURE IS "design_1_axi_bram_ctrl_0_1,axi_bram_ctrl,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=2048,C_BRAM_ADDR_WIDTH=11,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_SELECT_XPM=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC" &
"=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_a: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MASTER_TYPE BRAM_CTRL, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_WRITE";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 13, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_0_1_arch;
| mit | 462b82554e3c956a2d64a378eb01535c | 0.68104 | 3.072278 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_2/syn/vhdl/aesl_mux_load_7_3_x_s.vhd | 1 | 21,565 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity aesl_mux_load_7_3_x_s is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
empty_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_2_EN_A : OUT STD_LOGIC;
empty_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_3_EN_A : OUT STD_LOGIC;
empty_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_4_EN_A : OUT STD_LOGIC;
empty_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_5_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_5_EN_A : OUT STD_LOGIC;
empty_5_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_5_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_5_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_6_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_6_EN_A : OUT STD_LOGIC;
empty_6_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_6_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_6_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_7_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_7_EN_A : OUT STD_LOGIC;
empty_7_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_7_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_7_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_8_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_8_EN_A : OUT STD_LOGIC;
empty_8_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
empty_8_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
empty_8_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
empty_9 : IN STD_LOGIC_VECTOR (2 downto 0);
empty_10 : IN STD_LOGIC_VECTOR (1 downto 0);
empty : IN STD_LOGIC_VECTOR (2 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of aesl_mux_load_7_3_x_s is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv3_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_const_lv3_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_const_lv3_4 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC;
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_idle_pp0 : STD_LOGIC;
signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state2_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state3_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal tmp_15_reg_246 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter1_tmp_15_reg_246 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_reg_pp0_iter2_tmp_15_reg_246 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_22_fu_174_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_reg_256 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter1_tmp_22_reg_256 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_21_reg_302 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_22_reg_307 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_23_reg_312 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_24_reg_317 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_25_reg_322 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_26_reg_327 : STD_LOGIC_VECTOR (31 downto 0);
signal empty_27_reg_332 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp3_fu_196_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp3_reg_337 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp4_fu_203_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_reg_342 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_fu_208_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_reg_347 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_fu_213_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_reg_352 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp10_fu_218_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp10_reg_357 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal tmp_fu_156_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_shl_fu_164_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_cast_fu_152_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal p_cast1_fu_148_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_fu_168_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp_fu_180_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_fu_191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp1_fu_185_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp5_fu_223_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp7_fu_228_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp9_fu_234_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_idle_pp0_0to3 : STD_LOGIC;
signal ap_reset_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_start;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_tmp_15_reg_246 <= tmp_15_reg_246;
ap_reg_pp0_iter1_tmp_22_reg_256 <= tmp_22_reg_256;
tmp_15_reg_246 <= empty_9;
tmp_22_reg_256 <= tmp_22_fu_174_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) then
ap_reg_pp0_iter2_tmp_15_reg_246 <= ap_reg_pp0_iter1_tmp_15_reg_246;
empty_21_reg_302 <= empty_8_Dout_A;
empty_22_reg_307 <= empty_2_Dout_A;
empty_23_reg_312 <= empty_3_Dout_A;
empty_24_reg_317 <= empty_4_Dout_A;
empty_25_reg_322 <= empty_5_Dout_A;
empty_26_reg_327 <= empty_6_Dout_A;
empty_27_reg_332 <= empty_7_Dout_A;
sel_tmp10_reg_357 <= sel_tmp10_fu_218_p2;
sel_tmp3_reg_337 <= sel_tmp3_fu_196_p3;
sel_tmp4_reg_342 <= sel_tmp4_fu_203_p2;
sel_tmp6_reg_347 <= sel_tmp6_fu_208_p2;
sel_tmp8_reg_352 <= sel_tmp8_fu_213_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_block_pp0_stage0_flag00011011, ap_reset_idle_pp0)
begin
case ap_CS_fsm is
when ap_ST_fsm_pp0_stage0 =>
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(0);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001_assign_proc : process(ap_start)
begin
ap_block_pp0_stage0_flag00011001 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_start));
end process;
ap_block_pp0_stage0_flag00011011_assign_proc : process(ap_start)
begin
ap_block_pp0_stage0_flag00011011 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_start));
end process;
ap_block_state1_pp0_stage0_iter0_assign_proc : process(ap_start)
begin
ap_block_state1_pp0_stage0_iter0 <= (ap_const_logic_0 = ap_start);
end process;
ap_block_state2_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_done_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_enable_reg_pp0_iter0 <= ap_start;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_idle_pp0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_idle_pp0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3) and (ap_const_logic_0 = ap_enable_reg_pp0_iter4))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_0to3_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3))) then
ap_idle_pp0_0to3 <= ap_const_logic_1;
else
ap_idle_pp0_0to3 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to3)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to3))) then
ap_reset_idle_pp0 <= ap_const_logic_1;
else
ap_reset_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_return <=
empty_27_reg_332 when (sel_tmp10_reg_357(0) = '1') else
sel_tmp9_fu_234_p3;
empty_2_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_2_Din_A <= ap_const_lv32_0;
empty_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
empty_2_EN_A <= ap_const_logic_1;
else
empty_2_EN_A <= ap_const_logic_0;
end if;
end process;
empty_2_WEN_A <= ap_const_lv4_0;
empty_3_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_3_Din_A <= ap_const_lv32_0;
empty_3_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
empty_3_EN_A <= ap_const_logic_1;
else
empty_3_EN_A <= ap_const_logic_0;
end if;
end process;
empty_3_WEN_A <= ap_const_lv4_0;
empty_4_Addr_A <= std_logic_vector(shift_left(unsigned(ap_reg_pp0_iter1_tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_4_Din_A <= ap_const_lv32_0;
empty_4_EN_A_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
empty_4_EN_A <= ap_const_logic_1;
else
empty_4_EN_A <= ap_const_logic_0;
end if;
end process;
empty_4_WEN_A <= ap_const_lv4_0;
empty_5_Addr_A <= std_logic_vector(shift_left(unsigned(ap_reg_pp0_iter1_tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_5_Din_A <= ap_const_lv32_0;
empty_5_EN_A_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
empty_5_EN_A <= ap_const_logic_1;
else
empty_5_EN_A <= ap_const_logic_0;
end if;
end process;
empty_5_WEN_A <= ap_const_lv4_0;
empty_6_Addr_A <= std_logic_vector(shift_left(unsigned(ap_reg_pp0_iter1_tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_6_Din_A <= ap_const_lv32_0;
empty_6_EN_A_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
empty_6_EN_A <= ap_const_logic_1;
else
empty_6_EN_A <= ap_const_logic_0;
end if;
end process;
empty_6_WEN_A <= ap_const_lv4_0;
empty_7_Addr_A <= std_logic_vector(shift_left(unsigned(ap_reg_pp0_iter1_tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_7_Din_A <= ap_const_lv32_0;
empty_7_EN_A_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
empty_7_EN_A <= ap_const_logic_1;
else
empty_7_EN_A <= ap_const_logic_0;
end if;
end process;
empty_7_WEN_A <= ap_const_lv4_0;
empty_8_Addr_A <= std_logic_vector(shift_left(unsigned(tmp_22_reg_256),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
empty_8_Din_A <= ap_const_lv32_0;
empty_8_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
empty_8_EN_A <= ap_const_logic_1;
else
empty_8_EN_A <= ap_const_logic_0;
end if;
end process;
empty_8_WEN_A <= ap_const_lv4_0;
p_cast1_fu_148_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(empty),32));
p_cast_fu_152_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(empty_10),32));
p_shl_fu_164_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_156_p3),32));
sel_tmp10_fu_218_p2 <= "1" when (ap_reg_pp0_iter2_tmp_15_reg_246 = ap_const_lv3_5) else "0";
sel_tmp1_fu_185_p3 <=
empty_22_reg_307 when (sel_tmp_fu_180_p2(0) = '1') else
empty_21_reg_302;
sel_tmp2_fu_191_p2 <= "1" when (ap_reg_pp0_iter2_tmp_15_reg_246 = ap_const_lv3_1) else "0";
sel_tmp3_fu_196_p3 <=
empty_23_reg_312 when (sel_tmp2_fu_191_p2(0) = '1') else
sel_tmp1_fu_185_p3;
sel_tmp4_fu_203_p2 <= "1" when (ap_reg_pp0_iter2_tmp_15_reg_246 = ap_const_lv3_2) else "0";
sel_tmp5_fu_223_p3 <=
empty_24_reg_317 when (sel_tmp4_reg_342(0) = '1') else
sel_tmp3_reg_337;
sel_tmp6_fu_208_p2 <= "1" when (ap_reg_pp0_iter2_tmp_15_reg_246 = ap_const_lv3_3) else "0";
sel_tmp7_fu_228_p3 <=
empty_25_reg_322 when (sel_tmp6_reg_347(0) = '1') else
sel_tmp5_fu_223_p3;
sel_tmp8_fu_213_p2 <= "1" when (ap_reg_pp0_iter2_tmp_15_reg_246 = ap_const_lv3_4) else "0";
sel_tmp9_fu_234_p3 <=
empty_26_reg_327 when (sel_tmp8_reg_352(0) = '1') else
sel_tmp7_fu_228_p3;
sel_tmp_fu_180_p2 <= "1" when (ap_reg_pp0_iter2_tmp_15_reg_246 = ap_const_lv3_0) else "0";
tmp_21_fu_168_p2 <= std_logic_vector(unsigned(p_shl_fu_164_p1) - unsigned(p_cast_fu_152_p1));
tmp_22_fu_174_p2 <= std_logic_vector(unsigned(p_cast1_fu_148_p1) + unsigned(tmp_21_fu_168_p2));
tmp_fu_156_p3 <= (empty_10 & ap_const_lv3_0);
end behav;
| mit | c34e5b80df0b5fd20b11cf0f2213b58d | 0.591931 | 2.796291 | false | false | false | false |
davidhorrocks/1541UltimateII | fpga/6502/vhdl_source/proc_control.vhd | 2 | 17,181 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
entity proc_control is
port (
clock : in std_logic;
clock_en : in std_logic;
ready : in std_logic;
reset : in std_logic;
interrupt : in std_logic;
vect_sel : in std_logic_vector(2 downto 1);
i_reg : in std_logic_vector(7 downto 0);
index_carry : in std_logic;
pc_carry : in std_logic;
branch_taken : in boolean;
sync : out std_logic;
dummy_cycle : out std_logic;
latch_dreg : out std_logic;
copy_d2p : out std_logic;
reg_update : out std_logic;
rwn : out std_logic;
vect_addr : out std_logic_vector(3 downto 0);
irq_done : out std_logic;
vectoring : out std_logic;
a16 : out std_logic;
a_mux : out t_amux := c_amux_pc;
dout_mux : out t_dout_mux;
pc_oper : out t_pc_oper;
s_oper : out t_sp_oper;
adl_oper : out t_adl_oper;
adh_oper : out t_adh_oper );
end proc_control;
architecture gideon of proc_control is
type t_state is (fetch, decode, absolute, abs_hi, abs_fix, branch, branch_fix,
indir1, indir2, jump_sub, jump, retrn, rmw1, rmw2, vector, startup,
zp, zp_idx, zp_indir, push1, push2, push3, pull1, pull2, pull3, pre_irq );
signal state : t_state;
signal next_state : t_state;
signal rwn_i : std_logic;
signal next_cp_p : std_logic;
signal next_rwn : std_logic;
signal next_dreg : std_logic;
signal next_amux : t_amux;
signal next_dout : t_dout_mux;
signal next_dummy : std_logic;
signal vectoring_i : std_logic;
signal vect_bit_i : std_logic;
signal vect_reg : std_logic_vector(2 downto 1);
signal sync_i : std_logic;
signal interrupt_d : std_logic := '0';
signal interrupt_dd : std_logic := '0';
signal trigger_upd : boolean;
signal ready_d : std_logic := '1';
begin
-- combinatroial process
process(state, i_reg, index_carry, pc_carry, branch_taken, interrupt, vectoring_i, interrupt_d)
variable v_stack_idx : std_logic_vector(1 downto 0);
procedure check_irq is
begin
if interrupt='1' then
pc_oper <= keep;
next_state <= pre_irq;
else
pc_oper <= increment;
next_state <= decode;
sync_i <= '1';
end if;
end procedure;
begin
-- defaults
sync_i <= '0';
pc_oper <= increment;
next_amux <= c_amux_pc;
next_rwn <= '1';
next_state <= state;
adl_oper <= keep;
adh_oper <= keep;
s_oper <= keep;
next_dreg <= '1';
next_cp_p <= '0';
next_dout <= reg_d;
next_dummy <= '0';
v_stack_idx := stack_idx(i_reg);
case state is
when fetch =>
check_irq;
when pre_irq =>
pc_oper <= keep;
next_rwn <= '0';
next_dout <= reg_pch;
next_state <= push1;
next_amux <= c_amux_stack;
when decode =>
adl_oper <= load_bus;
adh_oper <= clear;
if is_absolute(i_reg) then
if is_abs_jump(i_reg) then
next_state <= jump;
else
next_state <= absolute;
end if;
elsif is_implied(i_reg) then
pc_oper <= keep;
if is_stack(i_reg) then -- PHP, PLP, PHA, PLA
next_amux <= c_amux_stack;
case v_stack_idx is
when "00" => -- PHP
next_state <= push3;
next_rwn <= '0';
next_dout <= reg_flags;
when "10" => -- PHA
next_state <= push3;
next_rwn <= '0';
next_dout <= reg_accu;
when others =>
next_state <= pull1;
end case;
else
next_state <= fetch;
end if;
elsif is_zeropage(i_reg) then
next_amux <= c_amux_addr;
if is_indirect(i_reg) then
if is_postindexed(i_reg) then
next_state <= zp_indir;
else
next_state <= zp;
next_dummy <= '1';
end if;
else
next_state <= zp;
if is_store(i_reg) and not is_postindexed(i_reg) then
next_rwn <= '0';
next_dout <= reg_axy;
end if;
end if;
elsif is_relative(i_reg) then
next_state <= branch;
elsif is_stack(i_reg) then -- non-implied stack operations like BRK, JSR, RTI and RTS
next_amux <= c_amux_stack;
case v_stack_idx is
when c_stack_idx_brk =>
next_rwn <= '0';
next_dout <= reg_pch;
next_state <= push1;
when c_stack_idx_jsr =>
next_dreg <= '0';
next_dout <= reg_pch;
next_state <= jump_sub;
when c_stack_idx_rti =>
next_state <= pull1;
when c_stack_idx_rts =>
next_state <= pull2;
when others =>
null;
end case;
elsif is_immediate(i_reg) then
next_state <= fetch;
end if;
when absolute =>
next_state <= abs_hi;
next_amux <= c_amux_addr;
adh_oper <= load_bus;
if is_postindexed(i_reg) then
adl_oper <= add_idx;
elsif not is_zeropage(i_reg) then
if is_store(i_reg) then
next_rwn <='0';
next_dout <= reg_axy;
end if;
end if;
if is_zeropage(i_reg) then
pc_oper <= keep;
else
pc_oper <= increment;
end if;
when abs_hi =>
pc_oper <= keep;
if is_postindexed(i_reg) then
if is_load(i_reg) and index_carry='0' then
next_amux <= c_amux_pc;
next_state <= fetch;
else
next_amux <= c_amux_addr;
next_state <= abs_fix;
if index_carry='1' then
adh_oper <= increment;
end if;
end if;
if is_store(i_reg) then
next_rwn <= '0';
next_dout <= reg_axy;
end if;
else -- not post-indexed
if is_jump(i_reg) then
next_amux <= c_amux_addr;
next_state <= jump;
adl_oper <= increment;
elsif is_rmw(i_reg) then
next_rwn <= '0';
next_dout <= reg_d;
next_dummy <= '1';
next_state <= rmw1;
next_amux <= c_amux_addr;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
end if;
when abs_fix =>
pc_oper <= keep;
if is_rmw(i_reg) then
next_state <= rmw1;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dout <= reg_d;
next_dummy <= '1';
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when branch =>
next_amux <= c_amux_pc;
if branch_taken then
pc_oper <= from_alu; -- add offset
next_state <= branch_fix;
else
check_irq; -- correct
end if;
when branch_fix =>
next_amux <= c_amux_pc;
if pc_carry='1' then
next_state <= fetch;
pc_oper <= keep; -- this will fix the PCH, since the carry is set
else
if interrupt_d='1' then
check_irq;
else
pc_oper <= increment;
next_state <= decode;
sync_i <= '1';
end if;
end if;
when indir1 =>
pc_oper <= keep;
next_state <= indir2;
next_amux <= c_amux_addr;
adl_oper <= copy_dreg;
adh_oper <= load_bus;
if is_store(i_reg) then
next_rwn <= '0';
next_dout <= reg_axy;
end if;
when indir2 =>
pc_oper <= keep;
if is_rmw(i_reg) then
next_dummy <= '1';
next_rwn <= '0';
next_dout <= reg_d;
next_state <= rmw1;
next_amux <= c_amux_addr;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when jump_sub =>
next_state <= push1;
pc_oper <= keep;
next_dout <= reg_pch;
next_rwn <= '0';
next_dreg <= '0';
next_amux <= c_amux_stack;
when jump =>
pc_oper <= copy;
next_amux <= c_amux_pc;
if is_stack(i_reg) and v_stack_idx=c_stack_idx_rts and vectoring_i='0' then
next_state <= retrn;
else
next_state <= fetch;
end if;
when retrn =>
pc_oper <= increment;
next_state <= fetch;
when pull1 =>
s_oper <= increment;
next_state <= pull2;
next_amux <= c_amux_stack;
pc_oper <= keep;
when pull2 =>
pc_oper <= keep;
if is_implied(i_reg) then
next_state <= fetch;
next_amux <= c_amux_pc;
next_cp_p <= not v_stack_idx(1); -- only for PLP
else -- it was a stack operation, but not implied (RTS/RTI)
s_oper <= increment;
next_state <= pull3;
next_amux <= c_amux_stack;
next_cp_p <= not v_stack_idx(0); -- only for RTI
end if;
when pull3 =>
pc_oper <= keep;
s_oper <= increment;
next_state <= jump;
next_amux <= c_amux_stack;
when push1 =>
pc_oper <= keep;
s_oper <= decrement;
next_state <= push2;
next_amux <= c_amux_stack;
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_pcl;
when push2 =>
pc_oper <= keep;
s_oper <= decrement;
if (v_stack_idx=c_stack_idx_jsr) and vectoring_i='0' then
next_state <= jump;
next_amux <= c_amux_pc;
else
next_state <= push3;
next_rwn <= '0';
next_dout <= reg_flags;
next_amux <= c_amux_stack;
end if;
when push3 =>
pc_oper <= keep;
s_oper <= decrement;
if is_implied(i_reg) and vectoring_i='0' then -- PHP, PHA
next_amux <= c_amux_pc;
next_state <= fetch;
else
next_state <= vector;
next_amux <= c_amux_vector;
end if;
when rmw1 =>
pc_oper <= keep;
next_state <= rmw2;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dout <= shift_res;
when rmw2 =>
pc_oper <= keep;
next_state <= fetch;
next_amux <= c_amux_pc;
when vector =>
next_state <= jump;
pc_oper <= keep;
next_amux <= c_amux_vector;
when startup =>
next_state <= vector;
pc_oper <= keep;
next_amux <= c_amux_vector;
when zp =>
pc_oper <= keep;
if is_postindexed(i_reg) or is_indirect(i_reg) then
adl_oper <= add_idx;
next_state <= zp_idx;
next_amux <= c_amux_addr;
if is_postindexed(i_reg) and is_store(i_reg) then
next_rwn <= '0';
next_dout <= reg_axy;
end if;
elsif is_rmw(i_reg) then
next_dummy <= '1';
next_state <= rmw1;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dout <= reg_d;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when zp_idx =>
pc_oper <= keep;
if is_indirect(i_reg) then
next_state <= indir1;
adl_oper <= increment;
next_amux <= c_amux_addr;
elsif is_rmw(i_reg) then
next_state <= rmw1;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dout <= reg_d;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when zp_indir =>
pc_oper <= keep;
next_state <= absolute;
next_amux <= c_amux_addr;
adl_oper <= increment;
when others =>
null;
end case;
end process;
reg_update <= '1' when (state = fetch) and vectoring_i='0' and trigger_upd else '0';
irq_done <= '1' when state = vector else '0';
vect_bit_i <= '0' when state = vector else '1';
vect_addr <= '1' & vect_reg & vect_bit_i;
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
ready_d <= ready;
if ready='1' or rwn_i='0' then
state <= next_state;
a_mux <= next_amux;
dout_mux <= next_dout;
rwn_i <= next_rwn;
latch_dreg <= next_dreg and next_rwn; -- disable dreg latch for writes
copy_d2p <= next_cp_p;
dummy_cycle <= next_dummy;
interrupt_d <= interrupt;-- and ready_d;
interrupt_dd <= interrupt_d;
trigger_upd <= affect_registers(i_reg);
if next_amux = c_amux_vector or next_amux = c_amux_pc then
a16 <= '1';
else
a16 <= '0';
end if;
if sync_i='1' then
vectoring_i <= '0';
elsif state = pre_irq then
vectoring_i <= '1';
vect_reg <= vect_sel;
end if;
end if;
end if;
if reset='1' then
a16 <= '1';
state <= startup; --vector;
vect_reg <= vect_sel;
a_mux <= c_amux_vector;
rwn_i <= '1';
latch_dreg <= '1';
dout_mux <= reg_d;
copy_d2p <= '0';
vectoring_i <= '0';
dummy_cycle <= '0';
end if;
end if;
end process;
vectoring <= vectoring_i;
sync <= sync_i;
rwn <= rwn_i;
end gideon;
| gpl-3.0 | 8f34fafa552b585a901f629d3842ac36 | 0.380304 | 4.200733 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-terasic-de0-nano/testbench.vhd | 1 | 6,521 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
romdepth : integer := 22 -- rom address depth (flash 4 MB)
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec";
constant sdramfile : string := "ram.srec";
signal clock_50 : std_logic := '0';
signal led : std_logic_vector(7 downto 0);
signal key : std_logic_vector(1 downto 0);
signal sw : std_logic_vector(3 downto 0);
signal dram_ba : std_logic_vector(1 downto 0);
signal dram_dqm : std_logic_vector(1 downto 0);
signal dram_ras_n : std_ulogic;
signal dram_cas_n : std_ulogic;
signal dram_cke : std_ulogic;
signal dram_clk : std_ulogic;
signal dram_we_n : std_ulogic;
signal dram_cs_n : std_ulogic;
signal dram_dq : std_logic_vector(15 downto 0);
signal dram_addr : std_logic_vector(12 downto 0);
signal epcs_data0 : std_logic;
signal epcs_dclk : std_logic;
signal epcs_ncso : std_logic;
signal epcs_asdo : std_logic;
signal i2c_sclk : std_logic;
signal i2c_sdat : std_logic;
signal g_sensor_cs_n : std_ulogic;
signal g_sensor_int : std_ulogic;
signal adc_cs_n : std_ulogic;
signal adc_saddr : std_ulogic;
signal adc_sclk : std_ulogic;
signal adc_sdat : std_ulogic;
signal gpio_2 : std_logic_vector(12 downto 0);
signal gpio_2_in : std_logic_vector(2 downto 0);
signal gpio_1_in : std_logic_vector(1 downto 0);
signal gpio_1 : std_logic_vector(33 downto 0);
signal gpio_0_in : std_logic_vector(1 downto 0);
signal gpio_0 : std_logic_vector(33 downto 0);
begin
clock_50 <= not clock_50 after 10 ns; --50 MHz clk
key(0) <= '0', '1' after 300 ns;
key(1) <= '1'; -- DSU break, disabled
sw <= (others => 'H');
gpio_0 <= (others => 'H');
gpio_0_in <= (others => 'H');
gpio_1 <= (others => 'H');
gpio_1_in <= (others => 'H');
gpio_2 <= (others => 'H');
gpio_2_in <= (others => 'H');
led(5 downto 0) <= (others => 'H');
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (
clock_50 => clock_50,
led => led,
key => key,
sw => sw,
dram_ba => dram_ba,
dram_dqm => dram_dqm,
dram_ras_n => dram_ras_n,
dram_cas_n => dram_cas_n,
dram_cke => dram_cke,
dram_clk => dram_clk,
dram_we_n => dram_we_n,
dram_cs_n => dram_cs_n,
dram_dq => dram_dq,
dram_addr => dram_addr,
epcs_data0 => epcs_data0,
epcs_dclk => epcs_dclk,
epcs_ncso => epcs_ncso,
epcs_asdo => epcs_asdo,
i2c_sclk => i2c_sclk,
i2c_sdat => i2c_sdat,
g_sensor_cs_n => g_sensor_cs_n,
g_sensor_int => g_sensor_int,
adc_cs_n => adc_cs_n,
adc_saddr => adc_saddr,
adc_sclk => adc_sclk,
adc_sdat => adc_sdat,
gpio_2 => gpio_2,
gpio_2_in => gpio_2_in,
gpio_1_in => gpio_1_in,
gpio_1 => gpio_1,
gpio_0_in => gpio_0_in,
gpio_0 => gpio_0);
sd1 : if (CFG_SDCTRL /= 0) generate
u1: entity work.mt48lc16m16a2 generic map (addr_bits => 13, col_bits => 8, index => 1024, fname => sdramfile)
PORT MAP(
Dq => dram_dq, Addr => dram_addr, Ba => dram_ba, Clk => dram_clk,
Cke => dram_cke, Cs_n => dram_cs_n, Ras_n => dram_ras_n,
Cas_n => dram_cas_n, We_n => dram_we_n, Dqm => dram_dqm);
end generate;
dram_dq <= buskeep(dram_dq) after 5 ns;
spif : if CFG_SPIMCTRL /= 0 generate
spi0: spi_flash
generic map (
ftype => 4,
debug => 0,
fname => promfile,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => CFG_SPIMCTRL_OFFSET)
port map (
sck => epcs_dclk,
di => epcs_asdo,
do => epcs_data0,
csn => epcs_ncso,
sd_cmd_timeout => open,
sd_data_timeout => open);
end generate;
iuerr : process
begin
wait for 2500 ns;
if to_x01(led(6)) = '1' then wait on led(6); end if;
assert (to_x01(led(6)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-2.0 | a7b85ff0b0ea3ccd5b29cd272df7c4f4 | 0.538721 | 3.532503 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/syn/vhdl/convolve_kernel_adEe.vhd | 3 | 7,926 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity convolve_kernel_adEe_AddSubnS_0 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
s: out std_logic_vector(63 downto 0));
end entity;
architecture behav of convolve_kernel_adEe_AddSubnS_0 is
component convolve_kernel_adEe_AddSubnS_0_fadder is
port (
faa : IN STD_LOGIC_VECTOR (22-1 downto 0);
fab : IN STD_LOGIC_VECTOR (22-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (22-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component convolve_kernel_adEe_AddSubnS_0_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (20-1 downto 0);
fab : IN STD_LOGIC_VECTOR (20-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (20-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(63 downto 0);
signal b_reg : std_logic_vector(63 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(21 downto 0);
signal b0_cb : std_logic_vector(21 downto 0);
signal a1_cb : std_logic_vector(43 downto 22);
signal b1_cb : std_logic_vector(43 downto 22);
signal a2_cb : std_logic_vector(63 downto 44);
signal b2_cb : std_logic_vector(63 downto 44);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(21 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(19 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
-- wires for each full adder sum
signal fas : std_logic_vector(63 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo1 is array (1 downto 0) of std_logic_vector(21 downto 0);
signal s0_ca_rego0 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(21 downto 0);
signal s1_ca_rego1 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(63 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= std_logic_vector(resize(unsigned(a), 64));
b_reg <= std_logic_vector(resize(unsigned(b), 64));
-- small adder input assigments
a0_cb <= a_reg(21 downto 0);
b0_cb <= b_reg(21 downto 0);
a1_cb <= a_reg(43 downto 22);
b1_cb <= b_reg(43 downto 22);
a2_cb <= a_reg(63 downto 44);
b2_cb <= b_reg(63 downto 44);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
end if;
end if;
end process;
-- small adder generation
u0 : convolve_kernel_adEe_AddSubnS_0_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(21 downto 0),
facout => faccout0_co0);
u1 : convolve_kernel_adEe_AddSubnS_0_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(43 downto 22),
facout => faccout1_co1);
u2 : convolve_kernel_adEe_AddSubnS_0_fadder_f
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(63 downto 44),
facout => faccout2_co2);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(21 downto 0);
s1_ca_rego1 (0) <= fas(43 downto 22);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(21 downto 0) <= s0_ca_rego0(1);
s_tmp(43 downto 22) <= s1_ca_rego1(0);
s_tmp(63 downto 44) <= fas(63 downto 44);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel_adEe_AddSubnS_0_fadder is
generic(N : natural :=22);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of convolve_kernel_adEe_AddSubnS_0_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel_adEe_AddSubnS_0_fadder_f is
generic(N : natural :=20);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of convolve_kernel_adEe_AddSubnS_0_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity convolve_kernel_adEe is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of convolve_kernel_adEe is
component convolve_kernel_adEe_AddSubnS_0 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
convolve_kernel_adEe_AddSubnS_0_U : component convolve_kernel_adEe_AddSubnS_0
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
| mit | 96f34f1272412e4205c3648ebb347797 | 0.609765 | 3.060232 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-arrow-bemicro-sdk/testbench.vhd | 1 | 7,265 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- LEON3 BeMicro SDK design testbench
-- Copyright (C) 2011 - 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
signal cpu_rst_n : std_ulogic := '0';
signal clk_fpga_50m : std_ulogic := '0';
-- DDR SDRAM
signal ram_a : std_logic_vector (13 downto 0); -- ddr address
signal ram_ck_p : std_logic;
signal ram_ck_n : std_logic;
signal ram_cke : std_logic;
signal ram_cs_n : std_logic;
signal ram_ws_n : std_ulogic; -- ddr write enable
signal ram_ras_n : std_ulogic; -- ddr ras
signal ram_cas_n : std_ulogic; -- ddr cas
signal ram_dm : std_logic_vector(1 downto 0); -- ram_udm & ram_ldm
signal ram_dqs : std_logic_vector (1 downto 0); -- ram_udqs & ram_lqds
signal ram_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ram_d : std_logic_vector (15 downto 0); -- ddr data
-- Ethernet PHY
signal txd : std_logic_vector(3 downto 0);
signal rxd : std_logic_vector(3 downto 0);
signal tx_clk : std_logic;
signal rx_clk : std_logic;
signal tx_en : std_logic;
signal rx_dv : std_logic;
signal eth_crs : std_logic;
signal rx_er : std_logic;
signal eth_col : std_logic;
signal mdio : std_logic;
signal mdc : std_logic;
signal eth_reset_n : std_logic;
-- Temperature sensor
signal temp_sc : std_logic;
signal temp_cs_n : std_logic;
signal temp_sio : std_logic;
-- LEDs
signal f_led : std_logic_vector(7 downto 0);
-- User push-button
signal pbsw_n : std_logic;
-- Reconfig SW1 and SW2
signal reconfig_sw : std_logic_vector(2 downto 1);
-- SD card interface
signal sd_dat0 : std_logic;
signal sd_dat1 : std_logic;
signal sd_dat2 : std_logic;
signal sd_dat3 : std_logic;
signal sd_cmd : std_logic;
signal sd_clk : std_logic;
-- Ethernet PHY sim model
signal phy_tx_er : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal txdt : std_logic_vector(7 downto 0) := (others => '0');
signal rxdt : std_logic_vector(7 downto 0) := (others => '0');
-- EPCS
signal epcs_data : std_ulogic;
signal epcs_dclk : std_ulogic;
signal epcs_csn : std_logic;
signal epcs_asdi : std_logic;
begin
-- clock and reset
clk_fpga_50m <= not clk_fpga_50m after ct * 1 ns;
cpu_rst_n <= '0', '1' after 200 ns;
-- Push button, connected to DSU break, kept high
pbsw_n <= 'H';
reconfig_sw <= (others => 'H');
-- LEON3 SoC
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, ncpu, disas, dbguart, pclow)
port map (
cpu_rst_n, clk_fpga_50m,
-- DDR SDRAM
ram_a, ram_ck_p, ram_ck_n, ram_cke, ram_cs_n, ram_ws_n,
ram_ras_n, ram_cas_n, ram_dm, ram_dqs, ram_ba, ram_d,
-- Ethernet PHY
txd, rxd, tx_clk, rx_clk, tx_en, rx_dv, eth_crs, rx_er,
eth_col, mdio, mdc, eth_reset_n,
-- Temperature sensor
temp_sc, temp_cs_n, temp_sio,
-- LEDs
f_led,
-- User push-button
pbsw_n,
-- Reconfig SW1 and SW2
reconfig_sw,
-- SD card interface
sd_dat0, sd_dat1, sd_dat2, sd_dat3, sd_cmd, sd_clk,
-- EPCS
epcs_data, epcs_dclk, epcs_csn, epcs_asdi
);
-- SD card signals
spiflashmod0 : spi_flash
generic map (ftype => 3, debug => 0, dummybyte => 0)
port map (sck => sd_clk, di => sd_cmd, do => sd_dat0, csn => sd_dat3);
sd_dat0 <= 'Z'; sd_cmd <= 'Z';
-- EPCS
spi0: spi_flash
generic map (
ftype => 4, debug => 0, fname => promfile, readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE, dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => CFG_SPIMCTRL_OFFSET)
port map (sck => epcs_dclk, di => epcs_asdi, do => epcs_data,
csn => epcs_csn, sd_cmd_timeout => open,
sd_data_timeout => open);
-- On the BeMicro the temp_* signals are connected to a temperature sensor
temp_sc <= 'H'; temp_sio <= 'H';
-- DDR memory
ddr0 : ddrram
generic map(width => 16, abits => 14, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ram_ck_p, cke => ram_cke, csn => ram_cs_n,
rasn => ram_ras_n, casn => ram_cas_n, wen => ram_ws_n,
dm => ram_dm, ba => ram_ba, a => ram_a, dq => ram_d,
dqs => ram_dqs);
-- Ethernet PHY
mdio <= 'H'; phy_tx_er <= '0'; phy_gtx_clk <= '0';
txdt(3 downto 0) <= txd; rxd <= rxdt(3 downto 0);
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(eth_reset_n, mdio, tx_clk, rx_clk, rxdt, rx_dv,
rx_er, eth_col, eth_crs, txdt, tx_en, phy_tx_er, mdc,
phy_gtx_clk);
-- LEDs
f_led <= (others => 'H');
-- Processor error mode indicator is connected to led(6).
iuerr : process
begin
wait for 2500 ns;
if to_x01(f_led(6)) = '1' then wait on f_led(6); end if;
assert (to_x01(f_led(6)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-2.0 | 63b865c0ce72df651e8984667a9cf18c | 0.572058 | 3.420433 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/ip_repo/xilinx_com_hls_nco_1_0/hdl/vhdl/nco_AXILiteS_s_axi.vhd | 2 | 9,041 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity nco_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
-- user signals
sine_sample_V :in STD_LOGIC_VECTOR(15 downto 0);
sine_sample_V_ap_vld :in STD_LOGIC;
step_size_V :out STD_LOGIC_VECTOR(15 downto 0));
end entity nco_AXILiteS_s_axi;
--------------------------Address Info-------------------
-- 0x00 : reserved
-- 0x04 : reserved
-- 0x08 : reserved
-- 0x0c : reserved
-- 0x10 : Data signal of sine_sample_V
-- bit 15~0 - sine_sample_V[15:0] (Read)
-- others - reserved
-- 0x14 : Control signal of sine_sample_V
-- bit 0 - sine_sample_V_ap_vld (Read/COR)
-- others - reserved
-- 0x18 : Data signal of step_size_V
-- bit 15~0 - step_size_V[15:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of nco_AXILiteS_s_axi is
constant ADDR_BITS : INTEGER := 5;
constant ADDR_SINE_SAMPLE_V_DATA_0 : INTEGER :=16#10#;
constant ADDR_SINE_SAMPLE_V_CTRL : INTEGER :=16#14#;
constant ADDR_STEP_SIZE_V_DATA_0 : INTEGER :=16#18#;
constant ADDR_STEP_SIZE_V_CTRL : INTEGER :=16#1c#;
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write FSM states
signal wstate, wnext, rstate, rnext: states;
-- Local signal
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_sine_sample_V : UNSIGNED(15 downto 0);
signal int_sine_sample_V_ap_vld : STD_LOGIC;
signal int_step_size_V : UNSIGNED(15 downto 0);
begin
-- axi write
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- axi read
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_SINE_SAMPLE_V_DATA_0 =>
rdata_data <= RESIZE(int_sine_sample_V(15 downto 0), 32);
when ADDR_SINE_SAMPLE_V_CTRL =>
rdata_data <= (0 => int_sine_sample_V_ap_vld, others => '0');
when ADDR_STEP_SIZE_V_DATA_0 =>
rdata_data <= RESIZE(int_step_size_V(15 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- internal registers
step_size_V <= STD_LOGIC_VECTOR(int_step_size_V);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_sine_sample_V <= (others => '0');
elsif (ACLK_EN = '1') then
if (sine_sample_V_ap_vld = '1') then
int_sine_sample_V <= UNSIGNED(sine_sample_V); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_sine_sample_V_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (sine_sample_V_ap_vld = '1') then
int_sine_sample_V_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_SINE_SAMPLE_V_CTRL) then
int_sine_sample_V_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_STEP_SIZE_V_DATA_0) then
int_step_size_V(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_step_size_V(15 downto 0));
end if;
end if;
end if;
end process;
end architecture behave;
| mit | 1ca01560d39668000cdd7c7f3f715308 | 0.465767 | 3.860376 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/RecComp_cnn_lab_convolve_kernel_1_0/hdl/vhdl/convolve_kernel_fcud.vhd | 1 | 3,595 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fcud is
generic (
ID : integer := 40;
NUM_STAGE : integer := 8;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fcud is
--------------------- Component ---------------------
component convolve_kernel_ap_fmul_6_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
signal ce_r : std_logic;
signal dout_i : std_logic_vector(dout_WIDTH-1 downto 0);
signal dout_r : std_logic_vector(dout_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fmul_6_max_dsp_32_u : component convolve_kernel_ap_fmul_6_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce_r;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout_i <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
ce_r <= ce;
end if;
end process;
process (clk) begin
if clk'event and clk = '1' then
if ce_r = '1' then
dout_r <= dout_i;
end if;
end if;
end process;
dout <= dout_i when ce_r = '1' else dout_r;
end architecture;
| mit | 94988681d3ab4de1a4e977bede80cfb1 | 0.484006 | 3.609438 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/387128e4034068b3/zqynq_lab_1_design_processing_system7_0_0_sim_netlist.vhdl | 1 | 197,367 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:08:04 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_processing_system7_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "zqynq_lab_1_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "zqynq_lab_1_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | b8897fc372f8d497f911dbb7fa138658 | 0.634468 | 2.756253 | false | false | false | false |
freecores/mdct | source/testbench/random1.vhd | 1 | 30,770 | -- Random number generators (RNG)
-- Author: Gnanasekaran Swaminathan
-- Random number generator algorithm is due to D. E. Knuth as
-- given in W. H. Press et al., "Numerical Recipes in C: The Art
-- of Scientific Computing," New York: Cambridge Univ. Press, 1988.
-- Translated into VHDL by Gnanasekaran Swaminathan <[email protected]>
-- Other algorithms are from libg++ by Dirk Grunwald <[email protected]>
-- Translated into VHDL by Gnanasekaran Swaminathan <[email protected]>
-- math functions factorial, "**", exp, ln, and sqrt are from
-- math_functions package due to Tom Ashworth <[email protected]>
-- USAGE:
-- Following 10 random variables are supported:
-- Uniform, Negative Exponential, Poisson, Normal, Log Normal,
-- Erlang, Geometric, Hyper Geometric, Binomial, Weibull.
--
-- Each random variable has its own copy of random number generator.
-- Hence, you can have as many random variables of any type as you
-- want only limited by the amount of memory your system has.
--
-- First a random variable must be initialized using the corresponding
-- Init function. Thenceforth, the new value of the random variable can
-- can be obtained by a call to GenRnd.
--
-- EXAMPLES:
-- Uniform random number in [-50, 100] with seed 7
-- process
-- variable unf: Uniform := InitUniform(7, -50.0, 100.0);
-- variable rnd: real := 0;
-- begin
-- GenRnd(unf);
-- rnd := unf.rnd; -- -50 <= rnd <= 100
-- end;
--
-- Negative exponential distribution with mean 25 and seed 13
-- variable nexp: NegExp := InitNegExp(13, 25.0);
-- GenRnd(nexp)
-- rnd := nexp.rnd; -- 0 <= rnd <= real'High
--
--
-- Please send bug reports and additions and subtractions
-- to me at [email protected]
--
-- Enjoy!
-- Gnanasekaran Swaminathan
package RNG is
subtype rn is Real range 0.0 to 1.0;
subtype PositiveReal is Real range 0.0 to Real'High;
type IntA0to98 is array (0 to 98) of Integer;
type distribution is ( UniformDist,
NegExpDist,
PoissonDist,
BinomialDist,
GeomDist,
HypGeomDist,
NormalDist,
LogNormalDist,
ErlangDist,
WeibullDist
);
type realParams is array (0 to 10) of Real;
subtype intParams is Integer;
subtype booleanParams is Boolean;
type RndNum is
record
rnd : rn;
init : Integer;
iy : Integer;
ir : IntA0to98;
status : Boolean;
end record;
type random is record
rnd: Real;
r: RndNum;
a: realParams;
b: intParams;
c: booleanParams;
dist: distribution;
end record;
type Uniform is
record
rnd : Real;
pHigh : Real;
pLow : Real;
delta : Real;
r : RndNum;
end record;
type NegExp is
record
rnd : Real;
pMean : PositiveReal;
r : RndNum;
end record;
type Poisson is
record
rnd : Real;
pMean : PositiveReal;
r : RndNum;
end record;
type Normal is
record
rnd : Real;
pMean : Real;
pStdDev : Real;
pVariance : Real;
CachedNormal : Real;
haveCachedNormal: Boolean;
r : RndNum;
end record;
type LogNormal is
record
rnd : Real;
pLogMean : Real;
pLogVariance : Real;
n : Normal;
end record;
type Erlang is
record
rnd : Real;
pMean : Real;
pVariance : Real;
a : Real;
k : Integer;
r : RndNum;
end record;
type Binomial is
record
rnd : Real;
pU : Real;
pN : Integer;
r : RndNum;
end record;
type Geom is
record
rnd : Real;
pMean : Real;
r : RndNum;
end record;
type HypGeom is
record
rnd : Real;
pMean : Real;
pVariance : Real;
pP : Real;
r : RndNum;
end record;
type Weibull is
record
rnd : Real;
pAlpha : Real;
pInvAlpha : Real;
pBeta : Real;
r : RndNum;
end record;
constant LN2: real := 0.693147181;
function factorial (n: integer) return real;
function "**"(z: Real; y: Real) return Real;
function ln (z: Real) return Real;
function ln1p(z: Real) return Real;
function exp (z: Real) return Real;
function sqrt(z: Real) return Real;
procedure GenRnd(r: inout RndNum; seed: in Integer := 13);
procedure GenRnd(r: inout Uniform);
procedure GenRnd(r: inout NegExp);
procedure GenRnd(r: inout Poisson);
procedure GenRnd(r: inout Normal);
procedure GenRnd(r: inout LogNormal);
procedure GenRnd(r: inout Erlang);
procedure GenRnd(r: inout Binomial);
procedure GenRnd(r: inout Geom);
procedure GenRnd(r: inout HypGeom);
procedure GenRnd(r: inout Weibull);
procedure GenRnd(r: inout random);
-- Initialization functions
function InitRndNum (seed: in Integer := 13) return RndNum;
function InitUniform (seed: Integer := 13;
low: Real := 0.0;
high: Real := 100.0) return Uniform;
function InitNegExp (seed: Integer := 13;
mean: PositiveReal := 50.0) return NegExp;
function InitPoisson (seed: Integer := 13;
mean: PositiveReal := 50.0) return Poisson;
function InitNormal (seed: Integer := 13;
mean: Real := 0.0;
var: Real := 100.0) return Normal;
function InitLogNormal (seed: Integer := 13;
mean: Real := 50.0;
var: Real := 100.0) return LogNormal;
function InitErlang (seed: Integer := 13;
mean: Real := 50.0;
var: Real := 100.0) return Erlang;
function InitBinomial (seed: Integer := 13;
n: Integer := 0;
u: Real := 0.0) return Binomial;
function InitGeom (seed: Integer := 13;
mean: Real := 0.0) return Geom;
function InitHypGeom (seed: Integer := 13;
mean: Real := 0.0;
var: Real := 0.0) return HypGeom;
function InitWeibull (seed: Integer := 13;
alpha: Real := 0.0;
beta: Real := 0.0) return Weibull;
function InitUniform (low: Real := 0.0;
high: Real := 100.0;
seed: Integer := 13) return random;
function InitNegExp (mean: PositiveReal := 50.0;
seed: Integer := 13) return random;
function InitPoisson (mean: PositiveReal := 50.0;
seed: Integer := 13) return random;
function InitNormal (mean: Real := 0.0;
var: Real := 100.0;
seed: Integer := 13) return random;
function InitLogNormal (mean: Real := 50.0;
var: Real := 100.0;
seed: Integer := 13) return random;
function InitErlang (mean: Real := 50.0;
var: Real := 100.0;
seed: Integer := 13) return random;
function InitBinomial (n: Integer := 0;
u: Real := 0.0;
seed: Integer := 13) return random;
function InitGeom (mean: Real := 0.0;
seed: Integer := 13) return random;
function InitHypGeom (mean: Real := 0.0;
var: Real := 0.0;
seed: Integer := 13) return random;
function InitWeibull (alpha: Real := 0.0;
beta: Real := 0.0;
seed: Integer := 13) return random;
-- conversion functions
function CvtRandom (uni: in Uniform) return random;
function CvtRandom (nex: in NegExp) return random;
function CvtRandom (poi: in Poisson) return random;
function CvtRandom (nom: in Normal) return random;
function CvtRandom (lnom: in LogNormal) return random;
function CvtRandom (erl: in Erlang) return random;
function CvtRandom (bin: in Binomial) return random;
function CvtRandom (geo: in Geom) return random;
function CvtRandom (hypg: in HypGeom) return random;
function CvtRandom (wei: in Weibull) return random;
function CvtUniform (r: in random) return Uniform;
function CvtNegExp (r: in random) return NegExp;
function CvtPoisson (r: in random) return Poisson;
function CvtNormal (r: in random) return Normal;
function CvtLogNormal (r: in random) return LogNormal;
function CvtErlang (r: in random) return Erlang;
function CvtBinomial (r: in random) return Binomial;
function CvtGeom (r: in random) return Geom;
function CvtHypGeom (r: in random) return HypGeom;
function CvtWeibull (r: in random) return Weibull;
end RNG;
package body RNG is
-------------------------------------------------------------------------------
function factorial(n : integer) return real is
variable result : Integer;
begin
result := 1;
if (n > 1) then
for i in 2 to n loop
result := result * i;
end loop;
end if;
return Real(result);
end factorial;
-------------------------------------------------------------------------------
function "**" (z: Real; y: Real) return Real is
begin
return exp(y * ln(z));
end;
-------------------------------------------------------------------------------
function ln (z : real) return real is
variable Result : real;
variable tmpx : real;
variable n : integer;
variable acc : integer;
begin
assert not (z <= 0.0)
report "ERROR : Can't take the ln of a negative number"
severity error;
tmpx := z;
n := 0;
--reduce z to a number less than one in order
--to use a more accurate model that converges
--much faster. This will render the log function
--to ln(z) = ln(tmpx) + n * ln(2) where ln(2) is
--defined as a constant.
while (tmpx >= 1.0) loop
tmpx := tmpx / 2.0;
n := n +1;
end loop;
--acc determines the number of iterations of the series
--these values are results from comparisons with the SUN
--log() C function at a accuracy of at least 0.00001.
if (tmpx < 0.5) then
acc := 100;
else
acc := 20;
end if;
tmpx := tmpx - 1.0;
result := real(n) * LN2;
n := 1;
while (n < acc) loop
result := result + (tmpx**n)/real(n) - (tmpx**(n+1))/real(n+1);
n := n +2;
end loop;
return Result;
end ln;
-------------------------------------------------------------------------------
function ln1p(z: Real) return Real is
begin
assert false
report "ln1p is not implemented"
severity error;
return ln(z);
end;
-------------------------------------------------------------------------------
function exp (z : real) return real is
variable result,tmp : real;
variable i : integer;
begin
if (z = 0.0) then
result := 1.0;
else
result := z + 1.0;
i := 2;
tmp := z*z/2.0;
result := result + tmp;
while (abs(tmp) > 0.000005) loop
i := i +1;
tmp := tmp * z / Real(i);
result := result + tmp;
end loop;
end if;
return result;
end exp;
-------------------------------------------------------------------------------
function sqrt(z: Real) return Real is
begin
assert z >= 0.0
report "sqrt (negative number) is undefined"
severity error;
return z ** 0.5;
end;
-------------------------------------------------------------------------------
procedure GenRnd(r: inout RndNum; seed: in Integer := 13) is
constant RN_M : Integer := 714025;
constant RN_IA: Integer := 1366;
constant RN_IC: Integer := 150889;
variable j : Integer := 0;
begin
if (not r.status) then
r.status := True;
r.init := seed;
r.init := abs ( (RN_IC - r.init) mod RN_M );
for i in 0 to 1 loop for j in 1 to 97 loop
r.init := (RN_IA * r.init + RN_IC) mod RN_M;
r.ir(j) := r.init;
end loop; end loop;
r.init := (RN_IA * r.init + RN_IC) mod RN_M;
r.iy := r.init;
r.rnd := REAL(r.iy) / REAL(RN_M);
return;
end if;
j := 1 + 97 * r.iy / RN_M;
assert (1 <= j and j <= 97)
report "this cannon happen in GenRnd(RndNum)"
severity error;
r.iy := r.ir(j);
r.init := (RN_IA * r.init + RN_IC) mod RN_M;
r.ir(j) := r.init;
r.rnd := REAL(r.iy) / REAL(RN_M);
end GenRnd; -- RndNum
-------------------------------------------------------------------------------
procedure GenRnd(r: inout Uniform) is
begin
assert r.r.status
report "Uniform variable is not initialized"
severity error;
GenRnd(r.r);
r.rnd := r.pLow + r.delta * r.r.rnd;
end GenRnd; -- Uniform
-------------------------------------------------------------------------------
procedure GenRnd(r: inout NegExp) is
begin
assert r.r.status
report "NegExp variable is not initialized"
severity error;
GenRnd(r.r);
r.rnd := - r.pMean * ln(1.0 - r.r.rnd);
-- ln1p will be better here
end GenRnd; -- NegExp
-------------------------------------------------------------------------------
procedure GenRnd(r: inout Poisson) is
variable product: Real := 1.0;
variable bound: Real := 0.0;
begin
assert r.r.status
report "Poisson variable is not initialized"
severity error;
bound := exp(-1.0 * r.pMean);
r.rnd := -1.0;
while (product >= bound) loop
r.rnd := r.rnd + 1.0;
GenRnd(r.r);
product := product * r.r.rnd;
end loop;
end GenRnd; -- Poisson
-------------------------------------------------------------------------------
procedure GenRnd(r: inout Normal) is
variable v1: Real := 0.0;
variable v2: Real := 0.0;
variable w : Real := 0.0;
variable x1: Real := 0.0;
variable x2: Real := 0.0;
begin
assert r.r.status
report "Normal variable is not initialized"
severity error;
if (r.haveCachedNormal) then
r.haveCachedNormal := False;
r.rnd := r.cachedNormal * r.pStdDev + r.pMean;
return;
end if;
while (True) loop
GenRnd(r.r); v1 := 2.0 * r.r.rnd - 1.0;
GenRnd(r.r); v2 := 2.0 * r.r.rnd - 1.0;
w := v1 * v1 + v2* v2;
if ( w <= 1.0 ) then
w := sqrt(-2.0 * ln (w) / w);
x1 := v1 * w;
x2 := v2 * w;
r.haveCachedNormal := True;
r.CachedNormal := x2;
r.rnd := x1 * r.pStdDev + r.pMean;
return;
end if;
end loop;
end GenRnd; -- Normal
-------------------------------------------------------------------------------
procedure GenRnd(r: inout LogNormal) is
begin
assert r.n.r.status
report "LogNormal variable is not initialized"
severity error;
GenRnd(r.n);
r.rnd := exp(r.n.rnd);
end GenRnd; -- LogNormal
-------------------------------------------------------------------------------
procedure GenRnd(r: inout Erlang) is
variable prod : Real := 1.0;
begin
assert r.r.status
report "Erlang variable is not initialized"
severity error;
for i in 1 to r.k loop
GenRnd(r.r);
prod := prod * r.r.rnd;
end loop;
r.rnd := - ln( prod ) / r.a;
end GenRnd; -- Erlang
-------------------------------------------------------------------------------
procedure GenRnd(r: inout Binomial) is
begin
assert r.r.status
report "Binomial variable is not initialized"
severity error;
r.rnd := 0.0;
for i in 1 to r.pN loop
GenRnd(r.r);
if (r.r.rnd < r.pU) then
r.rnd := r.rnd + 1.0;
end if;
end loop;
end GenRnd; -- Binomial
-------------------------------------------------------------------------------
procedure GenRnd(r: inout Geom) is
begin
assert r.r.status
report "Geom variable is not initialized"
severity error;
r.rnd := 1.0;
GenRnd(r.r);
while (r.r.rnd < r.pMean) loop
r.rnd := r.rnd + 1.0;
GenRnd(r.r);
end loop;
end GenRnd; -- Geom
-------------------------------------------------------------------------------
procedure GenRnd(r: inout HypGeom) is
variable z: Real := 0.0;
begin
assert r.r.status
report "HypGeom variable is not initialized"
severity error;
GenRnd(r.r);
if (r.r.rnd > r.pP) then
z := 1.0 - r.pP;
else
z := r.pP;
end if;
GenRnd(r.r);
r.rnd := -r.pMean * ln( r.r.rnd )/ (2.0*z);
end GenRnd; -- HypGeom
-------------------------------------------------------------------------------
procedure GenRnd(r: inout Weibull) is
begin
assert r.r.status
report "Weibull variable r is not initialized"
severity error;
GenRnd(r.r);
r.rnd := ( -r.pBeta * ln(1.0 - r.r.rnd) ) ** r.pInvAlpha;
end GenRnd; -- Weibull
-------------------------------------------------------------------------------
function InitRndNum (seed: in Integer := 13) return RndNum is
constant RN_M : Integer := 714025;
constant RN_IA: Integer := 1366;
constant RN_IC: Integer := 150889;
variable j : Integer := 0;
variable r : RndNum;
begin
r.status := True;
r.init := seed;
r.init := abs ( (RN_IC - r.init) mod RN_M );
for i in 0 to 1 loop for j in 1 to 97 loop
r.init := (RN_IA * r.init + RN_IC) mod RN_M;
r.ir(j) := r.init;
end loop; end loop;
r.init := (RN_IA * r.init + RN_IC) mod RN_M;
r.iy := r.init;
return r;
end InitRndNum;
-------------------------------------------------------------------------------
function InitUniform (seed: Integer := 13;
low: Real := 0.0;
high: Real := 100.0) return Uniform is
variable r : Uniform;
begin
r.r.status := False;
if (low < high) then
r.pLow := low;
r.pHigh := high;
else
r.pLow := high;
r.pHigh := low;
end if;
r.delta := high-low;
GenRnd(r.r, seed);
return r;
end InitUniform;
-------------------------------------------------------------------------------
function InitNegExp (seed: Integer := 13;
mean: PositiveReal := 50.0) return NegExp is
variable r : NegExp;
begin
r.r.status := False;
r.pMean := mean;
GenRnd(r.r, seed);
return r;
end InitNegExp;
-------------------------------------------------------------------------------
function InitPoisson (seed: Integer := 13;
mean: PositiveReal := 50.0) return Poisson is
variable r : Poisson;
begin
r.r.status := False;
r.pMean := mean;
GenRnd(r.r, seed);
return r;
end InitPoisson;
-------------------------------------------------------------------------------
function InitNormal (seed: Integer := 13;
mean: Real := 0.0;
var: Real := 100.0) return Normal is
variable r : Normal;
begin
r.r.status := False;
r.haveCachedNormal := False;
r.pMean := mean;
r.pVariance := var;
r.pStdDev := sqrt(r.pVariance);
GenRnd(r.r, seed);
return r;
end InitNormal;
-------------------------------------------------------------------------------
function InitLogNormal (seed: Integer := 13;
mean: Real := 50.0;
var: Real := 100.0) return LogNormal is
variable m2: Real := 0.0;
variable mn: Real := 0.0;
variable sd: Real := 0.0;
variable r : LogNormal;
begin
r.n.r.status := False;
r.pLogMean := mean;
r.pLogVariance := var;
m2 := r.pLogMean * r.pLogMean;
mn := ln( m2 / sqrt(r.pLogVariance + m2) );
sd := sqrt( ln( (r.pLogVariance + m2) / m2 ) );
r.n := InitNormal(seed, mn, sd);
return r;
end InitLogNormal;
-------------------------------------------------------------------------------
function InitErlang (seed: Integer := 13;
mean: Real := 50.0;
var: Real := 100.0) return Erlang is
variable r : Erlang;
begin
r.r.status := False;
r.pMean := mean;
r.pVariance := var;
r.k := Integer(r.pMean*r.pMean/r.pVariance+0.5);
if (r.k <= 0) then
r.k := 1;
end if;
r.a := Real(r.k) / r.pMean;
GenRnd(r.r, seed);
return r;
end InitErlang;
-------------------------------------------------------------------------------
function InitBinomial (seed: Integer := 13;
n: Integer := 0;
u: Real := 0.0) return Binomial is
variable r : Binomial;
begin
r.r.status := False;
r.pN := n;
r.pU := u;
GenRnd(r.r, seed);
return r;
end InitBinomial;
-------------------------------------------------------------------------------
function InitGeom (seed: Integer := 13;
mean: Real := 0.0) return Geom is
variable r : Geom;
begin
r.r.status := False;
r.pMean := mean;
GenRnd(r.r, seed);
return r;
end InitGeom;
-------------------------------------------------------------------------------
function InitHypGeom (seed: Integer := 13;
mean: Real := 0.0;
var: Real := 0.0) return HypGeom is
variable z: Real := 0.0;
variable r : HypGeom;
begin
r.r.status := False;
r.pMean := mean;
r.pVariance := var;
z := r.pVariance / (r.pMean * r.pMean);
z := sqrt( (z-1.0) / (z+1.0) );
r.pP := 0.5 * ( 1.0 - z );
GenRnd(r.r, seed);
return r;
end InitHypGeom;
-------------------------------------------------------------------------------
function InitWeibull (seed: Integer := 13;
alpha: Real := 0.0;
beta: Real := 0.0) return Weibull is
variable r : Weibull;
begin
r.r.status := False;
r.pAlpha := alpha;
r.pBeta := beta;
r.pInvAlpha := 1.0 / r.pAlpha;
GenRnd(r.r, seed);
return r;
end InitWeibull;
-------------------------------------------------------------------------------
function InitUniform (low: Real := 0.0;
high: Real := 100.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitUniform (seed, low, high));
end InitUniform;
-------------------------------------------------------------------------------
function InitNegExp (mean: PositiveReal := 50.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitNegExp (seed, mean));
end InitNegExp;
-------------------------------------------------------------------------------
function InitPoisson (mean: PositiveReal := 50.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitPoisson (seed, mean));
end InitPoisson;
-------------------------------------------------------------------------------
function InitNormal (mean: Real := 0.0;
var: Real := 100.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitNormal (seed, mean, var));
end InitNormal;
-------------------------------------------------------------------------------
function InitLogNormal (mean: Real := 50.0;
var: Real := 100.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitLogNormal (seed, mean, var));
end InitLogNormal;
-------------------------------------------------------------------------------
function InitErlang (mean: Real := 50.0;
var: Real := 100.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitErlang (seed, mean, var));
end InitErlang;
-------------------------------------------------------------------------------
function InitBinomial (n: Integer := 0;
u: Real := 0.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitBinomial (seed, n, u));
end InitBinomial;
-------------------------------------------------------------------------------
function InitGeom (mean: Real := 0.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitGeom (seed, mean));
end InitGeom;
-------------------------------------------------------------------------------
function InitHypGeom (mean: Real := 0.0;
var: Real := 0.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitHypGeom (seed, mean, var));
end InitHypGeom;
-------------------------------------------------------------------------------
function InitWeibull (alpha: Real := 0.0;
beta: Real := 0.0;
seed: Integer := 13) return random is
begin
return CvtRandom (InitWeibull (seed, alpha, beta));
end InitWeibull;
-------------------------------------------------------------------------------
procedure GenRnd (r: inout random) is
variable unf : Uniform;
variable nex : NegExp;
variable poi : Poisson;
variable nom : Normal;
variable lnom : LogNormal;
variable erl : Erlang;
variable geo : Geom;
variable hypg : HypGeom;
variable bin : Binomial;
variable wei : Weibull;
begin
case r.dist is
when UniformDist =>
unf := (r.rnd, r.a(2), r.a(1), r.a(3), r.r);
GenRnd(unf);
r.rnd := unf.rnd;
r.r := unf.r;
return;
when NegExpDist =>
nex := (r.rnd, PositiveReal'(r.a(1)), r.r);
GenRnd(nex);
r.rnd := nex.rnd;
r.r := nex.r;
return;
when PoissonDist =>
poi := (r.rnd, PositiveReal'(r.a(1)), r.r);
GenRnd(poi);
r.rnd := poi.rnd;
r.r := poi.r;
return;
when NormalDist =>
nom := (r.rnd, r.a(1), r.a(3), r.a(2),
r.a(4), r.c, r.r);
GenRnd(nom);
r.rnd := nom.rnd;
r.r := nom.r;
r.a(4):= nom.CachedNormal;
r.c := nom.haveCachedNormal;
return;
when LogNormalDist =>
nom := (r.rnd, r.a(1), r.a(3), r.a(2),
r.a(4), r.c, r.r);
lnom := (r.rnd, r.a(5), r.a(6), nom);
GenRnd(lnom);
r.rnd := lnom.rnd;
r.r := lnom.n.r;
r.a(4):= lnom.n.CachedNormal;
r.c := lnom.n.haveCachedNormal;
return;
when ErlangDist =>
erl := (r.rnd, r.a(1), r.a(2), r.a(3),
r.b, r.r);
GenRnd(erl);
r.rnd := erl.rnd;
r.r := erl.r;
return;
when BinomialDist =>
bin := (r.rnd, r.a(1), r.b, r.r);
GenRnd(bin);
r.rnd := bin.rnd;
r.r := bin.r;
return;
when GeomDist =>
geo := (r.rnd, r.a(1), r.r);
GenRnd(geo);
r.rnd := geo.rnd;
r.r := geo.r;
return;
when HypGeomDist =>
hypg := (r.rnd, r.a(1), r.a(2), r.a(3), r.r);
GenRnd(hypg);
r.rnd := hypg.rnd;
r.r := hypg.r;
return;
when WeibullDist =>
wei := (r.rnd, r.a(1), r.a(3), r.a(2), r.r);
GenRnd(wei);
r.rnd := wei.rnd;
r.r := wei.r;
return;
end case;
end GenRnd;
-------------------------------------------------------------------------------
function CvtRandom (uni: in Uniform) return random is
variable r : random;
begin
r.dist := UniformDist;
r.rnd := uni.rnd;
r.a(1) := uni.pLow;
r.a(2) := uni.pHigh;
r.a(3) := uni.delta;
r.r := uni.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (nex: in NegExp) return random is
variable r : random;
begin
r.dist := NegExpDist;
r.rnd := nex.rnd;
r.a(1) := nex.pMean;
r.r := nex.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (poi: in Poisson) return random is
variable r : random;
begin
r.dist := PoissonDist;
r.rnd := poi.rnd;
r.a(1) := poi.pMean;
r.r := poi.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (nom: in Normal) return random is
variable r : random;
begin
r.dist := NormalDist;
r.rnd := nom.rnd;
r.a(1) := nom.pMean;
r.a(2) := nom.pVariance;
r.a(3) := nom.pStdDev;
r.a(4) := nom.CachedNormal;
r.c := nom.haveCachedNormal;
r.r := nom.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (lnom: in LogNormal) return random is
variable r : random := CvtRandom(lnom.n);
begin
r.dist := LogNormalDist;
r.a(5) := lnom.pLogMean;
r.a(6) := lnom.pLogVariance;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (erl: in Erlang) return random is
variable r : random;
begin
r.dist := ErlangDist;
r.rnd := erl.rnd;
r.a(1) := erl.pMean;
r.a(2) := erl.pVariance;
r.a(3) := erl.a;
r.b := erl.k;
r.r := erl.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (bin: in Binomial) return random is
variable r : random;
begin
r.dist := BinomialDist;
r.rnd := bin.rnd;
r.a(1) := bin.pU;
r.b := bin.pN;
r.r := bin.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (geo: in Geom) return random is
variable r : random;
begin
r.dist := GeomDist;
r.a(1) := geo.pMean;
r.r := geo.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (hypg: in HypGeom) return random is
variable r : random;
begin
r.dist := HypGeomDist;
r.a(1) := hypg.pMean;
r.a(2) := hypg.pVariance;
r.a(3) := hypg.pP;
r.r := hypg.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtRandom (wei: in Weibull) return random is
variable r : random;
begin
r.dist := WeibullDist;
r.a(1) := wei.pAlpha;
r.a(2) := wei.pBeta;
r.a(3) := wei.pInvAlpha;
r.r := wei.r;
return r;
end CvtRandom;
-------------------------------------------------------------------------------
function CvtUniform (r: in random) return Uniform is
variable uni : Uniform := (r.rnd, r.a(2), r.a(1), r.a(3), r.r);
begin
return uni;
end CvtUniform;
-------------------------------------------------------------------------------
function CvtNegExp (r: in random) return NegExp is
variable nex : NegExp := (r.rnd, PositiveReal'(r.a(1)), r.r);
begin
return nex;
end CvtNegExp;
-------------------------------------------------------------------------------
function CvtPoisson (r: in random) return Poisson is
variable poi : Poisson := (r.rnd, PositiveReal'(r.a(1)), r.r);
begin
return poi;
end CvtPoisson;
-------------------------------------------------------------------------------
function CvtNormal (r: in random) return Normal is
variable nom : Normal := (r.rnd, r.a(1), r.a(3),
r.a(2), r.a(4), r.c, r.r);
begin
return nom;
end CvtNormal;
-------------------------------------------------------------------------------
function CvtLogNormal (r: in random) return LogNormal is
variable nom : Normal := (r.rnd, r.a(1), r.a(3), r.a(2),
r.a(4), r.c, r.r);
variable lnom : LogNormal := (r.rnd, r.a(5), r.a(6), nom);
begin
return lnom;
end CvtLogNormal;
-------------------------------------------------------------------------------
function CvtErlang (r: in random) return Erlang is
variable erl : Erlang := (r.rnd, r.a(1), r.a(2),
r.a(3), r.b, r.r);
begin
return erl;
end CvtErlang;
-------------------------------------------------------------------------------
function CvtBinomial (r: in random) return Binomial is
variable bin : Binomial := (r.rnd, r.a(1), r.b, r.r);
begin
return bin;
end CvtBinomial;
-------------------------------------------------------------------------------
function CvtGeom (r: in random) return Geom is
variable geo : Geom := (r.rnd, r.a(1), r.r);
begin
return geo;
end CvtGeom;
-------------------------------------------------------------------------------
function CvtHypGeom (r: in random) return HypGeom is
variable hypg : HypGeom := (r.rnd, r.a(1), r.a(2),
r.a(3), r.r);
begin
return hypg;
end CvtHypGeom;
-------------------------------------------------------------------------------
function CvtWeibull (r: in random) return Weibull is
variable wei : Weibull := (r.rnd, r.a(1), r.a(3),
r.a(2), r.r);
begin
return wei;
end CvtWeibull;
-------------------------------------------------------------------------------
end RNG;
| lgpl-3.0 | d8ad35669d26ceeffe7d7879a45bb0c0 | 0.51027 | 3.088737 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-2/src/structure/Var5.vhd | 1 | 1,482 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Var5 is port(
W,X,Y,Z: in std_logic;
F: out std_logic
);
end Var5;
--
architecture structual of Var5 is
signal nW : std_logic;
signal nY : std_logic;
signal nWX : std_logic;
signal nWXY : std_logic;
signal WXY : std_logic;
signal T : std_logic;
signal nT : std_logic;
signal WZ : std_logic;
signal nWZ : std_logic;
component AND2 is port(
a,b: in std_logic;
z: out std_logic);
end component;
component OR2 is port(
a,b: in std_logic;
z: out std_logic);
end component;
component NOT1 is port(
a: in std_logic;
z: out std_logic);
end component;
component NAND3 is port(
A,B,C: in std_logic;
Z: out std_logic);
end component;
component OR3 is port (
A,B,C: in std_logic;
Z: out std_logic);
end component;
begin
M1: NOT1 port map (W, nW);
M2: OR2 port map (nW, X, nWX);
M3: AND2 port map (nWX, Y, nWXY);
M4: NOT1 port map (nWXY, WXY);
M5: NOT1 port map (Y, nY);
M6: OR3 port map (nW, X, nY, T);
M7: NOT1 port map (T, nT);
M8: OR2 port map (W, Z, WZ);
M9: NOT1 port map (WZ, nWZ);
M10: NAND3 port map (nWZ, nT, WXY, F);
end structual;
architecture behavior of Var5 is
signal WX : std_logic;
signal WXY : std_logic;
signal WXY2 : std_logic;
signal WZ : std_logic;
begin
WX <= (not W) or X;
WXY <= not(WX and Y);
WXY2 <= not((not W) or X or (not Y));
WZ <= not(W or Z);
F <= not(WZ) and not(WXY) and not(WXY2);
end behavior; | mit | fb7719fe7a4787518b6a846c685bf51d | 0.620783 | 2.367412 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep3c25-eek/testbench.vhd | 1 | 14,713 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Altera Cyclone-III Embedded Evaluation Kit LEON3 Demonstration design test
-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
-- Adapted for EEK by Jan Andersson, Gaisler Research
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-3 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal ssram_cen : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adsp_n : std_ulogic;
signal ssram_adv_n : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clkin : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
-- Connections over HSMC connector
-- LCD touch panel display
signal hc_vd : std_logic;
signal hc_hd : std_logic;
signal hc_den : std_logic;
signal hc_nclk : std_logic;
signal hc_lcd_data : std_logic_vector(7 downto 0);
signal hc_grest : std_logic;
signal hc_scen : std_logic;
signal hc_sda : std_logic;
signal hc_adc_penirq_n : std_logic;
signal hc_adc_dout : std_logic;
signal hc_adc_busy : std_logic;
signal hc_adc_din : std_logic;
signal hc_adc_dclk : std_logic;
signal hc_adc_cs_n : std_logic;
-- Shared by video decoder and audio codec
signal hc_i2c_sclk : std_logic;
signal hc_i2c_sdat : std_logic;
-- Video decoder
signal hc_td_d : std_logic_vector(7 downto 0);
signal hc_td_hs : std_logic;
signal hc_td_vs : std_logic;
signal hc_td_27mhz : std_logic;
signal hc_td_reset : std_logic;
-- Audio codec
signal hc_aud_adclrck : std_logic;
signal hc_aud_adcdat : std_logic;
signal hc_aud_daclrck : std_logic;
signal hc_aud_dacdat : std_logic;
signal hc_aud_bclk : std_logic;
signal hc_aud_xck : std_logic;
-- SD card
signal hc_sd_dat : std_logic;
signal hc_sd_dat3 : std_logic;
signal hc_sd_cmd : std_logic;
signal hc_sd_clk : std_logic;
-- Ethernet PHY
signal hc_tx_d : std_logic_vector(3 downto 0);
signal hc_rx_d : std_logic_vector(3 downto 0);
signal hc_tx_clk : std_logic;
signal hc_rx_clk : std_logic;
signal hc_tx_en : std_logic;
signal hc_rx_dv : std_logic;
signal hc_rx_crs : std_logic;
signal hc_rx_err : std_logic;
signal hc_rx_col : std_logic;
signal hc_mdio : std_logic;
signal hc_mdc : std_logic;
signal hc_eth_reset_n : std_logic;
-- RX232 (console/debug UART)
signal hc_uart_rxd : std_logic;
signal hc_uart_txd : std_logic;
-- PS/2
signal hc_ps2_dat : std_logic;
signal hc_ps2_clk : std_logic;
-- VGA/DAC
signal hc_vga_data : std_logic_vector(9 downto 0);
signal hc_vga_clock : std_ulogic;
signal hc_vga_hs : std_ulogic;
signal hc_vga_vs : std_ulogic;
signal hc_vga_blank : std_ulogic;
signal hc_vga_sync : std_ulogic;
-- I2C EEPROM
signal hc_id_i2cscl : std_logic;
signal hc_id_i2cdat : std_logic;
-- Ethernet PHY sim model
signal phy_tx_er : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal hc_tx_dt : std_logic_vector(7 downto 0) := (others => '0');
signal hc_rx_dt : std_logic_vector(7 downto 0) := (others => '0');
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; hc_uart_rxd <= '1';
address(0) <= '0';
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error,
address(25 downto 1), data, romsn, oen, writen, open,
ssram_cen, ssram_wen, ssram_bw, ssram_oen,
ssram_clk, ssram_adscn, iosn,
-- DDR
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
-- DSU
dsubren, dsuact,
-- I/O port
gpio,
-- LCD
hc_vd, hc_hd, hc_den, hc_nclk, hc_lcd_data, hc_grest, hc_scen,
hc_sda, hc_adc_penirq_n, hc_adc_dout, hc_adc_busy, hc_adc_din,
hc_adc_dclk, hc_adc_cs_n,
-- Shared by video decoder and audio codec
hc_i2c_sclk, hc_i2c_sdat,
-- Video decoder
hc_td_d, hc_td_hs, hc_td_vs, hc_td_27mhz, hc_td_reset,
-- Audio codec
hc_aud_adclrck, hc_aud_adcdat, hc_aud_daclrck, hc_aud_dacdat,
hc_aud_bclk, hc_aud_xck,
-- SD card
hc_sd_dat, hc_sd_dat3, hc_sd_cmd, hc_sd_clk,
-- Ethernet PHY
hc_tx_d, hc_rx_d, hc_tx_clk, hc_rx_clk, hc_tx_en, hc_rx_dv, hc_rx_crs,
hc_rx_err, hc_rx_col, hc_mdio, hc_mdc, hc_eth_reset_n,
-- RX232 (console/debug UART)
hc_uart_rxd, hc_uart_txd,
-- PS/2
hc_ps2_dat, hc_ps2_clk,
-- VGA/DAC
hc_vga_data, hc_vga_clock, hc_vga_hs, hc_vga_vs, hc_vga_blank, hc_vga_sync,
-- I2C EEPROM
hc_id_i2cscl, hc_id_i2cdat
);
-- I2C bus pull-ups
hc_i2c_sclk <= 'H'; hc_i2c_sdat <= 'H';
hc_id_i2cscl <= 'H'; hc_id_i2cdat <= 'H';
-- SD card signals
spiflashmod : spi_flash
generic map (ftype => 3, debug => 0, dummybyte => 0)
port map (sck => hc_sd_clk, di => hc_sd_cmd, do => hc_sd_dat, csn => hc_sd_dat3);
hc_sd_dat <= 'Z'; hc_sd_cmd <= 'Z';
-- hc_sd_dat <= hc_sd_cmd; -- Loopback
-- ddr0 : mt46v16m16
-- generic map (index => -1, fname => sdramfile)
-- port map(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 1)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
datazz <= "HHHH";
ssram_adsp_n <= '1'; ssram_adv_n <= '1';
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => data,
iAddr => address(20 downto 2), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
inADSP => ssram_adsp_n, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_cen,
iCE2 => vcc, inCE3 => gnd, iZz => gnd);
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31 downto 16),
gnd, gnd, romsn, writen, oen);
-- Ethernet PHY
hc_mdio <= 'H';
phy_tx_er <= '0';
phy_gtx_clk <= '0';
hc_tx_dt(3 downto 0) <= hc_tx_d;
hc_rx_d <= hc_rx_dt(3 downto 0);
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(hc_eth_reset_n, hc_mdio, hc_tx_clk, hc_rx_clk, hc_rx_dt, hc_rx_dv,
hc_rx_err, hc_rx_col, hc_rx_crs, hc_tx_dt, hc_tx_en, phy_tx_er, hc_mdc, phy_gtx_clk);
-- I2C memory
i0: i2c_slave_model
port map (hc_id_i2cscl, hc_id_i2cdat);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | fca47d250a83337e6754e1d8144f16a0 | 0.566302 | 3.003266 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml40x/testbench.vhd | 1 | 10,381 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
signal sysace_clk_in : std_ulogic := '0';
constant ct : integer := clkperiod/2;
signal plb_error : std_logic;
signal opb_error : std_logic;
signal flash_a23 : std_ulogic;
signal sram_flash_addr : std_logic_vector(22 downto 0);
signal sram_flash_data : std_logic_vector(31 downto 0);
signal sram_cen : std_logic;
signal sram_bw : std_logic_vector (3 downto 0);
signal sram_flash_oe_n : std_ulogic;
signal sram_flash_we_n : std_ulogic;
signal flash_ce : std_logic;
signal sram_clk : std_ulogic;
signal sram_clk_fb : std_ulogic;
signal sram_mode : std_ulogic;
signal sram_adv_ld_n : std_ulogic;
signal sram_zz : std_ulogic;
signal iosn : std_ulogic;
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (3 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (3 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (31 downto 0); -- ddr data
signal txd1 : std_ulogic; -- UART1 tx data
signal rxd1 : std_ulogic; -- UART1 rx data
signal gpio : std_logic_vector(26 downto 0); -- I/O port
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_int_n : std_ulogic;
signal ps2_keyb_clk: std_logic;
signal ps2_keyb_data: std_logic;
signal ps2_mouse_clk: std_logic;
signal ps2_mouse_data: std_logic;
signal tft_lcd_clk : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal usb_csn : std_logic;
signal flash_cex : std_logic;
signal iic_scl : std_logic;
signal iic_sda : std_logic;
signal sace_usb_a : std_logic_vector(6 downto 0);
signal sace_mpce : std_ulogic;
signal sace_usb_d : std_logic_vector(15 downto 0);
signal sace_usb_oen : std_ulogic;
signal sace_usb_wen : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to 2) := "000";
signal spw_rxdn : std_logic_vector(0 to 2) := "000";
signal spw_rxsp : std_logic_vector(0 to 2) := "000";
signal spw_rxsn : std_logic_vector(0 to 2) := "000";
signal spw_txdp : std_logic_vector(0 to 2);
signal spw_txdn : std_logic_vector(0 to 2);
signal spw_txsp : std_logic_vector(0 to 2);
signal spw_txsn : std_logic_vector(0 to 2);
signal datazz : std_logic_vector(0 to 3);
constant lresp : boolean := false;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sys_rst_in <= '0', '1' after 200 ns;
sysace_clk_in <= not sysace_clk_in after 15 ns;
rxd1 <= 'H';
sram_clk_fb <= sram_clk; ddr_clk_fb <= ddr_clk;
ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
iic_scl <= 'H'; iic_sda <= 'H';
flash_cex <= not flash_ce;
sace_usb_d <= (others => 'H'); sysace_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, sysace_clk_in, plb_error, opb_error, flash_a23,
sram_flash_addr, sram_flash_data, sram_cen, sram_bw, sram_flash_oe_n,
sram_flash_we_n, flash_ce, sram_clk, sram_clk_fb, sram_mode, sram_adv_ld_n, iosn,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
txd1, rxd1, gpio, phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_int_n,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, ps2_keyb_clk,
ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data, tft_lcd_clk, vid_blankn, vid_syncn,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b,
usb_csn,
iic_scl, iic_sda,
sace_usb_a, sace_mpce, sace_usb_d, sace_usb_oen, sace_usb_wen,
sysace_mpirq
);
datazz <= "HHHH";
u0 : cy7c1354 generic map (fname => sramfile, tWEH => 0.0 ns, tAH => 0.0 ns)
port map(
Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data,
Addr => sram_flash_addr(17 downto 0), Mode => sram_mode,
Clk => sram_clk, CEN_n => gnd, AdvLd_n => sram_adv_ld_n,
Bwa_n => sram_bw(3), Bwb_n => sram_bw(2),
Bwc_n => sram_bw(1), Bwd_n => sram_bw(0),
Rw_n => sram_flash_we_n, Oe_n => sram_flash_oe_n,
Ce1_n => sram_cen,
Ce2 => vcc,
Ce3_n => gnd,
Zz => sram_zz);
sram_zz <= '0';
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 32)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
ddr0 : ddrram
generic map(width => 32, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(31-i*8 downto 24-i*8),
flash_cex, sram_bw(i), sram_flash_oe_n);
end generate;
phy_mii_data <= 'H';
p0: phy
port map(sys_rst_in, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data, phy_dv,
phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_gtx_clk);
i0: i2c_slave_model
port map (iic_scl, iic_sda);
plb_error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5000 ns;
if to_x01(plb_error) = '1' then wait on plb_error; end if;
assert (to_x01(plb_error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, plb_error, sram_flash_addr(19 downto 0), sram_flash_data,
iosn, sram_flash_oe_n, sram_bw(0), open);
sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
| gpl-2.0 | 40b358211c2eac97ce73fc9cc47edf1e | 0.611116 | 2.995095 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/inferred/ddr_phy_inferred.vhd | 1 | 16,449 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: generic_ddr_phy
-- File: ddr_phy_inferred.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Modified: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR PHY (simulation only)
------------------------------------------------------------------------------
--###################################################################################
-- Generic DDR1 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb: in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic -- Mobile DDR enable
);
end;
architecture rtl of generic_ddr_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
signal ckl: std_logic_vector(nclk-1 downto 0);
signal ckel: std_logic_vector(ncs-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl, rst)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' or rst='0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
-- For mobile SDRAM, force Cke high during reset and reset-delay,
-- For regular SDRAM, force Cke low
-- also disable outgoing clock until we have achieved PLL lock
mobgen: if mobile > 1 generate
ckel <= cke or (cke'range => not locked);
end generate;
nmobgen: if mobile < 2 generate
ckel <= cke and (cke'range => locked);
end generate;
ckl <= ck and (ck'range => lockl);
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2, ncs => ncs, nclk => nclk,
resync => 2 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => open,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba,
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => ckel,
odt => (others => '0'),
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ckl
);
end;
--###################################################################################
-- Generic DDR2 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
eightbanks: integer := 0; abits: integer := 14;
cben: integer := 0; chkbits: integer := 8;
nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic; -- system clock returned
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0); -- ddr odt
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector (2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(2 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of generic_ddr2_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr2 without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2+EIGHTBANKS, ncs => ncs, nclk => nclk,
resync => 0 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => ddr_odt,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba(1+eightbanks downto 0),
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => cke,
odt => odt,
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ck(nclk-1 downto 0)
);
end;
| gpl-2.0 | ca761e7d25479b99329079f099abdd23 | 0.500334 | 3.732471 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/gencomp/netcomp.vhd | 1 | 67,952 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: netcomp
-- File: netcomp.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler
-- Description: Declaration of netlists components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use work.gencomp.all;
package netcomp is
---------------------------------------------------------------------------
-- netlists ---------------------------------------------------------------
---------------------------------------------------------------------------
component grusbhc_net is
generic (
tech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debug_abits : integer := 12);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- grusb_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
suspendm : out std_ulogic;
dbus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
txenablen : out std_ulogic;
txdat : out std_ulogic;
txse0 : out std_ulogic;
-- grusb_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
urstdrive : in std_logic_vector((nports-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic;
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic;
-- debug signals
debug_raddr : out std_logic_vector(15 downto 0);
debug_waddr : out std_logic_vector(15 downto 0);
debug_wdata : out std_logic_vector(31 downto 0);
debug_we : out std_ulogic;
debug_rdata : in std_logic_vector(31 downto 0));
end component;
component grspwc_net
generic(
tech : integer := 0;
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc2_net is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0;
interruptdist : integer range 0 to 32 := 0;
intscalerbits : integer range 0 to 31 := 0;
intisrtimerbits : integer range 0 to 31 := 0;
intiatimerbits : integer range 0 to 31 := 0;
intctimerbits : integer range 0 to 31 := 0;
tickinasync : integer range 0 to 1 := 0;
pnp : integer range 0 to 2 := 0;
pnpvendid : integer range 0 to 16#FFFF# := 0;
pnpprodid : integer range 0 to 16#FFFF# := 0;
pnpmajorver : integer range 0 to 16#FF# := 0;
pnpminorver : integer range 0 to 16#FF# := 0;
pnppatch : integer range 0 to 16#FF# := 0;
num_txdesc : integer range 64 to 512 := 64;
num_rxdesc : integer range 128 to 1024 := 128
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_logic;
tickinraw : in std_logic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_logic;
tickout : out std_logic;
tickoutraw : out std_logic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(5 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(5 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(5 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(5 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(9 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(9 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic;
testrst : in std_logic;
testen : in std_logic;
rxdav : out std_logic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_logic;
-- interrupt dist. default values
intpreload : in std_logic_vector(30 downto 0);
inttreload : in std_logic_vector(30 downto 0);
intiareload : in std_logic_vector(30 downto 0);
intcreload : in std_logic_vector(30 downto 0);
irqtxdefault : in std_logic_vector(4 downto 0);
--SpW PnP enable
pnpen : in std_ulogic;
pnpuvendid : in std_logic_vector(15 downto 0);
pnpuprodid : in std_logic_vector(15 downto 0);
pnpusn : in std_logic_vector(31 downto 0)
);
end component;
component grlfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component leon3ft_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic
);
end component;
component ssrctrl_net
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
component ftsrctrl_net
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0;
netlist : integer := 0;
tech : integer := 0
);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri_data: in Std_Logic_Vector(31 downto 0); -- Data bus address
sri_brdyn: in Std_Logic;
sri_bexcn: in Std_Logic;
sri_writen: in Std_Logic;
sri_wrn: in Std_Logic_Vector(3 downto 0);
sri_bwidth: in Std_Logic_Vector(1 downto 0);
sri_sd: in Std_Logic_Vector(63 downto 0);
sri_cb: in Std_Logic_Vector(15 downto 0);
sri_scb: in Std_Logic_Vector(15 downto 0);
sri_edac: in Std_Logic;
sro_address: out Std_Logic_Vector(31 downto 0);
sro_data: out Std_Logic_Vector(31 downto 0);
sro_sddata: out Std_Logic_Vector(63 downto 0);
sro_ramsn: out Std_Logic_Vector(7 downto 0);
sro_ramoen: out Std_Logic_Vector(7 downto 0);
sro_ramn: out Std_ULogic;
sro_romn: out Std_ULogic;
sro_mben: out Std_Logic_Vector(3 downto 0);
sro_iosn: out Std_Logic;
sro_romsn: out Std_Logic_Vector(7 downto 0);
sro_oen: out Std_Logic;
sro_writen: out Std_Logic;
sro_wrn: out Std_Logic_Vector(3 downto 0);
sro_bdrive: out Std_Logic_Vector(3 downto 0);
sro_vbdrive: out Std_Logic_Vector(31 downto 0); --vector bus drive
sro_svbdrive: out Std_Logic_Vector(63 downto 0); --vector bus drive sdram
sro_read: out Std_Logic;
sro_sa: out Std_Logic_Vector(14 downto 0);
sro_cb: out Std_Logic_Vector(15 downto 0);
sro_scb: out Std_Logic_Vector(15 downto 0);
sro_vcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb
sro_svcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb sdram
sro_ce: out Std_ULogic;
sdo_sdcke: out Std_Logic_Vector( 1 downto 0); -- clk en
sdo_sdcsn: out Std_Logic_Vector( 1 downto 0); -- chip sel
sdo_sdwen: out Std_ULogic; -- write en
sdo_rasn: out Std_ULogic; -- row addr stb
sdo_casn: out Std_ULogic; -- col addr stb
sdo_dqm: out Std_Logic_Vector(15 downto 0); -- data i/o mask
sdo_bdrive: out Std_ULogic; -- bus drive
sdo_qdrive: out Std_ULogic; -- bus drive
sdo_vbdrive: out Std_Logic_Vector(31 downto 0); -- vector bus drive
sdo_address: out Std_Logic_Vector(16 downto 2); -- address out
sdo_data: out Std_Logic_Vector(127 downto 0); -- data out
sdo_cb: out Std_Logic_Vector(15 downto 0);
sdo_ce: out Std_ULogic;
sdo_ba: out Std_Logic_Vector(2 downto 0)); -- bank address
end component;
component grlfpw4_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0;
wrt : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(63 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(63 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw4_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(63 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(63 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component spictrl_net
generic (
tech : integer range 0 to NTECH := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0;
odmode : integer range 0 to 1 := 0;
automode : integer range 0 to 1 := 0;
acntbits : integer range 1 to 32 := 32;
aslvsel : integer range 0 to 1 := 0;
twen : integer range 0 to 1 := 1;
maxwlen : integer range 0 to 15 := 0;
automask0 : integer := 0;
automask1 : integer := 0;
automask2 : integer := 0;
automask3 : integer := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end component;
component leon4_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
hclken : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic);
end component;
component grpci2_phy_net is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0
);
port(
pciclk : in std_logic;
pcii_rst : in std_ulogic;
pcii_gnt : in std_ulogic;
pcii_idsel : in std_ulogic;
pcii_ad : in std_logic_vector(31 downto 0);
pcii_cbe : in std_logic_vector(3 downto 0);
pcii_frame : in std_ulogic;
pcii_irdy : in std_ulogic;
pcii_trdy : in std_ulogic;
pcii_devsel : in std_ulogic;
pcii_stop : in std_ulogic;
pcii_lock : in std_ulogic;
pcii_perr : in std_ulogic;
pcii_serr : in std_ulogic;
pcii_par : in std_ulogic;
pcii_host : in std_ulogic;
pcii_pci66 : in std_ulogic;
pcii_pme_status : in std_ulogic;
pcii_int : in std_logic_vector(3 downto 0);
phyi_pcirstout : in std_logic;
phyi_pciasyncrst : in std_logic;
phyi_pcisoftrst : in std_logic_vector(2 downto 0);
phyi_pciinten : in std_logic_vector(3 downto 0);
phyi_m_request : in std_logic;
phyi_m_mabort : in std_logic;
phyi_pr_m_fstate : in std_logic_vector(1 downto 0);
phyi_pr_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_0_last : in std_logic;
phyi_pr_m_cfifo_0_stlast : in std_logic;
phyi_pr_m_cfifo_0_hold : in std_logic;
phyi_pr_m_cfifo_0_valid : in std_logic;
phyi_pr_m_cfifo_0_err : in std_logic;
phyi_pr_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_1_last : in std_logic;
phyi_pr_m_cfifo_1_stlast : in std_logic;
phyi_pr_m_cfifo_1_hold : in std_logic;
phyi_pr_m_cfifo_1_valid : in std_logic;
phyi_pr_m_cfifo_1_err : in std_logic;
phyi_pr_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_m_cfifo_2_last : in std_logic;
phyi_pr_m_cfifo_2_stlast : in std_logic;
phyi_pr_m_cfifo_2_hold : in std_logic;
phyi_pr_m_cfifo_2_valid : in std_logic;
phyi_pr_m_cfifo_2_err : in std_logic;
phyi_pv_m_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_0_last : in std_logic;
phyi_pv_m_cfifo_0_stlast : in std_logic;
phyi_pv_m_cfifo_0_hold : in std_logic;
phyi_pv_m_cfifo_0_valid : in std_logic;
phyi_pv_m_cfifo_0_err : in std_logic;
phyi_pv_m_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_1_last : in std_logic;
phyi_pv_m_cfifo_1_stlast : in std_logic;
phyi_pv_m_cfifo_1_hold : in std_logic;
phyi_pv_m_cfifo_1_valid : in std_logic;
phyi_pv_m_cfifo_1_err : in std_logic;
phyi_pv_m_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pv_m_cfifo_2_last : in std_logic;
phyi_pv_m_cfifo_2_stlast : in std_logic;
phyi_pv_m_cfifo_2_hold : in std_logic;
phyi_pv_m_cfifo_2_valid : in std_logic;
phyi_pv_m_cfifo_2_err : in std_logic;
phyi_pr_m_addr : in std_logic_vector(31 downto 0);
phyi_pr_m_cbe_data : in std_logic_vector(3 downto 0);
phyi_pr_m_cbe_cmd : in std_logic_vector(3 downto 0);
phyi_pr_m_first : in std_logic_vector(1 downto 0);
phyi_pv_m_term : in std_logic_vector(1 downto 0);
phyi_pr_m_ltimer : in std_logic_vector(7 downto 0);
phyi_pr_m_burst : in std_logic;
phyi_pr_m_abort : in std_logic_vector(0 downto 0);
phyi_pr_m_perren : in std_logic_vector(0 downto 0);
phyi_pr_m_done_fifo : in std_logic;
phyi_t_abort : in std_logic;
phyi_t_ready : in std_logic;
phyi_t_retry : in std_logic;
phyi_pr_t_state : in std_logic_vector(2 downto 0);
phyi_pv_t_state : in std_logic_vector(2 downto 0);
phyi_pr_t_fstate : in std_logic_vector(1 downto 0);
phyi_pr_t_cfifo_0_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_0_last : in std_logic;
phyi_pr_t_cfifo_0_stlast : in std_logic;
phyi_pr_t_cfifo_0_hold : in std_logic;
phyi_pr_t_cfifo_0_valid : in std_logic;
phyi_pr_t_cfifo_0_err : in std_logic;
phyi_pr_t_cfifo_1_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_1_last : in std_logic;
phyi_pr_t_cfifo_1_stlast : in std_logic;
phyi_pr_t_cfifo_1_hold : in std_logic;
phyi_pr_t_cfifo_1_valid : in std_logic;
phyi_pr_t_cfifo_1_err : in std_logic;
phyi_pr_t_cfifo_2_data : in std_logic_vector(31 downto 0);
phyi_pr_t_cfifo_2_last : in std_logic;
phyi_pr_t_cfifo_2_stlast : in std_logic;
phyi_pr_t_cfifo_2_hold : in std_logic;
phyi_pr_t_cfifo_2_valid : in std_logic;
phyi_pr_t_cfifo_2_err : in std_logic;
phyi_pv_t_diswithout : in std_logic;
phyi_pr_t_stoped : in std_logic;
phyi_pr_t_lcount : in std_logic_vector(2 downto 0);
phyi_pr_t_first_word : in std_logic;
phyi_pr_t_cur_acc_0_read : in std_logic;
phyi_pv_t_hold_write : in std_logic;
phyi_pv_t_hold_reset : in std_logic;
phyi_pr_conf_comm_perren : in std_logic;
phyi_pr_conf_comm_serren : in std_logic;
pcio_aden : out std_ulogic;
pcio_vaden : out std_logic_vector(31 downto 0);
pcio_cbeen : out std_logic_vector(3 downto 0);
pcio_frameen : out std_ulogic;
pcio_irdyen : out std_ulogic;
pcio_trdyen : out std_ulogic;
pcio_devselen : out std_ulogic;
pcio_stopen : out std_ulogic;
pcio_ctrlen : out std_ulogic;
pcio_perren : out std_ulogic;
pcio_paren : out std_ulogic;
pcio_reqen : out std_ulogic;
pcio_locken : out std_ulogic;
pcio_serren : out std_ulogic;
pcio_inten : out std_ulogic;
pcio_vinten : out std_logic_vector(3 downto 0);
pcio_req : out std_ulogic;
pcio_ad : out std_logic_vector(31 downto 0);
pcio_cbe : out std_logic_vector(3 downto 0);
pcio_frame : out std_ulogic;
pcio_irdy : out std_ulogic;
pcio_trdy : out std_ulogic;
pcio_devsel : out std_ulogic;
pcio_stop : out std_ulogic;
pcio_perr : out std_ulogic;
pcio_serr : out std_ulogic;
pcio_par : out std_ulogic;
pcio_lock : out std_ulogic;
pcio_power_state : out std_logic_vector(1 downto 0);
pcio_pme_enable : out std_ulogic;
pcio_pme_clear : out std_ulogic;
pcio_int : out std_ulogic;
pcio_rst : out std_ulogic;
phyo_pciv_rst : out std_ulogic;
phyo_pciv_gnt : out std_ulogic;
phyo_pciv_idsel : out std_ulogic;
phyo_pciv_ad : out std_logic_vector(31 downto 0);
phyo_pciv_cbe : out std_logic_vector(3 downto 0);
phyo_pciv_frame : out std_ulogic;
phyo_pciv_irdy : out std_ulogic;
phyo_pciv_trdy : out std_ulogic;
phyo_pciv_devsel : out std_ulogic;
phyo_pciv_stop : out std_ulogic;
phyo_pciv_lock : out std_ulogic;
phyo_pciv_perr : out std_ulogic;
phyo_pciv_serr : out std_ulogic;
phyo_pciv_par : out std_ulogic;
phyo_pciv_host : out std_ulogic;
phyo_pciv_pci66 : out std_ulogic;
phyo_pciv_pme_status : out std_ulogic;
phyo_pciv_int : out std_logic_vector(3 downto 0);
phyo_pr_m_state : out std_logic_vector(2 downto 0);
phyo_pr_m_last : out std_logic_vector(1 downto 0);
phyo_pr_m_hold : out std_logic_vector(1 downto 0);
phyo_pr_m_term : out std_logic_vector(1 downto 0);
phyo_pr_t_hold : out std_logic_vector(0 downto 0);
phyo_pr_t_stop : out std_logic;
phyo_pr_t_abort : out std_logic;
phyo_pr_t_diswithout : out std_logic;
phyo_pr_t_addr_perr : out std_logic;
phyo_pcirsto : out std_logic_vector(0 downto 0);
phyo_pr_po_ad : out std_logic_vector(31 downto 0);
phyo_pr_po_aden : out std_logic_vector(31 downto 0);
phyo_pr_po_cbe : out std_logic_vector(3 downto 0);
phyo_pr_po_cbeen : out std_logic_vector(3 downto 0);
phyo_pr_po_frame : out std_logic;
phyo_pr_po_frameen : out std_logic;
phyo_pr_po_irdy : out std_logic;
phyo_pr_po_irdyen : out std_logic;
phyo_pr_po_trdy : out std_logic;
phyo_pr_po_trdyen : out std_logic;
phyo_pr_po_stop : out std_logic;
phyo_pr_po_stopen : out std_logic;
phyo_pr_po_devsel : out std_logic;
phyo_pr_po_devselen : out std_logic;
phyo_pr_po_par : out std_logic;
phyo_pr_po_paren : out std_logic;
phyo_pr_po_perr : out std_logic;
phyo_pr_po_perren : out std_logic;
phyo_pr_po_lock : out std_logic;
phyo_pr_po_locken : out std_logic;
phyo_pr_po_req : out std_logic;
phyo_pr_po_reqen : out std_logic;
phyo_pr_po_serren : out std_logic;
phyo_pr_po_inten : out std_logic;
phyo_pr_po_vinten : out std_logic_vector(3 downto 0);
phyo_pio_rst : out std_ulogic;
phyo_pio_gnt : out std_ulogic;
phyo_pio_idsel : out std_ulogic;
phyo_pio_ad : out std_logic_vector(31 downto 0);
phyo_pio_cbe : out std_logic_vector(3 downto 0);
phyo_pio_frame : out std_ulogic;
phyo_pio_irdy : out std_ulogic;
phyo_pio_trdy : out std_ulogic;
phyo_pio_devsel : out std_ulogic;
phyo_pio_stop : out std_ulogic;
phyo_pio_lock : out std_ulogic;
phyo_pio_perr : out std_ulogic;
phyo_pio_serr : out std_ulogic;
phyo_pio_par : out std_ulogic;
phyo_pio_host : out std_ulogic;
phyo_pio_pci66 : out std_ulogic;
phyo_pio_pme_status : out std_ulogic;
phyo_pio_int : out std_logic_vector(3 downto 0);
phyo_poo_ad : out std_logic_vector(31 downto 0);
phyo_poo_aden : out std_logic_vector(31 downto 0);
phyo_poo_cbe : out std_logic_vector(3 downto 0);
phyo_poo_cbeen : out std_logic_vector(3 downto 0);
phyo_poo_frame : out std_logic;
phyo_poo_frameen : out std_logic;
phyo_poo_irdy : out std_logic;
phyo_poo_irdyen : out std_logic;
phyo_poo_trdy : out std_logic;
phyo_poo_trdyen : out std_logic;
phyo_poo_stop : out std_logic;
phyo_poo_stopen : out std_logic;
phyo_poo_devsel : out std_logic;
phyo_poo_devselen : out std_logic;
phyo_poo_par : out std_logic;
phyo_poo_paren : out std_logic;
phyo_poo_perr : out std_logic;
phyo_poo_perren : out std_logic;
phyo_poo_lock : out std_logic;
phyo_poo_locken : out std_logic;
phyo_poo_req : out std_logic;
phyo_poo_reqen : out std_logic;
phyo_poo_serren : out std_logic;
phyo_poo_inten : out std_logic;
phyo_poo_vinten : out std_logic_vector(3 downto 0)
);
end component;
end;
| gpl-2.0 | 9676fe4c667be81203da4f73d385d55f | 0.536261 | 3.357976 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/gracectrl.vhd | 1 | 14,024 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: gracectrl
-- File: gracectrl.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- Contact: [email protected]
-- Description: Provides a GRLIB AMBA AHB slave interface to Xilinx System ACE
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, gaisler;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use gaisler.misc.all;
entity gracectrl is
generic (
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
haddr : integer := 16#000#; -- Base address
hmask : integer := 16#fff#; -- Area mask
split : integer range 0 to 1 := 0; -- Enable AMBA SPLIT support
swap : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0; -- Output enable polarity
mode : integer range 0 to 2 := 0 -- 0: 16-bit mode only
-- 1: 8-bit mode only
-- 2: 8-bit, emulate 16-bit
);
port (
rstn : in std_ulogic;
clk : in std_ulogic; -- System (AMBA) clock
clkace : in std_ulogic; -- System ACE clock
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
acei : in gracectrl_in_type;
aceo : out gracectrl_out_type
);
end gracectrl;
architecture rtl of gracectrl is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant REVISION : amba_version_type := 0;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_GRACECTRL, 0, REVISION, hirq),
-- 1 => conv_std_logic_vector(swap*4 + mode, 32),
4 => ahb_iobar(haddr, hmask), others => zero32);
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1);
constant INPUT : std_ulogic := not conv_std_logic(oepol = 1);
constant ACEDW : integer := 16-8*(mode mod 2);
-----------------------------------------------------------------------------
-- Functions
-----------------------------------------------------------------------------
-- purpose: swaps a hword if 'swap' is non-zero and mode is zero,
-- otherwise just propagate data
function condhswap (d : std_logic_vector)
return std_logic_vector is
variable dx : std_logic_vector(15 downto 0);
begin -- hswap
dx(ACEDW-1 downto 0) := d;
if swap /= 0 and mode = 0 then
return dx(7 downto 0) & dx(15 downto 8);
end if;
return dx;
end condhswap;
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type sys_sync_type is record
accdone : std_logic_vector(1 downto 0);
irq : std_logic_vector(2 downto 0);
end record;
type sys_reg_type is record
acc : std_ulogic; -- Perform access
active : std_ulogic; -- Access active
sync : sys_sync_type;
-- AHB
insplit : std_ulogic; -- SPLIT response issued
unsplit : std_ulogic; -- SPLIT complete not issued
irq : std_ulogic; -- Interrupt request
hwrite : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 1);
haddr : std_logic_vector(6 downto 0);
hready : std_ulogic;
wdata : std_logic_vector(ACEDW-1 downto 0);
hresp : std_logic_vector(1 downto 0);
splmst : std_logic_vector(log2(NAHBMST)-1 downto 0); -- SPLIT:ed master
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- Other SPLIT:ed masters
ahbcancel : std_ulogic; -- Locked access cancels ongoing SPLIT
-- response
end record;
type ace_state_type is (idle, en, rd, done);
type ace_sync_type is record
acc : std_logic_vector(1 downto 0);
rstn : std_logic_vector(1 downto 0);
hwrite : std_logic_vector(1 downto 0);
dummy : std_logic_vector(1 downto 0);
end record;
type ace_reg_type is record
state : ace_state_type;
sync : ace_sync_type;
accdone : std_ulogic;
rdata : std_logic_vector(ACEDW-1 downto 0);
edone : std_ulogic;
aceo : gracectrl_out_type;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : sys_reg_type;
signal s, sin : ace_reg_type;
begin -- rtl
-----------------------------------------------------------------------------
-- System clock domain
-----------------------------------------------------------------------------
combsys: process (r, s, rstn, ahbsi, acei.irq)
variable v : sys_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable hsplit : std_logic_vector(NAHBMST-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin -- process comb
v := r; v.irq := '0'; irq := (others => '0'); irq(hirq) := r.irq;
v.hresp := HRESP_OKAY; v.hready := '1'; hsplit := (others => '0');
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
-- Sync
v.sync.accdone := r.sync.accdone(0) & s.accdone;
v.sync.irq := r.sync.irq(1 downto 0) & acei.irq;
-- AHB communication
if ahbsi.hready = '1' then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hmbsel := ahbsi.hmbsel(r.hmbsel'range);
if split = 0 or (not (r.active or r.acc) or ahbsi.hmastlock) = '1' then
v.hready := '0';
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr(6 downto 0);
v.hsel := '1';
if r.insplit = '0' then
v.acc := '1';
end if;
if split /= 0 then
if ahbsi.hmastlock = '0' then
v.hresp := HRESP_SPLIT;
v.splmst := ahbsi.hmaster;
v.unsplit := '1';
else
v.ahbcancel := r.insplit;
end if;
v.insplit := not ahbsi.hmastlock;
end if;
else
-- Core is busy, transfer is not locked respond with SPLIT
v.hready := '0';
if split /= 0 then
v.hresp := HRESP_SPLIT;
v.hsplit(conv_integer(ahbsi.hmaster)) := '1';
end if;
end if;
else
v.hsel := '0';
end if;
end if;
if (r.hready = '0') then
if (r.hresp = HRESP_OKAY) then v.hready := '0';
else v.hresp := r.hresp; end if;
end if;
if r.acc = '1' then
-- Propagate data
if r.active = '0' then
if mode /= 1 then
if r.haddr(1) = '0' then v.wdata := hwdata(ACEDW+15 downto 16);
else v.wdata := hwdata(ACEDW-1 downto 0); end if;
else
case r.haddr(1 downto 0) is
when "00" => v.wdata(7 downto 0) := hwdata(31 downto 24);
when "01" => v.wdata(7 downto 0) := hwdata(23 downto 16);
when "10" => v.wdata(7 downto 0) := hwdata(15 downto 8);
when others => v.wdata(7 downto 0) := hwdata(7 downto 0);
end case;
end if;
if mode = 2 then
-- Override writes to busmode register
if r.haddr(6 downto 1) = zero32(6 downto 1) then
v.wdata := (others => '0'); -- Byte
end if;
end if;
end if;
-- Remove access signal when access is done
if r.sync.accdone(1) = '1' then
v.acc := '0';
end if;
v.active := '1';
end if;
-- AMBA response when access is complete
if r.acc = '0' and r.sync.accdone(1) = '0' and r.active = '1' then
if split /= 0 and r.unsplit = '1' then
hsplit(conv_integer(r.splmst)) := '1';
v.unsplit := '0';
end if;
if ((split = 0 or v.ahbcancel = '0') and
(split = 0 or ahbsi.hmaster = r.splmst or r.insplit = '0') and
(((ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1') or
((split = 0 or r.insplit = '0') and r.hready = '0' and r.hresp = HRESP_OKAY))) then
v.hresp := HRESP_OKAY;
if split /= 0 then
v.insplit := '0';
v.hsplit := r.hsplit;
end if;
v.hready := '1';
v.hsel := '0';
v.active := '0';
elsif split /= 0 and v.ahbcancel = '1' then
v.acc := '1';
v.ahbcancel := '0';
end if;
end if;
-- Interrupt request, not filtered, pulsed
if (not r.sync.irq(2) and r.sync.irq(1)) = '1' then
v.irq := '1';
end if;
-- Reset
if rstn = '0' then
v.acc := '0';
v.active := '0';
--
v.insplit := '0';
v.unsplit := '0';
v.hready := '1';
v.hwrite := '0';
v.hsel := '0';
v.hmbsel := (others => '0');
v.ahbcancel := '0';
end if;
if split = 0 then
v.insplit := '0';
v.unsplit := '0';
v.splmst := (others => '0');
v.hsplit := (others => '0');
v.ahbcancel := '0';
end if;
-- Update registers
rin <= v;
-- AHB slave output
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
ahbso.hrdata <= ahbdrivedata(s.rdata); -- Bad, but does not toggle much
ahbso.hconfig <= HCONFIG;
ahbso.hirq <= irq;
ahbso.hindex <= hindex;
ahbso.hsplit <= hsplit;
end process combsys;
regsys: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process regsys;
-----------------------------------------------------------------------------
-- System ACE clock domain
-----------------------------------------------------------------------------
combace: process (r, s, rstn, acei)
variable v : ace_reg_type;
begin -- process comb
v := s;
-- Synchronize inputs
v.sync.acc := s.sync.acc(0) & r.acc;
v.sync.rstn := s.sync.rstn(0) & rstn;
v.sync.hwrite := s.sync.hwrite(0) & r.hwrite;
if mode = 2 then
-- Fake reads from BUSMODE register?
v.sync.dummy := s.sync.dummy(0) & not orv(r.haddr(6 downto 1));
else
v.sync.dummy := (others => '0');
end if;
case s.state is
when idle =>
v.aceo.addr := r.haddr(6 downto 0);
if mode = 2 then v.aceo.do(7 downto 0) := r.wdata(7 downto 0);
else v.aceo.do(r.wdata'range) := condhswap(r.wdata); end if;
if s.sync.acc(1) = '1' then
v.aceo.cen := '0';
v.aceo.doen := INPUT xor r.hwrite;
v.state := en;
end if;
if mode = 2 then v.edone := '0'; end if;
when en =>
v.aceo.wen := not r.hwrite;
if s.sync.hwrite(1) = '1' then
v.state := done;
else
v.state := rd;
end if;
when rd =>
v.aceo.oen := '0';
v.state := done;
when done =>
v.aceo.oen := '1';
v.aceo.wen := '1';
if mode = 2 and s.edone = '0' then
-- Keep 16-bit address map
v.aceo.addr(0) := '1';
v.aceo.do(7 downto 0) := r.wdata(ACEDW-1 downto ACEDW-8);
v.rdata(7 downto 0) := acei.di(7 downto 0);
v.edone := '1';
v.state := en;
else
v.aceo.cen := '1';
if s.accdone = '0' then
if mode = 2 then
v.rdata(ACEDW-1 downto ACEDW-8) := acei.di(7 downto 0);
if s.sync.dummy(1) = '1' then -- Fake read
v.rdata := (others => '0'); v.rdata(0) := '1';
end if;
else
v.rdata := condhswap(acei.di)(s.rdata'range);
end if;
v.accdone := '1';
else
v.aceo.doen := INPUT;
end if;
if s.sync.acc(1) = '0' then
v.state := idle;
v.accdone := '0';
end if;
end if;
end case;
-- Reset
if s.sync.rstn(1) = '0' then
v.state := idle;
v.accdone := '0';
v.aceo.cen := '1';
v.aceo.wen := '1';
v.aceo.oen := '1';
v.aceo.doen := INPUT;
end if;
if mode = 1 then v.aceo.do(15 downto 8) := (others => '0'); end if;
if mode /= 2 then v.edone := '0'; end if;
-- Update registers
sin <= v;
-- Assign outputs to System ACE
aceo <= s.aceo;
end process combace;
regace: process (clkace)
begin -- process reg
if rising_edge(clkace) then
s <= sin;
end if;
end process regace;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"gracectrl" & tost(hindex) & ": System ACE I/F Controller, rev " &
tost(REVISION) & ", irq " & tost(hirq));
-- pragma translate_on
end rtl;
| gpl-2.0 | 45f3f30c41e9b09d6ee4bf978c0c32ae | 0.484883 | 3.760794 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/RecComp_cnn_lab_convolve_kernel_1_0/hdl/ip/convolve_kernel_ap_fadd_12_no_dsp_32.vhd | 1 | 14,039 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_5;
USE floating_point_v7_1_5.floating_point_v7_1_5;
ENTITY convolve_kernel_ap_fadd_12_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fadd_12_no_dsp_32;
ARCHITECTURE convolve_kernel_ap_fadd_12_no_dsp_32_arch OF convolve_kernel_ap_fadd_12_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_12_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_5 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_12_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_5,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_12_no_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_12_no_dsp_32,floating_point_v7_1_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_12_no_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_12_no_dsp_32,floating_point_v7_1_5,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HA" &
"S_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=12,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESE" &
"TN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNE" &
"D=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_result_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclken: SIGNAL IS "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
BEGIN
U0 : floating_point_v7_1_5
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 12,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fadd_12_no_dsp_32_arch;
| mit | aaaf9bb544418600cd2855568ccfbbb0 | 0.661016 | 3.024343 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-6/src/FIFO.vhd | 1 | 1,506 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity FIFO is
generic(
-- øèíà àäðåñà
m: integer := 2;
-- øèíà äàííûõ
n: integer := 2
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in std_logic;
-- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ
WR: in std_logic;
-- äâóíàïðàâëåííàÿ øèíà äàííûõ
DB: inout std_logic_vector (n-1 downto 0);
EMPTY: out std_logic;
FULL: out std_logic
);
end FIFO;
architecture Beh of FIFO is
-- òèï õðàíèìîãî ñëîâà
subtype word is std_logic_vector (n-1 downto 0);
-- íåïîñðåäñòâåííî òèï õðàíèëèùà äàííûõ
type tram is array (0 to 2**m - 1) of word;
signal sRAM: tram;
signal head: integer := 0;
constant Limit: integer := 2 ** m -1;
Begin
SH: process (CLK)
begin
if rising_edge(CLK) then
if (WR = '0') then
if (head <= Limit) then
head <= head + 1;
end if;
elsif (WR = '1') then
if (head > 0) then
head <= head - 1;
end if;
end if;
end if;
if (head = 0) then
empty <= '1';
full <= '0';
elsif (head = Limit + 1) then
empty <= '0';
full <= '1';
else
empty <= '0';
full <= '0';
end if;
end process;
WRP: process (head)
begin
if WR = '0' then
if (head > 0 and head <= Limit + 1) then
sRAM(head - 1) <= DB;
end if;
end if;
end process;
RDP: process(head)
begin
if WR = '1' then
if (head >= 0 and head <= Limit) then
DB <= sRAM (head);
end if;
else
DB <= (others => 'Z');
end if;
end process;
end Beh; | mit | 454f0dd518d10c54c09c289b4d566b71 | 0.587649 | 2.452769 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_0/zynq_design_1_axi_bram_ctrl_0_0_sim_netlist.vhdl | 1 | 330,721 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:42 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_0/zynq_design_1_axi_bram_ctrl_0_0_sim_netlist.vhdl
-- Design : zynq_design_1_axi_bram_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_0_SRL_FIFO is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bid_gets_fifo_load : out STD_LOGIC;
bvalid_cnt_inc : out STD_LOGIC;
bid_gets_fifo_load_d1_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
axi_wdata_full_cmb114_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\bvalid_cnt_reg[2]\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
bram_addr_ld_en : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
axi_bvalid_int_reg : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\bvalid_cnt_reg[1]\ : in STD_LOGIC;
aw_active : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
axi_wr_burst : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_0_SRL_FIFO : entity is "SRL_FIFO";
end zynq_design_1_axi_bram_ctrl_0_0_SRL_FIFO;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_0_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[11]_i_3_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_5_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_6_n_0 : STD_LOGIC;
signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC;
signal bid_fifo_ld : STD_LOGIC_VECTOR ( 11 downto 0 );
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC;
signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC;
signal \^bvalid_cnt_inc\ : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FIFO_RAM[0].SRL16E_I_i_1\ : label is "soft_lutpair44";
attribute BOX_TYPE of \FIFO_RAM[10].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[10].SRL16E_I_i_1\ : label is "soft_lutpair54";
attribute BOX_TYPE of \FIFO_RAM[11].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[11].SRL16E_I_i_1\ : label is "soft_lutpair55";
attribute BOX_TYPE of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[1].SRL16E_I_i_1\ : label is "soft_lutpair45";
attribute BOX_TYPE of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[2].SRL16E_I_i_1\ : label is "soft_lutpair46";
attribute BOX_TYPE of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[3].SRL16E_I_i_1\ : label is "soft_lutpair47";
attribute BOX_TYPE of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[4].SRL16E_I_i_1\ : label is "soft_lutpair48";
attribute BOX_TYPE of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[5].SRL16E_I_i_1\ : label is "soft_lutpair49";
attribute BOX_TYPE of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[6].SRL16E_I_i_1\ : label is "soft_lutpair50";
attribute BOX_TYPE of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[7].SRL16E_I_i_1\ : label is "soft_lutpair51";
attribute BOX_TYPE of \FIFO_RAM[8].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[8].SRL16E_I_i_1\ : label is "soft_lutpair52";
attribute BOX_TYPE of \FIFO_RAM[9].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[9].SRL16E_I_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[0]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \axi_bid_int[10]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \axi_bid_int[11]_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \axi_bid_int[1]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \axi_bid_int[2]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[3]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \axi_bid_int[4]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \axi_bid_int[5]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \axi_bid_int[6]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \axi_bid_int[7]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axi_bid_int[8]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \axi_bid_int[9]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair56";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair56";
begin
axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\;
bvalid_cnt_inc <= \^bvalid_cnt_inc\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => \axi_bid_int[11]_i_3_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_0,
Q => bid_fifo_not_empty,
R => SR(0)
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE0A"
)
port map (
I0 => bram_addr_ld_en,
I1 => Data_Exists_DFF_i_2_n_0,
I2 => Data_Exists_DFF_i_3_n_0,
I3 => bid_fifo_not_empty,
O => D_0
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFD"
)
port map (
I0 => \^bvalid_cnt_inc\,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
I3 => bvalid_cnt(1),
I4 => \^bid_gets_fifo_load_d1_reg\,
I5 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(11),
Q => bid_fifo_rd(11)
);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
O => bid_fifo_ld(11)
);
\FIFO_RAM[10].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(1),
Q => bid_fifo_rd(1)
);
\FIFO_RAM[10].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
O => bid_fifo_ld(1)
);
\FIFO_RAM[11].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(0),
Q => bid_fifo_rd(0)
);
\FIFO_RAM[11].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
O => bid_fifo_ld(0)
);
\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(10),
Q => bid_fifo_rd(10)
);
\FIFO_RAM[1].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
O => bid_fifo_ld(10)
);
\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(9),
Q => bid_fifo_rd(9)
);
\FIFO_RAM[2].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
O => bid_fifo_ld(9)
);
\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(8),
Q => bid_fifo_rd(8)
);
\FIFO_RAM[3].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
O => bid_fifo_ld(8)
);
\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(7),
Q => bid_fifo_rd(7)
);
\FIFO_RAM[4].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
O => bid_fifo_ld(7)
);
\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(6),
Q => bid_fifo_rd(6)
);
\FIFO_RAM[5].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
O => bid_fifo_ld(6)
);
\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(5),
Q => bid_fifo_rd(5)
);
\FIFO_RAM[6].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
O => bid_fifo_ld(5)
);
\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(4),
Q => bid_fifo_rd(4)
);
\FIFO_RAM[7].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
O => bid_fifo_ld(4)
);
\FIFO_RAM[8].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(3),
Q => bid_fifo_rd(3)
);
\FIFO_RAM[8].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
O => bid_fifo_ld(3)
);
\FIFO_RAM[9].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(2),
Q => bid_fifo_rd(2)
);
\FIFO_RAM[9].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
O => bid_fifo_ld(2)
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(0),
O => D(0)
);
\axi_bid_int[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(10),
O => D(10)
);
\axi_bid_int[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^bid_gets_fifo_load\,
I1 => \axi_bid_int[11]_i_3_n_0\,
O => E(0)
);
\axi_bid_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(11),
O => D(11)
);
\axi_bid_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888AAAAA8888888"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => s_axi_bready,
I3 => axi_bvalid_int_reg,
I4 => bid_gets_fifo_load_d1_i_3_n_0,
I5 => \^bvalid_cnt_inc\,
O => \axi_bid_int[11]_i_3_n_0\
);
\axi_bid_int[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(1),
O => D(1)
);
\axi_bid_int[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(2),
O => D(2)
);
\axi_bid_int[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(3),
O => D(3)
);
\axi_bid_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(4),
O => D(4)
);
\axi_bid_int[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(5),
O => D(5)
);
\axi_bid_int[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(6),
O => D(6)
);
\axi_bid_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(7),
O => D(7)
);
\axi_bid_int[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(8),
O => D(8)
);
\axi_bid_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(9),
O => D(9)
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000055FD00000000"
)
port map (
I0 => \out\(2),
I1 => \^axi_wdata_full_cmb114_out\,
I2 => axi_bvalid_int_i_4_n_0,
I3 => axi_wr_burst,
I4 => \out\(1),
I5 => axi_bvalid_int_i_5_n_0,
O => \^bvalid_cnt_inc\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FE000000"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => axi_bvalid_int_reg,
I4 => s_axi_bready,
O => \^bid_gets_fifo_load_d1_reg\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"1F11000000000000"
)
port map (
I0 => axi_bvalid_int_i_6_n_0,
I1 => \bvalid_cnt_reg[2]\,
I2 => wr_addr_sm_cs,
I3 => \bvalid_cnt_reg[2]_0\,
I4 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I5 => axi_awaddr_full,
O => axi_bvalid_int_i_4_n_0
);
axi_bvalid_int_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"74446444"
)
port map (
I0 => \out\(0),
I1 => \out\(2),
I2 => s_axi_wvalid,
I3 => s_axi_wlast,
I4 => \^axi_wdata_full_cmb114_out\,
O => axi_bvalid_int_i_5_n_0
);
axi_bvalid_int_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => curr_awlen_reg_1_or_2,
I1 => axi_awlen_pipe_1_or_2,
I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I3 => axi_awaddr_full,
I4 => last_data_ack_mod,
O => axi_bvalid_int_i_6_n_0
);
axi_wready_int_mod_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F007F007F00"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => aw_active,
I4 => s_axi_awready,
I5 => s_axi_awvalid,
O => \^axi_wdata_full_cmb114_out\
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800AA00AA00"
)
port map (
I0 => bram_addr_ld_en,
I1 => \^bid_gets_fifo_load_d1_reg\,
I2 => bid_fifo_not_empty,
I3 => \^bvalid_cnt_inc\,
I4 => \bvalid_cnt_reg[1]\,
I5 => bid_gets_fifo_load_d1_i_3_n_0,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => bid_gets_fifo_load_d1_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_0_wrap_brst is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_addr_ld_en_mod : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC;
bram_addr_ld_en : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_2\ : out STD_LOGIC;
curr_fixed_burst_reg_reg : out STD_LOGIC;
curr_wrap_burst_reg_reg : out STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
bram_addr_inc : in STD_LOGIC;
bram_addr_rst_cmb : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
aw_active : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
curr_fixed_burst : in STD_LOGIC;
curr_wrap_burst : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_0_wrap_brst : entity is "wrap_brst";
end zynq_design_1_axi_bram_ctrl_0_0_wrap_brst;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_0_wrap_brst is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^bram_addr_ld_en_mod\ : STD_LOGIC;
signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 15 downto 3 );
signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_2\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_2_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_3__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \curr_wrap_burst_reg_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_4\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3__0\ : label is "soft_lutpair57";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\;
SR(0) <= \^sr\(0);
bram_addr_ld_en <= \^bram_addr_ld_en\;
bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\;
\save_init_bram_addr_ld_reg[15]_2\ <= \^save_init_bram_addr_ld_reg[15]_2\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB8BBBBB88B88888"
)
port map (
I0 => bram_addr_ld(8),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(7),
I5 => bram_addr_a(8),
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(9),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(9),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\,
I4 => bram_addr_a(8),
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(12),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(13),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(14),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4500FFFF"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => bram_addr_inc,
I3 => bram_addr_rst_cmb,
I4 => s_axi_aresetn,
O => \^sr\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => \^bram_addr_ld_en_mod\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(15),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFFDF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => wrap_burst_total(1),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(0),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => bram_addr_a(2),
I1 => bram_addr_a(1),
I2 => wrap_burst_total(1),
I3 => bram_addr_a(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B800FFFF"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
I1 => axi_awaddr_full,
I2 => s_axi_awaddr(0),
I3 => \^bram_addr_ld_en\,
I4 => \^bram_addr_ld_en_mod\,
I5 => bram_addr_a(0),
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => bram_addr_ld(1),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(1),
I3 => bram_addr_a(0),
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BB8B8B8"
)
port map (
I0 => bram_addr_ld(2),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(2),
I3 => bram_addr_a(0),
I4 => bram_addr_a(1),
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BB8B8B8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(3),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(3),
I3 => bram_addr_a(2),
I4 => bram_addr_a(0),
I5 => bram_addr_a(1),
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => bram_addr_ld(4),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(5),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(5),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I4 => bram_addr_a(4),
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B88BB8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(6),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => bram_addr_a(4),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => bram_addr_a(5),
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => bram_addr_a(1),
I1 => bram_addr_a(0),
I2 => bram_addr_a(2),
I3 => bram_addr_a(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(7),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(6),
O => \^d\(7)
);
\curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_fixed_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_fixed_burst,
I3 => \^sr\(0),
O => curr_fixed_burst_reg_reg
);
\curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_wrap_burst,
I3 => \^sr\(0),
O => curr_wrap_burst_reg_reg
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(10),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(8),
O => bram_addr_ld(8)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(11),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(9),
O => bram_addr_ld(9)
);
\save_init_bram_addr_ld[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080808AA0808"
)
port map (
I0 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I1 => \^save_init_bram_addr_ld_reg[15]_0\,
I2 => wr_addr_sm_cs,
I3 => \^save_init_bram_addr_ld_reg[15]_1\,
I4 => last_data_ack_mod,
I5 => \^save_init_bram_addr_ld_reg[15]_2\,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"007F007F007F0000"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
I3 => aw_active,
I4 => axi_awaddr_full,
I5 => s_axi_awvalid,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[15]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => \^save_init_bram_addr_ld_reg[15]_1\
);
\save_init_bram_addr_ld[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I2 => axi_awlen_pipe_1_or_2,
I3 => curr_awlen_reg_1_or_2,
O => \^save_init_bram_addr_ld_reg[15]_2\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(1),
O => bram_addr_ld(1)
);
\save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => save_init_bram_addr_ld(3),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2__0_n_0\
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(2),
O => bram_addr_ld(2)
);
\save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => save_init_bram_addr_ld(4),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2__0_n_0\
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808F8F8F808080"
)
port map (
I0 => save_init_bram_addr_ld(5),
I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
I4 => axi_awaddr_full,
I5 => s_axi_awaddr(3),
O => bram_addr_ld(3)
);
\save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(0),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2__0_n_0\
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(4),
O => bram_addr_ld(4)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(5),
O => bram_addr_ld(5)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(8),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(6),
O => bram_addr_ld(6)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(7),
O => bram_addr_ld(7)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(8),
Q => save_init_bram_addr_ld(10),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(9),
Q => save_init_bram_addr_ld(11),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => save_init_bram_addr_ld(12),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => save_init_bram_addr_ld(13),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => save_init_bram_addr_ld(14),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => save_init_bram_addr_ld(15),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(1),
Q => save_init_bram_addr_ld(3),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(2),
Q => save_init_bram_addr_ld(4),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(3),
Q => save_init_bram_addr_ld(5),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(4),
Q => save_init_bram_addr_ld(6),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(5),
Q => save_init_bram_addr_ld(7),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(6),
Q => save_init_bram_addr_ld(8),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(7),
Q => save_init_bram_addr_ld(9),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A22200000000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => \wrap_burst_total[0]_i_3_n_0\,
I2 => Q(1),
I3 => Q(2),
I4 => \wrap_burst_total[2]_i_2__0_n_0\,
I5 => \wrap_burst_total[1]_i_2_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCA533A5FFA5FFA5"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
I5 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_awaddr_full,
I1 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_3_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08000800F3000000"
)
port map (
I0 => \wrap_burst_total[2]_i_3__0_n_0\,
I1 => axi_awaddr_full,
I2 => axi_awsize_pipe(0),
I3 => \wrap_burst_total[1]_i_2_n_0\,
I4 => \wrap_burst_total[1]_i_3_n_0\,
I5 => \wrap_burst_total[2]_i_2__0_n_0\,
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(0),
O => \wrap_burst_total[1]_i_2_n_0\
);
\wrap_burst_total[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(1),
O => \wrap_burst_total[1]_i_3_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000000088008800"
)
port map (
I0 => \wrap_burst_total[2]_i_2__0_n_0\,
I1 => s_axi_awlen(0),
I2 => Q(0),
I3 => \wrap_burst_total[2]_i_3__0_n_0\,
I4 => axi_awsize_pipe(0),
I5 => axi_awaddr_full,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(3),
O => \wrap_burst_total[2]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
O => \wrap_burst_total[2]_i_3__0_n_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => s_axi_aresetn_0(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_0_wrap_brst_0 is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_1\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_3\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_addr_ld_en : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC;
\rd_data_sm_cs_reg[1]\ : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
axi_b2b_brst_reg : out STD_LOGIC;
\rd_data_sm_cs_reg[3]\ : out STD_LOGIC;
rd_adv_buf67_out : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_araddr_full : in STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
\rd_data_sm_cs_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_rd_burst_two_reg : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
axi_aresetn_d2 : in STD_LOGIC;
rd_addr_sm_cs : in STD_LOGIC;
last_bram_addr : in STD_LOGIC;
ar_active : in STD_LOGIC;
pend_rd_op : in STD_LOGIC;
no_ar_ack : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
brst_zero : in STD_LOGIC;
axi_rvalid_int_reg : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
end_brst_rd : in STD_LOGIC;
axi_b2b_brst : in STD_LOGIC;
axi_arsize_pipe_max : in STD_LOGIC;
disable_b2b_brst : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_arlen_pipe_1_or_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_0_wrap_brst_0 : entity is "wrap_brst";
end zynq_design_1_axi_bram_ctrl_0_0_wrap_brst_0;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_0_wrap_brst_0 is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axi_b2b_brst_reg\ : STD_LOGIC;
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^rd_adv_buf67_out\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[15]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[13]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[14]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[15]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair3";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\;
SR(0) <= \^sr\(0);
axi_b2b_brst_reg <= \^axi_b2b_brst_reg\;
bram_addr_ld_en <= \^bram_addr_ld_en\;
rd_adv_buf67_out <= \^rd_adv_buf67_out\;
\rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\;
\rd_data_sm_cs_reg[3]\ <= \^rd_data_sm_cs_reg[3]\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\;
\wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\;
\wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF20FFFFDF200000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I2 => curr_fixed_burst_reg,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0F0F0E0E0FFF0"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\,
I2 => \^rd_data_sm_cs_reg[1]\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \rd_data_sm_cs_reg[3]_0\(1),
I5 => \rd_data_sm_cs_reg[3]_0\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => \rd_data_sm_cs_reg[3]_0\(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080800080"
)
port map (
I0 => \rd_data_sm_cs_reg[3]_0\(0),
I1 => axi_rvalid_int_reg,
I2 => s_axi_rready,
I3 => end_brst_rd,
I4 => axi_b2b_brst,
I5 => brst_zero,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[12]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[13]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[14]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
O => E(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[15]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A80000"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\,
I2 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I4 => curr_wrap_burst_reg,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00A000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \wrap_burst_total_reg_n_0_[1]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I4 => \wrap_burst_total_reg_n_0_[0]\,
I5 => \wrap_burst_total_reg_n_0_[2]\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A808FD5D"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => s_axi_araddr(0),
I2 => axi_araddr_full,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAFFFFA6AA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
O => \^d\(7)
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rvalid_int_reg,
I1 => s_axi_rready,
O => \^rd_adv_buf67_out\
);
axi_b2b_brst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => axi_arsize_pipe_max,
I1 => disable_b2b_brst,
I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\,
I3 => axi_arlen_pipe_1_or_2,
I4 => axi_araddr_full,
O => \^axi_b2b_brst_reg\
);
bram_en_int_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rd_data_sm_cs_reg[3]_0\(3),
I1 => \rd_data_sm_cs_reg[3]_0\(2),
O => \^rd_data_sm_cs_reg[3]\
);
bram_en_int_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => end_brst_rd,
I1 => brst_zero,
I2 => \rd_data_sm_cs_reg[3]_0\(2),
I3 => \rd_data_sm_cs_reg[3]_0\(0),
I4 => axi_rvalid_int_reg,
I5 => s_axi_rready,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\
);
bram_rst_b_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000E000F0000"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => axi_rd_burst,
I2 => \rd_data_sm_cs_reg[3]_0\(3),
I3 => \rd_data_sm_cs_reg[3]_0\(2),
I4 => \rd_data_sm_cs_reg[3]_0\(1),
I5 => \rd_data_sm_cs_reg[3]_0\(0),
O => \^rd_data_sm_cs_reg[1]\
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[10]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(8),
O => \save_init_bram_addr_ld[10]_i_1__0_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(9),
O => \save_init_bram_addr_ld[11]_i_1__0_n_0\
);
\save_init_bram_addr_ld[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"02AA0202"
)
port map (
I0 => axi_aresetn_d2,
I1 => rd_addr_sm_cs,
I2 => \save_init_bram_addr_ld[15]_i_2__0_n_0\,
I3 => \^save_init_bram_addr_ld_reg[15]_0\,
I4 => last_bram_addr,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFEFEFF"
)
port map (
I0 => ar_active,
I1 => pend_rd_op,
I2 => no_ar_ack,
I3 => s_axi_arvalid,
I4 => axi_araddr_full,
O => \save_init_bram_addr_ld[15]_i_2__0_n_0\
);
\save_init_bram_addr_ld[15]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \^axi_b2b_brst_reg\,
I1 => \rd_data_sm_cs_reg[3]_0\(0),
I2 => \rd_data_sm_cs_reg[3]_0\(1),
I3 => \^rd_data_sm_cs_reg[3]\,
I4 => brst_zero,
I5 => \^rd_adv_buf67_out\,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(1),
O => \save_init_bram_addr_ld[3]_i_1__0_n_0\
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A282"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[3]\,
I1 => \wrap_burst_total_reg_n_0_[1]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[0]\,
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(2),
O => \save_init_bram_addr_ld[4]_i_1__0_n_0\
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[4]\,
I1 => \wrap_burst_total_reg_n_0_[0]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[5]\,
I1 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
I4 => axi_araddr_full,
I5 => s_axi_araddr(3),
O => \save_init_bram_addr_ld[5]_i_1__0_n_0\
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \wrap_burst_total_reg_n_0_[0]\,
I1 => \wrap_burst_total_reg_n_0_[2]\,
I2 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[6]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(4),
O => \save_init_bram_addr_ld[6]_i_1__0_n_0\
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[7]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(5),
O => \save_init_bram_addr_ld[7]_i_1__0_n_0\
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[8]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(6),
O => \save_init_bram_addr_ld[8]_i_1__0_n_0\
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[9]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(7),
O => \save_init_bram_addr_ld[9]_i_1__0_n_0\
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[10]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[11]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => \save_init_bram_addr_ld_reg_n_0_[12]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => \save_init_bram_addr_ld_reg_n_0_[13]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => \save_init_bram_addr_ld_reg_n_0_[14]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => \save_init_bram_addr_ld_reg_n_0_[15]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[3]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[4]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[5]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[6]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[7]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[8]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[9]\,
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3202010100000000"
)
port map (
I0 => \^wrap_burst_total_reg[0]_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => \wrap_burst_total[0]_i_3__0_n_0\,
I3 => Q(2),
I4 => \^wrap_burst_total_reg[0]_2\,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_araddr_full,
I2 => s_axi_arlen(2),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
O => \wrap_burst_total[0]_i_3__0_n_0\
);
\wrap_burst_total[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
O => \^wrap_burst_total_reg[0]_2\
);
\wrap_burst_total[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_araddr_full,
I2 => s_axi_arlen(0),
O => \^wrap_burst_total_reg[0]_3\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220A880A000A880A"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => axi_arsize_pipe(0),
I2 => s_axi_arlen(3),
I3 => axi_araddr_full,
I4 => Q(3),
I5 => Q(2),
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8088008880000000"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => axi_arsize_pipe(0),
I3 => axi_araddr_full,
I4 => Q(2),
I5 => s_axi_arlen(2),
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_arlen(1),
I1 => Q(1),
I2 => s_axi_arlen(0),
I3 => axi_araddr_full,
I4 => Q(0),
O => \wrap_burst_total[2]_i_2_n_0\
);
\wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_araddr_full,
I2 => s_axi_arlen(3),
O => \^wrap_burst_total_reg[0]_1\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[0]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[1]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[2]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_0_rd_chnl is
port (
bram_rst_a : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aclk : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
axi_aresetn_d2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_aresetn_re_reg : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_0_rd_chnl : entity is "rd_chnl";
end zynq_design_1_axi_bram_ctrl_0_0_rd_chnl;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_0_rd_chnl is
signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_4_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC;
signal I_WRAP_BRST_n_1 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_26 : STD_LOGIC;
signal I_WRAP_BRST_n_27 : STD_LOGIC;
signal I_WRAP_BRST_n_28 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_6 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_i_1_n_0 : STD_LOGIC;
signal act_rd_burst_i_3_n_0 : STD_LOGIC;
signal act_rd_burst_i_4_n_0 : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal act_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal ar_active : STD_LOGIC;
signal araddr_pipe_ld43_out : STD_LOGIC;
signal axi_araddr_full : STD_LOGIC;
signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_arid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_arlen_pipe_1_or_2 : STD_LOGIC;
signal axi_arready_int : STD_LOGIC;
signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_arsize_pipe_max : STD_LOGIC;
signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst : STD_LOGIC;
signal axi_b2b_brst_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst_i_3_n_0 : STD_LOGIC;
signal axi_early_arready_int : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_i_2_n_0 : STD_LOGIC;
signal axi_rd_burst_i_3_n_0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_two_reg_n_0 : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2_full : STD_LOGIC;
signal axi_rid_temp_full : STD_LOGIC;
signal axi_rid_temp_full_d1 : STD_LOGIC;
signal axi_rlast_int_i_1_n_0 : STD_LOGIC;
signal axi_rlast_set : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC;
signal axi_rvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal \^bram_en_b\ : STD_LOGIC;
signal bram_en_int_i_10_n_0 : STD_LOGIC;
signal bram_en_int_i_11_n_0 : STD_LOGIC;
signal bram_en_int_i_1_n_0 : STD_LOGIC;
signal bram_en_int_i_2_n_0 : STD_LOGIC;
signal bram_en_int_i_3_n_0 : STD_LOGIC;
signal bram_en_int_i_4_n_0 : STD_LOGIC;
signal bram_en_int_i_6_n_0 : STD_LOGIC;
signal bram_en_int_i_7_n_0 : STD_LOGIC;
signal bram_en_int_i_9_n_0 : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal brst_cnt_max : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_one0 : STD_LOGIC;
signal brst_one_i_1_n_0 : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal brst_zero_i_1_n_0 : STD_LOGIC;
signal brst_zero_i_2_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal disable_b2b_brst_i_2_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_3_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_4_n_0 : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC;
signal end_brst_rd_i_1_n_0 : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal last_bram_addr_i_2_n_0 : STD_LOGIC;
signal last_bram_addr_i_3_n_0 : STD_LOGIC;
signal last_bram_addr_i_4_n_0 : STD_LOGIC;
signal last_bram_addr_i_5_n_0 : STD_LOGIC;
signal last_bram_addr_i_6_n_0 : STD_LOGIC;
signal last_bram_addr_i_7_n_0 : STD_LOGIC;
signal last_bram_addr_i_8_n_0 : STD_LOGIC;
signal last_bram_addr_i_9_n_0 : STD_LOGIC;
signal no_ar_ack : STD_LOGIC;
signal no_ar_ack_i_1_n_0 : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_26_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal pend_rd_op_i_1_n_0 : STD_LOGIC;
signal pend_rd_op_i_2_n_0 : STD_LOGIC;
signal pend_rd_op_i_3_n_0 : STD_LOGIC;
signal pend_rd_op_i_4_n_0 : STD_LOGIC;
signal pend_rd_op_i_5_n_0 : STD_LOGIC;
signal pend_rd_op_i_6_n_0 : STD_LOGIC;
signal pend_rd_op_i_7_n_0 : STD_LOGIC;
signal pend_rd_op_i_8_n_0 : STD_LOGIC;
signal pend_rd_op_i_9_n_0 : STD_LOGIC;
signal rd_addr_sm_cs : STD_LOGIC;
signal rd_adv_buf67_out : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC;
signal rd_data_sm_ns : STD_LOGIC;
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rddata_mux_sel_cmb : STD_LOGIC;
signal rddata_mux_sel_i_1_n_0 : STD_LOGIC;
signal rddata_mux_sel_i_3_n_0 : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of rlast_sm_cs : signal is "yes";
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[0]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[10]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[11]_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[4]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[7]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[8]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[9]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_3 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of brst_zero_i_2 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of last_bram_addr_i_4 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of last_bram_addr_i_5 : label is "soft_lutpair23";
attribute SOFT_HLUTNM of last_bram_addr_i_7 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of last_bram_addr_i_9 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of pend_rd_op_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of pend_rd_op_i_7 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of pend_rd_op_i_8 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of pend_rd_op_i_9 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_4\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_5\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_3\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair13";
begin
Q(13 downto 0) <= \^q\(13 downto 0);
bram_en_b <= \^bram_en_b\;
bram_rst_a <= \^bram_rst_a\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rvalid <= \^s_axi_rvalid\;
\/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0011001300130013"
)
port map (
I0 => axi_rd_burst,
I1 => rlast_sm_cs(1),
I2 => act_rd_burst_two,
I3 => axi_rd_burst_two_reg_n_0,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\
);
\/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F007F003F0055"
)
port map (
I0 => axi_rd_burst,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rlast_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_two,
O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\
);
\/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F111F000E000"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rlast_sm_cs(0),
I5 => last_bram_addr,
O => \/i__n_0\
);
\/i___0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080000F8080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(1),
I4 => rlast_sm_cs(2),
I5 => \^s_axi_rlast\,
O => axi_rlast_set
);
\FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(0),
O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(1),
O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A4FFFF00A40000"
)
port map (
I0 => rlast_sm_cs(1),
I1 => p_0_in13_in,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
I4 => \/i__n_0\,
I5 => rlast_sm_cs(2),
O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst,
O => p_0_in13_in
);
\FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\,
Q => rlast_sm_cs(0),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\,
Q => rlast_sm_cs(1),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\,
Q => rlast_sm_cs(2),
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEEE"
)
port map (
I0 => p_9_out,
I1 => axi_arready_int,
I2 => s_axi_arvalid,
I3 => axi_araddr_full,
I4 => araddr_pipe_ld43_out,
O => \GEN_ARREADY.axi_arready_int_i_1_n_0\
);
\GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BAAA"
)
port map (
I0 => axi_aresetn_re_reg,
I1 => axi_early_arready_int,
I2 => axi_araddr_full,
I3 => bram_addr_ld_en,
O => p_9_out
);
\GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_ARREADY.axi_arready_int_i_1_n_0\,
Q => axi_arready_int,
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\,
I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\,
I2 => rd_data_sm_cs(3),
I3 => brst_one,
I4 => axi_arready_int,
I5 => I_WRAP_BRST_n_26,
O => p_48_out
);
\GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CC304400000044"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => axi_araddr_full,
I1 => s_axi_arvalid,
O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\
);
\GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_48_out,
Q => axi_early_arready_int,
R => \^bram_rst_a\
);
\GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDCDCDDDCCCCCCCC"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => \GEN_AR_DUAL.ar_active_i_3_n_0\,
I3 => end_brst_rd,
I4 => brst_zero,
I5 => ar_active,
O => \GEN_AR_DUAL.ar_active_i_1_n_0\
);
\GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"808880808088A280"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_data_sm_cs(1),
I2 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I3 => rd_data_sm_cs(0),
I4 => axi_rd_burst_two_reg_n_0,
I5 => axi_rd_burst,
O => \GEN_AR_DUAL.ar_active_i_2_n_0\
);
\GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \GEN_AR_DUAL.ar_active_i_3_n_0\
);
\GEN_AR_DUAL.ar_active_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A88000000000000"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => brst_zero,
I2 => axi_b2b_brst,
I3 => end_brst_rd,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => \GEN_AR_DUAL.ar_active_i_4_n_0\
);
\GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.ar_active_i_1_n_0\,
Q => ar_active,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10001000F0F01000"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I4 => last_bram_addr,
I5 => I_WRAP_BRST_n_26,
O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\
);
\GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\,
Q => rd_addr_sm_cs,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(8),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(9),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(10),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(11),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(12),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(13),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(0),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(1),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(2),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(3),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(4),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(5),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(6),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(7),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C08888CCCC8888"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => s_axi_aresetn,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I4 => axi_araddr_full,
I5 => bram_addr_ld_en,
O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\,
Q => axi_araddr_full,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"03AA"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
I1 => s_axi_arburst(0),
I2 => s_axi_arburst(1),
I3 => araddr_pipe_ld43_out,
O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(0),
Q => axi_arburst_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(1),
Q => axi_arburst_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(0),
Q => axi_arid_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(10),
Q => axi_arid_pipe(10),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(11),
Q => axi_arid_pipe(11),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(1),
Q => axi_arid_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(2),
Q => axi_arid_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(3),
Q => axi_arid_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(4),
Q => axi_arid_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(5),
Q => axi_arid_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(6),
Q => axi_arid_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(7),
Q => axi_arid_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(8),
Q => axi_arid_pipe(8),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(9),
Q => axi_arid_pipe(9),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220022002A002200"
)
port map (
I0 => axi_aresetn_d2,
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I2 => rd_addr_sm_cs,
I3 => s_axi_arvalid,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I5 => axi_araddr_full,
O => araddr_pipe_ld43_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => I_WRAP_BRST_n_26,
I1 => last_bram_addr,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => no_ar_ack,
I1 => pend_rd_op,
I2 => ar_active,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(7),
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(3),
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\,
O => p_13_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_axi_arlen(5),
I1 => s_axi_arlen(4),
I2 => s_axi_arlen(2),
I3 => s_axi_arlen(6),
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => p_13_out,
Q => axi_arlen_pipe_1_or_2,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(0),
Q => axi_arlen_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(1),
Q => axi_arlen_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(2),
Q => axi_arlen_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(3),
Q => axi_arlen_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(4),
Q => axi_arlen_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(5),
Q => axi_arlen_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(6),
Q => axi_arlen_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(7),
Q => axi_arlen_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => '1',
Q => axi_arsize_pipe(1),
R => '0'
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => brst_cnt_max,
I1 => pend_rd_op,
I2 => ar_active,
I3 => brst_zero,
I4 => s_axi_aresetn,
I5 => bram_addr_ld_en,
O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\,
Q => brst_cnt_max,
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \^q\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => I_WRAP_BRST_n_23,
I3 => \^q\(5),
I4 => \^q\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_13,
Q => \^q\(8),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_12,
Q => \^q\(9),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_11,
Q => \^q\(10),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_10,
Q => \^q\(11),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_9,
Q => \^q\(12),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_8,
Q => \^q\(13),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_21,
Q => \^q\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_20,
Q => \^q\(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_19,
Q => \^q\(2),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_18,
Q => \^q\(3),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_17,
Q => \^q\(4),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_16,
Q => \^q\(5),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_15,
Q => \^q\(6),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_14,
Q => \^q\(7),
R => '0'
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_b(0),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_b(10),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_b(11),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_b(12),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_b(13),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_b(14),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_b(15),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_b(16),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_b(17),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_b(18),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_b(19),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_b(1),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\,
Q => s_axi_rdata(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_b(20),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_b(21),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_b(22),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_b(23),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_b(24),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_b(25),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_b(26),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_b(27),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_b(28),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_b(29),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_b(2),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_b(30),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414545410000404"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_b(31),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
Q => s_axi_rdata(31),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_b(3),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_b(4),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_b(5),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_b(6),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_b(7),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_b(8),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_b(9),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAEAA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(3),
O => rd_skid_buf_ld
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(0),
Q => rd_skid_buf(0),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(10),
Q => rd_skid_buf(10),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(11),
Q => rd_skid_buf(11),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(12),
Q => rd_skid_buf(12),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(13),
Q => rd_skid_buf(13),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(14),
Q => rd_skid_buf(14),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(15),
Q => rd_skid_buf(15),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(16),
Q => rd_skid_buf(16),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(17),
Q => rd_skid_buf(17),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(18),
Q => rd_skid_buf(18),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(19),
Q => rd_skid_buf(19),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(1),
Q => rd_skid_buf(1),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(20),
Q => rd_skid_buf(20),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(21),
Q => rd_skid_buf(21),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(22),
Q => rd_skid_buf(22),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(23),
Q => rd_skid_buf(23),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(24),
Q => rd_skid_buf(24),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(25),
Q => rd_skid_buf(25),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(26),
Q => rd_skid_buf(26),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(27),
Q => rd_skid_buf(27),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(28),
Q => rd_skid_buf(28),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(29),
Q => rd_skid_buf(29),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(2),
Q => rd_skid_buf(2),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(30),
Q => rd_skid_buf(30),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(31),
Q => rd_skid_buf(31),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(3),
Q => rd_skid_buf(3),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(4),
Q => rd_skid_buf(4),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(5),
Q => rd_skid_buf(5),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(6),
Q => rd_skid_buf(6),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(7),
Q => rd_skid_buf(7),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(8),
Q => rd_skid_buf(8),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(9),
Q => rd_skid_buf(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_int[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
I2 => axi_b2b_brst,
I3 => s_axi_aresetn,
O => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_rvalid_set,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => axi_b2b_brst,
O => p_4_out
);
\GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(0),
Q => s_axi_rid(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(10),
Q => s_axi_rid(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(11),
Q => s_axi_rid(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(1),
Q => s_axi_rid(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(2),
Q => s_axi_rid(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(3),
Q => s_axi_rid(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(4),
Q => s_axi_rid(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(5),
Q => s_axi_rid(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(6),
Q => s_axi_rid(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(7),
Q => s_axi_rid(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(8),
Q => s_axi_rid(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(9),
Q => s_axi_rid(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
O => axi_rid_temp20_in(0)
);
\GEN_RID.axi_rid_temp2[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
O => axi_rid_temp20_in(10)
);
\GEN_RID.axi_rid_temp2[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rid_temp_full,
I1 => bram_addr_ld_en,
O => p_26_out
);
\GEN_RID.axi_rid_temp2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
O => axi_rid_temp20_in(11)
);
\GEN_RID.axi_rid_temp2[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
O => axi_rid_temp20_in(1)
);
\GEN_RID.axi_rid_temp2[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
O => axi_rid_temp20_in(2)
);
\GEN_RID.axi_rid_temp2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
O => axi_rid_temp20_in(3)
);
\GEN_RID.axi_rid_temp2[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
O => axi_rid_temp20_in(4)
);
\GEN_RID.axi_rid_temp2[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
O => axi_rid_temp20_in(5)
);
\GEN_RID.axi_rid_temp2[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
O => axi_rid_temp20_in(6)
);
\GEN_RID.axi_rid_temp2[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
O => axi_rid_temp20_in(7)
);
\GEN_RID.axi_rid_temp2[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
O => axi_rid_temp20_in(8)
);
\GEN_RID.axi_rid_temp2[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
O => axi_rid_temp20_in(9)
);
\GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080000C8C800C0"
)
port map (
I0 => bram_addr_ld_en,
I1 => s_axi_aresetn,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full_d1,
I4 => axi_rid_temp_full,
I5 => p_4_out,
O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\,
Q => axi_rid_temp2_full,
R => '0'
);
\GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(0),
Q => axi_rid_temp2(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(10),
Q => axi_rid_temp2(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(11),
Q => axi_rid_temp2(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(1),
Q => axi_rid_temp2(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(2),
Q => axi_rid_temp2(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(3),
Q => axi_rid_temp2(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(4),
Q => axi_rid_temp2(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(5),
Q => axi_rid_temp2(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(6),
Q => axi_rid_temp2(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(7),
Q => axi_rid_temp2(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(8),
Q => axi_rid_temp2(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(9),
Q => axi_rid_temp2(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(0),
O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(10),
O => \GEN_RID.axi_rid_temp[10]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0FFA0E0"
)
port map (
I0 => p_4_out,
I1 => axi_rid_temp_full_d1,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
O => \GEN_RID.axi_rid_temp[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(11),
O => \GEN_RID.axi_rid_temp[11]_i_2_n_0\
);
\GEN_RID.axi_rid_temp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(1),
O => \GEN_RID.axi_rid_temp[1]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(2),
O => \GEN_RID.axi_rid_temp[2]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(3),
O => \GEN_RID.axi_rid_temp[3]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(4),
O => \GEN_RID.axi_rid_temp[4]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(5),
O => \GEN_RID.axi_rid_temp[5]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(6),
O => \GEN_RID.axi_rid_temp[6]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(7),
O => \GEN_RID.axi_rid_temp[7]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(8),
O => \GEN_RID.axi_rid_temp[8]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(9),
O => \GEN_RID.axi_rid_temp[9]_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rid_temp_full,
Q => axi_rid_temp_full_d1,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E000F0A0A0"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_rid_temp_full_d1,
I2 => s_axi_aresetn,
I3 => p_4_out,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2_full,
O => \GEN_RID.axi_rid_temp_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp_full_i_1_n_0\,
Q => axi_rid_temp_full,
R => '0'
);
\GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\,
Q => axi_rid_temp(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[10]_i_1_n_0\,
Q => axi_rid_temp(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[11]_i_2_n_0\,
Q => axi_rid_temp(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[1]_i_1_n_0\,
Q => axi_rid_temp(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[2]_i_1_n_0\,
Q => axi_rid_temp(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[3]_i_1_n_0\,
Q => axi_rid_temp(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[4]_i_1_n_0\,
Q => axi_rid_temp(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[5]_i_1_n_0\,
Q => axi_rid_temp(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[6]_i_1_n_0\,
Q => axi_rid_temp(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[7]_i_1_n_0\,
Q => axi_rid_temp(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[8]_i_1_n_0\,
Q => axi_rid_temp(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[9]_i_1_n_0\,
Q => axi_rid_temp(9),
R => \^bram_rst_a\
);
I_WRAP_BRST: entity work.zynq_design_1_axi_bram_ctrl_0_0_wrap_brst_0
port map (
D(13) => I_WRAP_BRST_n_8,
D(12) => I_WRAP_BRST_n_9,
D(11) => I_WRAP_BRST_n_10,
D(10) => I_WRAP_BRST_n_11,
D(9) => I_WRAP_BRST_n_12,
D(8) => I_WRAP_BRST_n_13,
D(7) => I_WRAP_BRST_n_14,
D(6) => I_WRAP_BRST_n_15,
D(5) => I_WRAP_BRST_n_16,
D(4) => I_WRAP_BRST_n_17,
D(3) => I_WRAP_BRST_n_18,
D(2) => I_WRAP_BRST_n_19,
D(1) => I_WRAP_BRST_n_20,
D(0) => I_WRAP_BRST_n_21,
E(1) => bram_addr_ld_en_mod,
E(0) => I_WRAP_BRST_n_6,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_7,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_25,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9 downto 0) => \^q\(9 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_23,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\,
Q(3 downto 0) => axi_arlen_pipe(3 downto 0),
SR(0) => \^bram_rst_a\,
ar_active => ar_active,
axi_araddr_full => axi_araddr_full,
axi_aresetn_d2 => axi_aresetn_d2,
axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2,
axi_arsize_pipe(0) => axi_arsize_pipe(1),
axi_arsize_pipe_max => axi_arsize_pipe_max,
axi_b2b_brst => axi_b2b_brst,
axi_b2b_brst_reg => I_WRAP_BRST_n_27,
axi_rd_burst => axi_rd_burst,
axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0,
axi_rvalid_int_reg => \^s_axi_rvalid\,
bram_addr_ld_en => bram_addr_ld_en,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_wrap_burst_reg => curr_wrap_burst_reg,
disable_b2b_brst => disable_b2b_brst,
end_brst_rd => end_brst_rd,
last_bram_addr => last_bram_addr,
no_ar_ack => no_ar_ack,
pend_rd_op => pend_rd_op,
rd_addr_sm_cs => rd_addr_sm_cs,
rd_adv_buf67_out => rd_adv_buf67_out,
\rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_24,
\rd_data_sm_cs_reg[3]\ => I_WRAP_BRST_n_28,
\rd_data_sm_cs_reg[3]_0\(3 downto 0) => rd_data_sm_cs(3 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_26,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_1,
\wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_2,
\wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_3,
\wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_4
);
act_rd_burst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002EEE22E2"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_set,
I2 => bram_addr_ld_en,
I3 => axi_rd_burst_two,
I4 => axi_rd_burst,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_i_1_n_0
);
act_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8A8A8"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => act_rd_burst_i_4_n_0,
I2 => axi_b2b_brst_i_3_n_0,
I3 => \rd_data_sm_cs[2]_i_4_n_0\,
I4 => last_bram_addr_i_7_n_0,
I5 => bram_addr_ld_en,
O => act_rd_burst_set
);
act_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"04000010FFFFFFFF"
)
port map (
I0 => \rd_data_sm_cs[3]_i_6_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => s_axi_aresetn,
O => act_rd_burst_i_3_n_0
);
act_rd_burst_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"4440"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
O => act_rd_burst_i_4_n_0
);
act_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_i_1_n_0,
Q => act_rd_burst,
R => '0'
);
act_rd_burst_two_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst_set,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_two_i_1_n_0
);
act_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_two_i_1_n_0,
Q => act_rd_burst_two,
R => '0'
);
axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => axi_arsize_pipe_max,
O => axi_arsize_pipe_max_i_1_n_0
);
axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_arsize_pipe_max_i_1_n_0,
Q => axi_arsize_pipe_max,
R => \^bram_rst_a\
);
axi_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC0CCC55CC0CCCCC"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => axi_b2b_brst,
I2 => disable_b2b_brst_i_2_n_0,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => axi_b2b_brst_i_3_n_0,
O => axi_b2b_brst_i_1_n_0
);
axi_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088880080"
)
port map (
I0 => \rd_data_sm_cs[0]_i_3_n_0\,
I1 => rd_adv_buf67_out,
I2 => end_brst_rd,
I3 => axi_b2b_brst,
I4 => brst_zero,
I5 => I_WRAP_BRST_n_27,
O => axi_b2b_brst_i_3_n_0
);
axi_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_b2b_brst_i_1_n_0,
Q => axi_b2b_brst,
R => \^bram_rst_a\
);
axi_rd_burst_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"303000A0"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_i_1_n_0
);
axi_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => axi_rd_burst_i_3_n_0,
I2 => I_WRAP_BRST_n_3,
I3 => \brst_cnt[7]_i_3_n_0\,
I4 => I_WRAP_BRST_n_2,
I5 => I_WRAP_BRST_n_1,
O => axi_rd_burst_i_2_n_0
);
axi_rd_burst_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arlen(5),
I1 => axi_arlen_pipe(5),
I2 => s_axi_arlen(4),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(4),
O => axi_rd_burst_i_3_n_0
);
axi_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_i_1_n_0,
Q => axi_rd_burst,
R => '0'
);
axi_rd_burst_two_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0C000A0"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst_two,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_two_i_1_n_0
);
axi_rd_burst_two_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => axi_rd_burst_two
);
axi_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_two_i_1_n_0,
Q => axi_rd_burst_two_reg_n_0,
R => '0'
);
axi_rlast_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88A8"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_rlast_set,
I2 => \^s_axi_rlast\,
I3 => s_axi_rready,
O => axi_rlast_int_i_1_n_0
);
axi_rlast_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rlast_int_i_1_n_0,
Q => \^s_axi_rlast\,
R => '0'
);
axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEEEA"
)
port map (
I0 => axi_rvalid_clr_ok,
I1 => last_bram_addr,
I2 => disable_b2b_brst,
I3 => disable_b2b_brst_cmb,
I4 => axi_rvalid_clr_ok_i_2_n_0,
I5 => axi_rvalid_clr_ok_i_3_n_0,
O => axi_rvalid_clr_ok_i_1_n_0
);
axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => axi_rvalid_clr_ok_i_2_n_0
);
axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => I_WRAP_BRST_n_26,
I1 => bram_addr_ld_en,
I2 => s_axi_aresetn,
O => axi_rvalid_clr_ok_i_3_n_0
);
axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_clr_ok_i_1_n_0,
Q => axi_rvalid_clr_ok,
R => '0'
);
axi_rvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00E0E0E0E0E0E0E0"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => axi_rvalid_set,
I2 => s_axi_aresetn,
I3 => axi_rvalid_clr_ok,
I4 => \^s_axi_rlast\,
I5 => s_axi_rready,
O => axi_rvalid_int_i_1_n_0
);
axi_rvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_int_i_1_n_0,
Q => \^s_axi_rvalid\,
R => '0'
);
axi_rvalid_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
O => axi_rvalid_set_cmb
);
axi_rvalid_set_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^bram_rst_a\
);
bram_en_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFFFEEEEE000E"
)
port map (
I0 => bram_en_int_i_2_n_0,
I1 => bram_en_int_i_3_n_0,
I2 => bram_en_int_i_4_n_0,
I3 => I_WRAP_BRST_n_28,
I4 => bram_en_int_i_6_n_0,
I5 => \^bram_en_b\,
O => bram_en_int_i_1_n_0
);
bram_en_int_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF777FFFFFFFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => act_rd_burst,
I3 => act_rd_burst_two,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_10_n_0
);
bram_en_int_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"D0D000F0D0D0F0F0"
)
port map (
I0 => \rd_data_sm_cs[3]_i_7_n_0\,
I1 => I_WRAP_BRST_n_27,
I2 => rd_data_sm_cs(1),
I3 => brst_one,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => bram_en_int_i_11_n_0
);
bram_en_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FDF50000"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(1),
I5 => bram_en_int_i_7_n_0,
O => bram_en_int_i_2_n_0
);
bram_en_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEEAFAAAAAAEE"
)
port map (
I0 => I_WRAP_BRST_n_25,
I1 => bram_addr_ld_en,
I2 => p_0_in13_in,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_3_n_0
);
bram_en_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"000F007F0000007F"
)
port map (
I0 => pend_rd_op,
I1 => rd_adv_buf67_out,
I2 => \rd_data_sm_cs[0]_i_3_n_0\,
I3 => bram_en_int_i_9_n_0,
I4 => bram_addr_ld_en,
I5 => bram_en_int_i_10_n_0,
O => bram_en_int_i_4_n_0
);
bram_en_int_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"1010111111111110"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => bram_en_int_i_11_n_0,
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_6_n_0
);
bram_en_int_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"5500050544444444"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => axi_rd_burst_two_reg_n_0,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => \rd_data_sm_cs[3]_i_7_n_0\,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_7_n_0
);
bram_en_int_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111111000"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => brst_zero,
I5 => end_brst_rd,
O => bram_en_int_i_9_n_0
);
bram_en_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_int_i_1_n_0,
Q => \^bram_en_b\,
R => \^bram_rst_a\
);
\brst_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1DDD111"
)
port map (
I0 => brst_cnt(0),
I1 => bram_addr_ld_en,
I2 => axi_arlen_pipe(0),
I3 => axi_araddr_full,
I4 => s_axi_arlen(0),
O => \brst_cnt[0]_i_1_n_0\
);
\brst_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
I3 => bram_addr_ld_en,
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[1]_i_1_n_0\
);
\brst_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_1,
I1 => bram_addr_ld_en,
I2 => brst_cnt(2),
I3 => brst_cnt(1),
I4 => brst_cnt(0),
O => \brst_cnt[2]_i_1_n_0\
);
\brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => bram_addr_ld_en,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[3]_i_1_n_0\
);
\brst_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arlen(4),
I3 => bram_addr_ld_en,
I4 => brst_cnt(4),
I5 => \brst_cnt[4]_i_2_n_0\,
O => \brst_cnt[4]_i_1_n_0\
);
\brst_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => brst_cnt(2),
I1 => brst_cnt(0),
I2 => brst_cnt(1),
I3 => brst_cnt(3),
O => \brst_cnt[4]_i_2_n_0\
);
\brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => bram_addr_ld_en,
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[5]_i_1_n_0\
);
\brst_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(6),
I3 => brst_cnt(5),
I4 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[6]_i_1_n_0\
);
\brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arlen(6),
O => \brst_cnt[6]_i_2_n_0\
);
\brst_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_7,
O => \brst_cnt[7]_i_1_n_0\
);
\brst_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB8B8B8B8"
)
port map (
I0 => \brst_cnt[7]_i_3_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(7),
I3 => brst_cnt(6),
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[7]_i_2_n_0\
);
\brst_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arlen(7),
O => \brst_cnt[7]_i_3_n_0\
);
\brst_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => brst_cnt(3),
I1 => brst_cnt(1),
I2 => brst_cnt(0),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
O => \brst_cnt[7]_i_4_n_0\
);
brst_cnt_max_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_cnt_max,
Q => brst_cnt_max_d1,
R => \^bram_rst_a\
);
\brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[0]_i_1_n_0\,
Q => brst_cnt(0),
R => \^bram_rst_a\
);
\brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[1]_i_1_n_0\,
Q => brst_cnt(1),
R => \^bram_rst_a\
);
\brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[2]_i_1_n_0\,
Q => brst_cnt(2),
R => \^bram_rst_a\
);
\brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[3]_i_1_n_0\,
Q => brst_cnt(3),
R => \^bram_rst_a\
);
\brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[4]_i_1_n_0\,
Q => brst_cnt(4),
R => \^bram_rst_a\
);
\brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[5]_i_1_n_0\,
Q => brst_cnt(5),
R => \^bram_rst_a\
);
\brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[6]_i_1_n_0\,
Q => brst_cnt(6),
R => \^bram_rst_a\
);
\brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[7]_i_2_n_0\,
Q => brst_cnt(7),
R => \^bram_rst_a\
);
brst_one_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E0EE0000"
)
port map (
I0 => brst_one,
I1 => brst_one0,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => s_axi_aresetn,
I5 => last_bram_addr_i_6_n_0,
O => brst_one_i_1_n_0
);
brst_one_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_4,
I2 => axi_rd_burst_i_2_n_0,
I3 => brst_cnt(0),
I4 => brst_cnt(1),
I5 => last_bram_addr_i_8_n_0,
O => brst_one0
);
brst_one_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_one_i_1_n_0,
Q => brst_one,
R => '0'
);
brst_zero_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => brst_zero,
I1 => last_bram_addr_i_6_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero_i_2_n_0,
O => brst_zero_i_1_n_0
);
brst_zero_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_arlen_pipe(0),
I2 => axi_araddr_full,
I3 => s_axi_arlen(0),
I4 => axi_rd_burst_i_2_n_0,
O => brst_zero_i_2_n_0
);
brst_zero_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_zero_i_1_n_0,
Q => brst_zero,
R => '0'
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arburst(0),
I1 => axi_arburst_pipe(0),
I2 => s_axi_arburst(1),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^bram_rst_a\
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_arburst(1),
I1 => axi_arburst_pipe(1),
I2 => s_axi_arburst(0),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^bram_rst_a\
);
disable_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000D0000"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst_i_2_n_0,
I5 => disable_b2b_brst_i_3_n_0,
O => disable_b2b_brst_cmb
);
disable_b2b_brst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
O => disable_b2b_brst_i_2_n_0
);
disable_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F6EF0000F6EFF6EF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(0),
I4 => disable_b2b_brst,
I5 => disable_b2b_brst_i_4_n_0,
O => disable_b2b_brst_i_3_n_0
);
disable_b2b_brst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => brst_zero,
I4 => end_brst_rd,
I5 => brst_one,
O => disable_b2b_brst_i_4_n_0
);
disable_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^bram_rst_a\
);
end_brst_rd_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFF10100000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(0),
I5 => end_brst_rd_clr,
O => end_brst_rd_clr_i_1_n_0
);
end_brst_rd_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_clr_i_1_n_0,
Q => end_brst_rd_clr,
R => \^bram_rst_a\
);
end_brst_rd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0020F020"
)
port map (
I0 => brst_cnt_max,
I1 => brst_cnt_max_d1,
I2 => s_axi_aresetn,
I3 => end_brst_rd,
I4 => end_brst_rd_clr,
O => end_brst_rd_i_1_n_0
);
end_brst_rd_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_i_1_n_0,
Q => end_brst_rd,
R => '0'
);
last_bram_addr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF1F110000"
)
port map (
I0 => last_bram_addr_i_2_n_0,
I1 => rd_data_sm_cs(2),
I2 => last_bram_addr_i_3_n_0,
I3 => last_bram_addr_i_4_n_0,
I4 => last_bram_addr_i_5_n_0,
I5 => last_bram_addr_i_6_n_0,
O => last_bram_addr0
);
last_bram_addr_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"EF00EFFFEFFFEFFF"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_adv_buf67_out,
I3 => rd_data_sm_cs(3),
I4 => bram_addr_ld_en,
I5 => last_bram_addr_i_7_n_0,
O => last_bram_addr_i_2_n_0
);
last_bram_addr_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDFFFCFFFF"
)
port map (
I0 => last_bram_addr_i_7_n_0,
I1 => I_WRAP_BRST_n_28,
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => last_bram_addr_i_3_n_0
);
last_bram_addr_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => bram_addr_ld_en,
I3 => pend_rd_op,
O => last_bram_addr_i_4_n_0
);
last_bram_addr_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"81"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
O => last_bram_addr_i_5_n_0
);
last_bram_addr_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_8_n_0,
I1 => brst_cnt(0),
I2 => brst_cnt(1),
O => last_bram_addr_i_6_n_0
);
last_bram_addr_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"02A2"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => last_bram_addr_i_7_n_0
);
last_bram_addr_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => I_WRAP_BRST_n_7,
I1 => last_bram_addr_i_9_n_0,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
I5 => brst_cnt(7),
O => last_bram_addr_i_8_n_0
);
last_bram_addr_i_9: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_cnt(6),
I1 => brst_cnt(5),
O => last_bram_addr_i_9_n_0
);
last_bram_addr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^bram_rst_a\
);
no_ar_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA88C8AAAA"
)
port map (
I0 => no_ar_ack,
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_28,
O => no_ar_ack_i_1_n_0
);
no_ar_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => no_ar_ack_i_1_n_0,
Q => no_ar_ack,
R => \^bram_rst_a\
);
pend_rd_op_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAAEFEF20AA2020"
)
port map (
I0 => pend_rd_op_i_2_n_0,
I1 => pend_rd_op_i_3_n_0,
I2 => pend_rd_op_i_4_n_0,
I3 => pend_rd_op_i_5_n_0,
I4 => pend_rd_op_i_6_n_0,
I5 => pend_rd_op,
O => pend_rd_op_i_1_n_0
);
pend_rd_op_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFCC8C80CCCC8C8"
)
port map (
I0 => p_0_in13_in,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => pend_rd_op_i_7_n_0,
O => pend_rd_op_i_2_n_0
);
pend_rd_op_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00030005"
)
port map (
I0 => pend_rd_op_i_8_n_0,
I1 => pend_rd_op_i_7_n_0,
I2 => bram_addr_ld_en,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_28,
O => pend_rd_op_i_3_n_0
);
pend_rd_op_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF00EA"
)
port map (
I0 => bram_addr_ld_en,
I1 => end_brst_rd,
I2 => ar_active,
I3 => rd_data_sm_cs(0),
I4 => pend_rd_op_i_9_n_0,
O => pend_rd_op_i_4_n_0
);
pend_rd_op_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0303070733F3FFFF"
)
port map (
I0 => p_0_in13_in,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => \^s_axi_rlast\,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => pend_rd_op_i_5_n_0
);
pend_rd_op_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => pend_rd_op_i_6_n_0
);
pend_rd_op_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ar_active,
I1 => end_brst_rd,
O => pend_rd_op_i_7_n_0
);
pend_rd_op_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => pend_rd_op,
I1 => \^s_axi_rlast\,
O => pend_rd_op_i_8_n_0
);
pend_rd_op_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"8000FFFF"
)
port map (
I0 => pend_rd_op,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => pend_rd_op_i_9_n_0
);
pend_rd_op_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => pend_rd_op_i_1_n_0,
Q => pend_rd_op,
R => \^bram_rst_a\
);
\rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF54005555"
)
port map (
I0 => \rd_data_sm_cs[0]_i_2_n_0\,
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[0]_i_3_n_0\,
I5 => \rd_data_sm_cs[0]_i_4_n_0\,
O => \rd_data_sm_cs[0]_i_1_n_0\
);
\rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAAAAAFEAAFEAA"
)
port map (
I0 => I_WRAP_BRST_n_28,
I1 => act_rd_burst_two,
I2 => act_rd_burst,
I3 => disable_b2b_brst_i_2_n_0,
I4 => bram_addr_ld_en,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[0]_i_2_n_0\
);
\rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[0]_i_3_n_0\
);
\rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000300BF0003008F"
)
port map (
I0 => rd_adv_buf67_out,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => p_0_in13_in,
O => \rd_data_sm_cs[0]_i_4_n_0\
);
\rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => I_WRAP_BRST_n_28,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(0),
I4 => I_WRAP_BRST_n_24,
I5 => \rd_data_sm_cs[1]_i_3_n_0\,
O => \rd_data_sm_cs[1]_i_1_n_0\
);
\rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0CCCCCC88888888"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => I_WRAP_BRST_n_27,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[1]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAABAEAFAAAB"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => \rd_data_sm_cs[2]_i_3_n_0\,
I4 => \rd_data_sm_cs[2]_i_4_n_0\,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => \rd_data_sm_cs[2]_i_1_n_0\
);
\rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000DF00000"
)
port map (
I0 => bram_addr_ld_en,
I1 => \rd_data_sm_cs[3]_i_6_n_0\,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(3),
O => \rd_data_sm_cs[2]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C0FFFF33F3BBBB"
)
port map (
I0 => axi_rd_burst,
I1 => rd_data_sm_cs(0),
I2 => rd_adv_buf67_out,
I3 => I_WRAP_BRST_n_27,
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => \rd_data_sm_cs[2]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[2]_i_4_n_0\
);
\rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => \rd_data_sm_cs[2]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F80FF8F8F80F080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \rd_data_sm_cs[3]_i_3_n_0\,
I3 => bram_addr_ld_en,
I4 => \rd_data_sm_cs[3]_i_4_n_0\,
I5 => \rd_data_sm_cs[3]_i_5_n_0\,
O => rd_data_sm_ns
);
\rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004050005040"
)
port map (
I0 => I_WRAP_BRST_n_28,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => \rd_data_sm_cs[3]_i_6_n_0\,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[3]_i_2_n_0\
);
\rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4052"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_3_n_0\
);
\rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0035"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_4_n_0\
);
\rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF5EFFFF"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_7_n_0\,
O => \rd_data_sm_cs[3]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FFF"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \rd_data_sm_cs[3]_i_6_n_0\
);
\rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => brst_zero,
I1 => axi_b2b_brst,
I2 => end_brst_rd,
O => \rd_data_sm_cs[3]_i_7_n_0\
);
\rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[0]_i_1_n_0\,
Q => rd_data_sm_cs(0),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[3]_i_2_n_0\,
Q => rd_data_sm_cs(3),
R => \^bram_rst_a\
);
rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1110011001100110"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => s_axi_rready,
I5 => \^s_axi_rvalid\,
O => rd_skid_buf_ld_cmb
);
rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^bram_rst_a\
);
rddata_mux_sel_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => rddata_mux_sel_cmb,
I1 => rd_data_sm_cs(3),
I2 => rddata_mux_sel_i_3_n_0,
I3 => rddata_mux_sel,
O => rddata_mux_sel_i_1_n_0
);
rddata_mux_sel_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F010F00F00F000"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
I5 => rd_adv_buf67_out,
O => rddata_mux_sel_cmb
);
rddata_mux_sel_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F700070FF70F070F"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => rddata_mux_sel_i_3_n_0
);
rddata_mux_sel_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rddata_mux_sel_i_1_n_0,
Q => rddata_mux_sel,
R => \^bram_rst_a\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_arready_int,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => axi_early_arready_int,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_0_wr_chnl is
port (
axi_aresetn_d2 : out STD_LOGIC;
axi_aresetn_re_reg : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_0_wr_chnl : entity is "wr_chnl";
end zynq_design_1_axi_bram_ctrl_0_0_wr_chnl;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_0_wr_chnl is
signal BID_FIFO_n_0 : STD_LOGIC;
signal BID_FIFO_n_10 : STD_LOGIC;
signal BID_FIFO_n_11 : STD_LOGIC;
signal BID_FIFO_n_12 : STD_LOGIC;
signal BID_FIFO_n_13 : STD_LOGIC;
signal BID_FIFO_n_14 : STD_LOGIC;
signal BID_FIFO_n_15 : STD_LOGIC;
signal BID_FIFO_n_3 : STD_LOGIC;
signal BID_FIFO_n_4 : STD_LOGIC;
signal BID_FIFO_n_5 : STD_LOGIC;
signal BID_FIFO_n_6 : STD_LOGIC;
signal BID_FIFO_n_7 : STD_LOGIC;
signal BID_FIFO_n_8 : STD_LOGIC;
signal BID_FIFO_n_9 : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC;
signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC;
signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal aw_active : STD_LOGIC;
signal \^axi_aresetn_d2\ : STD_LOGIC;
signal axi_aresetn_re : STD_LOGIC;
signal \^axi_aresetn_re_reg\ : STD_LOGIC;
signal axi_awaddr_full : STD_LOGIC;
signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_awid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_awlen_pipe_1_or_2 : STD_LOGIC;
signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_cmb114_out : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_cmb : STD_LOGIC;
signal axi_wr_burst_cmb0 : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_3_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal bram_addr_inc : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 13 downto 10 );
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal bram_addr_rst_cmb : STD_LOGIC;
signal bram_en_cmb : STD_LOGIC;
signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal bvalid_cnt_inc11_out : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal clr_bram_we_cmb : STD_LOGIC;
signal curr_awlen_reg_1_or_2 : STD_LOGIC;
signal curr_awlen_reg_1_or_20 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_3_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal delay_aw_active_clr : STD_LOGIC;
signal last_data_ack_mod : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_addr_sm_cs : STD_LOGIC;
signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of wr_data_sm_cs : signal is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair65";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair63";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair62";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair62";
begin
\GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\;
axi_aresetn_d2 <= \^axi_aresetn_d2\;
axi_aresetn_re_reg <= \^axi_aresetn_re_reg\;
bram_addr_a(13 downto 0) <= \^bram_addr_a\(13 downto 0);
s_axi_awready <= \^s_axi_awready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
BID_FIFO: entity work.zynq_design_1_axi_bram_ctrl_0_0_SRL_FIFO
port map (
D(11) => BID_FIFO_n_4,
D(10) => BID_FIFO_n_5,
D(9) => BID_FIFO_n_6,
D(8) => BID_FIFO_n_7,
D(7) => BID_FIFO_n_8,
D(6) => BID_FIFO_n_9,
D(5) => BID_FIFO_n_10,
D(4) => BID_FIFO_n_11,
D(3) => BID_FIFO_n_12,
D(2) => BID_FIFO_n_13,
D(1) => BID_FIFO_n_14,
D(0) => BID_FIFO_n_15,
E(0) => BID_FIFO_n_0,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
Q(11 downto 0) => axi_awid_pipe(11 downto 0),
SR(0) => SR(0),
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_bvalid_int_reg => \^s_axi_bvalid\,
axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => BID_FIFO_n_3,
bram_addr_ld_en => bram_addr_ld_en,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
bvalid_cnt_inc => bvalid_cnt_inc,
\bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0,
\bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_20,
\bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_19,
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_addr_sm_cs => wr_addr_sm_cs
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(0),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05051F1A"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => axi_wr_burst_cmb0,
I2 => wr_data_sm_cs(0),
I3 => axi_wdata_full_cmb114_out,
I4 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => I_WRAP_BRST_n_21,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
O => axi_wr_burst_cmb0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(1),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000554000555540"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => s_axi_wlast,
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(2),
I5 => axi_wr_burst,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44010001"
)
port map (
I0 => wr_data_sm_cs(2),
I1 => wr_data_sm_cs(1),
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7774777774744444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(0),
I5 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\,
Q => wr_data_sm_cs(0),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\,
Q => wr_data_sm_cs(1),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\,
Q => wr_data_sm_cs(2),
R => SR(0)
);
\GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_aresetn,
Q => \I_RD_CHNL/axi_aresetn_d1\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \I_RD_CHNL/axi_aresetn_d1\,
Q => \^axi_aresetn_d2\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => \I_RD_CHNL/axi_aresetn_d1\,
O => axi_aresetn_re
);
\GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_aresetn_re,
Q => \^axi_aresetn_re_reg\,
R => '0'
);
\GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBFFFFFAA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => bram_addr_ld_en,
I4 => \^axi_aresetn_re_reg\,
I5 => \^s_axi_awready\,
O => \GEN_AWREADY.axi_awready_int_i_1_n_0\
);
\GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5444444400000000"
)
port map (
I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\,
I1 => aw_active,
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => s_axi_awvalid,
O => \GEN_AWREADY.axi_awready_int_i_2_n_0\
);
\GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABABABABABABA"
)
port map (
I0 => wr_addr_sm_cs,
I1 => I_WRAP_BRST_n_21,
I2 => last_data_ack_mod,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \GEN_AWREADY.axi_awready_int_i_3_n_0\
);
\GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AWREADY.axi_awready_int_i_1_n_0\,
Q => \^s_axi_awready\,
R => SR(0)
);
\GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi_aresetn_d2\,
O => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFF0000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => wr_data_sm_cs(2),
I3 => delay_aw_active_clr,
I4 => bram_addr_ld_en,
I5 => aw_active,
O => \GEN_AW_DUAL.aw_active_i_2_n_0\
);
\GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.aw_active_i_2_n_0\,
Q => aw_active,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => p_18_out
);
\GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_18_out,
Q => last_data_ack_mod,
R => SR(0)
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000100000"
)
port map (
I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\,
I1 => wr_addr_sm_cs,
I2 => s_axi_awvalid,
I3 => axi_awaddr_full,
I4 => I_WRAP_BRST_n_20,
I5 => aw_active,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => I_WRAP_BRST_n_20,
I1 => last_data_ack_mod,
I2 => axi_awaddr_full,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => axi_awlen_pipe_1_or_2,
I5 => curr_awlen_reg_1_or_2,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\,
Q => wr_addr_sm_cs,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(8),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(9),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(10),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(11),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(12),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(13),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(0),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(1),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(2),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(3),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(4),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(5),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(6),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(7),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000EA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => s_axi_aresetn,
I4 => bram_addr_ld_en,
O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\,
Q => axi_awaddr_full,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00FF40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(0),
Q => axi_awburst_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(1),
Q => axi_awburst_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(0),
Q => axi_awid_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(10),
Q => axi_awid_pipe(10),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(11),
Q => axi_awid_pipe(11),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(1),
Q => axi_awid_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(2),
Q => axi_awid_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(3),
Q => axi_awid_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(4),
Q => axi_awid_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(5),
Q => axi_awid_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(6),
Q => axi_awid_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(7),
Q => axi_awid_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(8),
Q => axi_awid_pipe(8),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(9),
Q => axi_awid_pipe(9),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(1),
O => p_9_out
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awlen(6),
I2 => s_axi_awlen(7),
I3 => s_axi_awlen(5),
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => p_9_out,
Q => axi_awlen_pipe_1_or_2,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(0),
Q => axi_awlen_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(1),
Q => axi_awlen_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(2),
Q => axi_awlen_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(3),
Q => axi_awlen_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(4),
Q => axi_awlen_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(5),
Q => axi_awlen_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(6),
Q => axi_awlen_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(7),
Q => axi_awlen_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => '1',
Q => axi_awsize_pipe(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WRAP_BRST_n_17,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => s_axi_wvalid,
O => bram_addr_inc
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => wr_data_sm_cs(1),
O => bram_addr_rst_cmb
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_8,
Q => \^bram_addr_a\(8),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_7,
Q => \^bram_addr_a\(9),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(10),
Q => \^bram_addr_a\(10),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(11),
Q => \^bram_addr_a\(11),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(12),
Q => \^bram_addr_a\(12),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(13),
Q => \^bram_addr_a\(13),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_16,
Q => \^bram_addr_a\(0),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_15,
Q => \^bram_addr_a\(1),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_14,
Q => \^bram_addr_a\(2),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_13,
Q => \^bram_addr_a\(3),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_12,
Q => \^bram_addr_a\(4),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_11,
Q => \^bram_addr_a\(5),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_10,
Q => \^bram_addr_a\(6),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_9,
Q => \^bram_addr_a\(7),
R => I_WRAP_BRST_n_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15FF1500"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4777477444444444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => s_axi_wvalid,
O => bram_en_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_cmb,
Q => bram_en_a,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000101110"
)
port map (
I0 => wr_data_sm_cs(0),
I1 => wr_data_sm_cs(1),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I5 => axi_wr_burst,
O => clr_bram_we_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => clr_bram_we_cmb,
Q => clr_bram_we,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAFEFF02AA0200"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\,
I1 => axi_wr_burst,
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\,
I5 => delay_aw_active_clr,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222E"
)
port map (
I0 => s_axi_wlast,
I1 => wr_data_sm_cs(2),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(1),
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B338B0088008800"
)
port map (
I0 => delay_aw_active_clr,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => bvalid_cnt_inc11_out,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_wlast,
O => bvalid_cnt_inc11_out
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\,
Q => delay_aw_active_clr,
R => SR(0)
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => clr_bram_we,
I3 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(0),
Q => bram_we_a(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(1),
Q => bram_we_a(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(2),
Q => bram_we_a(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(3),
Q => bram_we_a(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.zynq_design_1_axi_bram_ctrl_0_0_wrap_brst
port map (
D(13 downto 10) => bram_addr_ld(13 downto 10),
D(9) => I_WRAP_BRST_n_7,
D(8) => I_WRAP_BRST_n_8,
D(7) => I_WRAP_BRST_n_9,
D(6) => I_WRAP_BRST_n_10,
D(5) => I_WRAP_BRST_n_11,
D(4) => I_WRAP_BRST_n_12,
D(3) => I_WRAP_BRST_n_13,
D(2) => I_WRAP_BRST_n_14,
D(1) => I_WRAP_BRST_n_15,
D(0) => I_WRAP_BRST_n_16,
E(0) => I_WRAP_BRST_n_2,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_17,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\,
Q(3 downto 0) => axi_awlen_pipe(3 downto 0),
SR(0) => I_WRAP_BRST_n_0,
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_awsize_pipe(0) => axi_awsize_pipe(1),
bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0),
bram_addr_inc => bram_addr_inc,
bram_addr_ld_en => bram_addr_ld_en,
bram_addr_ld_en_mod => bram_addr_ld_en_mod,
bram_addr_rst_cmb => bram_addr_rst_cmb,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
curr_fixed_burst => curr_fixed_burst,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_fixed_burst_reg_reg => I_WRAP_BRST_n_22,
curr_wrap_burst => curr_wrap_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
curr_wrap_burst_reg_reg => I_WRAP_BRST_n_23,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0(0) => SR(0),
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_19,
\save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_20,
\save_init_bram_addr_ld_reg[15]_2\ => I_WRAP_BRST_n_21,
wr_addr_sm_cs => wr_addr_sm_cs
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_15,
Q => s_axi_bid(0),
R => SR(0)
);
\axi_bid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_5,
Q => s_axi_bid(10),
R => SR(0)
);
\axi_bid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_4,
Q => s_axi_bid(11),
R => SR(0)
);
\axi_bid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_14,
Q => s_axi_bid(1),
R => SR(0)
);
\axi_bid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_13,
Q => s_axi_bid(2),
R => SR(0)
);
\axi_bid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_12,
Q => s_axi_bid(3),
R => SR(0)
);
\axi_bid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_11,
Q => s_axi_bid(4),
R => SR(0)
);
\axi_bid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_10,
Q => s_axi_bid(5),
R => SR(0)
);
\axi_bid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_9,
Q => s_axi_bid(6),
R => SR(0)
);
\axi_bid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_8,
Q => s_axi_bid(7),
R => SR(0)
);
\axi_bid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_7,
Q => s_axi_bid(8),
R => SR(0)
);
\axi_bid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_6,
Q => s_axi_bid(9),
R => SR(0)
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAA8A88"
)
port map (
I0 => s_axi_aresetn,
I1 => bvalid_cnt_inc,
I2 => BID_FIFO_n_3,
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => bvalid_cnt(1),
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^s_axi_bvalid\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_wr_burst_cmb,
I1 => axi_wr_burst_i_3_n_0,
I2 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"3088FCBB"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wlast,
O => axi_wr_burst_cmb
);
axi_wr_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA222"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(0),
I2 => axi_wr_burst_cmb0,
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(1),
I5 => wr_data_sm_cs(2),
O => axi_wr_burst_i_3_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => SR(0)
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EAFF00000000"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
I5 => s_axi_aresetn,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F8F9F0F0"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => axi_wdata_full_reg,
I3 => axi_wdata_full_cmb114_out,
I4 => s_axi_wvalid,
O => axi_wready_int_mod_i_3_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => SR(0)
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"95956A6A95956AAA"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5BFBF2A2A4000"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D52AFF00FF00BF00"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[0]_i_1_n_0\,
Q => bvalid_cnt(0),
R => SR(0)
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[1]_i_1_n_0\,
Q => bvalid_cnt(1),
R => SR(0)
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[2]_i_1_n_0\,
Q => bvalid_cnt(2),
R => SR(0)
);
curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00A0000000A0E0E0"
)
port map (
I0 => curr_awlen_reg_1_or_2_i_2_n_0,
I1 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I2 => curr_awlen_reg_1_or_2_i_3_n_0,
I3 => axi_awlen_pipe(3),
I4 => axi_awaddr_full,
I5 => s_axi_awlen(3),
O => curr_awlen_reg_1_or_20
);
curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => axi_awlen_pipe(7),
I1 => axi_awaddr_full,
I2 => axi_awlen_pipe(5),
I3 => axi_awlen_pipe(4),
I4 => axi_awlen_pipe(6),
O => curr_awlen_reg_1_or_2_i_2_n_0
);
curr_awlen_reg_1_or_2_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awlen(2),
I1 => axi_awlen_pipe(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => axi_awlen_pipe(1),
O => curr_awlen_reg_1_or_2_i_3_n_0
);
curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_awlen_reg_1_or_20,
Q => curr_awlen_reg_1_or_2,
R => SR(0)
);
curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_22,
Q => curr_fixed_burst_reg,
R => '0'
);
curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_23,
Q => curr_wrap_burst_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_0_full_axi is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_0_full_axi : entity is "full_axi";
end zynq_design_1_axi_bram_ctrl_0_0_full_axi;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_0_full_axi is
signal I_WR_CHNL_n_36 : STD_LOGIC;
signal axi_aresetn_d2 : STD_LOGIC;
signal axi_aresetn_re_reg : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
begin
bram_rst_a <= \^bram_rst_a\;
I_RD_CHNL: entity work.zynq_design_1_axi_bram_ctrl_0_0_rd_chnl
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36,
Q(13 downto 0) => bram_addr_b(13 downto 0),
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
I_WR_CHNL: entity work.zynq_design_1_axi_bram_ctrl_0_0_wr_chnl
port map (
\GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36,
SR(0) => \^bram_rst_a\,
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_en_a => bram_en_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl_top : entity is "axi_bram_ctrl_top";
end zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl_top;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.zynq_design_1_axi_bram_ctrl_0_0_full_axi
port map (
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_addr_b(13 downto 0) => bram_addr_b(13 downto 0),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "axi_bram_ctrl";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "yes";
end zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_rst_a\ : STD_LOGIC;
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(15 downto 2) <= \^bram_addr_a\(15 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(15 downto 2) <= \^bram_addr_b\(15 downto 2);
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \^s_axi_aclk\;
bram_rst_a <= \^bram_rst_a\;
bram_rst_b <= \^bram_rst_a\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl_top
port map (
bram_addr_a(13 downto 0) => \^bram_addr_a\(15 downto 2),
bram_addr_b(13 downto 0) => \^bram_addr_b\(15 downto 2),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(13 downto 0) => s_axi_araddr(15 downto 2),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(15 downto 2),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_axi_bram_ctrl_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_axi_bram_ctrl_0_0 : entity is "zynq_design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_bram_ctrl_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zynq_design_1_axi_bram_ctrl_0_0 : entity is "axi_bram_ctrl,Vivado 2017.2";
end zynq_design_1_axi_bram_ctrl_0_0;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_0 is
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.zynq_design_1_axi_bram_ctrl_0_0_axi_bram_ctrl
port map (
bram_addr_a(15 downto 0) => bram_addr_a(15 downto 0),
bram_addr_b(15 downto 0) => bram_addr_b(15 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => bram_clk_b,
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_rst_b => bram_rst_b,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => bram_we_b(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(15 downto 0) => s_axi_araddr(15 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(15 downto 0) => s_axi_awaddr(15 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 31c5715bcd88a2f7e339ed610682b0da | 0.545021 | 2.562418 | false | false | false | false |
khaledhassan/vhdl-examples | shift_reg/shift_reg.vhd | 1 | 2,175 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Implements a shift register of a given size.
library ieee;
use ieee.std_logic_1164.all;
entity shift_reg is
generic (
WIDTH : positive := 8
);
port (
rst : in std_logic;
clk : in std_logic;
load : in std_logic;
lsb : in std_logic;
output : out std_logic_vector(WIDTH-1 downto 0)
);
end shift_reg;
architecture BHV of shift_reg is
signal reg : std_logic_vector(WIDTH-1 downto 0);
begin
process(clk, rst, load, lsb)
begin
if(rst = '1') then
-- Reset to default value
reg <= (others => '0');
elsif(rising_edge(clk)) then
if(load = '1') then
reg <= reg(WIDTH-2 downto 0) & lsb; -- shift in the new LSB
else
reg <= reg;
end if;
end if;
end process;
-- Break out the register's value
output <= reg;
end BHV;
| mit | 3f0c63a0be469a832074f46746a6f364 | 0.650575 | 4.119318 | false | false | false | false |
thinkoco/de1_soc_opencl | de10_standard_sharedonly_vga/iface/acl_iface_system/acl_iface_system_inst.vhd | 1 | 16,752 | component acl_iface_system is
port (
config_clk_clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
kernel_clk_clk : out std_logic; -- clk
kernel_clk_snoop_clk : out std_logic; -- clk
kernel_mem0_waitrequest : out std_logic; -- waitrequest
kernel_mem0_readdata : out std_logic_vector(255 downto 0); -- readdata
kernel_mem0_readdatavalid : out std_logic; -- readdatavalid
kernel_mem0_burstcount : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
kernel_mem0_writedata : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
kernel_mem0_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
kernel_mem0_write : in std_logic := 'X'; -- write
kernel_mem0_read : in std_logic := 'X'; -- read
kernel_mem0_byteenable : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable
kernel_mem0_debugaccess : in std_logic := 'X'; -- debugaccess
kernel_reset_reset_n : out std_logic; -- reset_n
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
peripheral_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
peripheral_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
peripheral_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
peripheral_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
peripheral_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
peripheral_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
peripheral_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
peripheral_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
peripheral_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
peripheral_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
peripheral_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
peripheral_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
peripheral_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
peripheral_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
peripheral_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
peripheral_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
peripheral_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
peripheral_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
peripheral_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
peripheral_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
peripheral_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
peripheral_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
peripheral_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
peripheral_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
peripheral_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
peripheral_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
peripheral_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
peripheral_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
peripheral_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
peripheral_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
peripheral_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
peripheral_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
peripheral_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
peripheral_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
peripheral_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
peripheral_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
peripheral_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X' -- hps_io_gpio_inst_GPIO53
);
end component acl_iface_system;
u0 : component acl_iface_system
port map (
config_clk_clk => CONNECTED_TO_config_clk_clk, -- config_clk.clk
reset_n => CONNECTED_TO_reset_n, -- global_reset.reset_n
kernel_clk_clk => CONNECTED_TO_kernel_clk_clk, -- kernel_clk.clk
kernel_clk_snoop_clk => CONNECTED_TO_kernel_clk_snoop_clk, -- kernel_clk_snoop.clk
kernel_mem0_waitrequest => CONNECTED_TO_kernel_mem0_waitrequest, -- kernel_mem0.waitrequest
kernel_mem0_readdata => CONNECTED_TO_kernel_mem0_readdata, -- .readdata
kernel_mem0_readdatavalid => CONNECTED_TO_kernel_mem0_readdatavalid, -- .readdatavalid
kernel_mem0_burstcount => CONNECTED_TO_kernel_mem0_burstcount, -- .burstcount
kernel_mem0_writedata => CONNECTED_TO_kernel_mem0_writedata, -- .writedata
kernel_mem0_address => CONNECTED_TO_kernel_mem0_address, -- .address
kernel_mem0_write => CONNECTED_TO_kernel_mem0_write, -- .write
kernel_mem0_read => CONNECTED_TO_kernel_mem0_read, -- .read
kernel_mem0_byteenable => CONNECTED_TO_kernel_mem0_byteenable, -- .byteenable
kernel_mem0_debugaccess => CONNECTED_TO_kernel_mem0_debugaccess, -- .debugaccess
kernel_reset_reset_n => CONNECTED_TO_kernel_reset_reset_n, -- kernel_reset.reset_n
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
peripheral_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_peripheral_hps_io_emac1_inst_TX_CLK, -- peripheral.hps_io_emac1_inst_TX_CLK
peripheral_hps_io_emac1_inst_TXD0 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
peripheral_hps_io_emac1_inst_TXD1 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
peripheral_hps_io_emac1_inst_TXD2 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
peripheral_hps_io_emac1_inst_TXD3 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
peripheral_hps_io_emac1_inst_RXD0 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
peripheral_hps_io_emac1_inst_MDIO => CONNECTED_TO_peripheral_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
peripheral_hps_io_emac1_inst_MDC => CONNECTED_TO_peripheral_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
peripheral_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_peripheral_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
peripheral_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_peripheral_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
peripheral_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_peripheral_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
peripheral_hps_io_emac1_inst_RXD1 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
peripheral_hps_io_emac1_inst_RXD2 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
peripheral_hps_io_emac1_inst_RXD3 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
peripheral_hps_io_sdio_inst_CMD => CONNECTED_TO_peripheral_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
peripheral_hps_io_sdio_inst_D0 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
peripheral_hps_io_sdio_inst_D1 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
peripheral_hps_io_sdio_inst_CLK => CONNECTED_TO_peripheral_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
peripheral_hps_io_sdio_inst_D2 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
peripheral_hps_io_sdio_inst_D3 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
peripheral_hps_io_usb1_inst_D0 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
peripheral_hps_io_usb1_inst_D1 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
peripheral_hps_io_usb1_inst_D2 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
peripheral_hps_io_usb1_inst_D3 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
peripheral_hps_io_usb1_inst_D4 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
peripheral_hps_io_usb1_inst_D5 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
peripheral_hps_io_usb1_inst_D6 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
peripheral_hps_io_usb1_inst_D7 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
peripheral_hps_io_usb1_inst_CLK => CONNECTED_TO_peripheral_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
peripheral_hps_io_usb1_inst_STP => CONNECTED_TO_peripheral_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
peripheral_hps_io_usb1_inst_DIR => CONNECTED_TO_peripheral_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
peripheral_hps_io_usb1_inst_NXT => CONNECTED_TO_peripheral_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
peripheral_hps_io_uart0_inst_RX => CONNECTED_TO_peripheral_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
peripheral_hps_io_uart0_inst_TX => CONNECTED_TO_peripheral_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
peripheral_hps_io_i2c1_inst_SDA => CONNECTED_TO_peripheral_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
peripheral_hps_io_i2c1_inst_SCL => CONNECTED_TO_peripheral_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
peripheral_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_peripheral_hps_io_gpio_inst_GPIO53 -- .hps_io_gpio_inst_GPIO53
);
| apache-2.0 | 7aad4f9752638492d7fe8bce580961cd | 0.469138 | 3.42787 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_rst_ps7_0_100M_0/led_controller_design_rst_ps7_0_100M_0_sim_netlist.vhdl | 1 | 36,344 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:42 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_rst_ps7_0_100M_0/led_controller_design_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : led_controller_design_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_rst_ps7_0_100M_0_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_rst_ps7_0_100M_0_cdc_sync : entity is "cdc_sync";
end led_controller_design_rst_ps7_0_100M_0_cdc_sync;
architecture STRUCTURE of led_controller_design_rst_ps7_0_100M_0_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_rst_ps7_0_100M_0_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_rst_ps7_0_100M_0_cdc_sync_0 : entity is "cdc_sync";
end led_controller_design_rst_ps7_0_100M_0_cdc_sync_0;
architecture STRUCTURE of led_controller_design_rst_ps7_0_100M_0_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_rst_ps7_0_100M_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_rst_ps7_0_100M_0_upcnt_n : entity is "upcnt_n";
end led_controller_design_rst_ps7_0_100M_0_upcnt_n;
architecture STRUCTURE of led_controller_design_rst_ps7_0_100M_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_rst_ps7_0_100M_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_rst_ps7_0_100M_0_lpf : entity is "lpf";
end led_controller_design_rst_ps7_0_100M_0_lpf;
architecture STRUCTURE of led_controller_design_rst_ps7_0_100M_0_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.led_controller_design_rst_ps7_0_100M_0_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.led_controller_design_rst_ps7_0_100M_0_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_rst_ps7_0_100M_0_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_rst_ps7_0_100M_0_sequence_psr : entity is "sequence_psr";
end led_controller_design_rst_ps7_0_100M_0_sequence_psr;
architecture STRUCTURE of led_controller_design_rst_ps7_0_100M_0_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.led_controller_design_rst_ps7_0_100M_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_rst_ps7_0_100M_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of led_controller_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of led_controller_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of led_controller_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of led_controller_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of led_controller_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of led_controller_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of led_controller_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of led_controller_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of led_controller_design_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of led_controller_design_rst_ps7_0_100M_0_proc_sys_reset : entity is "proc_sys_reset";
end led_controller_design_rst_ps7_0_100M_0_proc_sys_reset;
architecture STRUCTURE of led_controller_design_rst_ps7_0_100M_0_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.led_controller_design_rst_ps7_0_100M_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.led_controller_design_rst_ps7_0_100M_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity led_controller_design_rst_ps7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of led_controller_design_rst_ps7_0_100M_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of led_controller_design_rst_ps7_0_100M_0 : entity is "led_controller_design_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of led_controller_design_rst_ps7_0_100M_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of led_controller_design_rst_ps7_0_100M_0 : entity is "proc_sys_reset,Vivado 2017.3";
end led_controller_design_rst_ps7_0_100M_0;
architecture STRUCTURE of led_controller_design_rst_ps7_0_100M_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.led_controller_design_rst_ps7_0_100M_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
| mit | 062532323ed24ddcc06f2b71459ec7ed | 0.592037 | 2.884444 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-clock-gate/config.vhd | 1 | 7,709 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (2);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000017#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 1;
constant CFG_GPT_WDOG : integer := 16#FFFF#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (12);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 73cd9435a14993d627343f3ddf4cc835 | 0.648852 | 3.600654 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ipshared/9183/hdl/axi_bram_ctrl_v4_0_rfs.vhd | 3 | 985,166 | -------------------------------------------------------------------------------
-- SRL_FIFO entity and architecture
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2013 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2001-05-11 First Version
-- KC 2001-06-20 Added Addr as an output port, for use as an occupancy
-- value
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
--
-- DET 1/17/2008 v4_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end entity SRL_FIFO;
architecture IMP of SRL_FIFO is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
buffer_Full <= '1' when (addr_i = "1111") else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
Addr <= addr_i;
end process;
end architecture IMP;
-------------------------------------------------------------------------------
-- axi_bram_ctrl_funcs.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: axi_bram_ctrl_funcs.vhd
--
-- Description: Support functions for axi_bram_ctrl library modules.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
--
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/16/2011 v1.03a
-- ~~~~~~
-- Update ECC size on 128-bit data width configuration.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Add MIG functions for Hsiao ECC.
-- ^^^^^^
-- JLJ 2/24/2011 v1.03a
-- ~~~~~~
-- Add Find_ECC_Size function.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Add REDUCTION_OR function.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Recode Create_Size_Max with a case statement.
-- ^^^^^^
-- JLJ 3/31/2011 v1.03a
-- ~~~~~~
-- Add coverage tags.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Remove Family_To_LUT_Size function.
-- Remove String_To_Family function.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package axi_bram_ctrl_funcs is
type TARGET_FAMILY_TYPE is (
-- pragma xilinx_rtl_off
SPARTAN3,
VIRTEX4,
VIRTEX5,
SPARTAN3E,
SPARTAN3A,
SPARTAN3AN,
SPARTAN3Adsp,
SPARTAN6,
VIRTEX6,
VIRTEX7,
KINTEX7,
-- pragma xilinx_rtl_on
RTL
);
-- function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
-- Get the maximum number of inputs to a LUT.
-- function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer;
function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN;
function log2(x : natural) return integer;
function Int_ECC_Size (i: integer) return integer;
function Find_ECC_Size (i: integer; j: integer) return integer;
function Find_ECC_Full_Bit_Size (i: integer; j: integer) return integer;
function Create_Size_Max (i: integer) return std_logic_vector;
function REDUCTION_OR (A: in std_logic_vector) return std_logic;
function REDUCTION_XOR (A: in std_logic_vector) return std_logic;
function REDUCTION_NOR (A: in std_logic_vector) return std_logic;
function BOOLEAN_TO_STD_LOGIC (A: in BOOLEAN) return std_logic;
end package axi_bram_ctrl_funcs;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body axi_bram_ctrl_funcs is
-------------------------------------------------------------------------------
-- Function: Int_ECC_Size
-- Purpose: Determine internal size of ECC when enabled.
-------------------------------------------------------------------------------
function Int_ECC_Size (i: integer) return integer is
begin
--coverage off
if (i = 32) then
return 7; -- 7-bits ECC for 32-bit data
-- ECC port size fixed @ 8-bits
elsif (i = 64) then
return 8;
elsif (i = 128) then
return 9; -- Hsiao is 9-bits for 128-bit data.
else
return 0;
end if;
--coverage on
end Int_ECC_Size;
-------------------------------------------------------------------------------
-- Function: Find_ECC_Size
-- Purpose: Determine external size of ECC signals when enabled.
-------------------------------------------------------------------------------
function Find_ECC_Size (i: integer; j: integer) return integer is
begin
--coverage off
if (i = 1) then
if (j = 32) then
return 8; -- Keep at 8 for port size matchings
-- Only 7-bits ECC per 32-bit data
elsif (j = 64) then
return 8;
elsif (j = 128) then
return 9;
else
return 0;
end if;
else
return 0;
-- ECC data width = 0 when C_ECC = 0 (disabled)
end if;
--coverage on
end Find_ECC_Size;
-------------------------------------------------------------------------------
-- Function: Find_ECC_Full_Bit_Size
-- Purpose: Determine external size of ECC signals when enabled in bytes.
-------------------------------------------------------------------------------
function Find_ECC_Full_Bit_Size (i: integer; j: integer) return integer is
begin
--coverage off
if (i = 1) then
if (j = 32) then
return 8;
elsif (j = 64) then
return 8;
elsif (j = 128) then
return 16;
else
return 0;
end if;
else
return 0;
-- ECC data width = 0 when C_ECC = 0 (disabled)
end if;
--coverage on
end Find_ECC_Full_Bit_Size;
-------------------------------------------------------------------------------
-- Function: Create_Size_Max
-- Purpose: Create maximum value for AxSIZE based on AXI data bus width.
-------------------------------------------------------------------------------
function Create_Size_Max (i: integer)
return std_logic_vector is
variable size_vector : std_logic_vector (2 downto 0);
begin
case (i) is
when 32 => size_vector := "010"; -- 2h (4 bytes)
when 64 => size_vector := "011"; -- 3h (8 bytes)
when 128 => size_vector := "100"; -- 4h (16 bytes)
when 256 => size_vector := "101"; -- 5h (32 bytes)
when 512 => size_vector := "110"; -- 5h (32 bytes)
when 1024 => size_vector := "111"; -- 5h (32 bytes)
--coverage off
when others => size_vector := "000"; -- 0h
--coverage on
end case;
return (size_vector);
end function Create_Size_Max;
-------------------------------------------------------------------------------
-- Function: REDUCTION_OR
-- Purpose: New in v1.03a
-------------------------------------------------------------------------------
function REDUCTION_OR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
-------------------------------------------------------------------------------
-- Function: REDUCTION_XOR
-- Purpose: Derived from MIG v3.7 ecc_gen module for use by Hsiao ECC.
-- New in v1.03a
-------------------------------------------------------------------------------
function REDUCTION_XOR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp xor A(i);
end loop;
return tmp;
end function REDUCTION_XOR;
-------------------------------------------------------------------------------
-- Function: REDUCTION_NOR
-- Purpose: Derived from MIG v3.7 ecc_dec_fix module for use by Hsiao ECC.
-- New in v1.03a
-------------------------------------------------------------------------------
function REDUCTION_NOR (A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return not tmp;
end function REDUCTION_NOR;
-------------------------------------------------------------------------------
-- Function: BOOLEAN_TO_STD_LOGIC
-- Purpose: Derived from MIG v3.7 ecc_dec_fix module for use by Hsiao ECC.
-- New in v1.03a
-------------------------------------------------------------------------------
function BOOLEAN_TO_STD_LOGIC (A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
-------------------------------------------------------------------------------
function LowerCase_Char(char : character) return character is
begin
--coverage off
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
--coverage on
end LowerCase_Char;
-------------------------------------------------------------------------------
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function Equal_String ( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
--coverage off
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
--coverage on
RETURN equal;
END Equal_String;
-------------------------------------------------------------------------------
-- Remove usage of C_FAMILY.
-- Remove usage of String_To_Family function.
--
--
-- function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
-- begin -- function String_To_Family
--
-- --coverage off
--
-- if ((Select_RTL) or Equal_String(S, "rtl")) then
-- return RTL;
-- elsif Equal_String(S, "spartan3") or Equal_String(S, "aspartan3") then
-- return SPARTAN3;
-- elsif Equal_String(S, "spartan3E") or Equal_String(S, "aspartan3E") then
-- return SPARTAN3E;
-- elsif Equal_String(S, "spartan3A") or Equal_String(S, "aspartan3A") then
-- return SPARTAN3A;
-- elsif Equal_String(S, "spartan3AN") then
-- return SPARTAN3AN;
-- elsif Equal_String(S, "spartan3Adsp") or Equal_String(S, "aspartan3Adsp") then
-- return SPARTAN3Adsp;
-- elsif Equal_String(S, "spartan6") or Equal_String(S, "spartan6l") or
-- Equal_String(S, "qspartan6") or Equal_String(S, "aspartan6") or Equal_String(S, "qspartan6l") then
-- return SPARTAN6;
-- elsif Equal_String(S, "virtex4") or Equal_String(S, "qvirtex4")
-- or Equal_String(S, "qrvirtex4") then
-- return VIRTEX4;
-- elsif Equal_String(S, "virtex5") or Equal_String(S, "qrvirtex5") then
-- return VIRTEX5;
-- elsif Equal_String(S, "virtex6") or Equal_String(S, "virtex6l") or Equal_String(S, "qvirtex6") then
-- return VIRTEX6;
-- elsif Equal_String(S, "virtex7") then
-- return VIRTEX7;
-- elsif Equal_String(S, "kintex7") then
-- return KINTEX7;
--
-- --coverage on
--
-- else
-- -- assert (false) report "No known target family" severity failure;
-- return RTL;
-- end if;
--
-- end function String_To_Family;
-------------------------------------------------------------------------------
-- Remove usage of C_FAMILY.
-- Remove usage of Family_To_LUT_Size function.
--
-- function Family_To_LUT_Size (Family : TARGET_FAMILY_TYPE) return integer is
-- begin
--
-- --coverage off
--
-- if (Family = SPARTAN3) or (Family = SPARTAN3E) or (Family = SPARTAN3A) or
-- (Family = SPARTAN3AN) or (Family = SPARTAN3Adsp) or (Family = VIRTEX4) then
-- return 4;
-- end if;
--
-- return 6;
--
-- --coverage on
--
-- end function Family_To_LUT_Size;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
--coverage off
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
--coverage on
end function log2;
-------------------------------------------------------------------------------
end package body axi_bram_ctrl_funcs;
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: coregen_comp_defs.vhd
-- Version: initial
-- Description:
-- Component declarations for all black box netlists generated by
-- running COREGEN and AXI BRAM CTRL when XST elaborated the client core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- coregen_comp_defs.vhd
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE coregen_comp_defs IS
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v8_3_6
-- Component declaration for blk_mem_gen_v8_3_6 pulled from the blk_mem_gen_v8_3_6.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v8_3_6
generic (
----------------------------------------------------------------------------
-- Generic Declarations
----------------------------------------------------------------------------
--Device Family & Elaboration Directory Parameters:
C_FAMILY : STRING := "virtex4";
C_XDEVICEFAMILY : STRING := "virtex4";
-- C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_AXI_TYPE : INTEGER := 1;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
--General Memory Parameters:
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 9;
C_ALGORITHM : INTEGER := 0;
C_PRIM_TYPE : INTEGER := 3;
--Memory Initialization Parameters:
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "111111111";
C_RST_TYPE : STRING := "SYNC";
--Port A Parameters:
--Reset Parameters:
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_A : INTEGER := 4;
C_READ_WIDTH_A : INTEGER := 4;
C_WRITE_DEPTH_A : INTEGER := 4096;
C_READ_DEPTH_A : INTEGER := 4096;
C_ADDRA_WIDTH : INTEGER := 12;
--Port B Parameters:
--Reset Parameters:
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "0";
--Enable Parameters:
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
--Byte Write Enable Parameters:
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
--Write Mode:
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
--Data-Addr Width Parameters:
C_WRITE_WIDTH_B : INTEGER := 4;
C_READ_WIDTH_B : INTEGER := 4;
C_WRITE_DEPTH_B : INTEGER := 4096;
C_READ_DEPTH_B : INTEGER := 4096;
C_ADDRB_WIDTH : INTEGER := 12;
--Output Registers/ Pipelining Parameters:
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
--Input/Output Registers for SoftECC :
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
--ECC Parameters
C_USE_ECC : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
--Simulation Model Parameters:
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 0;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
----------------------------------------------------------------------------
-- Input and Output Declarations
----------------------------------------------------------------------------
-- Native BMG Input and Output Port Declarations
--Port A:
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '0';
REGCEA : IN STD_LOGIC := '0';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
--Port B:
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '0';
REGCEB : IN STD_LOGIC := '0';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
--ECC:
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT; --blk_mem_gen_v8_3_6
END coregen_comp_defs;
-------------------------------------------------------------------------------
-- axi_lite_if.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_if.vhd
--
-- Description: Derived AXI-Lite interface module.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity axi_lite_if is
generic (
-- AXI4-Lite slave generics
-- C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
-- C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 4; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- lmb_bram_if_cntlr signals
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end entity axi_lite_if;
library unisim;
use unisim.vcomponents.all;
architecture IMP of axi_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal new_write_access : std_logic;
signal new_read_access : std_logic;
signal ongoing_write : std_logic;
signal ongoing_read : std_logic;
signal S_AXI_RVALID_i : std_logic;
signal RegRdData_i : std_logic_vector(C_DWIDTH - 1 downto 0);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (AR/AW/W)
-----------------------------------------------------------------------------
-- Detect new transaction.
-- Only allow one access at a time
new_write_access <= not (ongoing_read or ongoing_write) and S_AXI_AWVALID and S_AXI_WVALID;
new_read_access <= not (ongoing_read or ongoing_write) and S_AXI_ARVALID and not new_write_access;
-- Acknowledge new transaction.
S_AXI_AWREADY <= new_write_access;
S_AXI_WREADY <= new_write_access;
S_AXI_ARREADY <= new_read_access;
-- Store register address and write data
Reg: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
RegAddr <= (others => '0');
RegWrData <= (others => '0');
elsif new_write_access = '1' then
RegAddr <= S_AXI_AWADDR(C_REGADDR_WIDTH-1+2 downto 2);
RegWrData <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
elsif new_read_access = '1' then
RegAddr <= S_AXI_ARADDR(C_REGADDR_WIDTH-1+2 downto 2);
end if;
end if;
end process Reg;
-- Handle write access.
WriteAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_write <= '0';
elsif new_write_access = '1' then
ongoing_write <= '1';
elsif ongoing_write = '1' and S_AXI_BREADY = '1' then
ongoing_write <= '0';
end if;
RegWr <= new_write_access;
end if;
end process WriteAccess;
S_AXI_BVALID <= ongoing_write;
S_AXI_BRESP <= (others => '0');
-- Handle read access
ReadAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
elsif new_read_access = '1' then
ongoing_read <= '1';
S_AXI_RVALID_i <= '0';
elsif ongoing_read = '1' then
if S_AXI_RREADY = '1' and S_AXI_RVALID_i = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
else
S_AXI_RVALID_i <= '1'; -- Asserted one cycle after ongoing_read to match S_AXI_RDDATA
end if;
end if;
end if;
end process ReadAccess;
S_AXI_RVALID <= S_AXI_RVALID_i;
S_AXI_RRESP <= (others => '0');
Not_All_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
begin
S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0');
end generate Not_All_Bits_Are_Used;
RegRdData_i <= RegRdData; -- Swap to - downto
S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
begin
S_AXI_RDATA_FDRE : FDRE
port map (
Q => S_AXI_RDATA(I),
C => LMB_Clk,
CE => ongoing_read,
D => RegRdData_i(I),
R => LMB_Rst);
end generate S_AXI_RDATA_DFF;
end architecture IMP;
-------------------------------------------------------------------------------
-- checkbit_handler_64.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: checkbit_handler_64.vhd
--
-- Description: Generates the ECC checkbits for the input vector of
-- 64-bit data widths.
--
-- VHDL-Standard: VHDL'93/02
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity checkbit_handler_64 is
generic (
C_ENCODE : boolean := true;
C_REG : boolean := false;
C_USE_LUT6 : boolean := true);
port (
Clk : in std_logic;
DataIn : in std_logic_vector (63 downto 0);
CheckIn : in std_logic_vector (7 downto 0);
CheckOut : out std_logic_vector (7 downto 0);
Syndrome : out std_logic_vector (7 downto 0);
Syndrome_7 : out std_logic_vector (11 downto 0);
Syndrome_Chk : in std_logic_vector (0 to 7);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler_64;
library unisim;
use unisim.vcomponents.all;
-- library axi_bram_ctrl_v1_02_a;
-- use axi_bram_ctrl_v1_02_a.all;
architecture IMP of checkbit_handler_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
component XOR18 is
generic (
C_USE_LUT6 : boolean);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
-- component ParityEnable
-- generic (
-- C_USE_LUT6 : boolean;
-- C_SIZE : integer);
-- port (
-- InA : in std_logic_vector(0 to C_SIZE - 1);
-- Enable : in std_logic;
-- Res : out std_logic);
-- end component ParityEnable;
signal data_chk0 : std_logic_vector(0 to 34);
signal data_chk1 : std_logic_vector(0 to 34);
signal data_chk2 : std_logic_vector(0 to 34);
signal data_chk3 : std_logic_vector(0 to 30);
signal data_chk4 : std_logic_vector(0 to 30);
signal data_chk5 : std_logic_vector(0 to 30);
signal data_chk6 : std_logic_vector(0 to 6);
signal data_chk6_xor : std_logic;
-- signal data_chk7_a : std_logic_vector(0 to 17);
-- signal data_chk7_b : std_logic_vector(0 to 17);
-- signal data_chk7_i : std_logic;
-- signal data_chk7_xor : std_logic;
-- signal data_chk7_i_xor : std_logic;
-- signal data_chk7_a_xor : std_logic;
-- signal data_chk7_b_xor : std_logic;
begin -- architecture IMP
-- Add bits for 64-bit ECC
-- 0 <= 0 1 3 4 6 8 10 11 13 17 19 21 23 25 26 28 30
-- 32 34 36 38 40 42 44 46 48 50 52 54 56 57 59 61 63
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30) &
DataIn(32) & DataIn(34) & DataIn(36) & DataIn(38) & DataIn(40) &
DataIn(42) & DataIn(44) & DataIn(46) & DataIn(48) & DataIn(50) &
DataIn(52) & DataIn(54) & DataIn(56) & DataIn(57) & DataIn(59) &
DataIn(61) & DataIn(63) ;
-- 18 + 17 = 35
---------------------------------------------------------------------------
-- 1 <= 0 2 3 5 6 9 10 12 13 16 17 20 21 24 25 27 28 31
-- 32 35 36 39 40 43 44 47 48 51 52 55 56 58 59 62 63
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31) &
DataIn(32) & DataIn(35) & DataIn(36) & DataIn(39) & DataIn(40) &
DataIn(43) & DataIn(44) & DataIn(47) & DataIn(48) & DataIn(51) &
DataIn(52) & DataIn(55) & DataIn(56) & DataIn(58) & DataIn(59) &
DataIn(62) & DataIn(63) ;
-- 18 + 17 = 35
---------------------------------------------------------------------------
-- 2 <= 1 2 3 7 8 9 10 14 15 16 17 22 23 24 25 29 30 31
-- 32 37 38 39 40 45 46 47 48 53 54 55 56 60 61 62 63
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31) &
DataIn(32) & DataIn(37) & DataIn(38) & DataIn(39) & DataIn(40) & DataIn(45) &
DataIn(46) & DataIn(47) & DataIn(48) & DataIn(53) & DataIn(54) & DataIn(55) &
DataIn(56) & DataIn(60) & DataIn(61) & DataIn(62) & DataIn(63) ;
-- 18 + 17 = 35
---------------------------------------------------------------------------
-- 3 <= 4 5 6 7 8 9 10 18 19 20 21 22 23 24 25
-- 33 34 35 36 37 38 39 40 49 50 51 52 53 54 55 56
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) &
DataIn(33) & DataIn(34) & DataIn(35) & DataIn(36) & DataIn(37) & DataIn(38) & DataIn(39) &
DataIn(40) & DataIn(49) & DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) &
DataIn(55) & DataIn(56) ;
-- 15 + 16 = 31
---------------------------------------------------------------------------
-- 4 <= 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
-- 41-56
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) &
DataIn(41) & DataIn(42) & DataIn(43) & DataIn(44) & DataIn(45) & DataIn(46) & DataIn(47) &
DataIn(48) & DataIn(49) & DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) &
DataIn(55) & DataIn(56) ;
-- 15 + 16 = 31
---------------------------------------------------------------------------
-- 5 <= 26 - 31
-- 32 - 56
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31) &
DataIn(32) & DataIn(33) & DataIn(34) & DataIn(35) & DataIn(36) & DataIn(37) &
DataIn(38) & DataIn(39) & DataIn(40) & DataIn(41) & DataIn(42) & DataIn(43) &
DataIn(44) & DataIn(45) & DataIn(46) & DataIn(47) & DataIn(48) & DataIn(49) &
DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) & DataIn(55) &
DataIn(56) ;
-- 18 + 13 = 31
---------------------------------------------------------------------------
-- New additional checkbit for 64-bit data
-- 6 <= 57 - 63
data_chk6 <= DataIn(57) & DataIn(58) & DataIn(59) & DataIn(60) & DataIn(61) & DataIn(62) &
DataIn(63) ;
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
-- signal data_chk0_i : std_logic_vector(0 to 17);
-- signal data_chk0_xor : std_logic;
-- signal data_chk0_i_xor : std_logic;
-- signal data_chk1_i : std_logic_vector(0 to 17);
-- signal data_chk1_xor : std_logic;
-- signal data_chk1_i_xor : std_logic;
-- signal data_chk2_i : std_logic_vector(0 to 17);
-- signal data_chk2_xor : std_logic;
-- signal data_chk2_i_xor : std_logic;
-- signal data_chk3_i : std_logic_vector(0 to 17);
-- signal data_chk3_xor : std_logic;
-- signal data_chk3_i_xor : std_logic;
-- signal data_chk4_i : std_logic_vector(0 to 17);
-- signal data_chk4_xor : std_logic;
-- signal data_chk4_i_xor : std_logic;
-- signal data_chk5_i : std_logic_vector(0 to 17);
-- signal data_chk5_xor : std_logic;
-- signal data_chk5_i_xor : std_logic;
-- signal data_chk6_i : std_logic;
-- signal data_chk0_xor_reg : std_logic;
-- signal data_chk0_i_xor_reg : std_logic;
-- signal data_chk1_xor_reg : std_logic;
-- signal data_chk1_i_xor_reg : std_logic;
-- signal data_chk2_xor_reg : std_logic;
-- signal data_chk2_i_xor_reg : std_logic;
-- signal data_chk3_xor_reg : std_logic;
-- signal data_chk3_i_xor_reg : std_logic;
-- signal data_chk4_xor_reg : std_logic;
-- signal data_chk4_i_xor_reg : std_logic;
-- signal data_chk5_xor_reg : std_logic;
-- signal data_chk5_i_xor_reg : std_logic;
-- signal data_chk6_i_reg : std_logic;
-- signal data_chk7_a_xor_reg : std_logic;
-- signal data_chk7_b_xor_reg : std_logic;
-- Checkbit (0)
signal data_chk0_a : std_logic_vector (0 to 5);
signal data_chk0_b : std_logic_vector (0 to 5);
signal data_chk0_c : std_logic_vector (0 to 5);
signal data_chk0_d : std_logic_vector (0 to 5);
signal data_chk0_e : std_logic_vector (0 to 5);
signal data_chk0_f : std_logic_vector (0 to 4);
signal data_chk0_a_xor : std_logic;
signal data_chk0_b_xor : std_logic;
signal data_chk0_c_xor : std_logic;
signal data_chk0_d_xor : std_logic;
signal data_chk0_e_xor : std_logic;
signal data_chk0_f_xor : std_logic;
signal data_chk0_a_xor_reg : std_logic;
signal data_chk0_b_xor_reg : std_logic;
signal data_chk0_c_xor_reg : std_logic;
signal data_chk0_d_xor_reg : std_logic;
signal data_chk0_e_xor_reg : std_logic;
signal data_chk0_f_xor_reg : std_logic;
-- Checkbit (1)
signal data_chk1_a : std_logic_vector (0 to 5);
signal data_chk1_b : std_logic_vector (0 to 5);
signal data_chk1_c : std_logic_vector (0 to 5);
signal data_chk1_d : std_logic_vector (0 to 5);
signal data_chk1_e : std_logic_vector (0 to 5);
signal data_chk1_f : std_logic_vector (0 to 4);
signal data_chk1_a_xor : std_logic;
signal data_chk1_b_xor : std_logic;
signal data_chk1_c_xor : std_logic;
signal data_chk1_d_xor : std_logic;
signal data_chk1_e_xor : std_logic;
signal data_chk1_f_xor : std_logic;
signal data_chk1_a_xor_reg : std_logic;
signal data_chk1_b_xor_reg : std_logic;
signal data_chk1_c_xor_reg : std_logic;
signal data_chk1_d_xor_reg : std_logic;
signal data_chk1_e_xor_reg : std_logic;
signal data_chk1_f_xor_reg : std_logic;
-- Checkbit (2)
signal data_chk2_a : std_logic_vector (0 to 5);
signal data_chk2_b : std_logic_vector (0 to 5);
signal data_chk2_c : std_logic_vector (0 to 5);
signal data_chk2_d : std_logic_vector (0 to 5);
signal data_chk2_e : std_logic_vector (0 to 5);
signal data_chk2_f : std_logic_vector (0 to 4);
signal data_chk2_a_xor : std_logic;
signal data_chk2_b_xor : std_logic;
signal data_chk2_c_xor : std_logic;
signal data_chk2_d_xor : std_logic;
signal data_chk2_e_xor : std_logic;
signal data_chk2_f_xor : std_logic;
signal data_chk2_a_xor_reg : std_logic;
signal data_chk2_b_xor_reg : std_logic;
signal data_chk2_c_xor_reg : std_logic;
signal data_chk2_d_xor_reg : std_logic;
signal data_chk2_e_xor_reg : std_logic;
signal data_chk2_f_xor_reg : std_logic;
-- Checkbit (3)
signal data_chk3_a : std_logic_vector (0 to 5);
signal data_chk3_b : std_logic_vector (0 to 5);
signal data_chk3_c : std_logic_vector (0 to 5);
signal data_chk3_d : std_logic_vector (0 to 5);
signal data_chk3_e : std_logic_vector (0 to 5);
signal data_chk3_a_xor : std_logic;
signal data_chk3_b_xor : std_logic;
signal data_chk3_c_xor : std_logic;
signal data_chk3_d_xor : std_logic;
signal data_chk3_e_xor : std_logic;
signal data_chk3_f_xor : std_logic;
signal data_chk3_a_xor_reg : std_logic;
signal data_chk3_b_xor_reg : std_logic;
signal data_chk3_c_xor_reg : std_logic;
signal data_chk3_d_xor_reg : std_logic;
signal data_chk3_e_xor_reg : std_logic;
signal data_chk3_f_xor_reg : std_logic;
-- Checkbit (4)
signal data_chk4_a : std_logic_vector (0 to 5);
signal data_chk4_b : std_logic_vector (0 to 5);
signal data_chk4_c : std_logic_vector (0 to 5);
signal data_chk4_d : std_logic_vector (0 to 5);
signal data_chk4_e : std_logic_vector (0 to 5);
signal data_chk4_a_xor : std_logic;
signal data_chk4_b_xor : std_logic;
signal data_chk4_c_xor : std_logic;
signal data_chk4_d_xor : std_logic;
signal data_chk4_e_xor : std_logic;
signal data_chk4_f_xor : std_logic;
signal data_chk4_a_xor_reg : std_logic;
signal data_chk4_b_xor_reg : std_logic;
signal data_chk4_c_xor_reg : std_logic;
signal data_chk4_d_xor_reg : std_logic;
signal data_chk4_e_xor_reg : std_logic;
signal data_chk4_f_xor_reg : std_logic;
-- Checkbit (5)
signal data_chk5_a : std_logic_vector (0 to 5);
signal data_chk5_b : std_logic_vector (0 to 5);
signal data_chk5_c : std_logic_vector (0 to 5);
signal data_chk5_d : std_logic_vector (0 to 5);
signal data_chk5_e : std_logic_vector (0 to 5);
signal data_chk5_a_xor : std_logic;
signal data_chk5_b_xor : std_logic;
signal data_chk5_c_xor : std_logic;
signal data_chk5_d_xor : std_logic;
signal data_chk5_e_xor : std_logic;
signal data_chk5_f_xor : std_logic;
signal data_chk5_a_xor_reg : std_logic;
signal data_chk5_b_xor_reg : std_logic;
signal data_chk5_c_xor_reg : std_logic;
signal data_chk5_d_xor_reg : std_logic;
signal data_chk5_e_xor_reg : std_logic;
signal data_chk5_f_xor_reg : std_logic;
-- Checkbit (6)
signal data_chk6_a : std_logic;
signal data_chk6_b : std_logic;
signal data_chk6_a_reg : std_logic;
signal data_chk6_b_reg : std_logic;
-- Checkbit (7)
signal data_chk7_a : std_logic_vector (0 to 5);
signal data_chk7_b : std_logic_vector (0 to 5);
signal data_chk7_c : std_logic_vector (0 to 5);
signal data_chk7_d : std_logic_vector (0 to 5);
signal data_chk7_e : std_logic_vector (0 to 5);
signal data_chk7_f : std_logic_vector (0 to 4);
signal data_chk7_a_xor : std_logic;
signal data_chk7_b_xor : std_logic;
signal data_chk7_c_xor : std_logic;
signal data_chk7_d_xor : std_logic;
signal data_chk7_e_xor : std_logic;
signal data_chk7_f_xor : std_logic;
signal data_chk7_a_xor_reg : std_logic;
signal data_chk7_b_xor_reg : std_logic;
signal data_chk7_c_xor_reg : std_logic;
signal data_chk7_d_xor_reg : std_logic;
signal data_chk7_e_xor_reg : std_logic;
signal data_chk7_f_xor_reg : std_logic;
begin
-----------------------------------------------------------------------------
-- For timing improvements, if check bit XOR logic
-- needs to be pipelined. Add register level here
-- after 1st LUT level.
REG_BITS : if (C_REG) generate
begin
REG_CHK: process (Clk)
begin
if (Clk'event and Clk = '1' ) then
-- Checkbit (0)
-- data_chk0_xor_reg <= data_chk0_xor;
-- data_chk0_i_xor_reg <= data_chk0_i_xor;
data_chk0_a_xor_reg <= data_chk0_a_xor;
data_chk0_b_xor_reg <= data_chk0_b_xor;
data_chk0_c_xor_reg <= data_chk0_c_xor;
data_chk0_d_xor_reg <= data_chk0_d_xor;
data_chk0_e_xor_reg <= data_chk0_e_xor;
data_chk0_f_xor_reg <= data_chk0_f_xor;
-- Checkbit (1)
-- data_chk1_xor_reg <= data_chk1_xor;
-- data_chk1_i_xor_reg <= data_chk1_i_xor;
data_chk1_a_xor_reg <= data_chk1_a_xor;
data_chk1_b_xor_reg <= data_chk1_b_xor;
data_chk1_c_xor_reg <= data_chk1_c_xor;
data_chk1_d_xor_reg <= data_chk1_d_xor;
data_chk1_e_xor_reg <= data_chk1_e_xor;
data_chk1_f_xor_reg <= data_chk1_f_xor;
-- Checkbit (2)
-- data_chk2_xor_reg <= data_chk2_xor;
-- data_chk2_i_xor_reg <= data_chk2_i_xor;
data_chk2_a_xor_reg <= data_chk2_a_xor;
data_chk2_b_xor_reg <= data_chk2_b_xor;
data_chk2_c_xor_reg <= data_chk2_c_xor;
data_chk2_d_xor_reg <= data_chk2_d_xor;
data_chk2_e_xor_reg <= data_chk2_e_xor;
data_chk2_f_xor_reg <= data_chk2_f_xor;
-- Checkbit (3)
-- data_chk3_xor_reg <= data_chk3_xor;
-- data_chk3_i_xor_reg <= data_chk3_i_xor;
data_chk3_a_xor_reg <= data_chk3_a_xor;
data_chk3_b_xor_reg <= data_chk3_b_xor;
data_chk3_c_xor_reg <= data_chk3_c_xor;
data_chk3_d_xor_reg <= data_chk3_d_xor;
data_chk3_e_xor_reg <= data_chk3_e_xor;
data_chk3_f_xor_reg <= data_chk3_f_xor;
-- Checkbit (4)
-- data_chk4_xor_reg <= data_chk4_xor;
-- data_chk4_i_xor_reg <= data_chk4_i_xor;
data_chk4_a_xor_reg <= data_chk4_a_xor;
data_chk4_b_xor_reg <= data_chk4_b_xor;
data_chk4_c_xor_reg <= data_chk4_c_xor;
data_chk4_d_xor_reg <= data_chk4_d_xor;
data_chk4_e_xor_reg <= data_chk4_e_xor;
data_chk4_f_xor_reg <= data_chk4_f_xor;
-- Checkbit (5)
-- data_chk5_xor_reg <= data_chk5_xor;
-- data_chk5_i_xor_reg <= data_chk5_i_xor;
data_chk5_a_xor_reg <= data_chk5_a_xor;
data_chk5_b_xor_reg <= data_chk5_b_xor;
data_chk5_c_xor_reg <= data_chk5_c_xor;
data_chk5_d_xor_reg <= data_chk5_d_xor;
data_chk5_e_xor_reg <= data_chk5_e_xor;
data_chk5_f_xor_reg <= data_chk5_f_xor;
-- Checkbit (6)
-- data_chk6_i_reg <= data_chk6_i;
data_chk6_a_reg <= data_chk6_a;
data_chk6_b_reg <= data_chk6_b;
-- Checkbit (7)
-- data_chk7_a_xor_reg <= data_chk7_a_xor;
-- data_chk7_b_xor_reg <= data_chk7_b_xor;
data_chk7_a_xor_reg <= data_chk7_a_xor;
data_chk7_b_xor_reg <= data_chk7_b_xor;
data_chk7_c_xor_reg <= data_chk7_c_xor;
data_chk7_d_xor_reg <= data_chk7_d_xor;
data_chk7_e_xor_reg <= data_chk7_e_xor;
data_chk7_f_xor_reg <= data_chk7_f_xor;
end if;
end process REG_CHK;
-- Perform the last XOR after the register stage
-- CheckOut(0) <= data_chk0_xor_reg xor data_chk0_i_xor_reg;
CheckOut(0) <= data_chk0_a_xor_reg xor
data_chk0_b_xor_reg xor
data_chk0_c_xor_reg xor
data_chk0_d_xor_reg xor
data_chk0_e_xor_reg xor
data_chk0_f_xor_reg;
-- CheckOut(1) <= data_chk1_xor_reg xor data_chk1_i_xor_reg;
CheckOut(1) <= data_chk1_a_xor_reg xor
data_chk1_b_xor_reg xor
data_chk1_c_xor_reg xor
data_chk1_d_xor_reg xor
data_chk1_e_xor_reg xor
data_chk1_f_xor_reg;
-- CheckOut(2) <= data_chk2_xor_reg xor data_chk2_i_xor_reg;
CheckOut(2) <= data_chk2_a_xor_reg xor
data_chk2_b_xor_reg xor
data_chk2_c_xor_reg xor
data_chk2_d_xor_reg xor
data_chk2_e_xor_reg xor
data_chk2_f_xor_reg;
-- CheckOut(3) <= data_chk3_xor_reg xor data_chk3_i_xor_reg;
CheckOut(3) <= data_chk3_a_xor_reg xor
data_chk3_b_xor_reg xor
data_chk3_c_xor_reg xor
data_chk3_d_xor_reg xor
data_chk3_e_xor_reg xor
data_chk3_f_xor_reg;
-- CheckOut(4) <= data_chk4_xor_reg xor data_chk4_i_xor_reg;
CheckOut(4) <= data_chk4_a_xor_reg xor
data_chk4_b_xor_reg xor
data_chk4_c_xor_reg xor
data_chk4_d_xor_reg xor
data_chk4_e_xor_reg xor
data_chk4_f_xor_reg;
-- CheckOut(5) <= data_chk5_xor_reg xor data_chk5_i_xor_reg;
CheckOut(5) <= data_chk5_a_xor_reg xor
data_chk5_b_xor_reg xor
data_chk5_c_xor_reg xor
data_chk5_d_xor_reg xor
data_chk5_e_xor_reg xor
data_chk5_f_xor_reg;
-- CheckOut(6) <= data_chk6_i_reg;
CheckOut(6) <= data_chk6_a_reg xor data_chk6_b_reg;
-- CheckOut(7) <= data_chk7_a_xor_reg xor data_chk7_b_xor_reg;
CheckOut(7) <= data_chk7_a_xor_reg xor
data_chk7_b_xor_reg xor
data_chk7_c_xor_reg xor
data_chk7_d_xor_reg xor
data_chk7_e_xor_reg xor
data_chk7_f_xor_reg;
end generate REG_BITS;
NO_REG_BITS: if (not C_REG) generate
begin
-- CheckOut(0) <= data_chk0_xor xor data_chk0_i_xor;
CheckOut(0) <= data_chk0_a_xor xor
data_chk0_b_xor xor
data_chk0_c_xor xor
data_chk0_d_xor xor
data_chk0_e_xor xor
data_chk0_f_xor;
-- CheckOut(1) <= data_chk1_xor xor data_chk1_i_xor;
CheckOut(1) <= data_chk1_a_xor xor
data_chk1_b_xor xor
data_chk1_c_xor xor
data_chk1_d_xor xor
data_chk1_e_xor xor
data_chk1_f_xor;
-- CheckOut(2) <= data_chk2_xor xor data_chk2_i_xor;
CheckOut(2) <= data_chk2_a_xor xor
data_chk2_b_xor xor
data_chk2_c_xor xor
data_chk2_d_xor xor
data_chk2_e_xor xor
data_chk2_f_xor;
-- CheckOut(3) <= data_chk3_xor xor data_chk3_i_xor;
CheckOut(3) <= data_chk3_a_xor xor
data_chk3_b_xor xor
data_chk3_c_xor xor
data_chk3_d_xor xor
data_chk3_e_xor xor
data_chk3_f_xor;
-- CheckOut(4) <= data_chk4_xor xor data_chk4_i_xor;
CheckOut(4) <= data_chk4_a_xor xor
data_chk4_b_xor xor
data_chk4_c_xor xor
data_chk4_d_xor xor
data_chk4_e_xor xor
data_chk4_f_xor;
-- CheckOut(5) <= data_chk5_xor xor data_chk5_i_xor;
CheckOut(5) <= data_chk5_a_xor xor
data_chk5_b_xor xor
data_chk5_c_xor xor
data_chk5_d_xor xor
data_chk5_e_xor xor
data_chk5_f_xor;
-- CheckOut(6) <= data_chk6_i;
CheckOut(6) <= data_chk6_a xor data_chk6_b;
-- CheckOut(7) <= data_chk7_a_xor xor data_chk7_b_xor;
CheckOut(7) <= data_chk7_a_xor xor
data_chk7_b_xor xor
data_chk7_c_xor xor
data_chk7_d_xor xor
data_chk7_e_xor xor
data_chk7_f_xor;
end generate NO_REG_BITS;
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Checkbit 0 built up using 2x XOR18
-------------------------------------------------------------------------------
-- XOR18_I0_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk0 (0 to 17), -- [in std_logic_vector(0 to 17)]
-- res => data_chk0_xor); -- [out std_logic]
--
-- data_chk0_i <= data_chk0 (18 to 34) & '0';
--
-- XOR18_I0_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk0_i, -- [in std_logic_vector(0 to 17)]
-- res => data_chk0_i_xor); -- [out std_logic]
--
-- -- CheckOut(0) <= data_chk0_xor xor data_chk0_i_xor;
-- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG)
data_chk0_a <= data_chk0 (0 to 5);
data_chk0_b <= data_chk0 (6 to 11);
data_chk0_c <= data_chk0 (12 to 17);
data_chk0_d <= data_chk0 (18 to 23);
data_chk0_e <= data_chk0 (24 to 29);
data_chk0_f <= data_chk0 (30 to 34);
PARITY_CHK0_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk0_a_xor ); -- [out std_logic]
PARITY_CHK0_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk0_b_xor ); -- [out std_logic]
PARITY_CHK0_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk0_c_xor ); -- [out std_logic]
PARITY_CHK0_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk0_d_xor ); -- [out std_logic]
PARITY_CHK0_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk0_e_xor ); -- [out std_logic]
PARITY_CHK0_F : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk0_f (0 to 4), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk0_f_xor ); -- [out std_logic]
-------------------------------------------------------------------------------
-- Checkbit 1 built up using 2x XOR18
-------------------------------------------------------------------------------
-- XOR18_I1_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk1 (0 to 17), -- [in std_logic_vector(0 to 17)]
-- res => data_chk1_xor); -- [out std_logic]
--
-- data_chk1_i <= data_chk1 (18 to 34) & '0';
--
-- XOR18_I1_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk1_i, -- [in std_logic_vector(0 to 17)]
-- res => data_chk1_i_xor); -- [out std_logic]
--
-- -- CheckOut(1) <= data_chk1_xor xor data_chk1_i_xor;
-- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG)
data_chk1_a <= data_chk1 (0 to 5);
data_chk1_b <= data_chk1 (6 to 11);
data_chk1_c <= data_chk1 (12 to 17);
data_chk1_d <= data_chk1 (18 to 23);
data_chk1_e <= data_chk1 (24 to 29);
data_chk1_f <= data_chk1 (30 to 34);
PARITY_chk1_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk1_a_xor ); -- [out std_logic]
PARITY_chk1_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk1_b_xor ); -- [out std_logic]
PARITY_chk1_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk1_c_xor ); -- [out std_logic]
PARITY_chk1_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk1_d_xor ); -- [out std_logic]
PARITY_chk1_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk1_e_xor ); -- [out std_logic]
PARITY_chk1_F : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk1_f (0 to 4), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk1_f_xor ); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using 2x XOR18
------------------------------------------------------------------------------------------------
-- XOR18_I2_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk2 (0 to 17), -- [in std_logic_vector(0 to 17)]
-- res => data_chk2_xor); -- [out std_logic]
--
-- data_chk2_i <= data_chk2 (18 to 34) & '0';
--
-- XOR18_I2_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk2_i, -- [in std_logic_vector(0 to 17)]
-- res => data_chk2_i_xor); -- [out std_logic]
--
-- -- CheckOut(2) <= data_chk2_xor xor data_chk2_i_xor;
-- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG)
data_chk2_a <= data_chk2 (0 to 5);
data_chk2_b <= data_chk2 (6 to 11);
data_chk2_c <= data_chk2 (12 to 17);
data_chk2_d <= data_chk2 (18 to 23);
data_chk2_e <= data_chk2 (24 to 29);
data_chk2_f <= data_chk2 (30 to 34);
PARITY_chk2_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk2_a_xor ); -- [out std_logic]
PARITY_chk2_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk2_b_xor ); -- [out std_logic]
PARITY_chk2_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk2_c_xor ); -- [out std_logic]
PARITY_chk2_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk2_d_xor ); -- [out std_logic]
PARITY_chk2_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk2_e_xor ); -- [out std_logic]
PARITY_chk2_F : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk2_f (0 to 4), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk2_f_xor ); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using 2x XOR18
------------------------------------------------------------------------------------------------
-- XOR18_I3_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk3 (0 to 17), -- [in std_logic_vector(0 to 17)]
-- res => data_chk3_xor); -- [out std_logic]
--
-- data_chk3_i <= data_chk3 (18 to 30) & "00000";
--
-- XOR18_I3_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
-- res => data_chk3_i_xor); -- [out std_logic]
--
-- -- CheckOut(3) <= data_chk3_xor xor data_chk3_i_xor;
-- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG)
data_chk3_a <= data_chk3 (0 to 5);
data_chk3_b <= data_chk3 (6 to 11);
data_chk3_c <= data_chk3 (12 to 17);
data_chk3_d <= data_chk3 (18 to 23);
data_chk3_e <= data_chk3 (24 to 29);
data_chk3_f_xor <= data_chk3 (30);
PARITY_chk3_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk3_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk3_a_xor ); -- [out std_logic]
PARITY_chk3_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk3_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk3_b_xor ); -- [out std_logic]
PARITY_chk3_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk3_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk3_c_xor ); -- [out std_logic]
PARITY_chk3_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk3_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk3_d_xor ); -- [out std_logic]
PARITY_chk3_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk3_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk3_e_xor ); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using 2x XOR18
------------------------------------------------------------------------------------------------
-- XOR18_I4_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk4 (0 to 17), -- [in std_logic_vector(0 to 17)]
-- res => data_chk4_xor); -- [out std_logic]
--
-- data_chk4_i <= data_chk4 (18 to 30) & "00000";
--
-- XOR18_I4_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
-- res => data_chk4_i_xor); -- [out std_logic]
--
-- -- CheckOut(4) <= data_chk4_xor xor data_chk4_i_xor;
-- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG)
data_chk4_a <= data_chk4 (0 to 5);
data_chk4_b <= data_chk4 (6 to 11);
data_chk4_c <= data_chk4 (12 to 17);
data_chk4_d <= data_chk4 (18 to 23);
data_chk4_e <= data_chk4 (24 to 29);
data_chk4_f_xor <= data_chk4 (30);
PARITY_chk4_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk4_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk4_a_xor ); -- [out std_logic]
PARITY_chk4_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk4_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk4_b_xor ); -- [out std_logic]
PARITY_chk4_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk4_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk4_c_xor ); -- [out std_logic]
PARITY_chk4_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk4_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk4_d_xor ); -- [out std_logic]
PARITY_chk4_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk4_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk4_e_xor ); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up using 2x XOR18
------------------------------------------------------------------------------------------------
-- XOR18_I5_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk5 (0 to 17), -- [in std_logic_vector(0 to 17)]
-- res => data_chk5_xor); -- [out std_logic]
--
-- data_chk5_i <= data_chk5 (18 to 30) & "00000";
--
-- XOR18_I5_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk5_i, -- [in std_logic_vector(0 to 17)]
-- res => data_chk5_i_xor); -- [out std_logic]
--
-- -- CheckOut(5) <= data_chk5_xor xor data_chk5_i_xor;
-- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG)
data_chk5_a <= data_chk5 (0 to 5);
data_chk5_b <= data_chk5 (6 to 11);
data_chk5_c <= data_chk5 (12 to 17);
data_chk5_d <= data_chk5 (18 to 23);
data_chk5_e <= data_chk5 (24 to 29);
data_chk5_f_xor <= data_chk5 (30);
PARITY_chk5_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk5_a_xor ); -- [out std_logic]
PARITY_chk5_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk5_b_xor ); -- [out std_logic]
PARITY_chk5_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk5_c_xor ); -- [out std_logic]
PARITY_chk5_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk5_d_xor ); -- [out std_logic]
PARITY_chk5_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk5_e_xor ); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 1 LUT6 + 1 XOR
------------------------------------------------------------------------------------------------
Parity_chk6_I : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6 (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk6_xor); -- [out std_logic]
-- data_chk6_i <= data_chk6_xor xor data_chk6(6);
-- Push register stage to 1st ECC XOR logic stage (when enabled, C_REG)
data_chk6_a <= data_chk6_xor;
data_chk6_b <= data_chk6(6);
-- CheckOut(6) <= data_chk6_xor xor data_chk6(6);
-- CheckOut(6) <= data_chk6_i;
-- Overall checkbit
-- New checkbit (7) for 64-bit ECC
-- 7 <= 0 1 2 4 5 7 10 11 12 14 17 18 21 23 24 26 27 29
-- 32 33 36 38 39 41 44 46 47 50 51 53 56 57 58 60 63
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 2x XOR18
------------------------------------------------------------------------------------------------
-- data_chk7_a <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
-- DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
-- DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29) ;
--
-- data_chk7_b <= DataIn(32) & DataIn(33) & DataIn(36) & DataIn(38) & DataIn(39) &
-- DataIn(41) & DataIn(44) & DataIn(46) & DataIn(47) & DataIn(50) &
-- DataIn(51) & DataIn(53) & DataIn(56) & DataIn(57) & DataIn(58) &
-- DataIn(60) & DataIn(63) & '0';
--
-- XOR18_I7_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk7_a, -- [in std_logic_vector(0 to 17)]
-- res => data_chk7_a_xor); -- [out std_logic]
--
--
-- XOR18_I7_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk7_b, -- [in std_logic_vector(0 to 17)]
-- res => data_chk7_b_xor); -- [out std_logic]
-- Move register stage to earlier in LUT XOR logic when enabled (for C_ENCODE only)
-- Break up data_chk7_a & data_chk7_b into the following 6-input LUT XOR combinations.
data_chk7_a <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7);
data_chk7_b <= DataIn(10) & DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18);
data_chk7_c <= DataIn(21) & DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
data_chk7_d <= DataIn(32) & DataIn(33) & DataIn(36) & DataIn(38) & DataIn(39) & DataIn(41);
data_chk7_e <= DataIn(44) & DataIn(46) & DataIn(47) & DataIn(50) & DataIn(51) & DataIn(53);
data_chk7_f <= DataIn(56) & DataIn(57) & DataIn(58) & DataIn(60) & DataIn(63);
PARITY_CHK7_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk7_a_xor ); -- [out std_logic]
PARITY_CHK7_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk7_b_xor ); -- [out std_logic]
PARITY_CHK7_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk7_c_xor ); -- [out std_logic]
PARITY_CHK7_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk7_d_xor ); -- [out std_logic]
PARITY_CHK7_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk7_e_xor ); -- [out std_logic]
PARITY_CHK7_F : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk7_f (0 to 4), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk7_f_xor ); -- [out std_logic]
-- Merge all data bits
-- CheckOut(7) <= data_chk7_xor xor data_chk7_i_xor;
-- data_chk7_i <= data_chk7_a_xor xor data_chk7_b_xor;
-- CheckOut(7) <= data_chk7_i;
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 7) := (others => '0');
-- Unused signal syndrome_int_7 : std_logic;
signal chk0_1 : std_logic_vector(0 to 6);
signal chk1_1 : std_logic_vector(0 to 6);
signal chk2_1 : std_logic_vector(0 to 6);
signal data_chk3_i : std_logic_vector(0 to 31);
signal chk3_1 : std_logic_vector(0 to 3);
signal data_chk4_i : std_logic_vector(0 to 31);
signal chk4_1 : std_logic_vector(0 to 3);
signal data_chk5_i : std_logic_vector(0 to 31);
signal chk5_1 : std_logic_vector(0 to 3);
signal data_chk6_i : std_logic_vector(0 to 7);
signal data_chk7 : std_logic_vector(0 to 71);
signal chk7_1 : std_logic_vector(0 to 11);
-- signal syndrome7_a : std_logic;
-- signal syndrome7_b : std_logic;
signal syndrome_0_to_2 : std_logic_vector(0 to 2);
signal syndrome_3_to_6 : std_logic_vector(3 to 6);
signal syndrome_3_to_6_multi : std_logic;
signal syndrome_3_to_6_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 5 LUT6, 1 LUT5 and 1 7-bit XOR
------------------------------------------------------------------------------------------------
-- chk0_1(3) <= CheckIn(0);
chk0_1(6) <= CheckIn(0); -- 64-bit ECC
Parity_chk0_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
-- Checkbit 0
-- 18-bit for 32-bit data
-- 35-bit for 64-bit data
Parity_chk0_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(18 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(3)); -- [out std_logic]
Parity_chk0_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(24 to 29), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(4)); -- [out std_logic]
Parity_chk0_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk0(30 to 34), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(5)); -- [out std_logic]
-- Parity_chk0_7 : ParityEnable
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
-- port map (
-- InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Enable => Enable_ECC, -- [in std_logic]
-- Res => syndrome_i(0)); -- [out std_logic]
Parity_chk0_7 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 5 LUT6, 1 LUT5 and 1 7-bit XOR
------------------------------------------------------------------------------------------------
-- chk1_1(3) <= CheckIn(1);
chk1_1(6) <= CheckIn(1); -- 64-bit ECC
Parity_chk1_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
-- Checkbit 1
-- 18-bit for 32-bit data
-- 35-bit for 64-bit data
Parity_chk1_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(18 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(3)); -- [out std_logic]
Parity_chk1_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(24 to 29), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(4)); -- [out std_logic]
Parity_chk1_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk1(30 to 34), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(5)); -- [out std_logic]
-- Parity_chk1_7 : ParityEnable
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
-- port map (
-- InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Enable => Enable_ECC, -- [in std_logic]
-- Res => syndrome_i(1)); -- [out std_logic]
Parity_chk1_7 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 5 LUT6, 1 LUT5 and 1 7-bit XOR
------------------------------------------------------------------------------------------------
-- chk2_1(3) <= CheckIn(2);
chk2_1(6) <= CheckIn(2); -- 64-bit ECC
Parity_chk2_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
-- Checkbit 2
-- 18-bit for 32-bit data
-- 35-bit for 64-bit data
Parity_chk2_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(18 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(3)); -- [out std_logic]
Parity_chk2_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(24 to 29), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(4)); -- [out std_logic]
Parity_chk2_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk2(30 to 34), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(5)); -- [out std_logic]
-- Parity_chk2_7 : ParityEnable
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
-- port map (
-- InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Enable => Enable_ECC, -- [in std_logic]
-- Res => syndrome_i(2)); -- [out std_logic]
Parity_chk2_7 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 4 LUT8 and 1 LUT4
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
-- 15-bit for 32-bit ECC
-- 31-bit for 64-bit ECC
Parity_chk3_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(16 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(2)); -- [out std_logic]
Parity_chk3_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(24 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(3)); -- [out std_logic]
-- Parity_chk3_5 : ParityEnable
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
-- port map (
-- InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Enable => Enable_ECC, -- [in std_logic]
-- Res => syndrome_i(3)); -- [out std_logic]
Parity_chk3_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 4 LUT8 and 1 LUT4
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
-- 15-bit for 32-bit ECC
-- 31-bit for 64-bit ECC
Parity_chk4_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
Parity_chk4_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(16 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(2)); -- [out std_logic]
Parity_chk4_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(24 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(3)); -- [out std_logic]
Parity_chk4_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk4_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 4 LUT8 and 1 LUT4
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
-- 15-bit for 32-bit ECC
-- 31-bit for 64-bit ECC
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk5_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk5_1(0)); -- [out std_logic]
Parity_chk5_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk5_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk5_1(1)); -- [out std_logic]
Parity_chk5_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk5_i(16 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk5_1(2)); -- [out std_logic]
Parity_chk5_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk5_i(24 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk5_1(3)); -- [out std_logic]
Parity_chk5_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk5_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 1 LUT8
------------------------------------------------------------------------------------------------
data_chk6_i <= data_chk6 & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk6_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(6)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 7 built up from 3 LUT7 and 8 LUT6 and 1 LUT3 (12 total) + 2 LUT6 + 1 2-bit XOR
------------------------------------------------------------------------------------------------
-- 32-bit ECC uses DataIn(0:31) and Checkin (0 to 6)
-- 64-bit ECC will use DataIn(0:63) and Checkin (0 to 7)
data_chk7 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) &
DataIn(32) & DataIn(33) & DataIn(34) & DataIn(35) & DataIn(36) & DataIn(37) &
DataIn(38) & DataIn(39) & DataIn(40) & DataIn(41) & DataIn(42) & DataIn(43) &
DataIn(44) & DataIn(45) & DataIn(46) & DataIn(47) & DataIn(48) & DataIn(49) &
DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) & DataIn(55) &
DataIn(56) & DataIn(57) & DataIn(58) & DataIn(59) & DataIn(60) & DataIn(61) &
DataIn(62) & DataIn(63) &
CheckIn(6) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(7);
Parity_chk7_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(0)); -- [out std_logic]
Parity_chk7_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(1)); -- [out std_logic]
Parity_chk7_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(2)); -- [out std_logic]
Parity_chk7_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk7(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(3)); -- [out std_logic]
Parity_chk7_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk7(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(4)); -- [out std_logic]
Parity_chk7_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk7(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(5)); -- [out std_logic]
Parity_chk7_7 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(39 to 44), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(6)); -- [out std_logic]
Parity_chk7_8 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(45 to 50), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(7)); -- [out std_logic]
Parity_chk7_9 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(51 to 56), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(8)); -- [out std_logic]
Parity_chk7_10 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(57 to 62), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(9)); -- [out std_logic]
Parity_chk7_11 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(63 to 68), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(10)); -- [out std_logic]
Parity_chk7_12 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 3)
port map (
InA => data_chk7(69 to 71), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(11)); -- [out std_logic]
-- Unused
-- Parity_chk7_13 : Parity
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
-- port map (
-- InA => chk7_1 (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Res => syndrome7_a); -- [out std_logic]
--
--
-- Parity_chk7_14 : Parity
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
-- port map (
-- InA => chk7_1 (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Res => syndrome7_b); -- [out std_logic]
-- Unused syndrome_i(7) <= syndrome7_a xor syndrome7_b;
-- Unused syndrome_i (7) <= syndrome7_a;
-- syndrome_i (7) is not used here. Final XOR stage is done outside this module with Syndrome_7 vector output.
-- Clean up this statement.
syndrome_i (7) <= '0';
-- Unused syndrome_int_7 <= syndrome7_a xor syndrome7_b;
-- Unused Syndrome_7_b <= syndrome7_b;
Syndrome <= syndrome_i;
-- Bring out seperate output to do final XOR stage on Syndrome (7) after
-- the pipeline stage.
Syndrome_7 <= chk7_1 (0 to 11);
---------------------------------------------------------------------------
-- With final syndrome registered outside this module for pipeline balancing
-- Use registered syndrome to generate any error flags.
-- Use input signal, Syndrome_Chk which is the registered Syndrome used to
-- correct any single bit errors.
syndrome_0_to_2 <= Syndrome_Chk(0) & Syndrome_Chk(1) & Syndrome_Chk(2);
-- syndrome_3_to_6 <= syndrome_i(3) & syndrome_i(4) & syndrome_i(5) & syndrome_i(6);
syndrome_3_to_6 <= Syndrome_Chk(3) & Syndrome_Chk(4) & Syndrome_Chk(5) & Syndrome_Chk(6);
syndrome_3_to_6_zero <= '1' when syndrome_3_to_6 = "0000" else '0';
-- Syndrome bits (3:6) can indicate a double bit error if
-- Syndrome (6) = '1' AND any bits of Syndrome(3:5) are equal to a '1'.
syndrome_3_to_6_multi <= '1' when (syndrome_3_to_6 = "1111" or -- 15
syndrome_3_to_6 = "1101" or -- 13
syndrome_3_to_6 = "1011" or -- 11
syndrome_3_to_6 = "1001" or -- 9
syndrome_3_to_6 = "0111" or -- 7
syndrome_3_to_6 = "0101" or -- 5
syndrome_3_to_6 = "0011") -- 3
else '0';
-- A single bit error is detectable if
-- Syndrome (7) = '1' and a double bit error is not detectable in Syndrome (3:6)
-- CE <= Enable_ECC and (syndrome_i(7) or CE_Q) when (syndrome_3_to_6_multi = '0')
-- CE <= Enable_ECC and (syndrome_int_7 or CE_Q) when (syndrome_3_to_6_multi = '0')
-- CE <= Enable_ECC and (Syndrome_Chk(7) or CE_Q) when (syndrome_3_to_6_multi = '0')
-- else CE_Q and Enable_ECC;
-- Ensure that CE flag is only asserted for a single clock cycle (and does not keep
-- registered output value)
CE <= (Enable_ECC and Syndrome_Chk(7)) when (syndrome_3_to_6_multi = '0') else '0';
-- Uncorrectable error if Syndrome(7) = '0' and any other bits are = '1'.
-- ue_i_0 <= Enable_ECC when (syndrome_3_to_6_zero = '0') or (syndrome_i(0 to 2) /= "000")
-- else UE_Q and Enable_ECC;
-- ue_i_0 <= Enable_ECC when (syndrome_3_to_6_zero = '0') or (syndrome_0_to_2 /= "000")
-- else UE_Q and Enable_ECC;
--
-- ue_i_1 <= Enable_ECC and (syndrome_3_to_6_multi or UE_Q);
-- Similar edit from CE flag. Ensure that UE flags are only asserted for a single
-- clock cycle. The flags are registered outside this module for detection in
-- register module.
ue_i_0 <= Enable_ECC when (syndrome_3_to_6_zero = '0') or (syndrome_0_to_2 /= "000") else '0';
ue_i_1 <= Enable_ECC and (syndrome_3_to_6_multi);
Use_LUT6: if (C_USE_LUT6) generate
UE_MUXF7 : MUXF7
port map (
I0 => ue_i_0,
I1 => ue_i_1,
-- S => syndrome_i(7),
-- S => syndrome_int_7,
S => Syndrome_Chk(7),
O => UE );
end generate Use_LUT6;
Use_RTL: if (not C_USE_LUT6) generate
-- bit 6 in 32-bit ECC
-- bit 7 in 64-bit ECC
-- UE <= ue_i_1 when syndrome_i(7) = '1' else ue_i_0;
-- UE <= ue_i_1 when syndrome_int_7 = '1' else ue_i_0;
UE <= ue_i_1 when Syndrome_Chk(7) = '1' else ue_i_0;
end generate Use_RTL;
end generate Decode_Bits;
end architecture IMP;
-------------------------------------------------------------------------------
-- checkbit_handler.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: checkbit_handler.vhd
--
-- Description: Generates the ECC checkbits for the input vector of data bits.
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity checkbit_handler is
generic (
C_ENCODE : boolean := true;
C_USE_LUT6 : boolean := true
);
port (
DataIn : in std_logic_vector(0 to 31); --- changed from 31 downto 0 to 0 to 31 to make it compatabile with LMB Controller's hamming code.
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Syndrome_4 : out std_logic_vector (0 to 1);
Syndrome_6 : out std_logic_vector (0 to 5);
Syndrome_Chk : in std_logic_vector (0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler;
library unisim;
use unisim.vcomponents.all;
architecture IMP of checkbit_handler is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
component XOR18 is
generic (
C_USE_LUT6 : boolean);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
signal data_chk0 : std_logic_vector(0 to 17);
signal data_chk1 : std_logic_vector(0 to 17);
signal data_chk2 : std_logic_vector(0 to 17);
signal data_chk3 : std_logic_vector(0 to 14);
signal data_chk4 : std_logic_vector(0 to 14);
signal data_chk5 : std_logic_vector(0 to 5);
begin -- architecture IMP
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30);
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31);
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31);
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31);
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
signal data_chk3_i : std_logic_vector(0 to 17);
signal data_chk4_i : std_logic_vector(0 to 17);
signal data_chk6 : std_logic_vector(0 to 17);
begin
------------------------------------------------------------------------------------------------
-- Checkbit 0 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I0 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk0, -- [in std_logic_vector(0 to 17)]
res => CheckOut(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 1 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I1 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk1, -- [in std_logic_vector(0 to 17)]
res => CheckOut(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I2 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk2, -- [in std_logic_vector(0 to 17)]
res => CheckOut(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & "000";
XOR18_I3 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & "000";
XOR18_I4 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up from 1 LUT6
------------------------------------------------------------------------------------------------
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => CheckOut(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
XOR18_I6 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk6, -- [in std_logic_vector(0 to 17)]
res => CheckOut(6)); -- [out std_logic]
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 6) := (others => '0');
signal chk0_1 : std_logic_vector(0 to 3);
signal chk1_1 : std_logic_vector(0 to 3);
signal chk2_1 : std_logic_vector(0 to 3);
signal data_chk3_i : std_logic_vector(0 to 15);
signal chk3_1 : std_logic_vector(0 to 1);
signal data_chk4_i : std_logic_vector(0 to 15);
signal chk4_1 : std_logic_vector(0 to 1);
signal data_chk5_i : std_logic_vector(0 to 6);
signal data_chk6 : std_logic_vector(0 to 38);
signal chk6_1 : std_logic_vector(0 to 5);
signal syndrome_0_to_2 : std_logic_vector (0 to 2);
signal syndrome_3_to_5 : std_logic_vector (3 to 5);
signal syndrome_3_to_5_multi : std_logic;
signal syndrome_3_to_5_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk0_1(3) <= CheckIn(0);
Parity_chk0_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
Parity_chk0_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk1_1(3) <= CheckIn(1);
Parity_chk1_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
Parity_chk1_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk2_1(3) <= CheckIn(2);
Parity_chk2_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
Parity_chk2_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
-- For improved timing, remove Enable_ECC signal in this LUT level
Parity_chk3_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
Parity_chk4_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
-- Set bit 4 output with default. Real ECC XOR value will be determined post register
-- stage.
syndrome_i (4) <= '0';
-- For improved timing, move last LUT level XOR to next side of pipeline
-- stage in read path.
Syndrome_4 <= chk4_1;
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 1 LUT7
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(0)); -- [out std_logic]
Parity_chk6_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(1)); -- [out std_logic]
Parity_chk6_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(2)); -- [out std_logic]
Parity_chk6_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(3)); -- [out std_logic]
Parity_chk6_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(4)); -- [out std_logic]
Parity_chk6_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(5)); -- [out std_logic]
-- No internal use for MSB of syndrome (it is created after the
-- register stage, outside of this block)
syndrome_i(6) <= '0';
Syndrome <= syndrome_i;
-- (N:0) <= (0:N)
-- Bring out seperate output to do final XOR stage on Syndrome (6) after
-- the pipeline stage.
Syndrome_6 <= chk6_1 (0 to 5);
---------------------------------------------------------------------------
-- With final syndrome registered outside this module for pipeline balancing
-- Use registered syndrome to generate any error flags.
-- Use input signal, Syndrome_Chk which is the registered Syndrome used to
-- correct any single bit errors.
syndrome_0_to_2 <= Syndrome_Chk(0) & Syndrome_Chk(1) & Syndrome_Chk(2);
syndrome_3_to_5 <= Syndrome_Chk(3) & Syndrome_Chk(4) & Syndrome_Chk(5);
syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0';
syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or
syndrome_3_to_5 = "011" or
syndrome_3_to_5 = "101")
else '0';
-- Ensure that CE flag is only asserted for a single clock cycle (and does not keep
-- registered output value)
CE <= (Enable_ECC and Syndrome_Chk(6)) when (syndrome_3_to_5_multi = '0') else '0';
-- Similar edit from CE flag. Ensure that UE flags are only asserted for a single
-- clock cycle. The flags are registered outside this module for detection in
-- register module.
ue_i_0 <= Enable_ECC when (syndrome_3_to_5_zero = '0') or (syndrome_0_to_2 /= "000") else '0';
ue_i_1 <= Enable_ECC and (syndrome_3_to_5_multi);
Use_LUT6: if (C_USE_LUT6) generate
begin
UE_MUXF7 : MUXF7
port map (
I0 => ue_i_0,
I1 => ue_i_1,
S => Syndrome_Chk(6),
O => UE);
end generate Use_LUT6;
Use_RTL: if (not C_USE_LUT6) generate
begin
UE <= ue_i_1 when Syndrome_Chk(6) = '1' else ue_i_0;
end generate Use_RTL;
end generate Decode_Bits;
end architecture IMP;
-------------------------------------------------------------------------------
-- correct_one_bit_64.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit_64.vhd
--
-- Description: Identifies single bit to correct in 64-bit word of
-- data read from memory as indicated by the syndrome input
-- vector.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity Correct_One_Bit_64 is
generic (
C_USE_LUT6 : boolean := true;
Correct_Value : std_logic_vector(0 to 7));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 7);
DCorr : out std_logic);
end entity Correct_One_Bit_64;
architecture IMP of Correct_One_Bit_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 7)) return natural is
begin -- function find_one
for I in 0 to 7 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 6);
signal lut_corr_val : std_logic_vector(0 to 6);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 7);
lut_corr_val <= Correct_Value(1 to 7);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 6);
lut_corr_val <= Correct_Value(0 to 6);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 7);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 7);
end if;
end process Remove_DI_Index;
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MUXCY_L
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : XORCY
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
-------------------------------------------------------------------------------
-- correct_one_bit.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit.vhd
--
-- Description: Identifies single bit to correct in 32-bit word of
-- data read from memory as indicated by the syndrome input
-- vector.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity Correct_One_Bit is
generic (
C_USE_LUT6 : boolean := true;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end entity Correct_One_Bit;
architecture IMP of Correct_One_Bit is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 6)) return natural is
begin -- function find_one
for I in 0 to 6 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 5);
signal lut_corr_val : std_logic_vector(0 to 5);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 6);
lut_corr_val <= Correct_Value(1 to 6);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 5);
lut_corr_val <= Correct_Value(0 to 5);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 6);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 6);
end if;
end process Remove_DI_Index;
-- Corr_LUT : LUT6
-- generic map(
-- INIT => X"6996966996696996"
-- )
-- port map(
-- O => corr_sel, -- [out]
-- I0 => InA(5), -- [in]
-- I1 => InA(4), -- [in]
-- I2 => InA(3), -- [in]
-- I3 => InA(2), -- [in]
-- I4 => InA(1), -- [in]
-- I5 => InA(0) -- [in]
-- );
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MUXCY_L
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : XORCY
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
-------------------------------------------------------------------------------
-- xor18.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: xor18.vhd
--
-- Description: Basic 18-bit input XOR function.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add default on C_USE_LUT6 parameter.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity XOR18 is
generic (
C_USE_LUT6 : boolean := FALSE );
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end entity XOR18;
architecture IMP of XOR18 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
begin -- architecture IMP
Using_LUT6: if (C_USE_LUT6) generate
signal xor6_1 : std_logic;
signal xor6_2 : std_logic;
signal xor6_3 : std_logic;
signal xor18_c1 : std_logic;
signal xor18_c2 : std_logic;
begin -- generate Using_LUT6
XOR6_1_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => xor6_1,
I0 => InA(17),
I1 => InA(16),
I2 => InA(15),
I3 => InA(14),
I4 => InA(13),
I5 => InA(12));
XOR_1st_MUXCY : MUXCY_L
port map (
DI => '1',
CI => '0',
S => xor6_1,
LO => xor18_c1);
XOR6_2_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => xor6_2,
I0 => InA(11),
I1 => InA(10),
I2 => InA(9),
I3 => InA(8),
I4 => InA(7),
I5 => InA(6));
XOR_2nd_MUXCY : MUXCY_L
port map (
DI => xor6_1,
CI => xor18_c1,
S => xor6_2,
LO => xor18_c2);
XOR6_3_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => xor6_3,
I0 => InA(5),
I1 => InA(4),
I2 => InA(3),
I3 => InA(2),
I4 => InA(1),
I5 => InA(0));
XOR18_XORCY : XORCY
port map (
LI => xor6_3,
CI => xor18_c2,
O => res);
end generate Using_LUT6;
Not_Using_LUT6: if (not C_USE_LUT6) generate
begin -- generate Not_Using_LUT6
res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor
InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor
InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0);
end generate Not_Using_LUT6;
end architecture IMP;
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Parity is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
library unisim;
use unisim.vcomponents.all;
architecture IMP of Parity is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MUXF7
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MUXF7
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MUXF7
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MUXF8
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
----------------------------------------------------------------------------------------------
--
-- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006
-- Wed Jun 17 2009 01:03:24
--
-- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ecc/ecc_gen.v
-- Component name : ecc_gen
-- Author :
-- Company :
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Generate the ecc code. Note that the synthesizer should
-- generate this as a static logic. Code in this block should
-- never run during simulation phase, or directly impact timing.
--
-- The code generated is a single correct, double detect code.
-- It is the classic Hamming code. Instead, the code is
-- optimized for minimal/balanced tree depth and size. See
-- Hsiao IBM Technial Journal 1970.
--
-- The code is returned as a single bit vector, h_rows. This was
-- the only way to "subroutinize" this with the restrictions of
-- disallowed include files and that matrices cannot be passed
-- in ports.
--
-- Factorial and the combos functions are defined. Combos
-- simply computes the number of combinations from the set
-- size and elements at a time.
--
-- The function next_combo computes the next combination in
-- lexicographical order given the "current" combination. Its
-- output is undefined if given the last combination in the
-- lexicographical order.
--
-- next_combo is insensitive to the number of elements in the
-- combinations.
--
-- An H transpose matrix is generated because that's the easiest
-- way to do it. The H transpose matrix is generated by taking
-- the one at a time combinations, then the 3 at a time, then
-- the 5 at a time. The number combinations used is equal to
-- the width of the code (CODE_WIDTH). The boundaries between
-- the 1, 3 and 5 groups are hardcoded in the for loop.
--
-- At the same time the h_rows vector is generated from the
-- H transpose matrix.
entity ecc_gen is
generic (
CODE_WIDTH : integer := 72;
ECC_WIDTH : integer := 8;
DATA_WIDTH : integer := 64
);
port (
-- Outputs
-- function next_combo
-- Given a combination, return the next combo in lexicographical
-- order. Scans from right to left. Assumes the first combination
-- is k ones all of the way to the left.
--
-- Upon entry, initialize seen0, trig1, and ones. "seen0" means
-- that a zero has been observed while scanning from right to left.
-- "trig1" means that a one have been observed _after_ seen0 is set.
-- "ones" counts the number of ones observed while scanning the input.
--
-- If trig1 is one, just copy the input bit to the output and increment
-- to the next bit. Otherwise set the the output bit to zero, if the
-- input is a one, increment ones. If the input bit is a one and seen0
-- is true, dump out the accumulated ones. Set seen0 to the complement
-- of the input bit. Note that seen0 is not used subsequent to trig1
-- getting set.
-- The stuff above leads to excessive XST execution times. For now, hardwire to 72/64 bit.
h_rows : out std_logic_vector(CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
end entity ecc_gen;
architecture trans of ecc_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of trans : architecture is "yes";
function factorial (ivar: integer) return integer is
variable tmp : integer;
begin
if (ivar = 1) then
return 1;
else
tmp := 1;
for i in ivar downto 2 loop
tmp := tmp * i;
end loop;
end if;
return tmp;
end function factorial;
function combos ( n, k: integer) return integer is
begin
return factorial(n)/(factorial(k)*factorial(n-k));
end function combos;
function next_combo (i: std_logic_vector) return std_logic_vector is
variable seen0: std_logic;
variable trig1: std_logic;
variable ones: std_logic_vector (ECC_WIDTH-1 downto 0);
variable tmp: std_logic_vector (ECC_WIDTH-1 downto 0);
variable tmp_index : integer;
begin
seen0 := '0';
trig1 := '0';
ones := (others => '0');
for index in ECC_WIDTH -1 downto 0 loop
tmp_index := ECC_WIDTH -1 - index;
if (trig1 = '1') then
tmp(tmp_index) := i(tmp_index);
else
tmp(tmp_index) := '0';
ones := ones + i(tmp_index);
if ((i(tmp_index) = '1') and (seen0 = '1')) then
trig1 := '1';
for dump_index in tmp_index-1 downto 0 loop
if (dump_index >= (tmp_index- conv_integer(ones)) ) then
tmp(dump_index) := '1';
end if;
end loop;
end if;
seen0 := not(i(tmp_index));
end if;
end loop;
return tmp;
end function next_combo;
constant COMBOS_3 : integer := combos(ECC_WIDTH, 3);
constant COMBOS_5 : integer := combos(ECC_WIDTH, 5);
type twoDarray is array (CODE_WIDTH -1 downto 0) of std_logic_vector (ECC_WIDTH-1 downto 0);
signal ht_matrix : twoDarray;
begin
columns: for n in CODE_WIDTH - 1 downto 0 generate
column0: if (n = 0) generate
ht_matrix(n) <= "111" & conv_std_logic_vector(0,ECC_WIDTH-3);
end generate;
column_combos3: if ((n = COMBOS_3) and ( n < DATA_WIDTH) ) generate
ht_matrix(n) <= "11111" & conv_std_logic_vector(0,ECC_WIDTH-5);
end generate;
column_combos5: if ((n = COMBOS_3 + COMBOS_5) and ( n < DATA_WIDTH) ) generate
ht_matrix(n) <= "1111111" & conv_std_logic_vector(0,ECC_WIDTH-7);
end generate;
column_datawidth: if (n = DATA_WIDTH) generate
ht_matrix(n) <= "1" & conv_std_logic_vector(0,ECC_WIDTH-1);
end generate;
column_gen: if ( (n /= 0 ) and ((n /= COMBOS_3) or (n > DATA_WIDTH)) and ((n /= COMBOS_3+COMBOS_5) or (n > DATA_WIDTH)) and (n /= DATA_WIDTH) ) generate
ht_matrix(n) <= next_combo(ht_matrix(n-1));
end generate;
out_assign: for s in ECC_WIDTH-1 downto 0 generate
h_rows(s*CODE_WIDTH+n) <= ht_matrix(n)(s);
end generate;
end generate;
--h_row0 <= "100000000100100011101101001101001000110100100010000110100100010000100000";
--h_row1 <= "010000001010010011011010101010100100101010010001000101010010001000010000";
--h_row2 <= "001000001001001010110110010110010010011001001000100011001001000100001000";
--h_row3 <= "000100000111000101110001110001110001000111000100010000111000100010000100";
--h_row4 <= "000010000000111100001111110000001111000000111100001000000111100001000010";
--h_row5 <= "000001001111111100000000001111111111000000000011111000000000011111000001";
--h_row6 <= "000000101111111100000000000000000000111111111111111000000000000000111111";
--h_row7 <= "000000011111111100000000000000000000000000000000000111111111111111111111";
--h_rows <= (h_row7 & h_row6 & h_row5 & h_row4 & h_row3 & h_row2 & h_row1 & h_row0);
end architecture trans;
-------------------------------------------------------------------------------
-- lite_ecc_reg.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: lite_ecc_reg.vhd
--
-- Description: This module contains the register components for the
-- ECC status & control data when enabled.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/17/2011 v1.03a
-- ~~~~~~
-- Add ECC support for 128-bit BRAM data width.
-- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and
-- modify BRAM address registers.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_lite_if;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity lite_ecc_reg is
generic (
C_S_AXI_PROTOCOL : string := "AXI4";
-- Used in this module to differentiate timing for error capture
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_SINGLE_PORT_BRAM : INTEGER := 1;
-- Enable single port usage of BRAM
C_BRAM_ADDR_ADJUST_FACTOR : integer := 2;
-- Adjust factor to BRAM address width based on data width (in bits)
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Clock and Reset
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
-- AXI-Lite Clock and Reset
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk : in std_logic;
-- S_AXI_CTRL_AResetn : in std_logic;
Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- *** AXI-Lite ECC Register Interface Signals ***
-- All synchronized to S_AXI_CTRL_AClk
-- AXI-Lite Write Address Channel Signals (AW)
AXI_CTRL_AWVALID : in std_logic;
AXI_CTRL_AWREADY : out std_logic;
AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_WVALID : in std_logic;
AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_BVALID : out std_logic;
AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
AXI_CTRL_ARVALID : in std_logic;
AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_RVALID : out std_logic;
AXI_CTRL_RREADY : in std_logic;
-- *** Memory Controller Interface Signals ***
-- All synchronized to S_AXI_AClk
Enable_ECC : out std_logic;
-- Indicates if and when ECC is enabled
FaultInjectClr : in std_logic;
-- Clear for Fault Inject Registers
CE_Failing_We : in std_logic;
-- WE for CE Failing Registers
-- UE_Failing_We : in std_logic;
-- WE for CE Failing Registers
CE_CounterReg_Inc : in std_logic;
-- Increment CE Counter Register
Sl_CE : in std_logic;
-- Correctable Error Flag
Sl_UE : in std_logic;
-- Uncorrectable Error Flag
BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a
BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a
BRAM_Addr_En : in std_logic;
Active_Wr : in std_logic;
-- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1);
-- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1);
-- Outputs
FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1);
FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1)
);
end entity lite_ecc_reg;
-------------------------------------------------------------------------------
architecture implementation of lite_ecc_reg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4"));
constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE"));
-- Start LMB BRAM v3.00a HDL
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirrorring of registers in address space of module
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11
constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00
constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01
constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10
constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00
constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00
constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01
constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00
constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01
constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10
constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00
constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00
constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00
constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00
constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01
constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10
constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
constant C_ECC_ON_OFF_WIDTH : natural := 1;
-- End LMB BRAM v3.00a HDL
constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0');
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal S_AXI_AReset : std_logic;
-- Start LMB BRAM v3.00a HDL
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
--signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
--signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
signal RegWr : std_logic;
signal RegWr_i : std_logic;
--signal RegWr_d1 : std_logic;
--signal RegWr_d2 : std_logic;
-- Fault Inject Register
signal FaultInjectData_WE_0 : std_logic := '0';
signal FaultInjectData_WE_1 : std_logic := '0';
signal FaultInjectData_WE_2 : std_logic := '0';
signal FaultInjectData_WE_3 : std_logic := '0';
signal FaultInjectECC_WE : std_logic := '0';
--signal FaultInjectClr : std_logic := '0';
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0');
signal CE_Failing_We_i : std_logic := '0';
-- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
-- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
-- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0');
-- signal UE_Failing_We_i : std_logic := '0';
-- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
-- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0');
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0');
signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0');
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0');
signal ECC_EnableIRQReg_WE : std_logic := '0';
-- ECC On/Off Control register
signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0');
signal ECC_OnOffReg_WE : std_logic := '0';
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0');
signal CE_CounterReg_WE : std_logic := '0';
signal CE_CounterReg_Inc_i : std_logic := '0';
-- End LMB BRAM v3.00a HDL
signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0');
signal Enable_ECC_i : std_logic := '0';
signal ECC_UE_i : std_logic := '0';
signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
FaultInjectData <= FaultInjectData_i;
FaultInjectECC <= FaultInjectECC_i;
-- Reserve for future support.
-- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn);
S_AXI_AReset <= not (S_AXI_AResetn);
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
--
-- Description:
-- This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
--
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
--
-- Synchronized to AXI-Lite clock and reset.
-- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to
-- the AXI clock.
--
---------------------------------------------------------------------------
I_AXI_LITE_IF : entity work.axi_lite_if
generic map(
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH
)
port map (
-- Reserve for future support.
-- LMB_Clk => S_AXI_CTRL_AClk,
-- LMB_Rst => S_AXI_CTRL_AReset,
LMB_Clk => S_AXI_AClk,
LMB_Rst => S_AXI_AReset,
S_AXI_AWADDR => AXI_CTRL_AWADDR,
S_AXI_AWVALID => AXI_CTRL_AWVALID,
S_AXI_AWREADY => AXI_CTRL_AWREADY,
S_AXI_WDATA => AXI_CTRL_WDATA,
S_AXI_WSTRB => axi_lite_wstrb_int,
S_AXI_WVALID => AXI_CTRL_WVALID,
S_AXI_WREADY => AXI_CTRL_WREADY,
S_AXI_BRESP => AXI_CTRL_BRESP,
S_AXI_BVALID => AXI_CTRL_BVALID,
S_AXI_BREADY => AXI_CTRL_BREADY,
S_AXI_ARADDR => AXI_CTRL_ARADDR,
S_AXI_ARVALID => AXI_CTRL_ARVALID,
S_AXI_ARREADY => AXI_CTRL_ARREADY,
S_AXI_RDATA => AXI_CTRL_RDATA,
S_AXI_RRESP => AXI_CTRL_RRESP,
S_AXI_RVALID => AXI_CTRL_RVALID,
S_AXI_RREADY => AXI_CTRL_RREADY,
RegWr => RegWr_i,
RegWrData => RegWrData_i,
RegAddr => RegAddr_i,
RegRdData => RegRdData_i
);
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
--
-- Save HDL
-- If it is decided to go back and use seperate clock inputs
-- One for AXI4 and one for AXI4-Lite on this core.
-- For now, temporarily comment out and replace the *_i signal
-- assignments.
RegWr <= RegWr_i;
RegWrData <= RegWrData_i;
RegAddr <= RegAddr_i;
RegRdData_i <= RegRdData;
-- Reserve for future support.
--
-- ---------------------------------------------------------------------------
-- --
-- -- All registers must be synchronized to the correct clock.
-- -- RegWr must be synchronized to the S_AXI_Clk
-- -- RegWrData must be synchronized to the S_AXI_Clk
-- -- RegAddr must be synchronized to the S_AXI_Clk
-- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk
-- --
-- ---------------------------------------------------------------------------
--
-- SYNC_AXI_CLK: process (S_AXI_AClk)
-- begin
-- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- RegWr_d1 <= RegWr_i;
-- RegWr_d2 <= RegWr_d1;
-- RegWrData_d1 <= RegWrData_i;
-- RegWrData_d2 <= RegWrData_d1;
-- RegAddr_d1 <= RegAddr_i;
-- RegAddr_d2 <= RegAddr_d1;
-- end if;
-- end process SYNC_AXI_CLK;
--
-- RegWr <= RegWr_d2;
-- RegWrData <= RegWrData_d2;
-- RegAddr <= RegAddr_d2;
--
--
-- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk)
-- begin
-- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then
-- RegRdData_d1 <= RegRdData;
-- RegRdData_d2 <= RegRdData_d1;
-- end if;
-- end process SYNC_AXI_LITE_CLK;
--
-- RegRdData_i <= RegRdData_d2;
--
---------------------------------------------------------------------------
axi_lite_wstrb_int <= (others => '1');
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_REG_SNG
-- Purpose: Generate two deep wrap-around address pipeline to store
-- read address presented to BRAM. Used to update ECC
-- register value when ECC correctable or uncorrectable error
-- is detected.
--
-- If single port, only register Port A address.
--
-- With CE flag being registered, must account for one more
-- pipeline stage in stored BRAM addresss that correlates to
-- failing ECC.
---------------------------------------------------------------------------
GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
-- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY
signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
begin
BRAM_ADDR_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (BRAM_Addr_En = '1') then
BRAM_Addr_A_d1 <= BRAM_Addr_A;
BRAM_Addr_A_d2 <= BRAM_Addr_A_d1;
BRAM_Addr_A_d3 <= BRAM_Addr_A_d2;
else
BRAM_Addr_A_d1 <= BRAM_Addr_A_d1;
BRAM_Addr_A_d2 <= BRAM_Addr_A_d2;
BRAM_Addr_A_d3 <= BRAM_Addr_A_d3;
end if;
end if;
end process BRAM_ADDR_REG;
---------------------------------------------------------------------------
-- Generate: GEN_L_ADDR
-- Purpose: Lower order BRAM address bits fixed @ zero depending
-- on BRAM data width size.
---------------------------------------------------------------------------
GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
FailingAddr_Ld (i) <= '0';
end generate GEN_L_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Assign valid BRAM address bits based on BRAM data width size.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
GEN_FA_LITE: if IF_IS_AXI4LITE generate
begin
FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time.
end generate GEN_FA_LITE;
GEN_FA_AXI: if IF_IS_AXI4 generate
begin
-- During the RMW portion, only one active address (use _d1 pipeline).
-- During read operaitons, use 3-deep address pipeline to store address values.
FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i);
end generate GEN_FA_AXI;
end generate GEN_ADDR;
end generate GEN_ADDR_REG_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_REG_DUAL
-- Purpose: Generate two deep wrap-around address pipeline to store
-- read address presented to BRAM. Used to update ECC
-- register value when ECC correctable or uncorrectable error
-- is detected.
--
-- If dual port BRAM, register Port A & Port B address.
--
-- Account for CE flag register delay, add 3rd BRAM address
-- pipeline stage.
--
---------------------------------------------------------------------------
GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
-- Port B pipeline stages only used in a dual port mode configuration.
signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
begin
BRAM_ADDR_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (BRAM_Addr_En = '1') then
BRAM_Addr_A_d1 <= BRAM_Addr_A;
BRAM_Addr_B_d1 <= BRAM_Addr_B;
BRAM_Addr_B_d2 <= BRAM_Addr_B_d1;
BRAM_Addr_B_d3 <= BRAM_Addr_B_d2;
else
BRAM_Addr_A_d1 <= BRAM_Addr_A_d1;
BRAM_Addr_B_d1 <= BRAM_Addr_B_d1;
BRAM_Addr_B_d2 <= BRAM_Addr_B_d2;
BRAM_Addr_B_d3 <= BRAM_Addr_B_d3;
end if;
end if;
end process BRAM_ADDR_REG;
---------------------------------------------------------------------------
-- Generate: GEN_L_ADDR
-- Purpose: Lower order BRAM address bits fixed @ zero depending
-- on BRAM data width size.
---------------------------------------------------------------------------
GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
FailingAddr_Ld (i) <= '0';
end generate GEN_L_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Assign valid BRAM address bits based on BRAM data width size.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
GEN_FA_LITE: if IF_IS_AXI4LITE generate
begin
-- Only one active operation at a time.
-- Use one deep address pipeline. Determine if Port A or B based on active read or write.
FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i);
end generate GEN_FA_LITE;
GEN_FA_AXI: if IF_IS_AXI4 generate
begin
-- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A).
-- During read operations, use 3-deep address pipeline to store address values (and from Port B).
FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i);
end generate GEN_FA_AXI;
end generate GEN_ADDR;
end generate GEN_ADDR_REG_DUAL;
---------------------------------------------------------------------------
-- Generate: FAULT_INJECT
-- Purpose: Implement fault injection registers
-- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB)
---------------------------------------------------------------------------
FAULT_INJECT : if C_HAS_FAULT_INJECT generate
begin
-- FaultInjectClr added to top level port list.
-- Original LMB BRAM HDL
-- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0';
---------------------------------------------------------------------------
-- Generate: GEN_32_FAULT
-- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH
---------------------------------------------------------------------------
GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate
begin
FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0';
FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0';
-- Create fault vector for 32-bit data widths
FaultInjectDataReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
elsif FaultInjectData_WE_0 = '1' then
FaultInjectData_i (0 to 31) <= RegWrData;
elsif FaultInjectECC_WE = '1' then
-- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1);
-- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1);
-- (25:31)
FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1);
elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate GEN_32_FAULT;
---------------------------------------------------------------------------
-- Generate: GEN_64_FAULT
-- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH
---------------------------------------------------------------------------
GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate
begin
FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0';
FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0';
FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0';
-- Create fault vector for 64-bit data widths
FaultInjectDataReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
elsif FaultInjectData_WE_0 = '1' then
FaultInjectData_i (32 to 63) <= RegWrData;
elsif FaultInjectData_WE_1 = '1' then
FaultInjectData_i (0 to 31) <= RegWrData;
elsif FaultInjectECC_WE = '1' then
-- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1);
-- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1);
-- (24:31)
FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1);
elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate GEN_64_FAULT;
-- v1.03a
---------------------------------------------------------------------------
-- Generate: GEN_128_FAULT
-- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH
---------------------------------------------------------------------------
GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate
begin
FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0';
FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0';
FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0';
FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0';
FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0';
-- Create fault vector for 128-bit data widths
FaultInjectDataReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
elsif FaultInjectData_WE_0 = '1' then
FaultInjectData_i (96 to 127) <= RegWrData;
elsif FaultInjectData_WE_1 = '1' then
FaultInjectData_i (64 to 95) <= RegWrData;
elsif FaultInjectData_WE_2 = '1' then
FaultInjectData_i (32 to 63) <= RegWrData;
elsif FaultInjectData_WE_3 = '1' then
FaultInjectData_i (0 to 31) <= RegWrData;
elsif FaultInjectECC_WE = '1' then
FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1);
elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate GEN_128_FAULT;
end generate FAULT_INJECT;
---------------------------------------------------------------------------
-- Generate: NO_FAULT_INJECT
-- Purpose: Set default outputs when no fault inject capabilities.
-- Remove check from C_WRITE_ACCESS (from LMB)
---------------------------------------------------------------------------
NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate
begin
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end generate NO_FAULT_INJECT;
---------------------------------------------------------------------------
-- Generate: CE_FAILING_REGISTERS
-- Purpose: Implement Correctable Error First Failing Register
---------------------------------------------------------------------------
CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate
begin
-- TBD (could come from axi_lite)
-- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0')
-- else '0';
CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0')
else '0';
CE_FailingReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
CE_FailingAddress <= (others => '0');
-- Reserve for future support.
-- CE_FailingData <= (others => '0');
elsif CE_Failing_We_i = '1' then
--As the AXI Addr Width can now be lesser than 32, the address is getting shifted
--Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000
CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0);
--CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ;
-- Reserve for future support.
-- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1);
end if;
end if;
end process CE_FailingReg;
-- Note: Remove storage of CE_FFE & CE_FFD registers.
-- Here for future support.
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_CE_ECC_32
-- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate
-- begin
--
-- CE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- CE_FailingECC <= (others => '0');
-- elsif CE_Failing_We_i = '1' then
-- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39)
-- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process CE_FailingECCReg;
--
-- end generate GEN_CE_ECC_32;
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_CE_ECC_64
-- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate
-- begin
--
-- CE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- CE_FailingECC <= (others => '0');
-- elsif CE_Failing_We_i = '1' then
-- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process CE_FailingECCReg;
--
-- end generate GEN_CE_ECC_64;
end generate CE_FAILING_REGISTERS;
---------------------------------------------------------------------------
-- Generate: NO_CE_FAILING_REGISTERS
-- Purpose: No Correctable Error Failing registers.
---------------------------------------------------------------------------
NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
-- CE_FailingData <= (others => '0');
-- CE_FailingECC <= (others => '0');
end generate NO_CE_FAILING_REGISTERS;
-- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0
-- This generate clause will never be evaluated.
-- Here for future support.
--
-- ---------------------------------------------------------------------------
-- -- Generate: UE_FAILING_REGISTERS
-- -- Purpose: Implement Unorrectable Error First Failing Register
-- ---------------------------------------------------------------------------
--
-- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate
-- begin
--
-- -- TBD (could come from axi_lite)
-- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0')
-- -- else '0';
--
-- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0')
-- else '0';
--
--
-- UE_FailingReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- UE_FailingAddress <= (others => '0');
-- UE_FailingData <= (others => '0');
-- elsif UE_Failing_We = '1' then
-- UE_FailingAddress <= FailingAddr_Ld;
-- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1);
-- end if;
-- end if;
-- end process UE_FailingReg;
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_UE_ECC_32
-- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate
-- begin
--
-- UE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- UE_FailingECC <= (others => '0');
-- elsif UE_Failing_We = '1' then
-- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39)
-- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process UE_FailingECCReg;
--
-- end generate GEN_UE_ECC_32;
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_UE_ECC_64
-- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate
-- begin
--
-- UE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- UE_FailingECC <= (others => '0');
-- elsif UE_Failing_We = '1' then
-- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process UE_FailingECCReg;
--
-- end generate GEN_UE_ECC_64;
--
-- end generate UE_FAILING_REGISTERS;
--
--
-- ---------------------------------------------------------------------------
-- -- Generate: NO_UE_FAILING_REGISTERS
-- -- Purpose: No Uncorrectable Error Failing registers.
-- ---------------------------------------------------------------------------
--
-- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate
-- begin
-- UE_FailingAddress <= (others => '0');
-- UE_FailingData <= (others => '0');
-- UE_FailingECC <= (others => '0');
-- end generate NO_UE_FAILING_REGISTERS;
---------------------------------------------------------------------------
-- Generate: ECC_STATUS_REGISTERS
-- Purpose: Enable ECC status and interrupt enable registers.
---------------------------------------------------------------------------
ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE;
ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE;
StatusReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0';
EnableIRQReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
ECC_EnableIRQReg <= (others => '0');
elsif ECC_EnableIRQReg_WE = '1' then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
---------------------------------------------------------------------------
-- Generate output flag for UE sticky bit
-- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted.
REG_UE : process (S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE or
(Enable_ECC_i = '0') then
ECC_UE_i <= '0';
elsif Sl_UE = '1' then
ECC_UE_i <= '1';
elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then
ECC_UE_i <= '0';
else
ECC_UE_i <= ECC_UE_i;
end if;
end if;
end process REG_UE;
ECC_UE <= ECC_UE_i;
---------------------------------------------------------------------------
end generate ECC_STATUS_REGISTERS;
---------------------------------------------------------------------------
-- Generate: NO_ECC_STATUS_REGISTERS
-- Purpose: No ECC status or interrupt registers enabled.
---------------------------------------------------------------------------
NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
ECC_UE <= '0';
end generate NO_ECC_STATUS_REGISTERS;
---------------------------------------------------------------------------
-- Generate: GEN_ECC_ONOFF
-- Purpose: Implement ECC on/off control register.
---------------------------------------------------------------------------
GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate
begin
ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0';
EnableIRQReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
if (C_ECC_ONOFF_RESET_VALUE = 0) then
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0';
else
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1';
end if;
-- ECC on by default at reset (but can be disabled)
elsif ECC_OnOffReg_WE = '1' then
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH);
end if;
end if;
end process EnableIRQReg;
Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH);
Enable_ECC <= Enable_ECC_i;
end generate GEN_ECC_ONOFF;
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC_ONOFF
-- Purpose: No ECC on/off control register.
---------------------------------------------------------------------------
GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate
begin
Enable_ECC <= '0';
-- ECC ON/OFF register is only enabled when C_ECC = 1.
-- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then
-- ECC should be disabled.
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0';
end generate GEN_NO_ECC_ONOFF;
---------------------------------------------------------------------------
-- Generate: CE_COUNTER
-- Purpose: Enable Correctable Error Counter
-- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits.
-- Parameterized here for future enhancements.
---------------------------------------------------------------------------
CE_COUNTER : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0';
-- TBD (could come from axi_lite)
-- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and
-- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0')
-- else '0';
CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0')
else '0';
CountReg : process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
CE_CounterReg <= (others => '0');
elsif CE_CounterReg_WE = '1' then
-- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1);
CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31);
elsif CE_CounterReg_Inc_i = '1' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_COUNTER;
-- Note: Hit this generate when C_ECC = 0.
-- Reserve for future support.
--
-- ---------------------------------------------------------------------------
-- -- Generate: NO_CE_COUNTER
-- -- Purpose: Default for no CE counter register.
-- ---------------------------------------------------------------------------
--
-- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate
-- begin
-- CE_CounterReg <= (others => '0');
-- end generate NO_CE_COUNTER;
---------------------------------------------------------------------------
-- Generate: GEN_REG_32_DATA
-- Purpose: Generate read register values & signal assignments based on
-- 32-bit BRAM data width.
---------------------------------------------------------------------------
GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate
begin
SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg,
CE_CounterReg, CE_FailingAddress,
FaultInjectData_i,
FaultInjectECC_i
-- CE_FailingData, CE_FailingECC,
-- UE_FailingAddress, UE_FailingData, UE_FailingECC
)
begin
RegRdData <= (others => '0');
case RegAddr is
-- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- Temporary addition to readback fault inject register values
when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31);
when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1);
-- Note: For future enhancement.
-- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31);
-- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC;
-- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31);
-- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31);
-- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
end generate GEN_REG_32_DATA;
---------------------------------------------------------------------------
-- Generate: GEN_REG_64_DATA
-- Purpose: Generate read register values & signal assignments based on
-- 64-bit BRAM data width.
---------------------------------------------------------------------------
GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate
begin
SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg,
CE_CounterReg, CE_FailingAddress,
FaultInjectData_i,
FaultInjectECC_i
-- CE_FailingData, CE_FailingECC,
-- UE_FailingAddress, UE_FailingData, UE_FailingECC
)
begin
RegRdData <= (others => '0');
case RegAddr is
-- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31);
when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- Temporary addition to readback fault inject register values
when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31);
when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63);
when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1);
-- Note: For future enhancement.
-- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63);
-- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31);
-- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
-- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31);
-- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63);
-- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31);
-- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
end generate GEN_REG_64_DATA;
---------------------------------------------------------------------------
-- Generate: GEN_REG_128_DATA
-- Purpose: Generate read register values & signal assignments based on
-- 128-bit BRAM data width.
---------------------------------------------------------------------------
GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate
begin
SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg,
CE_CounterReg, CE_FailingAddress,
FaultInjectData_i,
FaultInjectECC_i
-- CE_FailingData, CE_FailingECC,
-- UE_FailingAddress, UE_FailingData, UE_FailingECC
)
begin
RegRdData <= (others => '0');
case RegAddr is
-- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31);
when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- Temporary addition to readback fault inject register values
when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31);
when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63);
when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95);
when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127);
when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1);
-- Note: For future enhancement.
-- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127);
-- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95);
-- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63);
-- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31);
-- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
-- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31);
-- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127);
-- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95);
-- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63);
-- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31);
-- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
end generate GEN_REG_128_DATA;
---------------------------------------------------------------------------
end architecture implementation;
-------------------------------------------------------------------------------
-- axi_lite.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_lite.vhd
--
-- Description: This file is the top level module for the AXI-Lite
-- instantiation of the BRAM controller interface.
--
-- Responsible for shared address pipelining between the
-- write address (AW) and read address (AR) channels.
-- Controls (seperately) the data flows for the write data
-- (W), write response (B), and read data (R) channels.
--
-- Creates a shared port to BRAM (for all read and write
-- transactions) or dual BRAM port utilization based on a
-- generic parameter setting.
--
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- ecc_gen.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Update BRAM address mapping to lite_ecc_reg module. Corrected
-- signal size for XST detected unused bits in vector.
-- Plus minor code cleanup.
--
-- Add top level parameter, C_ECC_TYPE for Hsiao ECC algorithm.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Add Hsiao ECC algorithm logic (similar to full_axi module HDL).
-- ^^^^^^
-- JLJ 2/24/2011 v1.03a
-- ~~~~~~
-- Move REG_RDATA register process out from C_ECC_TYPE generate block
-- to C_ECC generate block.
-- ^^^^^^
-- JLJ 3/22/2011 v1.03a
-- ~~~~~~
-- Add LUT level with reset signal to combinatorial outputs, AWREADY
-- and WREADY. This will ensure that the output remains LOW during reset,
-- regardless of AWVALID or WVALID input signals.
-- ^^^^^^
-- JLJ 3/28/2011 v1.03a
-- ~~~~~~
-- Remove combinatorial output paths on AWREADY and WREADY.
-- Combine AWREADY and WREADY registers.
-- Remove combinatorial output path on ARREADY. Can pre-assert ARREADY
-- (but only for non ECC configurations).
-- Create 3-bit counter for BVALID response, seperate from AW/W channels.
--
-- Delay assertion of WREADY in ECC configurations to minimize register
-- resource utilization.
-- No pre-assertion of ARREADY in ECC configurations (due to write latency
-- with ECC enabled).
--
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Update Sl_CE and Sl_UE flag assertions to a single clock cycle.
-- Clean up comments.
-- ^^^^^^
-- JLJ 4/19/2011 v1.03a
-- ~~~~~~
-- Update BVALID assertion when ECC is enabled to match the implementation
-- when C_ECC = 0. Optimize back to back write performance when C_ECC = 1.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Modify FaultInjectClr signal assertion. With BVALID counter, delay
-- when fault inject register gets cleared.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 7/7/2011 v1.03a
-- ~~~~~~
-- Fix DV regression failure with reset.
-- Hold off BRAM enable output with active reset signal.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.lite_ecc_reg;
use work.parity;
use work.checkbit_handler;
use work.correct_one_bit;
use work.ecc_gen;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity axi_lite is
generic (
C_S_AXI_PROTOCOL : string := "AXI4LITE";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_SINGLE_PORT_BRAM : integer := 1;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_TYPE : integer := 0; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic;
-- Unused AW AXI-Lite Signals
-- AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
-- AXI_AWLEN : in std_logic_vector(7 downto 0);
-- AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- AXI_AWBURST : in std_logic_vector(1 downto 0);
-- AXI_AWLOCK : in std_logic; -- Currently unused
-- AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused
-- AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused
-- *** AXI Write Data Channel Signals (W) ***
AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
AXI_WVALID : in std_logic;
AXI_WREADY : out std_logic;
-- Unused W AXI-Lite Signals
-- AXI_WLAST : in std_logic;
-- *** AXI Write Data Response Channel Signals (B) ***
AXI_BRESP : out std_logic_vector(1 downto 0);
AXI_BVALID : out std_logic;
AXI_BREADY : in std_logic;
-- Unused B AXI-Lite Signals
-- AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic;
-- *** AXI Read Data Channel Signals (R) ***
AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
AXI_RRESP : out std_logic_vector(1 downto 0);
AXI_RLAST : out std_logic;
AXI_RVALID : out std_logic;
AXI_RREADY : in std_logic;
-- *** AXI-Lite ECC Register Interface Signals ***
-- AXI-Lite Clock and Reset
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk : in std_logic;
-- S_AXI_CTRL_AResetn : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
AXI_CTRL_AWVALID : in std_logic;
AXI_CTRL_AWREADY : out std_logic;
AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_WVALID : in std_logic;
AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_BVALID : out std_logic;
AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
AXI_CTRL_ARVALID : in std_logic;
AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_RVALID : out std_logic;
AXI_CTRL_RREADY : in std_logic;
-- *** BRAM Port A Interface Signals ***
-- Note: Clock handled at top level (axi_bram_ctrl module)
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
-- Note: Remove BRAM_RdData_A port (unused in dual port mode)
-- Platgen will keep port open on BRAM block
-- *** BRAM Port B Interface Signals ***
-- Note: Clock handled at top level (axi_bram_ctrl module)
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) -- @ port level = 8-bits wide ECC
);
end entity axi_lite;
-------------------------------------------------------------------------------
architecture implementation of axi_lite is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future implementation.
-- constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8);
constant C_BRAM_ADDR_ADJUST : integer := C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
constant C_AXI_DATA_WIDTH_BYTES : integer := C_S_AXI_DATA_WIDTH/8;
-- Internal data width based on C_S_AXI_DATA_WIDTH.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH);
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
constant C_USE_LUT6 : boolean := TRUE;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type LITE_SM_TYPE is ( IDLE,
SNG_WR_DATA,
RD_DATA,
RMW_RD_DATA,
RMW_MOD_DATA,
RMW_WR_DATA
);
signal lite_sm_cs, lite_sm_ns : LITE_SM_TYPE;
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_reg : std_logic := '0';
signal axi_arready_int : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write Data Channel Signals
-------------------------------------------------------------------------------
signal axi_wready_cmb : std_logic := '0';
signal axi_wready_int : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write Response Channel Signals
-------------------------------------------------------------------------------
signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_bvalid_int : std_logic := '0';
signal bvalid_cnt_inc : std_logic := '0';
signal bvalid_cnt_inc_d1 : std_logic := '0';
signal bvalid_cnt_dec : std_logic := '0';
signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Read Data Channel Signals
-------------------------------------------------------------------------------
signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_rvalid_set : std_logic := '0';
signal axi_rvalid_set_r : std_logic := '0';
signal axi_rvalid_int : std_logic := '0';
signal axi_rlast_set : std_logic := '0';
signal axi_rlast_set_r : std_logic := '0';
signal axi_rlast_int : std_logic := '0';
signal axi_rdata_int : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int_corr : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Internal BRAM Signals
-------------------------------------------------------------------------------
signal bram_we_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0) := (others => '0');
signal bram_en_a_cmb : std_logic := '0';
signal bram_en_b_cmb : std_logic := '0';
signal bram_en_a_int : std_logic := '0';
signal bram_en_b_int : std_logic := '0';
signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_a_int_q : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Port level signal, 8-bits ECC
-------------------------------------------------------------------------------
-- Internal ECC Signals
-------------------------------------------------------------------------------
signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers
signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register
signal Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Sl_CE_i : std_logic := '0';
signal Sl_UE_i : std_logic := '0';
signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal FaultInjectECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal CorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal UnCorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal CE_Q : std_logic := '0';
signal UE_Q : std_logic := '0';
signal Enable_ECC : std_logic := '0';
signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence
signal RdModifyWr_Check : std_logic := '0'; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence
signal WrData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal WrData_cmb : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal Active_Wr : std_logic := '0';
signal BRAM_Addr_En : std_logic := '0';
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI-Lite ECC Register Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_REGS
-- Purpose: Generate default values if ECC registers are disabled (or when
-- ECC is disabled).
-- Include both AXI-Lite default signal values & internal
-- core signal values.
---------------------------------------------------------------------------
-- For future implementation.
-- GEN_NO_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) or (C_ECC = 0) generate
GEN_NO_REGS: if (C_ECC = 0) generate
begin
AXI_CTRL_AWREADY <= '0';
AXI_CTRL_WREADY <= '0';
AXI_CTRL_BRESP <= (others => '0');
AXI_CTRL_BVALID <= '0';
AXI_CTRL_ARREADY <= '0';
AXI_CTRL_RDATA <= (others => '0');
AXI_CTRL_RRESP <= (others => '0');
AXI_CTRL_RVALID <= '0';
-- No fault injection
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
-- Interrupt only enabled when ECC status/interrupt registers enabled
ECC_Interrupt <= '0';
ECC_UE <= '0';
BRAM_Addr_En <= '0';
-----------------------------------------------------------------------
-- Generate: GEN_DIS_ECC
-- Purpose: Disable ECC in read path when ECC is disabled in core.
-----------------------------------------------------------------------
GEN_DIS_ECC: if C_ECC = 0 generate
Enable_ECC <= '0';
end generate GEN_DIS_ECC;
-- For future implementation.
--
-- -----------------------------------------------------------------------
-- -- Generate: GEN_EN_ECC
-- -- Purpose: Enable ECC when C_ECC = 1 and no ECC registers are available.
-- -- ECC on/off control register is not accessible (so ECC is always
-- -- enabled in this configuraiton).
-- -----------------------------------------------------------------------
-- GEN_EN_ECC: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) generate
-- Enable_ECC <= '1'; -- ECC ON/OFF register can not be enabled (as no ECC
-- -- ECC registers are available. Therefore, ECC
-- -- is always enabled.
-- end generate GEN_EN_ECC;
end generate GEN_NO_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_REGS
-- Purpose: Generate ECC register module when ECC is enabled and
-- ECC registers are enabled.
---------------------------------------------------------------------------
-- For future implementation.
-- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate
GEN_REGS: if (C_ECC = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_LITE_ECC_REG : entity work.lite_ecc_reg
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock
-- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn ,
Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
AXI_CTRL_AWVALID => AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => AXI_CTRL_RREADY ,
Enable_ECC => Enable_ECC ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => CE_Failing_We ,
CE_CounterReg_Inc => CE_Failing_We ,
Sl_CE => Sl_CE ,
Sl_UE => Sl_UE ,
BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_En => BRAM_Addr_En ,
Active_Wr => Active_Wr ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC
);
FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0';
CE_Failing_We <= '1' when Enable_ECC = '1' and CE_Q = '1' else '0';
Active_Wr <= '1' when (RdModifyWr_Read = '1' or RdModifyWr_Check = '1' or RdModifyWr_Modify = '1' or RdModifyWr_Write = '1') else '0';
-----------------------------------------------------------------------
-- Add register delay on BVALID counter increment
-- Used to clear fault inject register.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt_inc_d1 <= '0';
else
bvalid_cnt_inc_d1 <= bvalid_cnt_inc;
end if;
end if;
end process REG_BVALID_CNT;
-----------------------------------------------------------------------
end generate GEN_REGS;
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
-- AXI_AWREADY <= axi_awready_cmb;
-- AXI_AWREADY <= '0' when (S_AXI_AResetn = '0') else axi_awready_cmb; -- v1.03a
AXI_AWREADY <= axi_wready_int; -- v1.03a
-- AXI Write Data Channel Output Signals
-- AXI_WREADY <= axi_wready_cmb;
-- AXI_WREADY <= '0' when (S_AXI_AResetn = '0') else axi_wready_cmb; -- v1.03a
AXI_WREADY <= axi_wready_int; -- v1.03a
-- AXI Write Response Channel Output Signals
AXI_BRESP <= axi_bresp_int;
AXI_BVALID <= axi_bvalid_int;
-- AXI Read Address Channel Output Signals
-- AXI_ARREADY <= axi_arready_cmb; -- v1.03a
AXI_ARREADY <= axi_arready_int; -- v1.03a
-- AXI Read Data Channel Output Signals
-- AXI_RRESP <= axi_rresp_int;
AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int;
-- AXI_RDATA <= axi_rdata_int;
-- Move assignment of RDATA to generate statements based on C_ECC.
AXI_RVALID <= axi_rvalid_int;
AXI_RLAST <= axi_rlast_int;
----------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert AWREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
----------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
-- Notes:
-- No address pipelining for AXI-Lite.
-- PDR feedback.
-- Remove address register stage to BRAM.
-- Rely on registers in AXI Interconnect.
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Generate all valid bits in the address(es) to BRAM.
-- If dual port, generate Port B address signal.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_SNG_PORT
-- Purpose: Generate BRAM address when a single port to BRAM.
-- Mux read and write addresses from AXI AW and AR channels.
---------------------------------------------------------------------------
GEN_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
-- Read takes priority over AWADDR
-- bram_addr_a_int (i) <= AXI_ARADDR (i) when (AXI_ARVALID = '1') else AXI_AWADDR (i);
-- ISE should optimize away this mux when connected to the AXI Interconnect
-- as the AXI Interconnect duplicates the write or read address on both channels.
-- v1.03a
-- ARVALID may get asserted while handling ECC read-modify-write.
-- With the delay in assertion of AWREADY/WREADY, must add some logic to the
-- control on this mux select.
bram_addr_a_int (i) <= AXI_ARADDR (i) when ((AXI_ARVALID = '1' and
(lite_sm_cs = IDLE or lite_sm_cs = SNG_WR_DATA)) or
(lite_sm_cs = RD_DATA))
else AXI_AWADDR (i);
end generate GEN_ADDR_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_DUAL_PORT
-- Purpose: Generate BRAM address when a single port to BRAM.
-- Mux read and write addresses from AXI AW and AR channels.
---------------------------------------------------------------------------
GEN_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
bram_addr_a_int (i) <= AXI_AWADDR (i);
bram_addr_b_int (i) <= AXI_ARADDR (i);
end generate GEN_ADDR_DUAL_PORT;
end generate GEN_ADDR;
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY
-- Purpose: Only pre-assert ARREADY for non ECC designs.
-- With ECC, a write requires a read-modify-write and
-- will miss the address associated with the ARVALID
-- (due to the # of clock cycles).
---------------------------------------------------------------------------
GEN_ARREADY: if (C_ECC = 0) generate
begin
REG_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- ARREADY is asserted until we detect the ARVALID.
-- Check for back-to-back ARREADY assertions (add axi_arready_int).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(AXI_ARVALID = '1' and axi_arready_int = '1') then
axi_arready_int <= '0';
-- Then ARREADY is asserted again when the read operation completes.
elsif (axi_aresetn_re = '1') or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_arready_int <= '1';
else
axi_arready_int <= axi_arready_int;
end if;
end if;
end process REG_ARREADY;
end generate GEN_ARREADY;
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_ECC
-- Purpose: Generate ARREADY from SM logic. ARREADY is not pre-asserted
-- as in the non ECC configuration.
---------------------------------------------------------------------------
GEN_ARREADY_ECC: if (C_ECC = 1) generate
begin
axi_arready_int <= axi_arready_reg;
end generate GEN_ARREADY_ECC;
---------------------------------------------------------------------------
-- *** AXI Write Data Channel Interface ***
---------------------------------------------------------------------------
-- No AXI_WLAST
---------------------------------------------------------------------------
-- Generate: GEN_WRDATA
-- Purpose: Generate BRAM port A write data. For AXI-Lite, pass
-- through from AXI bus. If ECC is enabled, merge with fault
-- inject vector.
-- Write data bits are in lower order bit lanes.
-- (31:0) or (63:0)
---------------------------------------------------------------------------
GEN_WRDATA: for i in C_S_AXI_DATA_WIDTH-1 downto 0 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Generate output write data when ECC is disabled.
-- Remove write data path register to BRAM
---------------------------------------------------------------------------
GEN_NO_ECC : if C_ECC = 0 generate
begin
bram_wrdata_a_int (i) <= AXI_WDATA (i);
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
-- Generate: GEN_W_ECC
-- Purpose: Generate output write data when ECC is enable
-- (use fault vector).
-- (N:0)
---------------------------------------------------------------------------
GEN_W_ECC : if C_ECC = 1 generate
begin
bram_wrdata_a_int (i) <= WrData (i) xor FaultInjectData (i);
end generate GEN_W_ECC;
end generate GEN_WRDATA;
---------------------------------------------------------------------------
-- *** AXI Write Response Channel Interface ***
---------------------------------------------------------------------------
-- No BID support (wrap around in Interconnect)
-- In AXI-Lite, no WLAST assertion
-- Drive constant value out on BRESP
-- axi_bresp_int <= RESP_OKAY;
axi_bresp_int <= RESP_SLVERR when (C_ECC = 1 and UE_Q = '1') else RESP_OKAY;
---------------------------------------------------------------------------
-- Implement BVALID with counter regardless of IP configuration.
--
-- BVALID counter to track the # of required BVALID/BREADY handshakes
-- needed to occur on the AXI interface. Based on early and seperate
-- AWVALID/AWREADY and WVALID/WREADY handshake exchanges.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt <= (others => '0');
-- Ensure we only increment counter wyhen BREADY is not asserted
elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1);
-- Ensure that we only decrement when SM is not incrementing
elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1);
else
bvalid_cnt <= bvalid_cnt;
end if;
end if;
end process REG_BVALID_CNT;
bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and axi_bvalid_int = '1' and bvalid_cnt /= "000") else '0';
-- Replace BVALID output register
-- Assert BVALID as long as BVALID counter /= zero
REG_BVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(bvalid_cnt = "001" and bvalid_cnt_dec = '1') then
axi_bvalid_int <= '0';
elsif (bvalid_cnt /= "000") then
axi_bvalid_int <= '1';
else
axi_bvalid_int <= '0';
end if;
end if;
end process REG_BVALID;
---------------------------------------------------------------------------
-- *** AXI Read Data Channel Interface ***
---------------------------------------------------------------------------
-- For reductions on AXI-Lite, drive constant value on RESP
axi_rresp_int <= RESP_OKAY;
---------------------------------------------------------------------------
-- Generate: GEN_R
-- Purpose: Generate AXI R channel outputs when ECC is disabled.
-- No register delay on AXI_RVALID and AXI_RLAST.
---------------------------------------------------------------------------
GEN_R: if C_ECC = 0 generate
begin
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rvalid_int <= '0';
elsif (axi_rvalid_set = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rlast_int <= '0';
elsif (axi_rlast_set = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
end generate GEN_R;
---------------------------------------------------------------------------
-- Generate: GEN_R_ECC
-- Purpose: Generate AXI R channel outputs when ECC is enabled.
-- Must use registered delayed control signals for RLAST
-- and RVALID to align with register inclusion for corrected
-- read data in ECC logic.
---------------------------------------------------------------------------
GEN_R_ECC: if C_ECC = 1 generate
begin
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rvalid_int <= '0';
elsif (axi_rvalid_set_r = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rlast_int <= '0';
elsif (axi_rlast_set_r = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
end generate GEN_R_ECC;
---------------------------------------------------------------------------
--
-- Generate AXI bus read data. No register. Pass through
-- read data from BRAM. Determine source on single port
-- vs. dual port configuration.
--
---------------------------------------------------------------------------
-----------------------------------------------------------------------
-- Generate: RDATA_NO_ECC
-- Purpose: Define port A/B from BRAM on AXI_RDATA when ECC disabled.
-----------------------------------------------------------------------
RDATA_NO_ECC: if (C_ECC = 0) generate
begin
AXI_RDATA <= axi_rdata_int;
-----------------------------------------------------------------------
-- Generate: GEN_RDATA_SNG_PORT
-- Purpose: Source of read data: Port A in single port configuration.
-----------------------------------------------------------------------
GEN_RDATA_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A(C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_RDATA_SNG_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_RDATA_DUAL_PORT
-- Purpose: Source of read data: Port B in dual port configuration.
-----------------------------------------------------------------------
GEN_RDATA_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_RDATA_DUAL_PORT;
end generate RDATA_NO_ECC;
-----------------------------------------------------------------------
-- Generate: RDATA_W_ECC
-- Purpose: Connect AXI_RDATA from ECC module when ECC enabled.
-----------------------------------------------------------------------
RDATA_W_ECC: if (C_ECC = 1) generate
subtype syndrome_bits is std_logic_vector (0 to 6);
type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
begin
-- Logic common to either type of ECC encoding/decoding
-- Renove bit reversal on AXI_RDATA output.
AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr;
CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0);
-- Remove GEN_RDATA that was doing bit reversal.
-- Read back data is registered prior to any single bit error correction.
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rdata_int <= (others => '0');
else
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1);
end if;
end if;
end process REG_RDATA;
---------------------------------------------------------------------------
-- Generate: RDATA_W_HAMMING
-- Purpose: Add generate statement for Hamming Code ECC algorithm
-- specific logic.
---------------------------------------------------------------------------
RDATA_W_HAMMING: if C_ECC_TYPE = 0 generate
begin
-- Move correct_one_bit logic to output side of AXI_RDATA output register.
-- Improves timing by balancing logic on both sides of pipeline stage.
-- Utilizing registers in AXI interconnect makes this feasible.
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl
-- w/ balanced pipeline stage) before correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_S_AXI_DATA_WIDTH-1 generate
begin
---------------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Generate ECC bits for checking data read from BRAM.
---------------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table (i))
port map (
DIn => axi_rdata_int (31-i),
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (31-i));
end generate GEN_CORR_32;
end generate RDATA_W_HAMMING;
-- Hsiao ECC done in seperate generate statement (GEN_HSIAO_ECC)
end generate RDATA_W_ECC;
---------------------------------------------------------------------------
-- Main AXI-Lite State Machine
--
-- Description: Central processing unit for AXI-Lite write and read address
-- channel interface handling and handshaking.
-- Handles all arbitration between write and read channels
-- to utilize single port to BRAM
--
-- Outputs: axi_wready_int Registered
-- axi_arready_reg Registered (used in ECC configurations)
-- bvalid_cnt_inc Combinatorial
-- axi_rvalid_set Combinatorial
-- axi_rlast_set Combinatorial
-- bram_en_a_cmb Combinatorial
-- bram_en_b_cmb Combinatorial
-- bram_we_a_int Combinatorial
--
--
-- LITE_SM_CMB_PROCESS: Combinational process to determine next state.
-- LITE_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
LITE_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_WVALID,
AXI_WSTRB,
AXI_ARVALID,
AXI_RREADY,
bvalid_cnt,
axi_rvalid_int,
lite_sm_cs )
begin
-- assign default values for state machine outputs
lite_sm_ns <= lite_sm_cs;
axi_wready_cmb <= '0';
axi_arready_cmb <= '0';
bvalid_cnt_inc <= '0';
axi_rvalid_set <= '0';
axi_rlast_set <= '0';
bram_en_a_cmb <= '0';
bram_en_b_cmb <= '0';
bram_we_a_int <= (others => '0');
case lite_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- AXI Interconnect will only issue AWVALID OR ARVALID
-- at a time. In the case when the core is attached
-- to another AXI master IP, arbitrate between read
-- and write operation. Read operation will always win.
if (AXI_ARVALID = '1') then
lite_sm_ns <= RD_DATA;
-- Initiate BRAM read transfer
-- For single port BRAM, use Port A
-- For dual port BRAM, use Port B
if (C_SINGLE_PORT_BRAM = 1) then
bram_en_a_cmb <= '1';
else
bram_en_b_cmb <= '1';
end if;
bram_we_a_int <= (others => '0');
-- RVALID to be asserted in next clock cycle
-- Only 1 clock cycle latency on reading data from BRAM
axi_rvalid_set <= '1';
-- Due to single data beat with AXI-Lite
-- Assert RLAST on AXI
axi_rlast_set <= '1';
-- Only in ECC configurations
-- Must assert ARREADY here (no pre-assertion)
if (C_ECC = 1) then
axi_arready_cmb <= '1';
end if;
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
elsif (AXI_AWVALID = '1') and (AXI_WVALID = '1') and
(bvalid_cnt /= "111") then
-- Initiate BRAM write transfer
bram_en_a_cmb <= '1';
-- Always perform a read-modify-write sequence with ECC is enabled.
if (C_ECC = 1) then
lite_sm_ns <= RMW_RD_DATA;
-- Disable Port A write enables
bram_we_a_int <= (others => '0');
else
-- Non ECC operation or an ECC full 32-bit word write
-- Assert acknowledge of data & address on AXI.
-- Wait to assert AWREADY and WREADY in ECC designs.
axi_wready_cmb <= '1';
-- Increment counter to track # of required BVALID responses.
bvalid_cnt_inc <= '1';
lite_sm_ns <= SNG_WR_DATA;
bram_we_a_int <= AXI_WSTRB;
end if;
end if;
------------------------- SNG_WR_DATA State -------------------------
when SNG_WR_DATA =>
-- With early assertion of ARREADY, the SM
-- must be able to accept a read address at any clock cycle.
-- Check here for active ARVALID and directly handle read
-- and do not proceed back to IDLE (no empty clock cycle in which
-- read address may be missed).
if (AXI_ARVALID = '1') and (C_ECC = 0) then
lite_sm_ns <= RD_DATA;
-- Initiate BRAM read transfer
-- For single port BRAM, use Port A
-- For dual port BRAM, use Port B
if (C_SINGLE_PORT_BRAM = 1) then
bram_en_a_cmb <= '1';
else
bram_en_b_cmb <= '1';
end if;
bram_we_a_int <= (others => '0');
-- RVALID to be asserted in next clock cycle
-- Only 1 clock cycle latency on reading data from BRAM
axi_rvalid_set <= '1';
-- Due to single data beat with AXI-Lite
-- Assert RLAST on AXI
axi_rlast_set <= '1';
-- Only in ECC configurations
-- Must assert ARREADY here (no pre-assertion)
-- Pre-assertion of ARREADY is only for non ECC configurations.
if (C_ECC = 1) then
axi_arready_cmb <= '1';
end if;
else
lite_sm_ns <= IDLE;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Data is presented to AXI bus
-- Wait for acknowledgment to process any next transfers
-- RVALID may not be asserted as we transition into this state.
if (AXI_RREADY = '1') and (axi_rvalid_int = '1') then
lite_sm_ns <= IDLE;
end if;
------------------------- RMW_RD_DATA State -------------------------
when RMW_RD_DATA =>
lite_sm_ns <= RMW_MOD_DATA;
------------------------- RMW_MOD_DATA State -------------------------
when RMW_MOD_DATA =>
lite_sm_ns <= RMW_WR_DATA;
-- Hold off on assertion of WREADY and AWREADY until
-- here, so no pipeline registers necessary.
-- Assert acknowledge of data & address on AXI
axi_wready_cmb <= '1';
-- Increment counter to track # of required BVALID responses.
-- Able to assert this signal early, then BVALID counter
-- will get incremented in the next clock cycle when WREADY
-- is asserted.
bvalid_cnt_inc <= '1';
------------------------- RMW_WR_DATA State -------------------------
when RMW_WR_DATA =>
-- Initiate BRAM write transfer
bram_en_a_cmb <= '1';
-- Enable all WEs to BRAM
bram_we_a_int <= (others => '1');
-- Complete write operation
lite_sm_ns <= IDLE;
--coverage off
------------------------------ Default ----------------------------
when others =>
lite_sm_ns <= IDLE;
--coverage on
end case;
end process LITE_SM_CMB_PROCESS;
---------------------------------------------------------------------------
LITE_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
lite_sm_cs <= IDLE;
axi_wready_int <= '0';
axi_arready_reg <= '0';
axi_rvalid_set_r <= '0';
axi_rlast_set_r <= '0';
else
lite_sm_cs <= lite_sm_ns;
axi_wready_int <= axi_wready_cmb;
axi_arready_reg <= axi_arready_cmb;
axi_rvalid_set_r <= axi_rvalid_set;
axi_rlast_set_r <= axi_rlast_set;
end if;
end if;
end process LITE_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite)
signal WrECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0); -- Specific to BRAM data width
signal WrECC_i : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0');
signal wrdata_i : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
signal AXI_WDATA_Q : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
signal AXI_WSTRB_Q : std_logic_vector ((C_S_AXI_DATA_WIDTH/8 - 1) downto 0);
signal bram_din_a_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal bram_rddata_in : std_logic_vector (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0) := (others => '0');
subtype syndrome_bits is std_logic_vector (0 to 6);
type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
-- Read on Port A
-- or any operation on Port B (it will be read only).
BRAM_Addr_En <= '1' when (bram_en_a_int = '1' and bram_we_a_int = "00000") or
(bram_en_b_int = '1')
else '0';
-- BRAM_WE generated from SM
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
REG_RMW_SIGS : process (S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Add reset values
if (S_AXI_AResetn = C_RESET_ACTIVE) then
RdModifyWr_Check <= '0';
RdModifyWr_Modify <= '0';
RdModifyWr_Write <= '0';
else
RdModifyWr_Check <= RdModifyWr_Read;
RdModifyWr_Modify <= RdModifyWr_Check;
RdModifyWr_Write <= RdModifyWr_Modify;
end if;
end if;
end process REG_RMW_SIGS;
-- v1.03a
-- Delay assertion of WREADY to minimize registers in core.
-- Use SM transition to RMW "read" to assert this signal.
RdModifyWr_Read <= '1' when (lite_sm_ns = RMW_RD_DATA) else '0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
STORE_WRITE_DBUS : process (S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
AXI_WDATA_Q <= (others => '0');
AXI_WSTRB_Q <= (others => '0');
-- v1.03a
-- With the delay assertion of WREADY, use WVALID
-- to register in WDATA and WSTRB signals.
elsif (AXI_WVALID = '1') then
AXI_WDATA_Q <= AXI_WDATA;
AXI_WSTRB_Q <= AXI_WSTRB;
end if;
end if;
end process STORE_WRITE_DBUS;
wrdata_i <= AXI_WDATA_Q when RdModifyWr_Modify = '1' else AXI_WDATA;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_WRDATA_CMB
-- Purpose: Replace manual signal assignment for WrData_cmb with
-- generate funtion.
--
-- Ensure correct byte swapping occurs with
-- CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) assignment
-- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0).
--
-- AXI_WSTRB_Q (C_S_AXI_DATA_WIDTH_BYTES-1 downto 0) matches
-- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0).
--
------------------------------------------------------------------------
GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate
begin
WrData_cmb ( (((i+1)*8)-1) downto i*8 ) <= wrdata_i ((((i+1)*8)-1) downto i*8) when
(RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1')
else CorrectedRdData ( (C_S_AXI_DATA_WIDTH - ((i+1)*8)) to
(C_S_AXI_DATA_WIDTH - (i*8) - 1) );
end generate GEN_WRDATA_CMB;
REG_WRDATA : process (S_AXI_AClk) is
begin
-- Remove reset value to minimize resources & improve timing
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
WrData <= WrData_cmb;
end if;
end process REG_WRDATA;
------------------------------------------------------------------------
-- New assignment of ECC bits to BRAM write data outside generate
-- blocks. Same signal assignment regardless of ECC type.
bram_wrdata_a_int (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) <= '0';
bram_wrdata_a_int ((C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH - 1) downto C_S_AXI_DATA_WIDTH)
<= WrECC xor FaultInjectECC;
------------------------------------------------------------------------
-- No need to use RdModifyWr_Write in the data path.
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_WR_32
-- Description: Generate ECC bits for writing into BRAM.
-- WrData (N:0)
---------------------------------------------------------------------------
CHK_HANDLER_WR_32: entity work.checkbit_handler
generic map (
C_ENCODE => true, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => open, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => open, -- [out std_logic_vector(0 to 5)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open ); -- [out std_logic]
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_RD_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_RD_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- DataIn (8:39)
-- CheckIn (1:7)
-- Bit swapping done at port level on checkbit_handler (31:0) & (6:0)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_S_AXI_DATA_WIDTH), -- [in std_logic_vector(8 to 39)]
CheckIn => bram_din_a_i (1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(1 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic to use registered syndrome value.
end generate GEN_HAMMING_ECC;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant CODE_WIDTH : integer := C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
type type_int0 is array (C_S_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
signal flip_bits : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
begin
---------------------- Hsiao ECC Write Logic ----------------------
-- Instantiate ecc_gen module, generated from MIG
ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_S_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
-- Merge muxed rd/write data to gen
HSIAO_ECC: process (h_rows, WrData)
constant DQ_WIDTH : integer := CODE_WIDTH;
variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
begin
-- Loop to generate all ECC bits
for k in 0 to ECC_WIDTH - 1 loop
ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_S_AXI_DATA_WIDTH - 1 downto 0)
and h_rows (k * CODE_WIDTH + C_S_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH)));
end loop;
WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
end process HSIAO_ECC;
---------------------- Hsiao ECC Read Logic -----------------------
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( bram_rddata_in (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
-- Replicate BRAM read back data register for Hamming ECC
ecc_rddata_r <= bram_rddata_in (C_S_AXI_DATA_WIDTH-1 downto 0);
end if;
end process REG_SYNDROME;
-- Reconstruct H-matrix
H_COL: for n in 0 to C_S_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
GEN_FLIP_BIT: for r in 0 to C_S_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0) <= ecc_rddata_r (C_S_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_S_AXI_DATA_WIDTH-1 downto 0);
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
-- Capture correctable/uncorrectable error from BRAM read.
-- Either during RMW of write operation or during BRAM read.
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if RdModifyWr_Modify = '1' or
((Enable_ECC = '1') and
(axi_rvalid_int = '1' and AXI_RREADY = '1')) then -- Capture error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- Register CE and UE flags to register block.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A
-- Purpose: Generate BRAM read data vector assignment to always be from Port A
-- in a single port BRAM configuration.
-- Map BRAM_RdData_A (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
---------------------------------------------------------------------------
GEN_DIN_A: if C_SINGLE_PORT_BRAM = 1 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A_HAMMING
-- Purpose: Standard input for Hamming ECC code generation.
-- MSB '0' is removed in port mapping to checkbit_handler module.
---------------------------------------------------------------------------
GEN_DIN_A_HAMMING: if C_ECC_TYPE = 0 generate
begin
bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_A_HAMMING;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A_HSIAO
-- Purpose: For Hsiao ECC implementation configurations.
-- Remove MSB '0' on 32-bit implementation with fixed
-- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix).
---------------------------------------------------------------------------
GEN_DIN_A_HSIAO: if C_ECC_TYPE = 1 generate
begin
bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_A_HSIAO;
end generate GEN_DIN_A;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B
-- Purpose: Generate BRAM read data vector assignment in a dual port
-- configuration to be either from Port B, or from Port A in a
-- read-modify-write sequence.
-- Map BRAM_RdData_A/B (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
---------------------------------------------------------------------------
GEN_DIN_B: if C_SINGLE_PORT_BRAM = 0 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B_HAMMING
-- Purpose: Standard input for Hamming ECC code generation.
-- MSB '0' is removed in port mapping to checkbit_handler module.
---------------------------------------------------------------------------
GEN_DIN_B_HAMMING: if C_ECC_TYPE = 0 generate
begin
bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
when (RdModifyWr_Check = '1')
else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_B_HAMMING;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B_HSIAO
-- Purpose: For Hsiao ECC implementation configurations.
-- Remove MSB '0' on 32-bit implementation with fixed
-- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix).
---------------------------------------------------------------------------
GEN_DIN_B_HSIAO: if C_ECC_TYPE = 1 generate
begin
bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0)
when (RdModifyWr_Check = '1')
else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_B_HSIAO;
end generate GEN_DIN_B;
-- Map data vector from BRAM to use in correct_one_bit module with
-- register syndrome (post AXI RDATA register).
UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_S_AXI_DATA_WIDTH-1) when (C_ECC_TYPE = 0) else bram_rddata_in(C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** BRAM Interface Signals ***
---------------------------------------------------------------------------
-- With AXI-LITE no narrow operations are allowed.
-- AXI_WSTRB is ignored and all byte lanes are written.
bram_en_a_int <= bram_en_a_cmb;
-- BRAM_En_A <= bram_en_a_int;
-- DV regression failure with reset
-- 7/7/11
BRAM_En_A <= '0' when (S_AXI_AResetn = C_RESET_ACTIVE) else bram_en_a_int;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_EN_DUAL_PORT
-- Purpose: Only generate Port B BRAM enable signal when
-- configured for dual port BRAM.
-----------------------------------------------------------------------
GEN_BRAM_EN_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
bram_en_b_int <= bram_en_b_cmb;
BRAM_En_B <= bram_en_b_int;
end generate GEN_BRAM_EN_DUAL_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_EN_SNG_PORT
-- Purpose: Drive default for unused BRAM Port B in single
-- port BRAM configuration.
-----------------------------------------------------------------------
GEN_BRAM_EN_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_En_B <= '0';
end generate GEN_BRAM_EN_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WE
-- Purpose: BRAM WE generate process
-- One WE per 8-bits of BRAM data.
---------------------------------------------------------------------------
GEN_BRAM_WE: for i in (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH)/8-1 downto 0 generate
begin
BRAM_WE_A (i) <= bram_we_a_int (i);
end generate GEN_BRAM_WE;
---------------------------------------------------------------------------
BRAM_Addr_A <= BRAM_Addr_A_i;
BRAM_Addr_B <= BRAM_Addr_B_i;
---------------------------------------------------------------------------
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr_A_i (i) <= '0';
BRAM_Addr_B_i (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
---------------------------------------------------------------------------
GEN_U_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr_A_i (i) <= bram_addr_a_int (i);
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR_DUAL_PORT
-- Purpose: Only generate Port B BRAM address when
-- configured for dual port BRAM.
-----------------------------------------------------------------------
GEN_BRAM_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
BRAM_Addr_B_i (i) <= bram_addr_b_int (i);
end generate GEN_BRAM_ADDR_DUAL_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR_SNG_PORT
-- Purpose: Drive default for unused BRAM Port B in single
-- port BRAM configuration.
-----------------------------------------------------------------------
GEN_BRAM_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_Addr_B_i (i) <= '0';
end generate GEN_BRAM_ADDR_SNG_PORT;
end generate GEN_U_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WRDATA
-- Purpose: Generate BRAM Write Data for Port A.
---------------------------------------------------------------------------
-- When C_ECC = 0, C_ECC_WIDTH = 0 (at top level HDL)
GEN_BRAM_WRDATA: for i in (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto 0 generate
begin
BRAM_WrData_A (i) <= bram_wrdata_a_int (i);
end generate GEN_BRAM_WRDATA;
BRAM_WrData_B <= (others => '0');
BRAM_WE_B <= (others => '0');
---------------------------------------------------------------------------
end architecture implementation;
-------------------------------------------------------------------------------
-- sng_port_arb.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: sng_port_arb.vhd
--
-- Description: This file is the top level arbiter for full AXI4 mode
-- when configured in a single port mode to BRAM.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add input signal, AW2Arb_BVALID_Cnt, from wr_chnl. For configurations
-- when WREADY is to be a registered output. With a seperate FIFO for BID,
-- ensure arbitration does not get more than 8 ahead of BID responses. A
-- value of 8 is the max of the BVALID counter.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
------------------------------------------------------------------------------
entity sng_port_arb is
generic (
C_S_AXI_ADDR_WIDTH : integer := 32
-- Width of AXI address bus (in bits)
);
port (
-- *** AXI Clock and Reset ***
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic := '0';
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic := '0';
-- *** Write Channel Interface Signals ***
Arb2AW_Active : out std_logic := '0';
AW2Arb_Busy : in std_logic;
AW2Arb_Active_Clr : in std_logic;
AW2Arb_BVALID_Cnt : in std_logic_vector (2 downto 0);
-- *** Read Channel Interface Signals ***
Arb2AR_Active : out std_logic := '0';
AR2Arb_Active_Clr : in std_logic
);
end entity sng_port_arb;
-------------------------------------------------------------------------------
architecture implementation of sng_port_arb is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant ARB_WR : std_logic := '0';
constant ARB_RD : std_logic := '1';
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type ARB_SM_TYPE is ( IDLE,
RD_DATA,
WR_DATA
);
signal arb_sm_cs, arb_sm_ns : ARB_SM_TYPE;
signal axi_awready_cmb : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal last_arb_won_cmb : std_logic := '0';
signal last_arb_won : std_logic := '0';
signal aw_active_cmb : std_logic := '0';
signal aw_active : std_logic := '0';
signal ar_active_cmb : std_logic := '0';
signal ar_active : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
AXI_AWREADY <= axi_awready_int;
-- AXI Read Address Channel Output Signals
AXI_ARREADY <= axi_arready_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** Internal Arbitration Interface ***
---------------------------------------------------------------------------
Arb2AW_Active <= aw_active;
Arb2AR_Active <= ar_active;
---------------------------------------------------------------------------
-- Main Arb State Machine
--
-- Description: Main arbitration logic when AXI BRAM controller
-- configured in a single port BRAM mode.
-- Module is instantiated when C_SINGLE_PORT_BRAM = 1.
--
-- Outputs: last_arb_won Registered
-- aw_active Registered
-- ar_active Registered
-- axi_awready_int Registered
-- axi_arready_int Registered
--
--
-- ARB_SM_CMB_PROCESS: Combinational process to determine next state.
-- ARB_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
ARB_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_ARVALID,
AW2Arb_BVALID_Cnt,
AW2Arb_Busy,
AW2Arb_Active_Clr,
AR2Arb_Active_Clr,
last_arb_won,
aw_active,
ar_active,
arb_sm_cs )
begin
-- assign default values for state machine outputs
arb_sm_ns <= arb_sm_cs;
axi_awready_cmb <= '0';
axi_arready_cmb <= '0';
last_arb_won_cmb <= last_arb_won;
aw_active_cmb <= aw_active;
ar_active_cmb <= ar_active;
case arb_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for valid read operation
-- Reads take priority over AW traffic (if both asserted)
-- 4/11
-- if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or
-- ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- 4/11
-- Add BVALID counter to AW arbitration.
-- Since this is arbitration to read, no need for BVALID counter.
if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- and
--(AW2Arb_BVALID_Cnt /= "111")) or
((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
-- 4/11 elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
end if;
------------------------- WR_DATA State -------------------------
when WR_DATA =>
-- Wait for write operation to complete
if (AW2Arb_Active_Clr = '1') then
aw_active_cmb <= '0';
-- Check early for pending read (to save clock cycle
-- in transitioning back to IDLE)
if (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Note: if timing paths occur b/w wr_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a read operation.
else
arb_sm_ns <= IDLE;
end if;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Wait for read operation to complete
if (AR2Arb_Active_Clr = '1') then
ar_active_cmb <= '0';
-- Check early for pending write operation (to save clock cycle
-- in transitioning back to IDLE)
-- 4/11 if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
-- Note: if timing paths occur b/w rd_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a write operation.
-- Check early for a pending back-to-back read operation
elsif (AXI_AWVALID = '0') and (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
else
arb_sm_ns <= IDLE;
end if;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
arb_sm_ns <= IDLE;
--coverage on
end case;
end process ARB_SM_CMB_PROCESS;
---------------------------------------------------------------------------
ARB_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
arb_sm_cs <= IDLE;
last_arb_won <= ARB_WR;
aw_active <= '0';
ar_active <= '0';
axi_awready_int <='0';
axi_arready_int <='0';
else
arb_sm_cs <= arb_sm_ns;
last_arb_won <= last_arb_won_cmb;
aw_active <= aw_active_cmb;
ar_active <= ar_active_cmb;
axi_awready_int <= axi_awready_cmb;
axi_arready_int <= axi_arready_cmb;
end if;
end if;
end process ARB_SM_REG_PROCESS;
---------------------------------------------------------------------------
end architecture implementation;
-------------------------------------------------------------------------------
-- ua_narrow.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: ua_narrow.vhd
--
-- Description: Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/8/2011 v1.03a
-- ~~~~~~
-- Update bit vector usage of address LSB for calculating ua_narrow_load.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 3/1/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/2/2011 v1.03a
-- ~~~~~~
-- Update range of integer signals.
-- ^^^^^^
-- JLJ 3/4/2011 v1.03a
-- ~~~~~~
-- Remove use of local function, Create_Size_Max.
-- ^^^^^^
-- JLJ 3/11/2011 v1.03a
-- ~~~~~~
-- Remove C_AXI_DATA_WIDTH generate statments.
-- ^^^^^^
-- JLJ 3/14/2011 v1.03a
-- ~~~~~~
-- Update ua_narrow_load signal assignment to pass simulations & XST.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, ua_narrow_wrap_gt_width,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity ua_narrow is
generic (
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_NARROW_BURST_CNT_LEN : integer := 4
-- Size of narrow burst counter
);
port (
curr_wrap_burst : in std_logic;
curr_incr_burst : in std_logic;
bram_addr_ld_en : in std_logic;
curr_axlen : in std_logic_vector (7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector (2 downto 0) := (others => '0');
curr_axaddr_lsb : in std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
curr_ua_narrow_wrap : out std_logic;
curr_ua_narrow_incr : out std_logic;
ua_narrow_load : out std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0)
:= (others => '0')
);
end entity ua_narrow;
-------------------------------------------------------------------------------
architecture implementation of ua_narrow is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- Use constant to compare when LSB of ADDR is equal to zero.
constant axaddr_lsb_zero : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Convert # of data bytes for AXI data bus into an unsigned vector (C_MAX_LSHIFT_SIZE:0).
constant C_AXI_DATA_WIDTH_BYTES_UNSIGNED : unsigned (C_MAX_LSHIFT_SIZE downto 0) :=
to_unsigned (C_AXI_DATA_WIDTH_BYTES, C_MAX_LSHIFT_SIZE+1);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal ua_narrow_wrap_gt_width : std_logic := '0';
signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal curr_axsize_int : integer := 0;
signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
signal curr_axlen_unsigned_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
signal bytes_per_addr : integer := 1; -- range 1 to 128 := 1;
signal size_plus_lsb : integer range 1 to 256 := 1;
signal narrow_addr_offset : integer := 1;
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
-- v1.03a
-- Added for narrow INCR bursts with UA addresses
-- Check if burst is a) INCR type,
-- b) a narrow burst (SIZE = full width of bus)
-- c) LSB of address is non zero
curr_ua_narrow_incr <= '1' when (curr_incr_burst = '1') and
(curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and
(curr_axaddr_lsb /= axaddr_lsb_zero) and
(bram_addr_ld_en = '1')
else '0';
-- v1.03a
-- Detect narrow WRAP bursts
-- Detect if the operation is a) WRAP type,
-- b) a narrow burst (SIZE = full width of bus)
-- c) LSB of address is non zero
-- d) complete size of WRAP is larger than width of BRAM
curr_ua_narrow_wrap <= '1' when (curr_wrap_burst = '1') and
(curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and
(curr_axaddr_lsb /= axaddr_lsb_zero) and
(bram_addr_ld_en = '1') and
(ua_narrow_wrap_gt_width = '1')
else '0';
---------------------------------------------------------------------------
-- v1.03a
-- Check condition if narrow burst wraps within the size of the BRAM width.
-- Check if size * length > BRAM width in bytes.
--
-- When asserted = '1', means that narrow burst counter is not preloaded early,
-- the BRAM burst will be contained within the BRAM data width.
curr_axsize_unsigned <= unsigned (curr_axsize);
curr_axsize_int <= to_integer (curr_axsize_unsigned);
curr_axlen_unsigned <= unsigned (curr_axlen);
-- Original logic with multiply function.
--
-- ua_narrow_wrap_gt_width <= '0' when (((2**(to_integer (curr_axsize_unsigned))) *
-- unsigned (curr_axlen (7 downto 0)))
-- < C_AXI_DATA_WIDTH_BYTES)
-- else '1';
-- Replace with left shift operation of AxLEN.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
LEN_LSHIFT: process (curr_axlen_unsigned, curr_axsize_int)
begin
for i in C_MAX_LSHIFT_SIZE downto 0 loop
if (i >= curr_axsize_int + 8) then
curr_axlen_unsigned_lshift (i) <= '0';
elsif (i >= curr_axsize_int) then
curr_axlen_unsigned_lshift (i) <= curr_axlen_unsigned (i - curr_axsize_int);
else
curr_axlen_unsigned_lshift (i) <= '0';
end if;
end loop;
end process LEN_LSHIFT;
-- Final result.
ua_narrow_wrap_gt_width <= '0' when (curr_axlen_unsigned_lshift < C_AXI_DATA_WIDTH_BYTES_UNSIGNED)
else '1';
---------------------------------------------------------------------------
-- v1.03a
-- For narrow burst transfer, provides the number of bytes per address
-- XST does not support divisors that are not constants AND powers of two.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_axsize_unsigned)));
-- With this new process:
-- Replace case statement with unsigned signal comparator.
DIV_AXSIZE: process (curr_axsize)
begin
case (curr_axsize) is
when "000" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 128; -- Max SIZE for 1024-bit AXI bus
when others => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES;
end case;
end process DIV_AXSIZE;
-- Original statement.
-- XST does not support divisors that are not constants AND powers of two.
-- Insert process to perform (size_plus_lsb / size_bytes_int) function in generation of ua_narrow_load.
--
-- size_bytes_int <= (2**(to_integer (curr_axsize_unsigned)));
--
-- ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr -
-- (size_plus_lsb / size_bytes_int), C_NARROW_BURST_CNT_LEN));
-- AxSIZE + LSB of address
-- Use all LSB address bit lanes for the narrow transfer based on C_S_AXI_DATA_WIDTH
size_plus_lsb <= (2**(to_integer (curr_axsize_unsigned))) +
to_integer (unsigned (curr_axaddr_lsb (C_AXI_DATA_WIDTH_BYTES_LOG2-1 downto 0)));
-- Process to keep synthesis with divide by constants that are a power of 2.
DIV_SIZE_BYTES: process (size_plus_lsb,
curr_axsize)
begin
-- Use unsigned w/ curr_axsize signal
case (curr_axsize) is
when "000" => narrow_addr_offset <= size_plus_lsb / 1;
when "001" => narrow_addr_offset <= size_plus_lsb / 2;
when "010" => narrow_addr_offset <= size_plus_lsb / 4;
when "011" => narrow_addr_offset <= size_plus_lsb / 8;
when "100" => narrow_addr_offset <= size_plus_lsb / 16;
when "101" => narrow_addr_offset <= size_plus_lsb / 32;
when "110" => narrow_addr_offset <= size_plus_lsb / 64;
when "111" => narrow_addr_offset <= size_plus_lsb / 128; -- Max SIZE for 1024-bit AXI bus
when others => narrow_addr_offset <= size_plus_lsb;
end case;
end process DIV_SIZE_BYTES;
-- Final new statement.
-- Passing in simulation and XST.
ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr -
narrow_addr_offset, C_NARROW_BURST_CNT_LEN))
when (bytes_per_addr >= narrow_addr_offset)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
end architecture implementation;
-------------------------------------------------------------------------------
-- wrap_brst.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wrap_brst.vhd
--
-- Description: Create sub module for logic to generate WRAP burst
-- address for rd_chnl and wr_chnl.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 2/7/2011 v1.03a
-- ~~~~~~
-- Remove axi_bram_ctrl_funcs package use.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, wrap_burst_total_cmb,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 3/24/2011 v1.03a
-- ~~~~~~
-- Add specific generate blocks based on C_AXI_DATA_WIDTH to calculate
-- total WRAP burst size for improved FPGA resource utilization.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Clean up code.
-- Re-code wrap_burst_total_cmb process blocks for each data width
-- to improve and catch all false conditions in code coverage analysis.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wrap_brst is
generic (
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_AXI_DATA_WIDTH : integer := 32
-- Width of AXI data bus (in bits)
);
port (
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
curr_axlen : in std_logic_vector(7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector(2 downto 0) := (others => '0');
curr_narrow_burst : in std_logic;
narrow_bram_addr_inc_re : in std_logic;
bram_addr_ld_en : in std_logic;
bram_addr_ld : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_int : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_ld_wrap : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
max_wrap_burst_mod : out std_logic := '0'
);
end entity wrap_brst;
-------------------------------------------------------------------------------
architecture implementation of wrap_brst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Constants for WRAP size decoding to simplify integer represenation.
constant C_WRAP_SIZE_2 : std_logic_vector (2 downto 0) := "001";
constant C_WRAP_SIZE_4 : std_logic_vector (2 downto 0) := "010";
constant C_WRAP_SIZE_8 : std_logic_vector (2 downto 0) := "011";
constant C_WRAP_SIZE_16 : std_logic_vector (2 downto 0) := "100";
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal max_wrap_burst : std_logic := '0';
signal save_init_bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1)
:= (others => '0');
-- signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
-- signal curr_axsize_int : integer := 0;
-- signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
-- Holds burst length/size total (based on width of BRAM width)
-- Max size = max length of burst (256 beats)
-- signal wrap_burst_total_cmb : integer range 0 to 256 := 1; -- Max 256 (= 32768d / 128 bytes)
-- signal wrap_burst_total : integer range 0 to 256 := 1;
signal wrap_burst_total_cmb : std_logic_vector (2 downto 0) := (others => '0');
signal wrap_burst_total : std_logic_vector (2 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1 : unsigned (7 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Modify counter size based on size of current write burst operation
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Based on AxSIZE and AxLEN
-- To minimize muxing on initial load of counter value
-- Detect on WRAP burst types, when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value.
-- Save initial load address value.
REG_INIT_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
save_init_bram_addr_ld <= (others => '0');
elsif (bram_addr_ld_en = '1') then
save_init_bram_addr_ld <= bram_addr_ld(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
else
save_init_bram_addr_ld <= save_init_bram_addr_ld;
end if;
end if;
end process REG_INIT_BRAM_ADDR;
---------------------------------------------------------------------------
-- v1.03a
-- Calculate AXI size (integer)
-- curr_axsize_unsigned <= unsigned (curr_axsize);
-- curr_axsize_int <= to_integer (curr_axsize_unsigned);
-- Calculate AXI length (integer)
-- curr_axlen_unsigned <= unsigned (curr_axlen);
-- curr_axlen_unsigned_plus1 <= curr_axlen_unsigned + "00000001";
-- WRAP = size * length (based on BRAM data width in bytes)
--
-- Original multiply function:
-- wrap_burst_total_cmb <= (size_bytes_int * len_int) / C_AXI_DATA_WIDTH_BYTES;
-- For XST, modify integer multiply function to improve timing.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
-- LEN_LSHIFT: process (curr_axlen_unsigned_plus1, curr_axsize_int)
-- begin
--
-- for i in C_MAX_LSHIFT_SIZE downto 0 loop
--
-- if (i >= curr_axsize_int + 8) then
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- elsif (i >= curr_axsize_int) then
-- curr_axlen_unsigned_plus1_lshift (i) <= curr_axlen_unsigned_plus1 (i - curr_axsize_int);
-- else
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- end if;
--
-- end loop;
--
-- end process LEN_LSHIFT;
-- Final signal assignment for XST & timing improvements.
-- wrap_burst_total_cmb <= to_integer (curr_axlen_unsigned_plus1_lshift) / C_AXI_DATA_WIDTH_BYTES;
---------------------------------------------------------------------------
-- v1.03a
-- For best FPGA resource implementation, hard code the generation of
-- WRAP burst size based on each C_AXI_DATA_WIDTH possibility.
---------------------------------------------------------------------------
-- Generate: GEN_32_WRAP_SIZE
-- Purpose: These wrap size values only apply to 32-bit BRAM.
---------------------------------------------------------------------------
GEN_32_WRAP_SIZE: if C_AXI_DATA_WIDTH = 32 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 4 bytes (full AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/2 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/4 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_32_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_64_WRAP_SIZE
-- Purpose: These wrap size values only apply to 64-bit BRAM.
---------------------------------------------------------------------------
GEN_64_WRAP_SIZE: if C_AXI_DATA_WIDTH = 64 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 8 bytes (full AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/2 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/4 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/8 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_64_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_128_WRAP_SIZE
-- Purpose: These wrap size values only apply to 128-bit BRAM.
---------------------------------------------------------------------------
GEN_128_WRAP_SIZE: if C_AXI_DATA_WIDTH = 128 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 16 bytes (full AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/2 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/4 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/8 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_128_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_256_WRAP_SIZE
-- Purpose: These wrap size values only apply to 256-bit BRAM.
---------------------------------------------------------------------------
GEN_256_WRAP_SIZE: if C_AXI_DATA_WIDTH = 256 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 32 bytes (full AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/2 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/4 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/8 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_256_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_512_WRAP_SIZE
-- Purpose: These wrap size values only apply to 512-bit BRAM.
---------------------------------------------------------------------------
GEN_512_WRAP_SIZE: if C_AXI_DATA_WIDTH = 512 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 64 bytes (full AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/2 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/4 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/8 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_512_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_1024_WRAP_SIZE
-- Purpose: These wrap size values only apply to 1024-bit BRAM.
---------------------------------------------------------------------------
GEN_1024_WRAP_SIZE: if C_AXI_DATA_WIDTH = 1024 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 128 bytes (full AXI size)
when C_AXI_SIZE_128BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 64 bytes (1/2 AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/4 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/8 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_1024_WRAP_SIZE;
---------------------------------------------------------------------------
-- Early decode to determine size of WRAP transfer
-- Goal to break up long timing path to generate max_wrap_burst signal.
REG_WRAP_TOTAL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wrap_burst_total <= (others => '0');
elsif (bram_addr_ld_en = '1') then
wrap_burst_total <= wrap_burst_total_cmb;
else
wrap_burst_total <= wrap_burst_total;
end if;
end if;
end process REG_WRAP_TOTAL;
---------------------------------------------------------------------------
CHECK_WRAP_MAX : process ( wrap_burst_total,
bram_addr_int,
save_init_bram_addr_ld )
begin
-- Check BRAM address value if max value is reached.
-- Max value is based on burst size/length for operation.
-- Address bits to check vary based on C_S_AXI_DATA_WIDTH and burst size/length.
-- (use signal, wrap_burst_total, based on current WRAP burst size/length/data width).
case wrap_burst_total is
when C_WRAP_SIZE_2 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR) = '1') then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
when C_WRAP_SIZE_4 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR) = "11") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "00";
when C_WRAP_SIZE_8 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR) = "111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "000";
when C_WRAP_SIZE_16 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR) = "1111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "0000";
when others =>
max_wrap_burst <= '0';
bram_addr_ld_wrap(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld;
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
end case;
end process CHECK_WRAP_MAX;
---------------------------------------------------------------------------
-- Move outside of CHECK_WRAP_MAX process.
-- Account for narrow burst operations.
--
-- Currently max_wrap_burst is getting asserted at the first address beat to BRAM
-- that indicates the maximum WRAP burst boundary. Must wait for the completion of the
-- narrow wrap burst counter to assert max_wrap_burst.
--
-- Indicates when narrow burst address counter hits max (all zeros value)
-- narrow_bram_addr_inc_re
max_wrap_burst_mod <= max_wrap_burst when (curr_narrow_burst = '0') else
(max_wrap_burst and narrow_bram_addr_inc_re);
---------------------------------------------------------------------------
end architecture implementation;
-------------------------------------------------------------------------------
-- rd_chnl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: rd_chnl.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller read channel interfaces. Controls all
-- handshaking and data flow on the AXI read address (AR)
-- and read data (R) channels.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/3/2011 v1.03a
-- ~~~~~~
-- Edits for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/14/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter.
-- Similar edits as wr_chnl on Hsiao ECC code.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update for usage of ecc_gen.vhd module directly from MIG.
-- Clean-up XST warnings.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Found issue with ECC decoding on read path. Remove MSB '0' usage
-- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits.
-- Modify read data signal used in single bit error correction.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Move all MIG functions to package body.
-- ^^^^^^
-- JLJ 3/2/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Clean-up unused signal, narrow_addr_inc.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 4/21/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- Add defaults to araddr_pipe_sel & axi_arready_int when in single port mode.
-- Remove use of IF_IS_AXI4 constant.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 5/26/2011 v1.03a
-- ~~~~~~
-- With CR # 609695, update else clause for narrow_burst_cnt_ld to
-- remove simulation warnings when axi_byte_div_curr_arsize = zero.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.wrap_brst;
use work.ua_narrow;
use work.checkbit_handler;
use work.checkbit_handler_64;
use work.correct_one_bit;
use work.correct_one_bit_64;
use work.ecc_gen;
use work.parity;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity rd_chnl is
generic (
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 2;
-- Adjust factor to BRAM address width based on data width (in bits)
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_AXI_ID_WIDTH : integer := 4;
-- AXI ID vector width
C_S_AXI_SUPPORTS_NARROW : integer := 1;
-- Support for narrow burst operations
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to "AXI4LITE" to optimize out burst transaction support
C_SINGLE_PORT_BRAM : integer := 0;
-- Enable single port usage of BRAM
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0 -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
);
port (
-- AXI Global Signals
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
-- AXI Read Address Channel Signals (AR)
AXI_ARID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_ARADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Specifies the number of data transfers in the burst
-- "0000 0000" 1 data transfer
-- "0000 0001" 2 data transfers
-- ...
-- "1111 1111" 256 data transfers
AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Specifies the max number of data bytes to transfer in each data beat
-- "000" 1 byte to transfer
-- "001" 2 bytes to transfer
-- "010" 3 bytes to transfer
-- ...
AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Specifies burst type
-- "00" FIXED = Fixed burst address (handled as INCR)
-- "01" INCR = Increment burst address
-- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary
-- "11" Reserved (not checked)
AXI_ARLOCK : in std_logic;
AXI_ARCACHE : in std_logic_vector(3 downto 0);
AXI_ARPROT : in std_logic_vector(2 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
AXI_RID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_RDATA : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0);
AXI_RRESP : out std_logic_vector(1 downto 0);
AXI_RLAST : out std_logic;
AXI_RVALID : out std_logic;
AXI_RREADY : in std_logic;
-- ECC Register Interface Signals
Enable_ECC : in std_logic;
BRAM_Addr_En : out std_logic;
CE_Failing_We : out std_logic := '0';
Sl_CE : out std_logic := '0';
Sl_UE : out std_logic := '0';
-- Single Port Arbitration Signals
Arb2AR_Active : in std_logic;
AR2Arb_Active_Clr : out std_logic := '0';
Sng_BRAM_Addr_Ld_En : out std_logic := '0';
Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
Sng_BRAM_Addr_Inc : out std_logic := '0';
Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
-- BRAM Read Port Interface Signals
BRAM_En : out std_logic;
BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0);
BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
);
end entity rd_chnl;
-------------------------------------------------------------------------------
architecture implementation of rd_chnl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Set constants for ARLEN equal to a count of one or two beats.
constant AXI_ARLEN_ONE : std_logic_vector(7 downto 0) := (others => '0');
constant AXI_ARLEN_TWO : std_logic_vector(7 downto 0) := "00000001";
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
-- Move to full_axi module
-- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8);
-- Not used
-- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
-- Determine maximum size for narrow burst length counter
-- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits
-- resulting in a count 3 downto 0 => so minimum counter width = 2 bits.
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits
-- resulting in a count 31 downto 0 => so minimum counter width = 5 bits.
constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8);
constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- Max length burst count AXI4 specification
constant C_MAX_BRST_CNT : integer := 256;
constant C_BRST_CNT_SIZE : integer := log2 (C_MAX_BRST_CNT);
-- When the burst count = 0
constant C_BRST_CNT_ZERO : std_logic_vector(C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
-- Burst count = 1
constant C_BRST_CNT_ONE : std_logic_vector(7 downto 0) := "00000001";
-- Burst count = 2
constant C_BRST_CNT_TWO : std_logic_vector(7 downto 0) := "00000010";
-- Read data mux select constants (for signal rddata_mux_sel)
-- '0' selects BRAM
-- '1' selects read skid buffer
constant C_RDDATA_MUX_BRAM : std_logic := '0';
constant C_RDDATA_MUX_SKID_BUF : std_logic := '1';
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
-- AXI Burst Types
-- AXI Spec 4.4
constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10";
constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01";
constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00";
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Internal ECC data width size.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH);
-- For use with ECC functions (to use LUT6 components or let synthesis infer the optimal implementation).
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
constant C_USE_LUT6 : boolean := TRUE;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type RD_ADDR_SM_TYPE is ( IDLE,
LD_ARADDR
);
signal rd_addr_sm_cs, rd_addr_sm_ns : RD_ADDR_SM_TYPE;
signal ar_active_set : std_logic := '0';
signal ar_active_set_i : std_logic := '0';
signal ar_active_clr : std_logic := '0';
signal ar_active : std_logic := '0';
signal ar_active_d1 : std_logic := '0';
signal ar_active_re : std_logic := '0';
signal axi_araddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal curr_araddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
signal araddr_pipe_ld : std_logic := '0';
signal araddr_pipe_ld_i : std_logic := '0';
signal araddr_pipe_sel : std_logic := '0';
-- '0' indicates mux select from AXI
-- '1' indicates mux select from AR Addr Register
signal axi_araddr_full : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal axi_early_arready_int : std_logic := '0';
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_d2 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
signal axi_aresetn_re_reg : std_logic := '0';
signal no_ar_ack_cmb : std_logic := '0';
signal no_ar_ack : std_logic := '0';
signal pend_rd_op_cmb : std_logic := '0';
signal pend_rd_op : std_logic := '0';
signal axi_arid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_arsize_pipe : std_logic_vector (2 downto 0) := (others => '0');
signal axi_arsize_pipe_4byte : std_logic := '0';
signal axi_arsize_pipe_8byte : std_logic := '0';
signal axi_arsize_pipe_16byte : std_logic := '0';
signal axi_arsize_pipe_32byte : std_logic := '0';
-- v1.03a
signal axi_arsize_pipe_max : std_logic := '0';
signal curr_arsize : std_logic_vector (2 downto 0) := (others => '0');
signal curr_arsize_reg : std_logic_vector (2 downto 0) := (others => '0');
signal axi_arlen_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal axi_arlen_pipe_1_or_2 : std_logic := '0';
signal curr_arlen : std_logic_vector(7 downto 0) := (others => '0');
signal curr_arlen_reg : std_logic_vector(7 downto 0) := (others => '0');
signal axi_arburst_pipe : std_logic_vector(1 downto 0) := (others => '0');
signal axi_arburst_pipe_fixed : std_logic := '0';
signal curr_arburst : std_logic_vector(1 downto 0) := (others => '0');
signal curr_wrap_burst : std_logic := '0';
signal curr_wrap_burst_reg : std_logic := '0';
signal max_wrap_burst : std_logic := '0';
signal curr_incr_burst : std_logic := '0';
signal curr_fixed_burst : std_logic := '0';
signal curr_fixed_burst_reg : std_logic := '0';
-- BRAM Address Counter
signal bram_addr_ld_en : std_logic := '0';
signal bram_addr_ld_en_i : std_logic := '0';
signal bram_addr_ld_en_mod : std_logic := '0';
signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_inc : std_logic := '0';
signal bram_addr_inc_mod : std_logic := '0';
signal bram_addr_inc_wrap_mod : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Read Data Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type RD_DATA_SM_TYPE is ( IDLE,
SNG_ADDR,
SEC_ADDR,
FULL_PIPE,
FULL_THROTTLE,
LAST_ADDR,
LAST_THROTTLE,
LAST_DATA,
LAST_DATA_AR_PEND
);
signal rd_data_sm_cs, rd_data_sm_ns : RD_DATA_SM_TYPE;
signal rd_adv_buf : std_logic := '0';
signal axi_rd_burst : std_logic := '0';
signal axi_rd_burst_two : std_logic := '0';
signal act_rd_burst : std_logic := '0';
signal act_rd_burst_set : std_logic := '0';
signal act_rd_burst_clr : std_logic := '0';
signal act_rd_burst_two : std_logic := '0';
-- Rd Data Buffer/Register
signal rd_skid_buf_ld_cmb : std_logic := '0';
signal rd_skid_buf_ld_reg : std_logic := '0';
signal rd_skid_buf_ld : std_logic := '0';
signal rd_skid_buf_ld_imm : std_logic := '0';
signal rd_skid_buf : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal rddata_mux_sel_cmb : std_logic := '0';
signal rddata_mux_sel : std_logic := '0';
signal axi_rdata_en : std_logic := '0';
signal axi_rdata_mux : std_logic_vector (C_AXI_DATA_WIDTH+8*C_ECC-1 downto 0) := (others => '0');
-- Read Burst Counter
signal brst_cnt_max : std_logic := '0';
signal brst_cnt_max_d1 : std_logic := '0';
signal brst_cnt_max_re : std_logic := '0';
signal end_brst_rd_clr_cmb : std_logic := '0';
signal end_brst_rd_clr : std_logic := '0';
signal end_brst_rd : std_logic := '0';
signal brst_zero : std_logic := '0';
signal brst_one : std_logic := '0';
signal brst_cnt_ld : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
signal brst_cnt_rst : std_logic := '0';
signal brst_cnt_ld_en : std_logic := '0';
signal brst_cnt_ld_en_i : std_logic := '0';
signal brst_cnt_dec : std_logic := '0';
signal brst_cnt : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
-- AXI Read Response Signals
signal axi_rid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rid_temp_full : std_logic := '0';
signal axi_rid_temp_full_d1 : std_logic := '0';
signal axi_rid_temp_full_fe : std_logic := '0';
signal axi_rid_temp2 : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rid_temp2_full : std_logic := '0';
signal axi_b2b_rid_adv : std_logic := '0';
signal axi_rid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_rvalid_clr_ok : std_logic := '0';
signal axi_rvalid_set_cmb : std_logic := '0';
signal axi_rvalid_set : std_logic := '0';
signal axi_rvalid_int : std_logic := '0';
signal axi_rlast_int : std_logic := '0';
signal axi_rlast_set : std_logic := '0';
-- Internal BRAM Signals
signal bram_en_cmb : std_logic := '0';
signal bram_en_int : std_logic := '0';
signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
-- Narrow Burst Signals
signal curr_narrow_burst_cmb : std_logic := '0';
signal curr_narrow_burst : std_logic := '0';
signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_addr_rst : std_logic := '0';
signal narrow_addr_ld_en : std_logic := '0';
signal narrow_addr_dec : std_logic := '0';
signal narrow_bram_addr_inc : std_logic := '0';
signal narrow_bram_addr_inc_d1 : std_logic := '0';
signal narrow_bram_addr_inc_re : std_logic := '0';
signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal curr_ua_narrow_wrap : std_logic := '0';
signal curr_ua_narrow_incr : std_logic := '0';
signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- State machine type declarations
type RLAST_SM_TYPE is ( IDLE,
W8_THROTTLE,
W8_2ND_LAST_DATA,
W8_LAST_DATA,
-- W8_LAST_DATA_B2,
W8_THROTTLE_B2
);
signal rlast_sm_cs, rlast_sm_ns : RLAST_SM_TYPE;
signal last_bram_addr : std_logic := '0';
signal set_last_bram_addr : std_logic := '0';
signal alast_bram_addr : std_logic := '0';
signal rd_b2b_elgible : std_logic := '0';
signal rd_b2b_elgible_no_thr_check : std_logic := '0';
signal throttle_last_data : std_logic := '0';
signal disable_b2b_brst_cmb : std_logic := '0';
signal disable_b2b_brst : std_logic := '0';
signal axi_b2b_brst_cmb : std_logic := '0';
signal axi_b2b_brst : std_logic := '0';
signal do_cmplt_burst_cmb : std_logic := '0';
signal do_cmplt_burst : std_logic := '0';
signal do_cmplt_burst_clr : std_logic := '0';
-------------------------------------------------------------------------------
-- ECC Signals
-------------------------------------------------------------------------------
signal UnCorrectedRdData : std_logic_vector (0 to C_AXI_DATA_WIDTH-1) := (others => '0');
-- Move vector from core ECC module to use in AXI RDATA register output
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to ECC @ 32-bit data width
signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to ECC @ 64-bit data width
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Sl_UE_i : std_logic := '0';
signal UE_Q : std_logic := '0';
-- v1.03a
-- Hsiao ECC
signal syndrome_r : std_logic_vector (C_INT_ECC_WIDTH - 1 downto 0) := (others => '0');
constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- AXI Read Address Channel Output Signals
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_DUAL
-- Purpose: Generate AXI_ARREADY when in dual port mode.
---------------------------------------------------------------------------
GEN_ARREADY_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-- Ensure ARREADY only gets asserted early when acknowledge recognized
-- on AXI read data channel.
AXI_ARREADY <= axi_arready_int or (axi_early_arready_int and rd_adv_buf);
end generate GEN_ARREADY_DUAL;
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_SNG
-- Purpose: Generate AXI_ARREADY when in single port mode.
---------------------------------------------------------------------------
GEN_ARREADY_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- ARREADY generated by sng_port_arb module
AXI_ARREADY <= '0';
axi_arready_int <= '0';
end generate GEN_ARREADY_SNG;
---------------------------------------------------------------------------
-- AXI Read Data Channel Output Signals
---------------------------------------------------------------------------
-- UE flag is detected is same clock cycle that read data is presented on
-- the AXI bus. Must drive SLVERR combinatorially to align with corrupted
-- detected data word.
AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int;
AXI_RVALID <= axi_rvalid_int;
AXI_RID <= axi_rid_int;
AXI_RLAST <= axi_rlast_int;
---------------------------------------------------------------------------
--
-- *** AXI Read Address Channel Interface ***
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_AR_PIPE_SNG
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AR_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- Unused AW pipeline (set default values)
araddr_pipe_ld <= '0';
axi_araddr_pipe <= AXI_ARADDR;
axi_arid_pipe <= AXI_ARID;
axi_arsize_pipe <= AXI_ARSIZE;
axi_arlen_pipe <= AXI_ARLEN;
axi_arburst_pipe <= AXI_ARBURST;
axi_arlen_pipe_1_or_2 <= '0';
axi_arburst_pipe_fixed <= '0';
axi_araddr_full <= '0';
end generate GEN_AR_PIPE_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_AR_PIPE_DUAL
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AR_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-----------------------------------------------------------------------
-- AXI Read Address Buffer/Register
-- (mimic behavior of address pipeline for AXI_ARID)
-----------------------------------------------------------------------
GEN_ARADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate
begin
REG_ARADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- No reset condition to save resources/timing
if (araddr_pipe_ld = '1') then
axi_araddr_pipe (i) <= AXI_ARADDR (i);
else
axi_araddr_pipe (i) <= axi_araddr_pipe (i);
end if;
end if;
end process REG_ARADDR;
end generate GEN_ARADDR;
-------------------------------------------------------------------
-- Register ARID
-- No reset condition to save resources/timing
-------------------------------------------------------------------
REG_ARID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (araddr_pipe_ld = '1') then
axi_arid_pipe <= AXI_ARID;
else
axi_arid_pipe <= axi_arid_pipe;
end if;
end if;
end process REG_ARID;
---------------------------------------------------------------------------
-- In parallel to ARADDR pipeline and ARID
-- Use same control signals to capture AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST.
-- Register AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST
-- No reset condition to save resources/timing
REG_ARCTRL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (araddr_pipe_ld = '1') then
axi_arsize_pipe <= AXI_ARSIZE;
axi_arlen_pipe <= AXI_ARLEN;
axi_arburst_pipe <= AXI_ARBURST;
else
axi_arsize_pipe <= axi_arsize_pipe;
axi_arlen_pipe <= axi_arlen_pipe;
axi_arburst_pipe <= axi_arburst_pipe;
end if;
end if;
end process REG_ARCTRL;
---------------------------------------------------------------------------
-- Create signals that indicate value of AXI_ARLEN in pipeline stage
-- Used to decode length of burst when BRAM address can be loaded early
-- when pipeline is full.
--
-- Add early decode of ARBURST in pipeline.
-- Copy logic from WR_CHNL module (similar logic).
-- Add early decode of ARSIZE = 4 bytes in pipeline.
REG_ARLEN_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- No reset condition to save resources/timing
if (araddr_pipe_ld = '1') then
-- Create merge to decode ARLEN of ONE or TWO
if (AXI_ARLEN = AXI_ARLEN_ONE) or (AXI_ARLEN = AXI_ARLEN_TWO) then
axi_arlen_pipe_1_or_2 <= '1';
else
axi_arlen_pipe_1_or_2 <= '0';
end if;
-- Early decode on value in pipeline of ARBURST
if (AXI_ARBURST = C_AXI_BURST_FIXED) then
axi_arburst_pipe_fixed <= '1';
else
axi_arburst_pipe_fixed <= '0';
end if;
else
axi_arlen_pipe_1_or_2 <= axi_arlen_pipe_1_or_2;
axi_arburst_pipe_fixed <= axi_arburst_pipe_fixed;
end if;
end if;
end process REG_ARLEN_PIPE;
---------------------------------------------------------------------------
-- Create full flag for ARADDR pipeline
-- Set when read address register is loaded.
-- Cleared when read address stored in register is loaded into BRAM
-- address counter.
REG_RDADDR_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- (bram_addr_ld_en = '1' and araddr_pipe_sel = '1') then
(bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and araddr_pipe_ld = '0') then
axi_araddr_full <= '0';
elsif (araddr_pipe_ld = '1') then
axi_araddr_full <= '1';
else
axi_araddr_full <= axi_araddr_full;
end if;
end if;
end process REG_RDADDR_FULL;
---------------------------------------------------------------------------
end generate GEN_AR_PIPE_DUAL;
---------------------------------------------------------------------------
-- v1.03a
-- Add early decode of ARSIZE = max size in pipeline based on AXI data
-- bus width (use constant, C_AXI_SIZE_MAX)
REG_ARSIZE_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_arsize_pipe_max <= '0';
elsif (araddr_pipe_ld = '1') then
-- Early decode of ARSIZE in pipeline equal to max # of bytes
-- based on AXI data bus width
if (AXI_ARSIZE = C_AXI_SIZE_MAX) then
axi_arsize_pipe_max <= '1';
else
axi_arsize_pipe_max <= '0';
end if;
else
axi_arsize_pipe_max <= axi_arsize_pipe_max;
end if;
end if;
end process REG_ARSIZE_PIPE;
---------------------------------------------------------------------------
-- Generate: GE_ARREADY
-- Purpose: ARREADY is only created here when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_ARREADY: if (C_SINGLE_PORT_BRAM = 0) generate
begin
----------------------------------------------------------------------------
-- AXI_ARREADY Output Register
-- Description: Keep AXI_ARREADY output asserted until ARADDR pipeline
-- is full. When a full condition is reached, negate
-- ARREADY as another AR address can not be accepted.
-- Add condition to keep ARReady asserted if loading current
--- ARADDR pipeline value into the BRAM address counter.
-- Indicated by assertion of bram_addr_ld_en & araddr_pipe_sel.
--
----------------------------------------------------------------------------
REG_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_arready_int <= '0';
-- Detect end of S_AXI_AResetn to assert AWREADY and accept
-- new AWADDR values
elsif (axi_aresetn_re_reg = '1') or
-- Add condition for early ARREADY to keep pipeline full
(bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and axi_early_arready_int = '0') then
axi_arready_int <= '1';
-- Add conditional check if ARREADY is asserted (with ARVALID) (one clock cycle later)
-- when the address pipeline is full.
elsif (araddr_pipe_ld = '1') or
(AXI_ARVALID = '1' and axi_arready_int = '1' and axi_araddr_full = '1') then
axi_arready_int <= '0';
else
axi_arready_int <= axi_arready_int;
end if;
end if;
end process REG_ARREADY;
----------------------------------------------------------------------------
REG_EARLY_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_early_arready_int <= '0';
-- Pending ARADDR and ARREADY is not yet asserted to accept
-- operation (due to ARADDR being full)
elsif (AXI_ARVALID = '1' and axi_arready_int = '0' and
axi_araddr_full = '1') and
(alast_bram_addr = '1') and
-- Add check for elgible back-to-back BRAM load
(rd_b2b_elgible = '1') then
axi_early_arready_int <= '1';
else
axi_early_arready_int <= '0';
end if;
end if;
end process REG_EARLY_ARREADY;
---------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert ARREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
axi_aresetn_d2 <= axi_aresetn_d1;
axi_aresetn_re_reg <= axi_aresetn_re;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
----------------------------------------------------------------------------
end generate GEN_ARREADY;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL_ADDR_CNT
-- Purpose: Instantiate BRAM address counter unique for wr_chnl logic
-- only when controller configured in dual port mode.
---------------------------------------------------------------------------
GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
---------------------------------------------------------------------------
-- Replace I_ADDR_CNT module usage of pf_counter in proc_common library.
-- Only need to use lower 12-bits of address due to max AXI burst size
-- Since AXI guarantees bursts do not cross 4KB boundary, the counting part
-- of I_ADDR_CNT can be reduced to max 4KB.
--
-- No reset on bram_addr_int.
-- Increment ONLY.
REG_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (bram_addr_ld_en_mod = '1') then
bram_addr_int <= bram_addr_ld;
elsif (bram_addr_inc_mod = '1') then
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process REG_ADDR_CNT;
---------------------------------------------------------------------------
-- Set defaults to shared address counter
-- Only used in single port configurations
Sng_BRAM_Addr_Ld_En <= '0';
Sng_BRAM_Addr_Ld <= (others => '0');
Sng_BRAM_Addr_Inc <= '0';
end generate GEN_DUAL_ADDR_CNT;
---------------------------------------------------------------------------
-- Generate: GEN_SNG_ADDR_CNT
-- Purpose: When configured in single port BRAM mode, address counter
-- is shared with rd_chnl module. Assign output signals here
-- to counter instantiation at full_axi module level.
---------------------------------------------------------------------------
GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod;
Sng_BRAM_Addr_Ld <= bram_addr_ld;
Sng_BRAM_Addr_Inc <= bram_addr_inc_mod;
bram_addr_int <= Sng_BRAM_Addr;
end generate GEN_SNG_ADDR_CNT;
---------------------------------------------------------------------------
-- BRAM address load mux.
-- Either load BRAM counter directly from AXI bus or from stored registered value
-- Use registered signal to indicate current operation is a WRAP burst
--
-- Match bram_addr_ld to what asserts bram_addr_ld_en_mod
-- Include bram_addr_inc_mod when asserted to use bram_addr_ld_wrap value
-- (otherwise use pipelined or AXI bus value to load BRAM address counter)
bram_addr_ld <= bram_addr_ld_wrap when (max_wrap_burst = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1') else
axi_araddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
when (araddr_pipe_sel = '1') else
AXI_ARADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
---------------------------------------------------------------------------
-- On wrap burst max loads (simultaneous BRAM address increment is asserted).
-- Ensure that load has higher priority over increment.
-- Use registered signal to indicate current operation is a WRAP burst
bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or
(max_wrap_burst = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1'))
else '0';
-- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal
-- logic. No need for the check if the current operation is NOT a fixed AND a wrap
-- burst. The transfer will be one or the other.
-- Found issue when narrow FIXED length burst is incorrectly
-- incrementing BRAM address counter
bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0')
else narrow_bram_addr_inc_re;
----------------------------------------------------------------------------
-- Narrow bursting
--
-- Handle read burst addressing on narrow burst operations
-- Intercept BRAM address increment flag, bram_addr_inc and only
-- increment address when the number of BRAM reads match the width of the
-- AXI data bus.
-- For a 32-bit BRAM, byte burst will increment the BRAM address
-- after four reads from BRAM.
-- For a 256-bit BRAM, a byte burst will increment the BRAM address
-- after 32 reads from BRAM.
-- Based on current operation being a narrow burst, hold off BRAM
-- address increment until narrow burst fits BRAM data width.
-- For non narrow burst operations, use bram_addr_inc from data SM.
--
-- Add in check that burst type is not FIXED, curr_fixed_burst_reg
-- bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else
-- narrow_bram_addr_inc_re;
--
--
-- Replace w/ below generate statements based on supporting narrow transfers or not.
-- Create generate statement around the signal assignment for bram_addr_inc_mod.
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_INC_MOD_W_NARROW
-- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers
-- are supported in design instantiation.
---------------------------------------------------------------------------
GEN_BRAM_INC_MOD_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter
bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else
(narrow_bram_addr_inc_re and not (curr_fixed_burst_reg));
end generate GEN_BRAM_INC_MOD_W_NARROW;
---------------------------------------------------------------------------
-- Generate: GEN_WO_NARROW
-- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers
-- are not supported in the design instantiation.
-- Drive default values for narrow counter and logic when
-- narrow operation support is disabled.
---------------------------------------------------------------------------
GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
-- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter
bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg);
narrow_addr_rst <= '0';
narrow_burst_cnt_ld_mod <= (others => '0');
narrow_addr_dec <= '0';
narrow_addr_ld_en <= '0';
narrow_bram_addr_inc <= '0';
narrow_bram_addr_inc_d1 <= '0';
narrow_bram_addr_inc_re <= '0';
narrow_addr_int <= (others => '0');
curr_narrow_burst <= '0';
end generate GEN_WO_NARROW;
---------------------------------------------------------------------------
--
-- Only instantiate NARROW_CNT and supporting logic when narrow transfers
-- are supported and utilized by masters in the AXI system.
-- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this.
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT
-- Purpose: Instantiate narrow counter and logic when narrow
-- operation support is enabled.
---------------------------------------------------------------------------
GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
--
-- Generate seperate smaller counter for narrow burst operations
-- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library.
--
-- Counter size is adjusted based on size of data burst.
--
-- For example, 32-bit data width BRAM, minimum narrow width
-- burst is 8 bits resulting in a count 3 downto 0. So the
-- minimum counter width = 2 bits.
--
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst
-- is 8 bits resulting in a count 31 downto 0. So the
-- minimum counter width = 5 bits.
--
-- Size of counter = C_NARROW_BURST_CNT_LEN
--
---------------------------------------------------------------------------
REG_NARROW_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (narrow_addr_rst = '1') then
narrow_addr_int <= (others => '0');
-- Load enable
elsif (narrow_addr_ld_en = '1') then
narrow_addr_int <= narrow_burst_cnt_ld_mod;
-- Decrement ONLY (no increment functionality)
elsif (narrow_addr_dec = '1') then
narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <=
std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1);
end if;
end if;
end process REG_NARROW_CNT;
---------------------------------------------------------------------------
narrow_addr_rst <= not (S_AXI_AResetn);
-- Modify narrow burst count load value based on
-- unalignment of AXI address value
narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else
narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else
narrow_burst_cnt_ld_reg;
narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0';
narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re;
narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and
(curr_narrow_burst = '1')
-- Ensure that narrow address counter doesn't
-- flag max or get loaded to
-- reset narrow counter until AXI read data
-- bus has acknowledged current
-- data on the AXI bus. Use rd_adv_buf signal
-- to indicate the non throttle
-- condition on the AXI bus.
and (bram_addr_inc = '1')
else '0';
----------------------------------------------------------------------------
-- Detect rising edge of narrow_bram_addr_inc
REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_bram_addr_inc_d1 <= '0';
else
narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc;
end if;
end if;
end process REG_NARROW_BRAM_ADDR_INC;
narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and
(narrow_bram_addr_inc_d1 = '0')
else '0';
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT;
----------------------------------------------------------------------------
-- Specify current ARSIZE signal
-- Address pipeline MUX
curr_arsize <= axi_arsize_pipe when (araddr_pipe_sel = '1') else AXI_ARSIZE;
REG_ARSIZE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_arsize_reg <= (others => '0');
-- Register curr_arsize when bram_addr_ld_en = '1'
elsif (bram_addr_ld_en = '1') then
curr_arsize_reg <= curr_arsize;
else
curr_arsize_reg <= curr_arsize_reg;
end if;
end if;
end process REG_ARSIZE;
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_EN
-- Purpose: Only instantiate logic to determine if current burst
-- is a narrow burst when narrow bursting logic is supported.
---------------------------------------------------------------------------
GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-----------------------------------------------------------------------
-- Determine "narrow" burst transfers
-- Compare the ARSIZE to the BRAM data width
-----------------------------------------------------------------------
-- v1.03a
-- Detect if current burst operation is of size /= to the full
-- AXI data bus width. If not, then the current operation is a
-- "narrow" burst.
curr_narrow_burst_cmb <= '1' when (curr_arsize /= C_AXI_SIZE_MAX) else '0';
---------------------------------------------------------------------------
-- Register flag indicating the current operation
-- is a narrow read burst
NARROW_BURST_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Need to reset this flag at end of narrow burst operation
-- Ensure if curr_narrow_burst got set during previous transaction, axi_rlast_set
-- doesn't clear the flag (add check for pend_rd_op negated).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_set = '1' and pend_rd_op = '0' and bram_addr_ld_en = '0') then
curr_narrow_burst <= '0';
-- Add check for burst operation using ARLEN value
-- Ensure that narrow burst flag does not get set during FIXED burst types
elsif (bram_addr_ld_en = '1') and (curr_arlen /= AXI_ARLEN_ONE) and
(curr_fixed_burst = '0') then
curr_narrow_burst <= curr_narrow_burst_cmb;
end if;
end if;
end process NARROW_BURST_REG;
end generate GEN_NARROW_EN;
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT_LD
-- Purpose: Only instantiate logic to determine narrow burst counter
-- load value when narrow bursts are enabled.
---------------------------------------------------------------------------
GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
signal curr_arsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal axi_byte_div_curr_arsize : integer := 1;
begin
-- v1.03a
-- Create narrow burst counter load value based on current operation
-- "narrow" data width (indicated by value of AWSIZE).
curr_arsize_unsigned <= unsigned (curr_arsize);
-- XST does not support divisors that are not constants and powers of 2.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- narrow_burst_cnt_ld <= std_logic_vector (
-- to_unsigned (
-- (C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_arsize_unsigned))) ) - 1,
-- C_NARROW_BURST_CNT_LEN));
-- -- With this new process and subsequent signal assignment:
-- DIV_AWSIZE: process (curr_arsize_unsigned)
-- begin
--
-- case (to_integer (curr_arsize_unsigned)) is
-- when 0 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1;
-- when 1 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2;
-- when 2 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4;
-- when 3 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8;
-- when 4 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16;
-- when 5 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32;
-- when 6 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64;
-- when 7 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128;
-- --coverage off
-- when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES;
-- --coverage on
-- end case;
--
-- end process DIV_AWSIZE;
-- w/ CR # 609695
-- With this new process and subsequent signal assignment:
DIV_AWSIZE: process (curr_arsize_unsigned)
begin
case (curr_arsize_unsigned) is
when "000" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128;
--coverage off
when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES;
--coverage on
end case;
end process DIV_AWSIZE;
-- v1.03a
-- Replace with new signal assignment.
-- For synthesis to support only divisors that are constant and powers of two.
-- Updated else clause for simulation warnings w/ CR # 609695
narrow_burst_cnt_ld <= std_logic_vector (
to_unsigned (
(axi_byte_div_curr_arsize) - 1, C_NARROW_BURST_CNT_LEN))
when (axi_byte_div_curr_arsize > 0)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
-- Register narrow burst count load indicator
REG_NAR_BRST_CNT_LD: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_burst_cnt_ld_reg <= (others => '0');
elsif (bram_addr_ld_en = '1') then
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld;
else
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg;
end if;
end if;
end process REG_NAR_BRST_CNT_LD;
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT_LD;
----------------------------------------------------------------------------
-- Handling for WRAP burst types
--
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Boundary is reached based on ARSIZE and ARLEN.
--
-- Goal is to minimize muxing on initial load of counter value.
-- On WRAP burst types, detect when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value set to '0'.
----------------------------------------------------------------------------
-- Detect valid WRAP burst types
curr_wrap_burst <= '1' when (curr_arburst = C_AXI_BURST_WRAP) else '0';
curr_incr_burst <= '1' when (curr_arburst = C_AXI_BURST_INCR) else '0';
curr_fixed_burst <= '1' when (curr_arburst = C_AXI_BURST_FIXED) else '0';
----------------------------------------------------------------------------
-- Register curr_wrap_burst & curr_fixed_burst signals when BRAM
-- address counter is initially loaded
REG_CURR_BRST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_wrap_burst_reg <= '0';
curr_fixed_burst_reg <= '0';
elsif (bram_addr_ld_en = '1') then
curr_wrap_burst_reg <= curr_wrap_burst;
curr_fixed_burst_reg <= curr_fixed_burst;
else
curr_wrap_burst_reg <= curr_wrap_burst_reg;
curr_fixed_burst_reg <= curr_fixed_burst_reg;
end if;
end if;
end process REG_CURR_BRST;
---------------------------------------------------------------------------
-- Instance: I_WRAP_BRST
--
-- Description:
--
-- Instantiate WRAP_BRST module
-- Logic to generate the wrap around value to load into the BRAM address
-- counter on WRAP burst transactions.
-- WRAP value is based on current ARLEN, ARSIZE (for narrows) and
-- data width of BRAM module.
--
---------------------------------------------------------------------------
I_WRAP_BRST : entity work.wrap_brst
generic map (
C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
curr_axlen => curr_arlen ,
curr_axsize => curr_arsize ,
curr_narrow_burst => curr_narrow_burst ,
narrow_bram_addr_inc_re => narrow_bram_addr_inc_re ,
bram_addr_ld_en => bram_addr_ld_en ,
bram_addr_ld => bram_addr_ld ,
bram_addr_int => bram_addr_int ,
bram_addr_ld_wrap => bram_addr_ld_wrap ,
max_wrap_burst_mod => max_wrap_burst
);
----------------------------------------------------------------------------
-- Specify current ARBURST signal
-- Input address pipeline MUX
curr_arburst <= axi_arburst_pipe when (araddr_pipe_sel = '1') else AXI_ARBURST;
----------------------------------------------------------------------------
-- Specify current AWBURST signal
-- Input address pipeline MUX
curr_arlen <= axi_arlen_pipe when (araddr_pipe_sel = '1') else AXI_ARLEN;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_UA_NARROW
-- Purpose: Only instantiate logic for burst narrow WRAP operations when
-- AXI bus protocol is not set for AXI-LITE and narrow
-- burst operations are supported.
--
---------------------------------------------------------------------------
GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
--
-- New logic to detect unaligned address on a narrow WRAP burst transaction.
-- If this condition is met, then the narrow burst counter will be
-- initially loaded with an offset value corresponding to the unalignment
-- in the ARADDR value.
--
--
-- Create a sub module for all logic to determine the narrow burst counter
-- offset value on unaligned WRAP burst operations.
--
-- Module generates the following signals:
--
-- => curr_ua_narrow_wrap, to indicate the current
-- operation is an unaligned narrow WRAP burst.
--
-- => curr_ua_narrow_incr, to load narrow burst counter
-- for unaligned INCR burst operations.
--
-- => ua_narrow_load, narrow counter load value.
-- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0)
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Instance: I_UA_NARROW
--
-- Description:
--
-- Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- Logic is customized for each C_AXI_DATA_WIDTH.
--
---------------------------------------------------------------------------
I_UA_NARROW : entity work.ua_narrow
generic map (
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN
)
port map (
curr_wrap_burst => curr_wrap_burst , -- in
curr_incr_burst => curr_incr_burst , -- in
bram_addr_ld_en => bram_addr_ld_en , -- in
curr_axlen => curr_arlen , -- in
curr_axsize => curr_arsize , -- in
curr_axaddr_lsb => curr_araddr_lsb , -- in
curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out
curr_ua_narrow_incr => curr_ua_narrow_incr , -- out
ua_narrow_load => ua_narrow_load -- out
);
-- Use in all C_AXI_DATA_WIDTH generate statements
-- Only probe least significant BRAM address bits
-- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0.
curr_araddr_lsb <= axi_araddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0)
when (araddr_pipe_sel = '1') else
AXI_ARADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0);
end generate GEN_UA_NARROW;
----------------------------------------------------------------------------
--
-- New logic to detect if pending operation in ARADDR pipeline is
-- elgible for back-to-back no "bubble" performance. And BRAM address
-- counter can be loaded upon last BRAM address presented for the current
-- operation.
-- This condition exists when the ARADDR pipeline is full and the pending
-- operation is a burst >= length of two data beats.
-- And not a FIXED burst type (must be INCR or WRAP type).
-- The DATA SM handles detecting a throttle condition and will void
-- the capability to be a back-to-back in performance transaction.
--
-- Add check if new operation is a narrow burst (to be loaded into BRAM
-- counter)
-- Add check for throttling condition on after last BRAM address is
-- presented
--
----------------------------------------------------------------------------
-- v1.03a
rd_b2b_elgible_no_thr_check <= '1' when (axi_araddr_full = '1') and
(axi_arlen_pipe_1_or_2 /= '1') and
(axi_arburst_pipe_fixed /= '1') and
(disable_b2b_brst = '0') and
(axi_arsize_pipe_max = '1')
else '0';
rd_b2b_elgible <= '1' when (rd_b2b_elgible_no_thr_check = '1') and
(throttle_last_data = '0')
else '0';
-- Check if SM is in LAST_THROTTLE state which also indicates we are throttling at
-- the last data beat in the read burst. Ensures that the bursts are not implemented
-- as back-to-back bursts and RVALID will negate upon recognition of RLAST and RID
-- pipeline will be advanced properly.
-- Fix timing path on araddr_pipe_sel generated in RDADDR SM
-- SM uses rd_b2b_elgible signal which checks throttle condition on
-- last data beat to hold off loading new BRAM address counter for next
-- back-to-back operation.
-- Attempt to modify logic in generation of throttle_last_data signal.
throttle_last_data <= '1' when ((brst_zero = '1') and (rd_adv_buf = '0')) or
(rd_data_sm_cs = LAST_THROTTLE)
else '0';
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_AR_SNG
-- Purpose: If single port BRAM configuration, set all AR flags from
-- logic generated in sng_port_arb module.
--
---------------------------------------------------------------------------
GEN_AR_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
araddr_pipe_sel <= '0'; -- Unused in single port configuration
ar_active <= Arb2AR_Active;
bram_addr_ld_en <= ar_active_re;
brst_cnt_ld_en <= ar_active_re;
AR2Arb_Active_Clr <= axi_rlast_int and AXI_RREADY;
-- Rising edge detect of Arb2AR_Active
RE_AR_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Clear ar_active_d1 early w/ ar_active
-- So back to back ar_active assertions see the new transaction
-- and initiate the read transfer.
if (S_AXI_AResetn = C_RESET_ACTIVE) or ((axi_rlast_int and AXI_RREADY) = '1') then
ar_active_d1 <= '0';
else
ar_active_d1 <= ar_active;
end if;
end if;
end process RE_AR_ACT;
ar_active_re <= '1' when (ar_active = '1' and ar_active_d1 = '0') else '0';
end generate GEN_AR_SNG;
---------------------------------------------------------------------------
--
-- Generate: GEN_AW_DUAL
-- Purpose: Generate AW control state machine logic only when AXI4
-- controller is configured for dual port mode. In dual port
-- mode, wr_chnl has full access over AW & port A of BRAM.
--
---------------------------------------------------------------------------
GEN_AR_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
AR2Arb_Active_Clr <= '0'; -- Only used in single port case
---------------------------------------------------------------------------
-- RD ADDR State Machine
--
-- Description: Central processing unit for AXI write address
-- channel interface handling and handshaking.
--
-- Outputs: araddr_pipe_ld Not Registered
-- araddr_pipe_sel Not Registered
-- bram_addr_ld_en Not Registered
-- brst_cnt_ld_en Not Registered
-- ar_active_set Not Registered
--
-- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RD_ADDR_SM_CMB_PROCESS: process ( AXI_ARVALID,
axi_araddr_full,
ar_active,
no_ar_ack,
pend_rd_op,
last_bram_addr,
rd_b2b_elgible,
rd_addr_sm_cs )
begin
-- assign default values for state machine outputs
rd_addr_sm_ns <= rd_addr_sm_cs;
araddr_pipe_ld_i <= '0';
bram_addr_ld_en_i <= '0';
brst_cnt_ld_en_i <= '0';
ar_active_set_i <= '0';
case rd_addr_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Reload BRAM address counter on last BRAM address of current burst
-- if a new address is pending in the AR pipeline and is elgible to
-- be loaded for subsequent back-to-back performance.
if (last_bram_addr = '1' and rd_b2b_elgible = '1') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- If loading BRAM counter for subsequent operation
-- AND ARVALID is pending on the bus, go ahead and respond
-- and fill ARADDR pipeline with next operation.
--
-- Asserting the signal to load the ARADDR pipeline here
-- allows the full bandwidth utilization to BRAM on
-- back to back bursts of two data beats.
if (AXI_ARVALID = '1') then
araddr_pipe_ld_i <= '1';
rd_addr_sm_ns <= LD_ARADDR;
else
rd_addr_sm_ns <= IDLE;
end if;
elsif (AXI_ARVALID = '1') then
-- If address pipeline is full
-- ARReady output is negated
-- Remain in this state
--
-- Add check for already pending read operation
-- in data SM, but waiting on throttle (even though ar_active is
-- already set to '0').
if (ar_active = '0') and (no_ar_ack = '0') and (pend_rd_op = '0') then
rd_addr_sm_ns <= IDLE;
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- Address counter is currently busy
else
-- Check if ARADDR pipeline is not full and can be loaded
if (axi_araddr_full = '0') then
rd_addr_sm_ns <= LD_ARADDR;
araddr_pipe_ld_i <= '1';
end if;
end if; -- ar_active
-- Pending operation in pipeline that is waiting
-- until current operation is complete (ar_active = '0')
elsif (axi_araddr_full = '1') and
(ar_active = '0') and
(no_ar_ack = '0') and
(pend_rd_op = '0') then
rd_addr_sm_ns <= IDLE;
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
end if; -- ARVALID
---------------------------- LD_ARADDR State ---------------------------
when LD_ARADDR =>
-- Check here for subsequent BRAM address load when ARADDR pipe is loaded
-- in previous clock cycle.
--
-- Reload BRAM address counter on last BRAM address of current burst
-- if a new address is pending in the AR pipeline and is elgible to
-- be loaded for subsequent back-to-back performance.
if (last_bram_addr = '1' and rd_b2b_elgible = '1') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- If loading BRAM counter for subsequent operation
-- AND ARVALID is pending on the bus, go ahead and respond
-- and fill ARADDR pipeline with next operation.
--
-- Asserting the signal to load the ARADDR pipeline here
-- allows the full bandwidth utilization to BRAM on
-- back to back bursts of two data beats.
if (AXI_ARVALID = '1') then
araddr_pipe_ld_i <= '1';
rd_addr_sm_ns <= LD_ARADDR;
-- Stay in this state another clock cycle
else
rd_addr_sm_ns <= IDLE;
end if;
else
rd_addr_sm_ns <= IDLE;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rd_addr_sm_ns <= IDLE;
--coverage on
end case;
end process RD_ADDR_SM_CMB_PROCESS;
---------------------------------------------------------------------------
-- CR # 582705
-- Ensure combinatorial SM output signals do not get set before
-- the end of the reset (and ARREAADY can be set).
bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d2;
brst_cnt_ld_en <= brst_cnt_ld_en_i and axi_aresetn_d2;
ar_active_set <= ar_active_set_i and axi_aresetn_d2;
araddr_pipe_ld <= araddr_pipe_ld_i and axi_aresetn_d2;
RD_ADDR_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
-- Ensure that ar_active does not get asserted (from SM) before
-- the end of reset and the ARREADY flag is set.
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
rd_addr_sm_cs <= IDLE;
else
rd_addr_sm_cs <= rd_addr_sm_ns;
end if;
end if;
end process RD_ADDR_SM_REG_PROCESS;
---------------------------------------------------------------------------
-- Assert araddr_pipe_sel outside of SM logic
-- The BRAM address counter will get loaded with value in ARADDR pipeline
-- when data is stored in the ARADDR pipeline.
araddr_pipe_sel <= '1' when (axi_araddr_full = '1') else '0';
---------------------------------------------------------------------------
-- Register for ar_active
REG_AR_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
ar_active <= '0';
elsif (ar_active_set = '1') then
ar_active <= '1';
-- For code coverage closure, ensure priority encoding in if/else clause
-- to prevent checking ar_active_set in reset clause.
elsif (ar_active_clr = '1') then
ar_active <= '0';
else
ar_active <= ar_active;
end if;
end if;
end process REG_AR_ACT;
end generate GEN_AR_DUAL;
---------------------------------------------------------------------------
--
-- REG_BRST_CNT.
-- Read Burst Counter.
-- No need to decrement burst counter.
-- Able to load with fixed burst length value.
-- Replace usage of proc_common_v4_0_2 library with direct HDL.
--
-- Size of counter = C_BRST_CNT_SIZE
-- Max size of burst transfer = 256 data beats
--
---------------------------------------------------------------------------
REG_BRST_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (brst_cnt_rst = '1') then
brst_cnt <= (others => '0');
-- Load burst counter
elsif (brst_cnt_ld_en = '1') then
brst_cnt <= brst_cnt_ld;
-- Decrement ONLY (no increment functionality)
elsif (brst_cnt_dec = '1') then
brst_cnt (C_BRST_CNT_SIZE-1 downto 0) <=
std_logic_vector (unsigned (brst_cnt (C_BRST_CNT_SIZE-1 downto 0)) - 1);
end if;
end if;
end process REG_BRST_CNT;
---------------------------------------------------------------------------
brst_cnt_rst <= not (S_AXI_AResetn);
-- Determine burst count load value
-- Either load BRAM counter directly from AXI bus or from stored registered value.
-- Use mux signal for ARLEN
BRST_CNT_LD_PROCESS : process (curr_arlen)
variable brst_cnt_ld_int : integer := 0;
begin
brst_cnt_ld_int := to_integer (unsigned (curr_arlen (7 downto 0)));
brst_cnt_ld <= std_logic_vector (to_unsigned (brst_cnt_ld_int, 8));
end process BRST_CNT_LD_PROCESS;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_BRST_MAX_W_NARROW
-- Purpose: Generate registered logic for brst_cnt_max when the
-- design instantiation supports narrow operations.
--
---------------------------------------------------------------------------
GEN_BRST_MAX_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
REG_BRST_MAX: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1')
-- Added with single port (13.1 release)
or (end_brst_rd_clr = '1') then
brst_cnt_max <= '0';
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then
-- Hold off assertion of brst_cnt_max on narrow burst transfers
-- Must wait until narrow burst count = 0.
if (curr_narrow_burst = '1') then
if (narrow_bram_addr_inc = '1') then
brst_cnt_max <= '1';
end if;
else
brst_cnt_max <= '1';
end if;
else
brst_cnt_max <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX;
end generate GEN_BRST_MAX_W_NARROW;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRST_MAX_WO_NARROW
-- Purpose: Generate registered logic for brst_cnt_max when the
-- design instantiation does not support narrow operations.
--
---------------------------------------------------------------------------
GEN_BRST_MAX_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
REG_BRST_MAX: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1') then
brst_cnt_max <= '0';
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then
-- When narrow operations are not supported in the core
-- configuration, no check for curr_narrow_burst on assertion.
brst_cnt_max <= '1';
else
brst_cnt_max <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX;
end generate GEN_BRST_MAX_WO_NARROW;
---------------------------------------------------------------------------
REG_BRST_MAX_D1: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
brst_cnt_max_d1 <= '0';
else
brst_cnt_max_d1 <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX_D1;
brst_cnt_max_re <= '1' when (brst_cnt_max = '1') and (brst_cnt_max_d1 = '0') else '0';
-- Set flag that end of burst is reached
-- Need to capture this condition as the burst
-- counter may get reloaded for a subsequent read burst
REG_END_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- SM may assert clear flag early (in case of narrow bursts)
-- Wait until the end_brst_rd flag is asserted to clear the flag.
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(end_brst_rd_clr = '1' and end_brst_rd = '1') then
end_brst_rd <= '0';
elsif (brst_cnt_max_re = '1') then
end_brst_rd <= '1';
end if;
end if;
end process REG_END_BURST;
---------------------------------------------------------------------------
-- Create flag that indicates burst counter is reaching ZEROs (max of burst
-- length)
REG_BURST_ZERO: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ZERO)) then
brst_zero <= '0';
elsif (brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE) then
brst_zero <= '1';
else
brst_zero <= brst_zero;
end if;
end if;
end process REG_BURST_ZERO;
---------------------------------------------------------------------------
-- Create additional flag that indicates burst counter is reaching ONEs
-- (near end of burst length). Used to disable back-to-back condition in SM.
REG_BURST_ONE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ONE)) or
((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE)) then
brst_one <= '0';
elsif ((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_TWO)) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld = C_BRST_CNT_ONE)) then
brst_one <= '1';
else
brst_one <= brst_one;
end if;
end if;
end process REG_BURST_ONE;
---------------------------------------------------------------------------
-- Register flags for read burst operation
REG_RD_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear axi_rd_burst flags when burst count gets to zeros (unless the burst
-- counter is getting subsequently loaded for the new burst operation)
--
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_zero = '1' and brst_cnt_ld_en = '0') then
axi_rd_burst <= '0';
axi_rd_burst_two <= '0';
elsif (brst_cnt_ld_en = '1') then
if (curr_arlen /= AXI_ARLEN_ONE and curr_arlen /= AXI_ARLEN_TWO) then
axi_rd_burst <= '1';
else
axi_rd_burst <= '0';
end if;
if (curr_arlen = AXI_ARLEN_TWO) then
axi_rd_burst_two <= '1';
else
axi_rd_burst_two <= '0';
end if;
else
axi_rd_burst <= axi_rd_burst;
axi_rd_burst_two <= axi_rd_burst_two;
end if;
end if;
end process REG_RD_BURST;
---------------------------------------------------------------------------
-- Seeing issue with axi_rd_burst getting cleared too soon
-- on subsquent brst_cnt_ld_en early assertion and pend_rd_op is asserted.
-- Create flag for currently active read burst operation
-- Gets asserted when burst counter is loaded, but does not
-- get cleared until the RD_DATA_SM has completed the read
-- burst operation
REG_ACT_RD_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (act_rd_burst_clr = '1') then
act_rd_burst <= '0';
act_rd_burst_two <= '0';
elsif (act_rd_burst_set = '1') then
-- If not loading the burst counter for a B2B operation
-- Then act_rd_burst follows axi_rd_burst and
-- act_rd_burst_two follows axi_rd_burst_two.
-- Get registered value of axi_* signal.
if (brst_cnt_ld_en = '0') then
act_rd_burst <= axi_rd_burst;
act_rd_burst_two <= axi_rd_burst_two;
else
-- Otherwise, duplicate logic for axi_* signals if burst counter
-- is getting loaded.
-- For improved code coverage here
-- The act_rd_burst_set signal will never get asserted if the burst
-- size is less than two data beats. So, the conditional check
-- for (curr_arlen /= AXI_ARLEN_ONE) is never evaluated. Removed
-- from this if clause.
if (curr_arlen /= AXI_ARLEN_TWO) then
act_rd_burst <= '1';
else
act_rd_burst <= '0';
end if;
if (curr_arlen = AXI_ARLEN_TWO) then
act_rd_burst_two <= '1';
else
act_rd_burst_two <= '0';
end if;
-- Note: re-code this if/else clause.
end if;
else
act_rd_burst <= act_rd_burst;
act_rd_burst_two <= act_rd_burst_two;
end if;
end if;
end process REG_ACT_RD_BURST;
---------------------------------------------------------------------------
rd_adv_buf <= axi_rvalid_int and AXI_RREADY;
---------------------------------------------------------------------------
-- RD DATA State Machine
--
-- Description: Central processing unit for AXI write data
-- channel interface handling and AXI write data response
-- handshaking.
--
-- Outputs: Name Type
--
-- bram_en_int Registered
-- bram_addr_inc Not Registered
-- brst_cnt_dec Not Registered
-- rddata_mux_sel Registered
-- axi_rdata_en Not Registered
-- axi_rvalid_set Registered
--
--
-- RD_DATA_SM_CMB_PROCESS: Combinational process to determine next state.
-- RD_DATA_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RD_DATA_SM_CMB_PROCESS: process ( bram_addr_ld_en,
rd_adv_buf,
ar_active,
axi_araddr_full,
rd_b2b_elgible_no_thr_check,
disable_b2b_brst,
curr_arlen,
axi_rd_burst,
axi_rd_burst_two,
act_rd_burst,
act_rd_burst_two,
end_brst_rd,
brst_zero,
brst_one,
axi_b2b_brst,
bram_en_int,
rddata_mux_sel,
end_brst_rd_clr,
no_ar_ack,
pend_rd_op,
axi_rlast_int,
rd_data_sm_cs )
begin
-- assign default values for state machine outputs
rd_data_sm_ns <= rd_data_sm_cs;
bram_en_cmb <= bram_en_int;
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_skid_buf_ld_cmb <= '0';
rd_skid_buf_ld_imm <= '0';
rddata_mux_sel_cmb <= rddata_mux_sel;
-- Change axi_rdata_en generated from SM to be a combinatorial signal
-- Can't afford the latency when throttling on the AXI bus.
axi_rdata_en <= '0';
axi_rvalid_set_cmb <= '0';
end_brst_rd_clr_cmb <= end_brst_rd_clr;
no_ar_ack_cmb <= no_ar_ack;
pend_rd_op_cmb <= pend_rd_op;
act_rd_burst_set <= '0';
act_rd_burst_clr <= '0';
set_last_bram_addr <= '0';
alast_bram_addr <= '0';
axi_b2b_brst_cmb <= axi_b2b_brst;
disable_b2b_brst_cmb <= disable_b2b_brst;
ar_active_clr <= '0';
case rd_data_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Initiate BRAM read when address is available in controller
-- Indicated by load of BRAM address counter
-- Remove use of pend_rd_op signal.
-- Never asserted as we transition back to IDLE
-- Detected in code coverage
if (bram_addr_ld_en = '1') then
-- At start of new read, clear end burst signal
end_brst_rd_clr_cmb <= '0';
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- If currently loading BRAM address counter
-- Must check curr_arlen (mux output from pipe or AXI bus)
-- to determine length of next operation.
-- If ARLEN = 1 data beat, then set last_bram_addr signal
-- Otherwise, increment BRAM address counter.
if (curr_arlen /= AXI_ARLEN_ONE) then
-- Start of new operation, update act_rd_burst and
-- act_rd_burst_two signals
act_rd_burst_set <= '1';
else
-- Set flag for last_bram_addr on transition
-- to SNG_ADDR on single operations.
set_last_bram_addr <= '1';
end if;
-- Go to single active read address state
rd_data_sm_ns <= SNG_ADDR;
end if;
------------------------- SNG_ADDR State --------------------------
when SNG_ADDR =>
-- Clear flag once pending read is recognized
-- Duplicate logic here in case combinatorial flag was getting
-- set as the SM transitioned into this state.
if (pend_rd_op = '1') then
pend_rd_op_cmb <= '0';
end if;
-- At start of new read, clear end burst signal
end_brst_rd_clr_cmb <= '0';
-- Reach this state on first BRAM address & enable assertion
-- For burst operation, create next BRAM address and keep enable
-- asserted
-- Note:
-- No ability to throttle yet as RVALID has not yet been
-- asserted on the AXI bus
-- Reset data mux select between skid buffer and BRAM
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Assert RVALID on AXI when 1st data beat available
-- from BRAM
axi_rvalid_set_cmb <= '1';
-- Reach this state when BRAM address counter is loaded
-- Use axi_rd_burst and axi_rd_burst_two to indicate if
-- operation is a single data beat burst.
if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then
-- Proceed directly to get BRAM read data
rd_data_sm_ns <= LAST_ADDR;
-- End of active current read address
ar_active_clr <= '1';
-- Negate BRAM enable
bram_en_cmb <= '0';
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
-- Read burst
else
-- Increment BRAM address counter (2nd data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (2nd data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
rd_data_sm_ns <= SEC_ADDR;
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Start of new operation, update act_rd_burst and
-- act_rd_burst_two signals
act_rd_burst_set <= '1';
-- If new burst is 2 data beats
-- Then disable capability on back-to-back bursts
if (axi_rd_burst_two = '1') then
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
else
-- Support back-to-back for all other burst lengths
disable_b2b_brst_cmb <= '0';
end if;
end if;
------------------------- SEC_ADDR State --------------------------
when SEC_ADDR =>
-- Reach this state when the 2nd incremented address of the burst
-- is presented to the BRAM.
-- Only reach this state when axi_rd_burst = '1',
-- an active read burst.
-- Note:
-- No ability to throttle yet as RVALID has not yet been
-- asserted on the AXI bus
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Only in dual port mode can the address counter get loaded early
if C_SINGLE_PORT_BRAM = 0 then
-- If we see the next address get loaded into the BRAM counter
-- then set flag for pending operation
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
end if;
-- Check here for burst length of two data transfers
-- If so, then the SM will NOT hit the condition of a full
-- pipeline:
-- Operation A) 1st BRAM address data on AXI bus
-- Operation B) 2nd BRAm address data read from BRAM
-- Operation C) 3rd BRAM address presented to BRAM
--
-- Full pipeline condition is hit for any read burst
-- length greater than 2 data beats.
if (axi_rd_burst_two = '1') then
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
rd_data_sm_ns <= LAST_ADDR;
-- End of active current read address
ar_active_clr <= '1';
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- Load read data skid buffer for BRAM capture
-- in next clock cycle.
-- This signal will negate in the next state
-- if the data is not accepted on the AXI bus.
-- So that no new data from BRAM is registered into the
-- read channel controller.
rd_skid_buf_ld_cmb <= '1';
else
-- Burst length will hit full pipeline condition
-- Increment BRAM address counter (3rd data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (3rd data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
rd_data_sm_ns <= FULL_PIPE;
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- Replace usage of brst_cnt with signal, brst_one.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
end if; -- ARLEN = "0000 0001"
------------------------- FULL_PIPE State -------------------------
when FULL_PIPE =>
-- Reach this state when all three data beats in the burst
-- are active
--
-- Operation A) 1st BRAM address data on AXI bus
-- Operation B) 2nd BRAM address data read from BRAM
-- Operation C) 3rd BRAM address presented to BRAM
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- With new pipelining capability BRAM address counter may be
-- loaded in this state. This only occurs on back-to-back
-- bursts (when enabled).
-- No flag set for pending operation.
-- Modify the if clause here to check for back-to-back burst operations
-- If we load the BRAM address in this state for a subsequent burst, then
-- this condition indicates a back-to-back burst and no need to assert
-- the pending read operation flag.
-- Seeing corner case when pend_rd_op needs to be asserted and cleared
-- in this state. If the BRAM address counter is loaded early, but
-- axi_rlast_set is delayed in getting asserted (all while in this state).
-- The signal, curr_narrow_burst can not get cleared.
-- Only in dual port mode can the address counter get loaded early
if C_SINGLE_PORT_BRAM = 0 then
-- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
-- Clear flag once pending read is recognized and
-- earlier read data phase is complete.
elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then
pend_rd_op_cmb <= '0';
end if;
end if;
-- Check AXI throttling condition
-- If AXI bus advances and accepts read data, SM can
-- proceed with next data beat of burst.
-- If not, then go to FULL_THROTTLE state to wait for
-- AXI_RREADY = '1'.
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
axi_rdata_en <= '1';
-- Load read data skid buffer for BRAM capture in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- Replace usage of brst_cnt with signal, brst_one.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Check burst counter for max
-- If max burst count is reached, no new addresses
-- presented to BRAM, advance to last capture data states.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1' and axi_b2b_brst = '0') then
-- Check for elgible pending read operation to support back-to-back performance.
-- If so, load BRAM address counter.
--
-- Replace rd_b2b_elgible signal check to remove path from
-- arlen_pipe through rd_b2b_elgible
-- (with data throttle check)
if (rd_b2b_elgible_no_thr_check = '1') then
rd_data_sm_ns <= FULL_PIPE;
-- Set flag to indicate back-to-back read burst
-- RVALID will not clear in this case and remain asserted
axi_b2b_brst_cmb <= '1';
-- Set flag to update active read burst or
-- read burst of two flag
act_rd_burst_set <= '1';
-- Otherwise, complete current transaction
else
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_data_sm_ns <= LAST_ADDR;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- End of active current read address
ar_active_clr <= '1';
end if;
else
-- Remain in this state until burst count reaches zero
-- Increment BRAM address counter (Nth data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (Nth data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
-- Skid buffer load will remain asserted
-- AXI read data register is asserted
end if;
else
-- Throttling condition detected
rd_data_sm_ns <= FULL_THROTTLE;
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Skid buffer gets loaded from BRAM read data in next clock
-- cycle ONLY.
-- Only on transition to THROTTLE state does skid buffer get loaded.
-- Negate load of read data skid buffer for BRAM capture
-- in next clock cycle due to detection of Throttle condition
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
-- If transitioning to throttle state
-- Then next register enable assertion of the AXI read data
-- output register needs to come from the skid buffer
-- Set read data mux select here for SKID_BUFFER data
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- Detect if at end of burst read as we transition to FULL_THROTTLE
-- If so, negate the BRAM enable even if prior to throttle condition
-- on AXI bus. Read skid buffer will hold last beat of data in burst.
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
-- No back to back "non bubble" support when AXI master
-- is throttling on current burst.
-- Seperate signal throttle_last_data will be asserted outside SM.
-- End of burst read, negate BRAM enable
bram_en_cmb <= '0';
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Disable B2B capability if throttling detected when
-- burst count is equal to one.
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_one, indicating the
-- brst_cnt to be one when decrement.
elsif (brst_one = '1') then
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Throttle, but not end of burst
else
bram_en_cmb <= '1';
end if;
end if; -- rd_adv_buf (RREADY throttle)
------------------------- FULL_THROTTLE State ---------------------
when FULL_THROTTLE =>
-- Reach this state when the AXI bus throttles on the AXI data
-- beat read from BRAM (when the read pipeline is fully active)
-- Flag disable_b2b_brst_cmb should be asserted as we transition
-- to this state. Flag is asserted near the end of a read burst
-- to prevent the back-to-back performance pipelining in the BRAM
-- address counter.
-- Detect if at end of burst read
-- If so, negate the BRAM enable even if prior to throttle condition
-- on AXI bus. Read skid buffer will hold last beat of data in burst.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
bram_en_cmb <= '0';
end if;
-- Set new flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
-- Clear flag once pending read is recognized and
-- earlier read data phase is complete.
elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then
pend_rd_op_cmb <= '0';
end if;
-- Wait for RREADY to be asserted w/ RVALID on AXI bus
if (rd_adv_buf = '1') then
-- Ensure read data mux is set for skid buffer data
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- Ensure that AXI read data output register is enabled
axi_rdata_en <= '1';
-- Must reload skid buffer here from BRAM data
-- so if needed can be presented to AXI bus on the following clock cycle
rd_skid_buf_ld_imm <= '1';
-- When detecting end of throttle condition
-- Check first if burst count is complete
-- Check burst counter for max
-- If max burst count is reached, no new addresses
-- presented to BRAM, advance to last capture data states.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
-- No back-to-back performance when AXI master throttles
-- If we reach the end of the burst, proceed to LAST_ADDR state.
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_data_sm_ns <= LAST_ADDR;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- End of active current read address
ar_active_clr <= '1';
-- Not end of current burst w/ throttle condition
else
-- Go back to FULL_PIPE
rd_data_sm_ns <= FULL_PIPE;
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_one, indicating the
-- brst_cnt to be one when decrement.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Increment BRAM address counter (Nth data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (Nth data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
end if; -- Burst Max
else
-- Stay in this state
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Ensure that skid buffer is not getting loaded with
-- current read data from BRAM
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
end if; -- rd_adv_buf (RREADY throttle)
------------------------- LAST_ADDR State -------------------------
when LAST_ADDR =>
-- Reach this state in the clock cycle following the last address
-- presented to the BRAM. Capture the last BRAM data beat in the
-- next clock cycle.
--
-- Data is presented to AXI bus (if no throttling detected) and
-- loaded into the skid buffer.
-- If we reach this state after back to back burst transfers
-- then clear the flag to ensure that RVALID will clear when RLAST
-- is recognized
if (axi_b2b_brst = '1') then
axi_b2b_brst_cmb <= '0';
end if;
-- Clear flag that indicates end of read burst
-- Once we reach this state, we have recognized the burst complete.
--
-- It is getting asserted too early
-- and recognition of the end of the burst is missed when throttling
-- on the last two data beats in the read.
end_brst_rd_clr_cmb <= '1';
-- Set new flag for pending operation if ar_active is asserted (BRAM
-- address has already been loaded) and we are waiting for the current
-- read burst to complete. If those two conditions apply, set this flag.
-- For dual port, support checking for early writes into BRAM address counter
if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- Support back-to-backs for single AND dual port modes.
-- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- if (ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
-- Load read data skid buffer for BRAM is asserted on transition
-- into this state. Only gets negated if done with operation
-- as detected in below if clause.
-- Check flag for no subsequent operations
-- Clear that now, with current operation completing
if (no_ar_ack = '1') then
no_ar_ack_cmb <= '0';
end if;
-- Check for single AXI read operations
-- If so, wait for RREADY to be asserted
-- Check for burst and bursts of two as seperate signals.
if (act_rd_burst = '0') and (act_rd_burst_two = '0') then
-- Create rvalid_set to only be asserted for a single clock
-- cycle.
-- Will get set as transitioning to LAST_ADDR on single read operations
-- Only assert RVALID here on single operations
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Data will not yet be acknowledged on AXI
-- in this state.
-- Go to wait for last data beat
rd_data_sm_ns <= LAST_DATA;
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
else
-- Only check throttling on AXI during read data burst operations
-- Check AXI throttling condition
-- If AXI bus advances and accepts read data, SM can
-- proceed with next data beat.
-- If not, then go to LAST_THROTTLE state to wait for
-- AXI_RREADY = '1'.
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
-- in next clock cycle
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Burst counter already at zero. Reached this state due to NO
-- pending ARADDR in the read address pipeline. However, check
-- here for any new read addresses.
-- New ARADDR detected and loaded into BRAM address counter
-- Add check here for previously loaded BRAM address
-- ar_active will be asserted (and qualify that with the
-- condition that the read burst is complete, for narrow reads).
if (bram_addr_ld_en = '1') then
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Instead of transitioning to SNG_ADDR
-- go to wait for last data beat.
rd_data_sm_ns <= LAST_DATA_AR_PEND;
else
-- No pending read address to initiate next read burst
-- Go to capture last data beat from BRAM and present on AXI bus.
rd_data_sm_ns <= LAST_DATA;
end if; -- bram_addr_ld_en (New read burst)
else
-- Throttling condition detected
rd_data_sm_ns <= LAST_THROTTLE;
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Skid buffer gets loaded from BRAM read data in next clock
-- cycle ONLY.
-- Only on transition to THROTTLE state does skid buffer get loaded.
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
end if; -- rd_adv_buf (RREADY throttle)
end if; -- AXI read burst
------------------------- LAST_THROTTLE State ---------------------
when LAST_THROTTLE =>
-- Reach this state when the AXI bus throttles on the last data
-- beat read from BRAM
-- Data to be sourced from read skid buffer
-- Add check in LAST_THROTTLE as well as LAST_ADDR
-- as we may miss the setting of this flag for a subsequent operation.
-- For dual port, support checking for early writes into BRAM address counter
if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- Support back-to-back for single AND dual port modes.
-- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
pend_rd_op_cmb <= '1';
end if;
-- Wait for RREADY to be asserted w/ RVALID on AXI bus
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
axi_rdata_en <= '1';
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- No pending read address to initiate next read burst
-- Go to capture last data beat from BRAM and present on AXI bus.
rd_data_sm_ns <= LAST_DATA;
-- Load read data skid buffer for BRAM capture in next clock cycle
-- of last data read
-- Read Skid buffer already loaded with last data beat from BRAM
-- Does not need to be asserted again in this state
else
-- Stay in this state
-- Ensure that AXI read data output register is disabled
axi_rdata_en <= '0';
-- Ensure that skid buffer is not getting loaded with
-- current read data from BRAM
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
-- Keep RVALID asserted on AXI
-- No need to assert RVALID again
end if; -- rd_adv_buf (RREADY throttle)
------------------------- LAST_DATA State -------------------------
when LAST_DATA =>
-- Reach this state when last BRAM data beat is
-- presented on AXI bus.
-- For a read burst, RLAST is not asserted until SM reaches
-- this state.
-- Ok to accept new operation if throttling detected
-- during current operation (and flag was previously set
-- to disable the back-to-back performance).
disable_b2b_brst_cmb <= '0';
-- Stay in this state until RREADY is asserted on AXI bus
-- Indicated by assertion of rd_adv_buf
if (rd_adv_buf = '1') then
-- Last data beat acknowledged on AXI bus
-- Check for new read burst or proceed back to IDLE
-- New ARADDR detected and loaded into BRAM address counter
-- Note: this condition may occur when C_SINGLE_PORT_BRAM = 0 or 1
if (bram_addr_ld_en = '1') or (pend_rd_op = '1') then
-- Clear flag once pending read is recognized
if (pend_rd_op = '1') then
pend_rd_op_cmb <= '0';
end if;
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- Go to SNG_ADDR state
rd_data_sm_ns <= SNG_ADDR;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
-- If we are loading the BRAM, then we have to view the curr_arlen
-- signal to determine if the next operation is a single transfer.
-- Or if the BRAM address counter is already loaded (and we reach
-- this if clause due to pend_rd_op then the axi_* signals will indicate
-- if the next operation is a burst or not.
-- If the operation is a single transaction, then set the last_bram_addr
-- signal when we reach SNG_ADDR.
if (bram_addr_ld_en = '1') then
if (curr_arlen = AXI_ARLEN_ONE) then
-- Set flag for last_bram_addr on transition
-- to SNG_ADDR on single operations.
set_last_bram_addr <= '1';
end if;
elsif (pend_rd_op = '1') then
if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then
set_last_bram_addr <= '1';
end if;
end if;
else
-- No pending read address to initiate next read burst.
-- Go to IDLE
rd_data_sm_ns <= IDLE;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
end if;
else
-- Throttling condition detected
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- If new ARADDR detected and loaded into BRAM address counter
if (bram_addr_ld_en = '1') then
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- Instead of transitioning to SNG_ADDR
-- to wait for last data beat.
rd_data_sm_ns <= LAST_DATA_AR_PEND;
-- For singles, block any subsequent loads into BRAM address
-- counter from AR SM
no_ar_ack_cmb <= '1';
end if;
end if; -- rd_adv_buf (RREADY throttle)
------------------------ LAST_DATA_AR_PEND --------------------
when LAST_DATA_AR_PEND =>
-- Ok to accept new operation if throttling detected
-- during current operation (and flag was previously set
-- to disable the back-to-back performance).
disable_b2b_brst_cmb <= '0';
-- Reach this state when new BRAM address is loaded into
-- BRAM address counter
-- But waiting for last RREADY/RVALID/RLAST to be asserted
-- Once this occurs, continue with pending AR operation
if (rd_adv_buf = '1') then
-- Go to SNG_ADDR state
rd_data_sm_ns <= SNG_ADDR;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
-- In this state, the BRAM address counter is already loaded,
-- the axi_rd_burst and axi_rd_burst_two signals will indicate
-- if the next operation is a burst or not.
-- If the operation is a single transaction, then set the last_bram_addr
-- signal when we reach SNG_ADDR.
if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then
set_last_bram_addr <= '1';
end if;
-- Code coverage tests are reporting that reaching this state
-- always when axi_rd_burst = '0' and axi_rd_burst_two = '0',
-- so no bursting operations.
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rd_data_sm_ns <= IDLE;
--coverage on
end case;
end process RD_DATA_SM_CMB_PROCESS;
---------------------------------------------------------------------------
RD_DATA_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_data_sm_cs <= IDLE;
bram_en_int <= '0';
rd_skid_buf_ld_reg <= '0';
rddata_mux_sel <= C_RDDATA_MUX_BRAM;
axi_rvalid_set <= '0';
end_brst_rd_clr <= '0';
no_ar_ack <= '0';
pend_rd_op <= '0';
axi_b2b_brst <= '0';
disable_b2b_brst <= '0';
else
rd_data_sm_cs <= rd_data_sm_ns;
bram_en_int <= bram_en_cmb;
rd_skid_buf_ld_reg <= rd_skid_buf_ld_cmb;
rddata_mux_sel <= rddata_mux_sel_cmb;
axi_rvalid_set <= axi_rvalid_set_cmb;
end_brst_rd_clr <= end_brst_rd_clr_cmb;
no_ar_ack <= no_ar_ack_cmb;
pend_rd_op <= pend_rd_op_cmb;
axi_b2b_brst <= axi_b2b_brst_cmb;
disable_b2b_brst <= disable_b2b_brst_cmb;
end if;
end if;
end process RD_DATA_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Create seperate registered process for last_bram_addr signal.
-- Only asserted for a single clock cycle
-- Gets set when the burst counter is loaded with 0's (for a single data beat operation)
-- (indicated by set_last_bram_addr from DATA SM)
-- or when the burst counter is decrement and the current value = 1
REG_LAST_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
last_bram_addr <= '0';
-- The signal, set_last_bram_addr, is asserted when the DATA SM transitions to SNG_ADDR
-- on a single data beat burst. Can not use condition of loading burst counter
-- with the value of 0's (as the burst counter may be loaded during prior single operation
-- when waiting on last throttle/data beat, ie. rd_adv_buf not yet asserted).
elsif (set_last_bram_addr = '1') or
-- On burst operations at the last BRAM address presented to BRAM
(brst_cnt_dec = '1' and brst_cnt = C_BRST_CNT_ONE) then
last_bram_addr <= '1';
else
last_bram_addr <= '0';
end if;
end if;
end process REG_LAST_BRAM_ADDR;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- *** AXI Read Data Channel Interface ***
--
---------------------------------------------------------------------------
rd_skid_buf_ld <= rd_skid_buf_ld_reg or rd_skid_buf_ld_imm;
---------------------------------------------------------------------------
-- Generate: GEN_RDATA_NO_ECC
-- Purpose: Generation of AXI_RDATA output register without ECC
-- logic (C_ECC = 0 parameterization in design)
---------------------------------------------------------------------------
GEN_RDATA_NO_ECC: if C_ECC = 0 generate
signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
begin
---------------------------------------------------------------------------
-- AXI RdData Skid Buffer/Register
-- Sized according to size of AXI/BRAM data width
---------------------------------------------------------------------------
REG_RD_BUF: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_skid_buf <= (others => '0');
-- Add immediate load of read skid buffer
-- Occurs in the case when at full throttle and RREADY/RVALID are asserted
elsif (rd_skid_buf_ld = '1') then
rd_skid_buf <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0);
else
rd_skid_buf <= rd_skid_buf;
end if;
end if;
end process REG_RD_BUF;
-- Rd Data Mux (selects between skid buffer and BRAM read data)
-- Select control signal from SM determines register load value
axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else
rd_skid_buf;
---------------------------------------------------------------------------
-- Generate: GEN_RDATA
-- Purpose: Generate each bit of AXI_RDATA.
---------------------------------------------------------------------------
GEN_RDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate
begin
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear output after last data beat accepted by requesting AXI master
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Don't clear RDDATA when a back to back burst is occuring on RLAST & RVALID assertion
-- For improved code coverage, can remove the signal, axi_rvalid_int from this if clause.
-- It will always be asserted in this case.
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rdata_int (i) <= '0';
elsif (axi_rdata_en = '1') then
axi_rdata_int (i) <= axi_rdata_mux (i);
else
axi_rdata_int (i) <= axi_rdata_int (i);
end if;
end if;
end process REG_RDATA;
end generate GEN_RDATA;
-- If C_ECC = 0, direct output assignment to AXI_RDATA
AXI_RDATA <= axi_rdata_int;
end generate GEN_RDATA_NO_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_RDATA_ECC
-- Purpose: Generation of AXI_RDATA output register when ECC
-- logic is enabled (C_ECC = 1 parameterization in design)
---------------------------------------------------------------------------
GEN_RDATA_ECC: if C_ECC = 1 generate
subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1);
-- 0:6 for 32-bit ECC
-- 0:7 for 64-bit ECC
type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits;
signal rd_skid_buf_i : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int_corr : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- Remove GEN_RD_BUF that was doing bit reversal.
-- Replace with direct register assignments. Sized according to AXI data width.
REG_RD_BUF: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_skid_buf_i <= (others => '0');
-- Add immediate load of read skid buffer
-- Occurs in the case when at full throttle and RREADY/RVALID are asserted
elsif (rd_skid_buf_ld = '1') then
rd_skid_buf_i (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1);
else
rd_skid_buf_i <= rd_skid_buf_i;
end if;
end if;
end process REG_RD_BUF;
-- Rd Data Mux (selects between skid buffer and BRAM read data)
-- Select control signal from SM determines register load value
-- axi_rdata_mux holds data + ECC bits.
-- Previous mux on input to checkbit_handler logic.
-- Removed now (mux inserted after checkbit_handler logic before register stage)
--
-- axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else
-- rd_skid_buf_i;
-- Remove GEN_RDATA that was doing bit reversal.
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rdata_int <= (others => '0');
elsif (axi_rdata_en = '1') then
-- Track uncorrected data vector with AXI RDATA output pipeline
-- Mimic mux logic here (from previous post checkbit XOR logic register)
if (rddata_mux_sel = C_RDDATA_MUX_BRAM) then
axi_rdata_int (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1);
else
axi_rdata_int <= rd_skid_buf_i;
end if;
else
axi_rdata_int <= axi_rdata_int;
end if;
end if;
end process REG_RDATA;
-- When C_ECC = 1, correct any single bit errors on output read data.
-- Post register stage to improve timing on ECC logic data path.
-- Use registers in AXI Interconnect IP core.
-- Perform bit swapping on output of correct_one_bit
-- module (axi_rdata_int_corr signal).
-- AXI_RDATA (i) <= axi_rdata_int (i) when (Enable_ECC = '0')
-- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i);
-- Found in HW debug
-- axi_rdata_int is reversed to be returned on AXI bus.
-- AXI_RDATA (i) <= axi_rdata_int (C_AXI_DATA_WIDTH-1-i) when (Enable_ECC = '0')
-- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i);
-- Remove bit reversal on AXI_RDATA output.
AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC_CORR
--
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Generate statements to correct BRAM read data
-- dependent on ECC type.
------------------------------------------------------------------------
GEN_HAMMING_ECC_CORR: if C_ECC_TYPE = 0 generate
begin
------------------------------------------------------------------------
-- Generate: CHK_ECC_32
-- Purpose: Check ECC data unique for 32-bit BRAM.
------------------------------------------------------------------------
CHK_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
constant correct_data_table_32 : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
begin
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
syndrome_reg <= (others => '0');
syndrome_4_reg <= (others => '0');
syndrome_6_reg <= (others => '0');
-- Align register stage of syndrome with AXI read data pipeline
elsif (axi_rdata_en = '1') then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
else
syndrome_reg <= syndrome_reg;
syndrome_4_reg <= syndrome_4_reg;
syndrome_6_reg <= syndrome_6_reg;
end if;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on specific syndrome bits after pipeline stage before
-- correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
-----------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Correct output read data based on syndrome vector.
-- A single error can be corrected by decoding the
-- syndrome value.
-- Input signal is declared (N:0).
-- Output signal is (N:0).
-- In order to reuse correct_one_bit module,
-- the single data bit correction is done LSB to MSB
-- in generate statement loop.
-----------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_32 (i))
port map (
DIn => axi_rdata_int (31-i), -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal)
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (31-i)); -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal)
end generate GEN_CORR_32;
end generate CHK_ECC_32;
------------------------------------------------------------------------
-- Generate: CHK_ECC_64
-- Purpose: Check ECC data unique for 64-bit BRAM.
------------------------------------------------------------------------
CHK_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
constant correct_data_table_64 : correct_data_table_type := (
0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001",
4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001",
8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001",
12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001",
16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001",
20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001",
24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101",
28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101",
32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101",
36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101",
40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101",
44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101",
48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101",
52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101",
56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011",
60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011"
);
signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0'); -- Specific for 64-bit ECC
signal syndrome_7_a : std_logic;
signal syndrome_7_b : std_logic;
begin
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Align register stage of syndrome with AXI read data pipeline
if (axi_rdata_en = '1') then
syndrome_reg <= Syndrome;
syndrome_7_reg <= Syndrome_7;
else
syndrome_reg <= syndrome_reg;
syndrome_7_reg <= syndrome_7_reg;
end if;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits after pipeline stage
-- before correct_one_bit_64 module.
PARITY_CHK7_A: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_7_a ); -- [out std_logic]
PARITY_CHK7_B: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_7_b ); -- [out std_logic]
-- Do last XOR on Syndrome MSB after pipeline stage before correct_one_bit module
-- PASSES: syndrome_reg_i (7) <= syndrome_reg (7) xor syndrome_7_b_reg;
syndrome_reg_i (7) <= syndrome_7_a xor syndrome_7_b;
syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6);
---------------------------------------------------------------------------
-- Generate: GEN_CORR_64
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
-----------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_64
-- Description: Correct output read data based on syndrome vector.
-- A single error can be corrected by decoding the
-- syndrome value.
-----------------------------------------------------------------------
CORR_ONE_BIT_64: entity work.correct_one_bit_64
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_64 (i))
port map (
DIn => axi_rdata_int (i),
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (i));
end generate GEN_CORR_64;
end generate CHK_ECC_64;
end generate GEN_HAMMING_ECC_CORR;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC_CORR
--
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
-- Generate statements to correct BRAM read data
-- dependent on ECC type.
------------------------------------------------------------------------
GEN_HSIAO_ECC_CORR: if C_ECC_TYPE = 1 generate
type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
begin
-- Reconstruct H-matrix
H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
-- Based on syndrome value, determine bits to flip in BRAM read data.
GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
ecc_rddata_r <= axi_rdata_int;
axi_rdata_int_corr (C_AXI_DATA_WIDTH-1 downto 0) <= -- UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) xor
ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_HSIAO_ECC_CORR;
end generate GEN_RDATA_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_RID_SNG
-- Purpose: Generate RID output pipeline when the core is configured
-- in a single port mode.
---------------------------------------------------------------------------
GEN_RID_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
REG_RID_TEMP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp <= (others => '0');
elsif (bram_addr_ld_en = '1') then
axi_rid_temp <= AXI_ARID;
else
axi_rid_temp <= axi_rid_temp;
end if;
end if;
end process REG_RID_TEMP;
REG_RID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rid_int <= (others => '0');
elsif (bram_addr_ld_en = '1') then
axi_rid_int <= AXI_ARID;
elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then
axi_rid_int <= axi_rid_temp;
else
axi_rid_int <= axi_rid_int;
end if;
end if;
end process REG_RID;
-- Advance RID pipeline values
axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and
AXI_RREADY = '1' and
axi_b2b_brst = '1')
else '0';
end generate GEN_RID_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_RID
-- Purpose: Generate RID in dual port mode (with read address pipeline).
---------------------------------------------------------------------------
GEN_RID: if (C_SINGLE_PORT_BRAM = 0) generate
begin
---------------------------------------------------------------------------
-- RID Output Register
--
-- Output RID value either comes from pipelined value or directly wrapped
-- ARID value. Determined by address pipeline usage.
---------------------------------------------------------------------------
-- Create intermediate temporary RID output register
REG_RID_TEMP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp <= (others => '0');
-- When BRAM address counter gets loaded
-- Set output RID value based on address source
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '0') then
-- If BRAM address counter gets loaded directly from
-- AXI bus, then save ARID value for wrapping to RID
if (araddr_pipe_sel = '0') then
axi_rid_temp <= AXI_ARID;
else
-- Use pipelined AWID value
axi_rid_temp <= axi_arid_pipe;
end if;
-- Add condition to check for temp utilized (temp_full now = '0'), but a
-- pending RID is stored in temp2. Must advance the pipeline.
elsif ((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp <= axi_rid_temp2;
else
axi_rid_temp <= axi_rid_temp;
end if;
end if;
end process REG_RID_TEMP;
-- Create flag that indicates if axi_rid_temp is full
REG_RID_TEMP_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rid_temp_full = '1' and
(axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and
axi_rid_temp2_full = '0') then
axi_rid_temp_full <= '0';
elsif (bram_addr_ld_en = '1') or
((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp_full <= '1';
else
axi_rid_temp_full <= axi_rid_temp_full;
end if;
end if;
end process REG_RID_TEMP_FULL;
-- Create flag to detect falling edge of axi_rid_temp_full flag
REG_RID_TEMP_FULL_D1: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp_full_d1 <= '0';
else
axi_rid_temp_full_d1 <= axi_rid_temp_full;
end if;
end if;
end process REG_RID_TEMP_FULL_D1;
axi_rid_temp_full_fe <= '1' when (axi_rid_temp_full = '0' and
axi_rid_temp_full_d1 = '1') else '0';
---------------------------------------------------------------------------
-- Create intermediate temporary RID output register
REG_RID_TEMP2: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp2 <= (others => '0');
-- When BRAM address counter gets loaded
-- Set output RID value based on address source
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then
-- If BRAM address counter gets loaded directly from
-- AXI bus, then save ARID value for wrapping to RID
if (araddr_pipe_sel = '0') then
axi_rid_temp2 <= AXI_ARID;
else
-- Use pipelined AWID value
axi_rid_temp2 <= axi_arid_pipe;
end if;
else
axi_rid_temp2 <= axi_rid_temp2;
end if;
end if;
end process REG_RID_TEMP2;
-- Create flag that indicates if axi_rid_temp2 is full
REG_RID_TEMP2_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rid_temp2_full = '1' and (axi_rvalid_set = '1' or axi_b2b_rid_adv = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp2_full <= '0';
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then
axi_rid_temp2_full <= '1';
else
axi_rid_temp2_full <= axi_rid_temp2_full;
end if;
end if;
end process REG_RID_TEMP2_FULL;
---------------------------------------------------------------------------
-- Output RID register is enabeld when RVALID is asserted on the AXI bus
-- Clear RID when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
REG_RID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, can remove the signal, axi_rvalid_int from statement.
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rid_int <= (others => '0');
-- Add back to back case to advance RID
elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then
axi_rid_int <= axi_rid_temp;
else
axi_rid_int <= axi_rid_int;
end if;
end if;
end process REG_RID;
-- Advance RID pipeline values
axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and
AXI_RREADY = '1' and
axi_b2b_brst = '1')
else '0';
end generate GEN_RID;
---------------------------------------------------------------------------
-- Generate: GEN_RRESP
-- Purpose: Create register output unique when ECC is disabled.
-- Only possible output value = OKAY response.
---------------------------------------------------------------------------
GEN_RRESP: if C_ECC = 0 generate
begin
-----------------------------------------------------------------------
-- AXI_RRESP Output Register
--
-- Set when RVALID is asserted on AXI bus.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking
-- sequence and recognized by AXI requesting master.
-----------------------------------------------------------------------
REG_RRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted.
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rresp_int <= (others => '0');
elsif (axi_rvalid_set = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
axi_rresp_int <= RESP_OKAY;
else
axi_rresp_int <= axi_rresp_int;
end if;
end if;
end process REG_RRESP;
end generate GEN_RRESP;
---------------------------------------------------------------------------
-- Generate: GEN_RRESP_ECC
-- Purpose: Create register output unique when ECC is disabled.
-- Only possible output value = OKAY response.
---------------------------------------------------------------------------
GEN_RRESP_ECC: if C_ECC = 1 generate
begin
-----------------------------------------------------------------------
-- AXI_RRESP Output Register
--
-- Set when RVALID is asserted on AXI bus.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking
-- sequence and recognized by AXI requesting master.
-----------------------------------------------------------------------
REG_RRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted.
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rresp_int <= (others => '0');
elsif (axi_rvalid_set = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
-- For ECC implementation
-- Check that an uncorrectable error has not occured.
-- If so, then respond with RESP_SLVERR on AXI.
-- Ok to use combinatorial signal here. The Sl_UE_i
-- flag is generated based on the registered syndrome value.
-- if (Sl_UE_i = '1') then
-- axi_rresp_int <= RESP_SLVERR;
-- else
axi_rresp_int <= RESP_OKAY;
-- end if;
else
axi_rresp_int <= axi_rresp_int;
end if;
end if;
end process REG_RRESP;
end generate GEN_RRESP_ECC;
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Clear AXI_RVALID at the end of tranfer when able to clear
-- (axi_rlast_int = '1' and axi_rvalid_int = '1' and AXI_RREADY = '1' and
-- For improved code coverage, remove signal axi_rvalid_int.
(axi_rlast_int = '1' and AXI_RREADY = '1' and
-- Added axi_rvalid_clr_ok to check if during a back-to-back burst
-- and the back-to-back is elgible for streaming performance
axi_rvalid_clr_ok = '1') then
axi_rvalid_int <= '0';
elsif (axi_rvalid_set = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
-- Create flag that gets set when we load BRAM address early in a B2B scenario
-- This will prevent the RVALID from getting cleared at the end of the current burst
-- Otherwise, the RVALID gets cleared after RLAST/RREADY dual assertion
REG_RVALID_CLR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rvalid_clr_ok <= '0';
-- When the new address loaded into the BRAM counter is for a back-to-back operation
-- Do not clear the RVALID
elsif (rd_b2b_elgible = '1' and bram_addr_ld_en = '1') then
axi_rvalid_clr_ok <= '0';
-- Else when we start a new transaction (that is not back-to-back)
-- Then enable the RVALID to get cleared upon RLAST/RREADY
elsif (bram_addr_ld_en = '1') or
(axi_rvalid_clr_ok = '0' and
(disable_b2b_brst = '1' or disable_b2b_brst_cmb = '1') and
last_bram_addr = '1') or
-- Add check for current SM state
-- If LAST_ADDR state reached, no longer performing back-to-back
-- transfers and keeping data streaming on AXI bus.
(rd_data_sm_cs = LAST_ADDR) then
axi_rvalid_clr_ok <= '1';
else
axi_rvalid_clr_ok <= axi_rvalid_clr_ok;
end if;
end if;
end process REG_RVALID_CLR;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- To improve code coverage, remove
-- use of axi_rvalid_int (it will always be asserted with RLAST).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_rlast_set = '0') then
axi_rlast_int <= '0';
elsif (axi_rlast_set = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
---------------------------------------------------------------------------
-- Generate complete flag
do_cmplt_burst_cmb <= '1' when (last_bram_addr = '1' and
axi_rd_burst = '1' and
axi_rd_burst_two = '0') else '0';
-- Register complete flags
REG_CMPLT_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (do_cmplt_burst_clr = '1') then
do_cmplt_burst <= '0';
elsif (do_cmplt_burst_cmb = '1') then
do_cmplt_burst <= '1';
else
do_cmplt_burst <= do_cmplt_burst;
end if;
end if;
end process REG_CMPLT_BURST;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- RLAST State Machine
--
-- Description: SM to generate axi_rlast_set signal.
-- Created based on IR # 555346 to track when RLAST needs
-- to be asserted for back to back transfers
-- Uses the indication when last BRAM address is presented
-- and then counts the handshaking cycles on the AXI bus
-- (RVALID and RREADY both asserted).
-- Uses rd_adv_buf to perform this operation.
--
-- Output: Name Type
-- axi_rlast_set Not Registered
-- do_cmplt_burst_clr Not Registered
--
--
-- RLAST_SM_CMB_PROCESS: Combinational process to determine next state.
-- RLAST_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RLAST_SM_CMB_PROCESS: process (
do_cmplt_burst,
last_bram_addr,
rd_adv_buf,
act_rd_burst,
axi_rd_burst,
act_rd_burst_two,
axi_rd_burst_two,
axi_rlast_int,
rlast_sm_cs )
begin
-- assign default values for state machine outputs
rlast_sm_ns <= rlast_sm_cs;
axi_rlast_set <= '0';
do_cmplt_burst_clr <= '0';
case rlast_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- If last read address is presented to BRAM
if (last_bram_addr = '1') then
-- If the operation is a single read operation
if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then
-- Go to wait for last data beat
rlast_sm_ns <= W8_LAST_DATA;
-- Else the transaction is a burst
else
-- Throttle condition on 3rd to last data beat
if (rd_adv_buf = '0') then
-- If AXI read burst = 2 (only two data beats to capture)
if (axi_rd_burst_two = '1' or act_rd_burst_two = '1') then
rlast_sm_ns <= W8_THROTTLE_B2;
else
rlast_sm_ns <= W8_THROTTLE;
end if;
-- No throttle on 3rd to last data beat
else
-- Only back-to-back support when burst size is greater
-- than two data beats. We will never toggle on a burst > 2
-- when last_bram_addr is asserted (as this is no toggle
-- condition)
-- Go to wait for 2nd to last data beat
rlast_sm_ns <= W8_2ND_LAST_DATA;
do_cmplt_burst_clr <= '1';
end if;
end if;
end if;
------------------------- W8_THROTTLE State -----------------------
when W8_THROTTLE =>
if (rd_adv_buf = '1') then
-- Go to wait for 2nd to last data beat
rlast_sm_ns <= W8_2ND_LAST_DATA;
-- If do_cmplt_burst flag is set, then clear it
if (do_cmplt_burst = '1') then
do_cmplt_burst_clr <= '1';
end if;
end if;
---------------------- W8_2ND_LAST_DATA State ---------------------
when W8_2ND_LAST_DATA =>
if (rd_adv_buf = '1') then
-- Assert RLAST on AXI
axi_rlast_set <= '1';
rlast_sm_ns <= W8_LAST_DATA;
end if;
------------------------- W8_LAST_DATA State ----------------------
when W8_LAST_DATA =>
-- If pending single to complete, keep RLAST asserted
-- Added to only assert axi_rlast_set for a single clock cycle
-- when we enter this state and are here waiting for the
-- throttle on the AXI bus.
if (axi_rlast_int = '1') then
axi_rlast_set <= '0';
else
axi_rlast_set <= '1';
end if;
-- Wait for last data beat to transition back to IDLE
if (rd_adv_buf = '1') then
rlast_sm_ns <= IDLE;
end if;
-------------------------- W8_THROTTLE_B2 ------------------------
when W8_THROTTLE_B2 =>
-- Wait for last data beat to transition back to IDLE
-- and set RLAST
if (rd_adv_buf = '1') then
rlast_sm_ns <= IDLE;
axi_rlast_set <= '1';
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rlast_sm_ns <= IDLE;
--coverage on
end case;
end process RLAST_SM_CMB_PROCESS;
---------------------------------------------------------------------------
RLAST_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rlast_sm_cs <= IDLE;
else
rlast_sm_cs <= rlast_sm_ns;
end if;
end if;
end process RLAST_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal CE_Q : std_logic := '0';
signal Sl_CE_i : std_logic := '0';
signal bram_en_int_d1 : std_logic := '0';
signal bram_en_int_d2 : std_logic := '0';
begin
-- Generate signal to advance BRAM read address pipeline to
-- capture address for ECC error conditions (in lite_ecc_reg module).
-- BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or
-- ((bram_en_int or bram_en_int_reg) and not (axi_rd_burst) and not (axi_rd_burst_two));
BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or rd_adv_buf or
((bram_en_int or bram_en_int_d1 or bram_en_int_d2) and not (axi_rd_burst) and not (axi_rd_burst_two));
-- Enable 2nd & 3rd pipeline stage for BRAM address storage with single read transfers.
BRAM_EN_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
bram_en_int_d1 <= bram_en_int;
bram_en_int_d2 <= bram_en_int_d1;
end if;
end process BRAM_EN_REG;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
------------------------------------------------------------------------
-- Generate: GEN_ECC_32
-- Purpose: Check ECC data unique for 32-bit BRAM.
-- Add extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 32-bit BRAM data widths.
-- ECC bits are in upper order bits.
------------------------------------------------------------------------
GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
signal bram_din_a_rev : std_logic_vector(31 downto 0) := (others => '0'); -- Specific to BRAM data width
signal bram_din_ecc_a_rev : std_logic_vector(6 downto 0) := (others => '0'); -- Specific to BRAM data width
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
-- process (bram_din_a_i) begin
-- for k in 0 to 31 loop
-- bram_din_a_rev(k) <= bram_din_a_i(39-k);
-- end loop;
-- for k in 0 to 6 loop
-- bram_din_ecc_a_rev(0) <= bram_din_a_i(6-k);
-- end loop;
-- end process;
CHK_HANDLER_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- In 32-bit BRAM use case: DataIn (8:39)
-- CheckIn (1:7)
DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)]
--DataIn => bram_din_a_rev, -- [in std_logic_vector(0 to 31)]
--CheckIn => bram_din_ecc_a_rev, -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [out std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic.
end generate GEN_ECC_32;
------------------------------------------------------------------------
-- Generate: GEN_ECC_64
-- Purpose: Check ECC data unique for 64-bit BRAM.
-- No extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 64-bit BRAM data widths.
-- ECC bits are in upper order bits.
------------------------------------------------------------------------
GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_64
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_64: entity work.checkbit_handler_64
generic map (
C_ENCODE => false, -- [boolean]
C_REG => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
Clk => S_AXI_AClk, -- [in std_logic]
-- In 64-bit BRAM use case: DataIn (8:71)
-- CheckIn (0:7)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)]
CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 7)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)]
Syndrome_7 => Syndrome_7,
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_64 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic.
end generate GEN_ECC_64;
end generate GEN_HAMMING_ECC;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal syndrome_ns : std_logic_vector (ECC_WIDTH - 1 downto 0) := (others => '0');
begin
-- Generate ECC check bits and syndrome values based on
-- BRAM read data.
-- Generate appropriate single or double bit error flags.
-- Instantiate ecc_gen_hsiao module, generated from MIG
I_ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( -- bram_din_a_i (0 to CODE_WIDTH-1)
BRAM_RdData (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome.
-- Same as Hamming ECC code. Syndrome value is registered.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
end if;
end process REG_SYNDROME;
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not(REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
-- Capture correctable/uncorrectable error from BRAM read
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (Enable_ECC = '1') and
(axi_rvalid_int = '1' and AXI_RREADY = '1') then -- Capture error flags
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- The signal, axi_rdata_en loads the syndrome_reg.
-- Use the AXI RVALID/READY signals to capture state of UE and CE.
-- Since flag generation uses the registered syndrome value.
-- ECC register block gets registered UE or CE conditions to update
-- ECC registers/interrupt/flag outputs.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
-- CE_Failing_We <= Sl_CE_i and Enable_ECC and axi_rvalid_set;
CE_Failing_We <= CE_Q;
---------------------------------------------------------------------------
-- Generate BRAM read data vector assignment to always be from Port A
-- in a single port BRAM configuration.
-- Map BRAM_RdData (Port A) (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
--
-- Port A or Port B sourcing done at full_axi module level
---------------------------------------------------------------------------
-- Original design with mux (BRAM vs. Skid Buffer) on input side of checkbit_handler logic.
-- Move mux to enable on AXI RDATA register.
bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
-- Map data vector from BRAM to use in correct_one_bit module with
-- register syndrome (post AXI RDATA register).
UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_AXI_DATA_WIDTH-1);
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Drive default output signals when ECC is diabled.
---------------------------------------------------------------------------
GEN_NO_ECC: if C_ECC = 0 generate
begin
BRAM_Addr_En <= '0';
CE_Failing_We <= '0';
Sl_CE <= '0';
Sl_UE <= '0';
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
--
-- *** BRAM Interface Signals ***
--
---------------------------------------------------------------------------
BRAM_En <= bram_en_int;
---------------------------------------------------------------------------
-- BRAM Address Generate
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
--
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
--
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
---------------------------------------------------------------------------
end architecture implementation;
-------------------------------------------------------------------------------
-- wr_chnl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wr_chnl.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller write channel interfaces. Controls all
-- handshaking and data flow on the AXI write address (AW),
-- write data (W) and write response (B) channels.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/3/2011 v1.03a
-- ~~~~~~
-- Edits for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/10/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter.
-- ^^^^^^
-- JLJ 2/14/2011 v1.03a
-- ~~~~~~
-- Shift Hsiao ECC generate logic so not dependent on C_S_AXI_DATA_WIDTH.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update WE size based on 128-bit ECC configuration.
-- Update for usage of ecc_gen.vhd module directly from MIG.
-- Clean-up XST warnings.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Found issue with ECC decoding on read path. Remove MSB '0' usage
-- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Code clean-up.
-- Move all MIG functions to package body.
-- ^^^^^^
-- JLJ 2/28/2011 v1.03a
-- ~~~~~~
-- Fix mapping on BRAM_WE with bram_we_int for 128-bit w/ ECC.
-- ^^^^^^
-- JLJ 3/1/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- Fix double clock assertion of CE/UE error flags when asserted
-- during the RMW sequence.
-- ^^^^^^
-- JLJ 3/23/2011 v1.03a
-- ~~~~~~
-- Code clean-up.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Add code coverage on/off statements.
-- ^^^^^^
-- JLJ 4/8/2011 v1.03a
-- ~~~~~~
-- Modify back-to-back capability to remove combinatorial loop
-- on WREADY to AXI interface. Add internal constant, C_REG_WREADY.
-- Update axi_wready_int reset value (ensure it is '0').
--
-- Create new SM for C_REG_WREADY with dual port. Seperate assertion of BVALID
-- from WREADY. Create a FIFO to store AWID/BID values.
-- Use counter (with max of 8 ID values) to allow WREADY assertions
-- to be ahead of BVALID assertions.
-- Add sub module, SRL_FIFO.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Implement similar updates on WREADY for single port & ECC configurations.
-- Remove use of signal, axi_wready_sng with constant, C_REG_WREADY.
--
-- For single port operation with registered WREADY, provide BVALID counter
-- value to arbitration SM, add output signal, AW2Arb_BVALID_Cnt.
--
-- Create an additional SM for single port when C_REG_WREADY.
-- ^^^^^^
-- JLJ 4/14/2011 v1.03a
-- ~~~~~~
-- Remove attempt to create AXI write data pipeline full flag outside of SM
-- logic. Add corner case checks for BID FIFO/BVALID counter.
-- ^^^^^^
-- JLJ 4/15/2011 v1.03a
-- ~~~~~~
-- Clean up all code not related to C_REG_WREADY.
-- Goal to remove internal constant, C_REG_WREADY.
-- Work on size optimization. Implement signals to represent BVALID
-- counter values.
-- ^^^^^^
-- JLJ 4/20/2011 v1.03a
-- ~~~~~~
-- Code clean up. Remove unused signals.
-- Remove additional generate blocks with C_REG_WREADY.
-- ^^^^^^
-- JLJ 4/21/2011 v1.03a
-- ~~~~~~
-- Code clean up. Remove use of IF_IS_AXI4 constant.
-- Create new SM TYPE for each configuration.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Add check in data SM on back-to-back for BVALID counter max.
-- Clean up AXI_WREADY generate blocks.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 5/26/2011 v1.03a
-- ~~~~~~
-- Fix CR # 609695.
-- Modify usage of WLAST. Ensure that WLAST is qualified with
-- WVALID/WREADY assertions.
--
-- With CR # 609695, update else clause for narrow_burst_cnt_ld to
-- remove simulation warnings when axi_byte_div_curr_awsize = zero.
--
-- Catch code clean up with WLAST in data SM for axi_wr_burst_cmb
-- signal assertion.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.srl_fifo;
use work.wrap_brst;
use work.ua_narrow;
use work.checkbit_handler;
use work.checkbit_handler_64;
use work.correct_one_bit;
use work.correct_one_bit_64;
use work.ecc_gen;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wr_chnl is
generic (
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 2;
-- Adjust factor to BRAM address width based on data width (in bits)
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_SUPPORTS_NARROW : INTEGER := 1;
-- Support for narrow burst operations
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to "AXI4LITE" to optimize out burst transaction support
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0 -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
);
port (
-- AXI Global Signals
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
-- AXI Write Address Channel Signals (AW)
AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_AWADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWLEN : in std_logic_vector(7 downto 0);
-- Specifies the number of data transfers in the burst
-- "0000 0000" 1 data transfer
-- "0000 0001" 2 data transfers
-- ...
-- "1111 1111" 256 data transfers
AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- Specifies the max number of data bytes to transfer in each data beat
-- "000" 1 byte to transfer
-- "001" 2 bytes to transfer
-- "010" 3 bytes to transfer
-- ...
AXI_AWBURST : in std_logic_vector(1 downto 0);
-- Specifies burst type
-- "00" FIXED = Fixed burst address (handled as INCR)
-- "01" INCR = Increment burst address
-- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary
-- "11" Reserved (not checked)
AXI_AWLOCK : in std_logic; -- Currently unused
AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused
AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic;
-- AXI Write Data Channel Signals (W)
AXI_WDATA : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0);
AXI_WSTRB : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0);
AXI_WLAST : in std_logic;
AXI_WVALID : in std_logic;
AXI_WREADY : out std_logic;
-- AXI Write Data Response Channel Signals (B)
AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_BRESP : out std_logic_vector(1 downto 0);
AXI_BVALID : out std_logic;
AXI_BREADY : in std_logic;
-- ECC Register Interface Signals
Enable_ECC : in std_logic;
BRAM_Addr_En : out std_logic := '0';
FaultInjectClr : out std_logic := '0';
CE_Failing_We : out std_logic := '0';
Sl_CE : out std_logic := '0';
Sl_UE : out std_logic := '0';
Active_Wr : out std_logic := '0';
FaultInjectData : in std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0);
FaultInjectECC : in std_logic_vector (C_ECC_WIDTH-1 downto 0);
-- Single Port Arbitration Signals
Arb2AW_Active : in std_logic;
AW2Arb_Busy : out std_logic := '0';
AW2Arb_Active_Clr : out std_logic := '0';
AW2Arb_BVALID_Cnt : out std_logic_vector (2 downto 0) := (others => '0');
Sng_BRAM_Addr_Rst : out std_logic := '0';
Sng_BRAM_Addr_Ld_En : out std_logic := '0';
Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
Sng_BRAM_Addr_Inc : out std_logic := '0';
Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
-- BRAM Write Port Interface Signals
BRAM_En : out std_logic := '0';
BRAM_WE : out std_logic_vector (C_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
BRAM_WrData : out std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
);
end entity wr_chnl;
-------------------------------------------------------------------------------
architecture implementation of wr_chnl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Set constants for AWLEN equal to a count of one or two beats.
constant AXI_AWLEN_ONE : std_logic_vector (7 downto 0) := (others => '0');
constant AXI_AWLEN_TWO : std_logic_vector (7 downto 0) := "00000001";
constant AXI_AWSIZE_ONE : std_logic_vector (2 downto 0) := "001";
-- Determine maximum size for narrow burst length counter
-- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits
-- resulting in a count 3 downto 0 => so minimum counter width = 2 bits.
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits
-- resulting in a count 31 downto 0 => so minimum counter width = 5 bits.
constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8);
constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
-- Move to full_axi module
-- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8);
-- Not used
-- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
-- AXI Burst Types
-- AXI Spec 4.4
constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10";
constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01";
constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00";
-- Internal ECC data width size.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type WR_ADDR_SM_TYPE is ( IDLE,
LD_AWADDR
);
signal wr_addr_sm_cs, wr_addr_sm_ns : WR_ADDR_SM_TYPE;
signal aw_active_set : std_logic := '0';
signal aw_active_set_i : std_logic := '0';
signal aw_active_clr : std_logic := '0';
signal delay_aw_active_clr_cmb : std_logic := '0';
signal delay_aw_active_clr : std_logic := '0';
signal aw_active : std_logic := '0';
signal aw_active_d1 : std_logic := '0';
signal aw_active_re : std_logic := '0';
signal axi_awaddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal curr_awaddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
signal awaddr_pipe_ld : std_logic := '0';
signal awaddr_pipe_ld_i : std_logic := '0';
signal awaddr_pipe_sel : std_logic := '0';
-- '0' indicates mux select from AXI
-- '1' indicates mux select from AW Addr Register
signal axi_awaddr_full : std_logic := '0';
signal axi_awid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_awsize_pipe : std_logic_vector(2 downto 0) := (others => '0');
signal curr_awsize : std_logic_vector(2 downto 0) := (others => '0');
signal curr_awsize_reg : std_logic_vector (2 downto 0) := (others => '0');
-- Narrow Burst Signals
signal curr_narrow_burst_cmb : std_logic := '0';
signal curr_narrow_burst : std_logic := '0';
signal curr_narrow_burst_en : std_logic := '0';
signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_addr_rst : std_logic := '0';
signal narrow_addr_ld_en : std_logic := '0';
signal narrow_addr_dec : std_logic := '0';
signal axi_awlen_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal axi_awlen_pipe_1_or_2 : std_logic := '0';
signal curr_awlen : std_logic_vector(7 downto 0) := (others => '0');
signal curr_awlen_reg : std_logic_vector(7 downto 0) := (others => '0');
signal curr_awlen_reg_1_or_2 : std_logic := '0';
signal axi_awburst_pipe : std_logic_vector(1 downto 0) := (others => '0');
signal axi_awburst_pipe_fixed : std_logic := '0';
signal curr_awburst : std_logic_vector(1 downto 0) := (others => '0');
signal curr_wrap_burst : std_logic := '0';
signal curr_wrap_burst_reg : std_logic := '0';
signal curr_incr_burst : std_logic := '0';
signal curr_fixed_burst : std_logic := '0';
signal curr_fixed_burst_reg : std_logic := '0';
signal max_wrap_burst_mod : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_d2 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
signal axi_aresetn_re_reg : std_logic := '0';
-- BRAM Address Counter
signal bram_addr_ld_en : std_logic := '0';
signal bram_addr_ld_en_i : std_logic := '0';
signal bram_addr_ld_en_mod : std_logic := '0';
signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_inc : std_logic := '0';
signal bram_addr_inc_mod : std_logic := '0';
signal bram_addr_inc_wrap_mod : std_logic := '0';
signal bram_addr_rst : std_logic := '0';
signal bram_addr_rst_cmb : std_logic := '0';
signal narrow_bram_addr_inc : std_logic := '0';
signal narrow_bram_addr_inc_d1 : std_logic := '0';
signal narrow_bram_addr_inc_re : std_logic := '0';
signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal curr_ua_narrow_wrap : std_logic := '0';
signal curr_ua_narrow_incr : std_logic := '0';
signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Write Data Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type WR_DATA_SM_TYPE is ( IDLE,
W8_AWADDR,
-- W8_BREADY,
SNG_WR_DATA,
BRST_WR_DATA,
-- NEW_BRST_WR_DATA,
B2B_W8_WR_DATA --,
-- B2B_W8_BRESP,
-- W8_BRESP
);
signal wr_data_sm_cs, wr_data_sm_ns : WR_DATA_SM_TYPE;
type WR_DATA_SNG_SM_TYPE is ( IDLE,
SNG_WR_DATA,
BRST_WR_DATA );
signal wr_data_sng_sm_cs, wr_data_sng_sm_ns : WR_DATA_SNG_SM_TYPE;
type WR_DATA_ECC_SM_TYPE is ( IDLE,
RMW_RD_DATA,
RMW_CHK_DATA,
RMW_MOD_DATA,
RMW_WR_DATA );
signal wr_data_ecc_sm_cs, wr_data_ecc_sm_ns : WR_DATA_ECC_SM_TYPE;
-- Wr Data Buffer/Register
signal wrdata_reg_ld : std_logic := '0';
signal axi_wready_int : std_logic := '0';
signal axi_wready_int_mod : std_logic := '0';
signal axi_wdata_full_cmb : std_logic := '0';
signal axi_wdata_full : std_logic := '0';
signal axi_wdata_empty : std_logic := '0';
signal axi_wdata_full_reg : std_logic := '0';
-- WE Generator Signals
signal clr_bram_we_cmb : std_logic := '0';
signal clr_bram_we : std_logic := '0';
signal bram_we_ld : std_logic := '0';
signal axi_wr_burst_cmb : std_logic := '0';
signal axi_wr_burst : std_logic := '0';
signal wr_b2b_elgible : std_logic := '0';
-- CR # 609695 signal last_data_ack : std_logic := '0';
-- CR # 609695 signal last_data_ack_throttle : std_logic := '0';
signal last_data_ack_mod : std_logic := '0';
-- CR # 609695 signal w8_b2b_bresp : std_logic := '0';
signal axi_wlast_d1 : std_logic := '0';
signal axi_wlast_re : std_logic := '0';
-- Single Port Signals
-- Write busy flags only used in ECC configuration
-- when waiting for BVALID/BREADY handshake
signal wr_busy_cmb : std_logic := '0';
signal wr_busy_reg : std_logic := '0';
-- Only used by ECC register module.
signal active_wr_cmb : std_logic := '0';
signal active_wr_reg : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write Response Channel Signals
-------------------------------------------------------------------------------
signal axi_bid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_bid_temp_full : std_logic := '0';
signal axi_bid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_bvalid_int : std_logic := '0';
signal axi_bvalid_set_cmb : std_logic := '0';
-------------------------------------------------------------------------------
-- Internal BRAM Signals
-------------------------------------------------------------------------------
signal reset_bram_we : std_logic := '0';
signal set_bram_we_cmb : std_logic := '0';
signal set_bram_we : std_logic := '0';
signal bram_we_int : std_logic_vector (C_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal bram_en_cmb : std_logic := '0';
signal bram_en_int : std_logic := '0';
signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_wrdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- ECC Signals
-------------------------------------------------------------------------------
signal CorrectedRdData : std_logic_vector(0 to C_AXI_DATA_WIDTH-1);
signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence
signal WrData : std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal WrData_cmb : std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal UE_Q : std_logic := '0';
-------------------------------------------------------------------------------
-- BVALID Signals
-------------------------------------------------------------------------------
signal bvalid_cnt_inc : std_logic := '0';
signal bvalid_cnt_inc_d1 : std_logic := '0';
signal bvalid_cnt_dec : std_logic := '0';
signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0');
signal bvalid_cnt_amax : std_logic := '0';
signal bvalid_cnt_max : std_logic := '0';
signal bvalid_cnt_non_zero : std_logic := '0';
-------------------------------------------------------------------------------
-- BID FIFO Signals
-------------------------------------------------------------------------------
signal bid_fifo_rst : std_logic := '0';
signal bid_fifo_ld_en : std_logic := '0';
signal bid_fifo_ld : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal bid_fifo_rd_en : std_logic := '0';
signal bid_fifo_rd : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal bid_fifo_not_empty : std_logic := '0';
signal bid_gets_fifo_load : std_logic := '0';
signal bid_gets_fifo_load_d1 : std_logic := '0';
signal first_fifo_bid : std_logic := '0';
signal b2b_fifo_bid : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
---------------------------------------------------------------------------
AXI_AWREADY <= axi_awready_int;
---------------------------------------------------------------------------
-- AXI Write Data Channel Output Signals
---------------------------------------------------------------------------
-- WREADY same signal assertion regardless of ECC or single port configuration.
AXI_WREADY <= axi_wready_int_mod;
---------------------------------------------------------------------------
-- AXI Write Response Channel Output Signals
---------------------------------------------------------------------------
AXI_BRESP <= axi_bresp_int;
AXI_BVALID <= axi_bvalid_int;
AXI_BID <= axi_bid_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_AW_PIPE_SNG
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AW_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- Unused AW pipeline (set default values)
awaddr_pipe_ld <= '0';
axi_awaddr_pipe <= AXI_AWADDR;
axi_awid_pipe <= AXI_AWID;
axi_awsize_pipe <= AXI_AWSIZE;
axi_awlen_pipe <= AXI_AWLEN;
axi_awburst_pipe <= AXI_AWBURST;
axi_awlen_pipe_1_or_2 <= '0';
axi_awburst_pipe_fixed <= '0';
axi_awaddr_full <= '0';
end generate GEN_AW_PIPE_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_AW_PIPE_DUAL
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AW_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-----------------------------------------------------------------------
--
-- AXI Write Address Buffer/Register
-- (mimic behavior of address pipeline for AXI_AWID)
--
-----------------------------------------------------------------------
GEN_AWADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate
begin
REG_AWADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (awaddr_pipe_ld = '1') then
axi_awaddr_pipe (i) <= AXI_AWADDR (i);
else
axi_awaddr_pipe (i) <= axi_awaddr_pipe (i);
end if;
end if;
end process REG_AWADDR;
end generate GEN_AWADDR;
-----------------------------------------------------------------------
-- Register AWID
REG_AWID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (awaddr_pipe_ld = '1') then
axi_awid_pipe <= AXI_AWID;
else
axi_awid_pipe <= axi_awid_pipe;
end if;
end if;
end process REG_AWID;
---------------------------------------------------------------------------
-- In parallel to AWADDR pipeline and AWID
-- Use same control signals to capture AXI_AWSIZE, AXI_AWLEN & AXI_AWBURST.
-- Register AXI_AWSIZE, AXI_AWLEN & AXI_AWBURST
REG_AWCTRL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (awaddr_pipe_ld = '1') then
axi_awsize_pipe <= AXI_AWSIZE;
axi_awlen_pipe <= AXI_AWLEN;
axi_awburst_pipe <= AXI_AWBURST;
else
axi_awsize_pipe <= axi_awsize_pipe;
axi_awlen_pipe <= axi_awlen_pipe;
axi_awburst_pipe <= axi_awburst_pipe;
end if;
end if;
end process REG_AWCTRL;
---------------------------------------------------------------------------
-- Create signals that indicate value of AXI_AWLEN in pipeline stage
-- Used to decode length of burst when BRAM address can be loaded early
-- when pipeline is full.
--
-- Add early decode of AWBURST in pipeline.
REG_AWLEN_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (awaddr_pipe_ld = '1') then
-- Create merge to decode AWLEN of ONE or TWO
if (AXI_AWLEN = AXI_AWLEN_ONE) or (AXI_AWLEN = AXI_AWLEN_TWO) then
axi_awlen_pipe_1_or_2 <= '1';
else
axi_awlen_pipe_1_or_2 <= '0';
end if;
-- Early decode on value in pipeline of AWBURST
if (AXI_AWBURST = C_AXI_BURST_FIXED) then
axi_awburst_pipe_fixed <= '1';
else
axi_awburst_pipe_fixed <= '0';
end if;
else
axi_awlen_pipe_1_or_2 <= axi_awlen_pipe_1_or_2;
axi_awburst_pipe_fixed <= axi_awburst_pipe_fixed;
end if;
end if;
end process REG_AWLEN_PIPE;
---------------------------------------------------------------------------
-- Create full flag for AWADDR pipeline
-- Set when write address register is loaded.
-- Cleared when write address stored in register is loaded into BRAM
-- address counter.
REG_WRADDR_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(bram_addr_ld_en = '1' and awaddr_pipe_sel = '1') then
axi_awaddr_full <= '0';
elsif (awaddr_pipe_ld = '1') then
axi_awaddr_full <= '1';
else
axi_awaddr_full <= axi_awaddr_full;
end if;
end if;
end process REG_WRADDR_FULL;
---------------------------------------------------------------------------
end generate GEN_AW_PIPE_DUAL;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL_ADDR_CNT
-- Purpose: Instantiate BRAM address counter unique for wr_chnl logic
-- only when controller configured in dual port mode.
---------------------------------------------------------------------------
GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
----------------------------------------------------------------------------
-- Replace I_ADDR_CNT module usage of pf_counter in proc_common library.
-- Only need to use lower 12-bits of address due to max AXI burst size
-- Since AXI guarantees bursts do not cross 4KB boundary, the counting part
-- of I_ADDR_CNT can be reduced to max 4KB.
--
-- Counter size is adjusted based on data width of BRAM.
-- For example, 32-bit data width BRAM, BRAM_Addr (1:0)
-- are fixed at "00". So, counter increments from
-- (C_AXI_ADDR_WIDTH - 1 : C_BRAM_ADDR_ADJUST).
----------------------------------------------------------------------------
I_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Reset usage differs from RD CHNL
if (bram_addr_rst = '1') then
bram_addr_int <= (others => '0');
elsif (bram_addr_ld_en_mod = '1') then
bram_addr_int <= bram_addr_ld;
elsif (bram_addr_inc_mod = '1') then
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process I_ADDR_CNT;
-- Set defaults to shared address counter
-- Only used in single port configurations
Sng_BRAM_Addr_Rst <= '0';
Sng_BRAM_Addr_Ld_En <= '0';
Sng_BRAM_Addr_Ld <= (others => '0');
Sng_BRAM_Addr_Inc <= '0';
end generate GEN_DUAL_ADDR_CNT;
---------------------------------------------------------------------------
-- Generate: GEN_SNG_ADDR_CNT
-- Purpose: When configured in single port BRAM mode, address counter
-- is shared with rd_chnl module. Assign output signals here
-- to counter instantiation at full_axi module level.
---------------------------------------------------------------------------
GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
Sng_BRAM_Addr_Rst <= bram_addr_rst;
Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod;
Sng_BRAM_Addr_Ld <= bram_addr_ld;
Sng_BRAM_Addr_Inc <= bram_addr_inc_mod;
bram_addr_int <= Sng_BRAM_Addr;
end generate GEN_SNG_ADDR_CNT;
---------------------------------------------------------------------------
--
-- Add BRAM counter reset for @ end of transfer
--
-- Create a unique BRAM address reset signal
-- If the write transaction is throttling on the AXI bus, then
-- the BRAM EN may get negated during the write transfer
--
-- Use combinatorial output from SM, bram_addr_rst_cmb, but ensure the
-- BRAM address is not reset while loading a new address.
bram_addr_rst <= (not (S_AXI_AResetn)) or (bram_addr_rst_cmb and
not (bram_addr_ld_en_mod) and not (bram_addr_inc_mod));
---------------------------------------------------------------------------
-- BRAM address counter load mux
--
-- Either load BRAM counter directly from AXI bus or from stored registered value
--
-- Added bram_addr_ld_wrap for loading on wrap burst types
-- Use registered signal to indicate current operation is a WRAP burst
--
-- Do not load bram_addr_ld_wrap when bram_addr_ld_en signal is asserted at beginning of write burst
-- BRAM address counter load. Due to condition when max_wrap_burst_mod remains asserted, due to BRAM address
-- counter not incrementing (at the end of the previous write burst).
-- bram_addr_ld <= bram_addr_ld_wrap when
-- (max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_ld_en = '0') else
-- axi_awaddr_pipe (C_BRAM_ADDR_SIZE-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
-- when (awaddr_pipe_sel = '1') else
-- AXI_AWADDR (C_BRAM_ADDR_SIZE-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
-- Replace C_BRAM_ADDR_SIZE w/ C_AXI_ADDR_WIDTH parameter usage
bram_addr_ld <= bram_addr_ld_wrap when
(max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_ld_en = '0') else
axi_awaddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
when (awaddr_pipe_sel = '1') else
AXI_AWADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
---------------------------------------------------------------------------
-- On wrap burst max loads (simultaneous BRAM address increment is asserted).
-- Ensure that load has higher priority over increment.
-- Use registered signal to indicate current operation is a WRAP burst
-- bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or
-- (max_wrap_burst_mod = '1' and
-- curr_wrap_burst_reg = '1' and
-- bram_addr_inc_mod = '1'))
-- else '0';
-- Use duplicate version of bram_addr_ld_en in effort
-- to reduce fanout of signal routed to BRAM address counter
bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or
(max_wrap_burst_mod = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1'))
else '0';
-- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal
-- logic. No need for the check if the current operation is NOT a fixed AND a wrap
-- burst. The transfer will be one or the other.
-- Found issue when narrow FIXED length burst is incorrectly
-- incrementing BRAM address counter
bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0')
else narrow_bram_addr_inc_re;
----------------------------------------------------------------------------
-- Handling for WRAP burst types
--
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Boundary is reached based on ARSIZE and ARLEN.
--
-- Goal is to minimize muxing on initial load of counter value.
-- On WRAP burst types, detect when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value set to '0'.
----------------------------------------------------------------------------
-- Detect valid WRAP burst types
curr_wrap_burst <= '1' when (curr_awburst = C_AXI_BURST_WRAP) else '0';
-- Detect INCR & FIXED burst type operations
curr_incr_burst <= '1' when (curr_awburst = C_AXI_BURST_INCR) else '0';
curr_fixed_burst <= '1' when (curr_awburst = C_AXI_BURST_FIXED) else '0';
----------------------------------------------------------------------------
-- Register curr_wrap_burst signal when BRAM address counter is initially
-- loaded
REG_CURR_WRAP_BRST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Add reset same as BRAM address counter
if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_rst = '1' and bram_addr_ld_en = '0') then
curr_wrap_burst_reg <= '0';
elsif (bram_addr_ld_en = '1') then
curr_wrap_burst_reg <= curr_wrap_burst;
else
curr_wrap_burst_reg <= curr_wrap_burst_reg;
end if;
end if;
end process REG_CURR_WRAP_BRST;
----------------------------------------------------------------------------
-- Register curr_fixed_burst signal when BRAM address counter is initially
-- loaded
REG_CURR_FIXED_BRST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Add reset same as BRAM address counter
if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_rst = '1' and bram_addr_ld_en = '0') then
curr_fixed_burst_reg <= '0';
elsif (bram_addr_ld_en = '1') then
curr_fixed_burst_reg <= curr_fixed_burst;
else
curr_fixed_burst_reg <= curr_fixed_burst_reg;
end if;
end if;
end process REG_CURR_FIXED_BRST;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Instance: I_WRAP_BRST
--
-- Description:
--
-- Instantiate WRAP_BRST module
-- Logic to generate the wrap around value to load into the BRAM address
-- counter on WRAP burst transactions.
-- WRAP value is based on current AWLEN, AWSIZE (for narrows) and
-- data width of BRAM module.
--
---------------------------------------------------------------------------
I_WRAP_BRST : entity work.wrap_brst
generic map (
C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk ,
S_AXI_AResetn => S_AXI_AResetn ,
curr_axlen => curr_awlen ,
curr_axsize => curr_awsize ,
curr_narrow_burst => curr_narrow_burst ,
narrow_bram_addr_inc_re => narrow_bram_addr_inc_re ,
bram_addr_ld_en => bram_addr_ld_en ,
bram_addr_ld => bram_addr_ld ,
bram_addr_int => bram_addr_int ,
bram_addr_ld_wrap => bram_addr_ld_wrap ,
max_wrap_burst_mod => max_wrap_burst_mod
);
---------------------------------------------------------------------------
-- Generate: GEN_WO_NARROW
-- Purpose: Create BRAM address increment signal when narrow bursts
-- are disabled.
---------------------------------------------------------------------------
GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
-- For non narrow burst operations, use bram_addr_inc from data SM.
-- Add in check that burst type is not FIXED, curr_fixed_burst_reg
bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg);
-- The signal, curr_narrow_burst should always be set to '0' when narrow bursts
-- are disabled.
curr_narrow_burst <= '0';
narrow_bram_addr_inc_re <= '0';
end generate GEN_WO_NARROW;
---------------------------------------------------------------------------
-- Only instantiate NARROW_CNT and supporting logic when narrow transfers
-- are supported and utilized by masters in the AXI system.
-- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this.
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT
-- Purpose: Instantiate narrow counter and logic when narrow
-- operation support is enabled.
-- And, only instantiate logic for narrow operations when
-- AXI bus protocol is not set for AXI-LITE.
---------------------------------------------------------------------------
GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-- Based on current operation being a narrow burst, hold off BRAM
-- address increment until narrow burst fits BRAM data width.
-- For non narrow burst operations, use bram_addr_inc from data SM.
-- Add in check that burst type is not FIXED, curr_fixed_burst_reg
bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0')
-- else narrow_bram_addr_inc_re;
-- Seeing incorrect BRAM address increment on narrow
-- fixed length burst operations.
-- Add this check for curr_fixed_burst_reg
else (narrow_bram_addr_inc_re and not (curr_fixed_burst_reg));
---------------------------------------------------------------------------
--
-- Generate seperate smaller counter for narrow burst operations
-- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library.
--
-- Counter size is adjusted based on size of data burst.
--
-- For example, 32-bit data width BRAM, minimum narrow width
-- burst is 8 bits resulting in a count 3 downto 0. So the
-- minimum counter width = 2 bits.
--
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst
-- is 8 bits resulting in a count 31 downto 0. So the
-- minimum counter width = 5 bits.
--
-- Size of counter = C_NARROW_BURST_CNT_LEN
--
---------------------------------------------------------------------------
I_NARROW_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (narrow_addr_rst = '1') then
narrow_addr_int <= (others => '0');
-- Load narrow address counter
elsif (narrow_addr_ld_en = '1') then
narrow_addr_int <= narrow_burst_cnt_ld_mod;
-- Decrement ONLY (no increment functionality)
elsif (narrow_addr_dec = '1') then
narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <=
std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1);
end if;
end if;
end process I_NARROW_CNT;
---------------------------------------------------------------------------
narrow_addr_rst <= not (S_AXI_AResetn);
-- Narrow burst counter load mux
-- Modify narrow burst count load value based on
-- unalignment of AXI address value
-- Account for INCR burst types at unaligned addresses
narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else
narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else
narrow_burst_cnt_ld_reg;
narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0';
narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re;
narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and (curr_narrow_burst = '1')
-- Ensure that narrow address counter doesn't
-- flag max or get loaded to
-- reset narrow counter until AXI read data
-- bus has acknowledged current
-- data on the AXI bus. Use rd_adv_buf signal
-- to indicate the non throttle
-- condition on the AXI bus.
and (bram_addr_inc = '1')
else '0';
-- Detect rising edge of narrow_bram_addr_inc
REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_bram_addr_inc_d1 <= '0';
else
narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc;
end if;
end if;
end process REG_NARROW_BRAM_ADDR_INC;
narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and
(narrow_bram_addr_inc_d1 = '0')
else '0';
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT;
---------------------------------------------------------------------------
-- Generate: GEN_AWREADY
-- Purpose: AWREADY is only created here when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AWREADY: if (C_SINGLE_PORT_BRAM = 0) generate
begin
-- v1.03a
----------------------------------------------------------------------------
-- AXI_AWREADY Output Register
-- Description: Keep AXI_AWREADY output asserted until AWADDR pipeline
-- is full. When a full condition is reached, negate
-- AWREADY as another AW address can not be accepted.
-- Add condition to keep AWReady asserted if loading current
--- AWADDR pipeline value into the BRAM address counter.
-- Indicated by assertion of bram_addr_ld_en & awaddr_pipe_sel.
--
----------------------------------------------------------------------------
REG_AWREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_awready_int <= '0';
-- Detect end of S_AXI_AResetn to assert AWREADY and accept
-- new AWADDR values
elsif (axi_aresetn_re_reg = '1') or (bram_addr_ld_en = '1' and awaddr_pipe_sel = '1') then
axi_awready_int <= '1';
elsif (awaddr_pipe_ld = '1') then
axi_awready_int <= '0';
else
axi_awready_int <= axi_awready_int;
end if;
end if;
end process REG_AWREADY;
----------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert AWREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
axi_aresetn_d2 <= axi_aresetn_d1;
axi_aresetn_re_reg <= axi_aresetn_re;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
end generate GEN_AWREADY;
----------------------------------------------------------------------------
-- Specify current AWSIZE signal
-- Address pipeline MUX
curr_awsize <= axi_awsize_pipe when (awaddr_pipe_sel = '1') else AXI_AWSIZE;
-- Register curr_awsize when bram_addr_ld_en = '1'
REG_AWSIZE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_awsize_reg <= (others => '0');
elsif (bram_addr_ld_en = '1') then
curr_awsize_reg <= curr_awsize;
else
curr_awsize_reg <= curr_awsize_reg;
end if;
end if;
end process REG_AWSIZE;
---------------------------------------------------------------------------
--
-- Generate: GEN_NARROW_EN
-- Purpose: Only instantiate logic to determine if current burst
-- is a narrow burst when narrow bursting logic is supported.
--
---------------------------------------------------------------------------
GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-----------------------------------------------------------------------
-- Determine "narrow" burst transfers
-- Compare the AWSIZE to the BRAM data width
-----------------------------------------------------------------------
-- v1.03a
-- Detect if current burst operation is of size /= to the full
-- AXI data bus width. If not, then the current operation is a
-- "narrow" burst.
curr_narrow_burst_cmb <= '1' when (curr_awsize /= C_AXI_SIZE_MAX) else '0';
---------------------------------------------------------------------------
curr_narrow_burst_en <= '1' when (bram_addr_ld_en = '1') and
(curr_awlen /= AXI_AWLEN_ONE) and
(curr_fixed_burst = '0')
else '0';
-- Register flag indicating the current operation
-- is a narrow write burst
NARROW_BURST_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Need to reset this flag at end of narrow burst operation
-- Use handshaking signals on AXI
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Check for back to back narrow burst. If that is the case, then
-- do not clear curr_narrow_burst flag.
(axi_wlast_re = '1' and
curr_narrow_burst_en = '0'
-- If ECC is enabled, no clear to curr_narrow_burst when WLAST is asserted
-- this causes the BRAM address to incorrectly get asserted on the last
-- beat in the burst (due to delay in RMW logic)
and C_ECC = 0) then
curr_narrow_burst <= '0';
elsif (curr_narrow_burst_en = '1') then
curr_narrow_burst <= curr_narrow_burst_cmb;
end if;
end if;
end process NARROW_BURST_REG;
---------------------------------------------------------------------------
-- Detect RE of AXI_WLAST
-- Only used when narrow bursts are enabled.
WLAST_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_wlast_d1 <= '0';
else
-- axi_wlast_d1 <= AXI_WLAST and axi_wready_int_mod;
-- CR # 609695
axi_wlast_d1 <= AXI_WLAST and axi_wready_int_mod and AXI_WVALID;
end if;
end if;
end process WLAST_REG;
-- axi_wlast_re <= (AXI_WLAST and axi_wready_int_mod) and not (axi_wlast_d1);
-- CR # 609695
axi_wlast_re <= (AXI_WLAST and axi_wready_int_mod and AXI_WVALID) and not (axi_wlast_d1);
end generate GEN_NARROW_EN;
---------------------------------------------------------------------------
-- Generate registered flag that active burst is a "narrow" burst
-- and load narrow burst counter
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_NARROW_CNT_LD
-- Purpose: Only instantiate logic to determine narrow burst counter
-- load value when narrow bursts are enabled.
--
---------------------------------------------------------------------------
GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
signal curr_awsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal axi_byte_div_curr_awsize : integer := 1;
begin
-- v1.03a
-- Create narrow burst counter load value based on current operation
-- "narrow" data width (indicated by value of AWSIZE).
curr_awsize_unsigned <= unsigned (curr_awsize);
-- XST does not support divisors that are not constants and powers of 2.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- narrow_burst_cnt_ld <= std_logic_vector (
-- to_unsigned (
-- (C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_awsize_unsigned))) ) - 1,
-- C_NARROW_BURST_CNT_LEN));
-- -- With this new process and subsequent signal assignment:
-- DIV_AWSIZE: process (curr_awsize_unsigned)
-- begin
--
-- case (to_integer (curr_awsize_unsigned)) is
-- when 0 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 1;
-- when 1 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 2;
-- when 2 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 4;
-- when 3 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 8;
-- when 4 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 16;
-- when 5 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 32;
-- when 6 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 64;
-- when 7 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 128;
-- --coverage off
-- when others => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES;
-- --coverage on
-- end case;
--
-- end process DIV_AWSIZE;
-- w/ CR # 609695
-- With this new process and subsequent signal assignment:
DIV_AWSIZE: process (curr_awsize_unsigned)
begin
case (curr_awsize_unsigned) is
when "000" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 128;
--coverage off
when others => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES;
--coverage on
end case;
end process DIV_AWSIZE;
---------------------------------------------------------------------------
-- Create narrow burst count load value.
--
-- Size is based on [C_NARROW_BURST_CNT_LEN-1 : 0]
-- For 32-bit BRAM, C_NARROW_BURST_CNT_LEN = 2.
-- For 64-bit BRAM, C_NARROW_BURST_CNT_LEN = 3.
-- For 128-bit BRAM, C_NARROW_BURST_CNT_LEN = 4. (etc.)
--
-- Signal, narrow_burst_cnt_ld signal is sized according to C_AXI_DATA_WIDTH.
-- Updated else clause for simulation warnings w/ CR # 609695
narrow_burst_cnt_ld <= std_logic_vector (
to_unsigned (
(axi_byte_div_curr_awsize) - 1,
C_NARROW_BURST_CNT_LEN))
when (axi_byte_div_curr_awsize > 0)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
-- Register narrow_burst_cnt_ld
REG_NAR_BRST_CNT_LD: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_burst_cnt_ld_reg <= (others => '0');
elsif (bram_addr_ld_en = '1') then
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld;
else
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg;
end if;
end if;
end process REG_NAR_BRST_CNT_LD;
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT_LD;
----------------------------------------------------------------------------
-- Specify current AWBURST signal
-- Input address pipeline MUX
curr_awburst <= axi_awburst_pipe when (awaddr_pipe_sel = '1') else AXI_AWBURST;
----------------------------------------------------------------------------
-- Specify current AWBURST signal
-- Input address pipeline MUX
curr_awlen <= axi_awlen_pipe when (awaddr_pipe_sel = '1') else AXI_AWLEN;
-- Duplicate early decode of AWLEN value to use in wr_b2b_elgible logic
REG_CURR_AWLEN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_awlen_reg_1_or_2 <= '0';
elsif (bram_addr_ld_en = '1') then
-- Create merge to decode AWLEN of ONE or TWO
if (curr_awlen = AXI_AWLEN_ONE) or (curr_awlen = AXI_AWLEN_TWO) then
curr_awlen_reg_1_or_2 <= '1';
else
curr_awlen_reg_1_or_2 <= '0';
end if;
else
curr_awlen_reg_1_or_2 <= curr_awlen_reg_1_or_2;
end if;
end if;
end process REG_CURR_AWLEN;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_UA_NARROW
-- Purpose: Only instantiate logic for burst narrow WRAP operations when
-- AXI bus protocol is not set for AXI-LITE and narrow
-- burst operations are supported.
--
---------------------------------------------------------------------------
GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
-- New logic to detect unaligned address on a narrow WRAP burst transaction.
-- If this condition is met, then the narrow burst counter will be
-- initially loaded with an offset value corresponding to the unalignment
-- in the ARADDR value.
-- Create a sub module for all logic to determine the narrow burst counter
-- offset value on unaligned WRAP burst operations.
-- Module generates the following signals:
--
-- => curr_ua_narrow_wrap, to indicate the current
-- operation is an unaligned narrow WRAP burst.
--
-- => curr_ua_narrow_incr, to load narrow burst counter
-- for unaligned INCR burst operations.
--
-- => ua_narrow_load, narrow counter load value.
-- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0)
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Instance: I_UA_NARROW
--
-- Description:
--
-- Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- Logic is customized for each C_AXI_DATA_WIDTH.
---------------------------------------------------------------------------
I_UA_NARROW : entity work.ua_narrow
generic map (
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN
)
port map (
curr_wrap_burst => curr_wrap_burst , -- in
curr_incr_burst => curr_incr_burst , -- in
bram_addr_ld_en => bram_addr_ld_en , -- in
curr_axlen => curr_awlen , -- in
curr_axsize => curr_awsize , -- in
curr_axaddr_lsb => curr_awaddr_lsb , -- in
curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out
curr_ua_narrow_incr => curr_ua_narrow_incr , -- out
ua_narrow_load => ua_narrow_load -- out
);
-- Use in all C_AXI_DATA_WIDTH generate statements
-- Only probe least significant BRAM address bits
-- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0.
curr_awaddr_lsb <= axi_awaddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0)
when (awaddr_pipe_sel = '1') else
AXI_AWADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0);
end generate GEN_UA_NARROW;
---------------------------------------------------------------------------
--
-- Generate: GEN_AW_SNG
-- Purpose: If single port BRAM configuration, set all AW flags from
-- logic generated in sng_port_arb module.
--
---------------------------------------------------------------------------
GEN_AW_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
aw_active <= Arb2AW_Active;
bram_addr_ld_en <= aw_active_re;
AW2Arb_Active_Clr <= aw_active_clr;
AW2Arb_Busy <= wr_busy_reg;
AW2Arb_BVALID_Cnt <= bvalid_cnt;
end generate GEN_AW_SNG;
-- Rising edge detect of aw_active
-- For single port configurations, aw_active = Arb2AW_Active.
-- For dual port configurations, aw_active generated in ADDR SM.
RE_AW_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
aw_active_d1 <= '0';
else
aw_active_d1 <= aw_active;
end if;
end if;
end process RE_AW_ACT;
aw_active_re <= '1' when (aw_active = '1' and aw_active_d1 = '0') else '0';
---------------------------------------------------------------------------
--
-- Generate: GEN_AW_DUAL
-- Purpose: Generate AW control state machine logic only when AXI4
-- controller is configured for dual port mode. In dual port
-- mode, wr_chnl has full access over AW & port A of BRAM.
--
---------------------------------------------------------------------------
GEN_AW_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
AW2Arb_Active_Clr <= '0'; -- Only used in single port case
AW2Arb_Busy <= '0'; -- Only used in single port case
AW2Arb_BVALID_Cnt <= (others => '0');
----------------------------------------------------------------------------
REG_LAST_DATA_ACK: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
last_data_ack_mod <= '0';
else
-- last_data_ack_mod <= AXI_WLAST;
-- CR # 609695
last_data_ack_mod <= AXI_WLAST and AXI_WVALID and axi_wready_int_mod;
end if;
end if;
end process REG_LAST_DATA_ACK;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
-- WR ADDR State Machine
--
-- Description: Central processing unit for AXI write address
-- channel interface handling and handshaking.
--
-- Outputs: awaddr_pipe_ld Combinatorial
-- awaddr_pipe_sel
-- bram_addr_ld_en
--
--
--
-- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine.
---------------------------------------------------------------------------
WR_ADDR_SM_CMB_PROCESS: process ( AXI_AWVALID,
bvalid_cnt_max,
axi_awaddr_full,
aw_active,
wr_b2b_elgible,
last_data_ack_mod,
wr_addr_sm_cs )
begin
-- assign default values for state machine outputs
wr_addr_sm_ns <= wr_addr_sm_cs;
awaddr_pipe_ld_i <= '0';
bram_addr_ld_en_i <= '0';
aw_active_set_i <= '0';
case wr_addr_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for pending operation in address pipeline that may
-- be elgible for back-to-back performance to BRAM.
-- Prevent loading BRAM address counter if BID FIFO can not
-- store the AWID value. Check the BVALID counter.
if (wr_b2b_elgible = '1') and (last_data_ack_mod = '1') and
-- Ensure the BVALID counter does not roll over (max = 8 ID values)
(bvalid_cnt_max = '0') then
wr_addr_sm_ns <= IDLE;
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
aw_active_set_i <= '1';
-- Ensure AWVALID is recognized.
-- Address pipeline may be loaded, but BRAM counter
-- can not be loaded if at max of BID FIFO.
elsif (AXI_AWVALID = '1') then
-- If address pipeline is full
-- AWReady output is negated
-- If write address logic is ready for new operation
-- Load BRAM address counter and set aw_active = '1'
-- If address pipeline is already full to start next operation
-- load address counter from pipeline.
-- Prevent loading BRAM address counter if BID FIFO can not
-- store the AWID value. Check the BVALID counter.
-- Remain in this state
if (aw_active = '0') and
-- Ensure the BVALID counter does not roll over (max = 8 ID values)
(bvalid_cnt_max = '0') then
wr_addr_sm_ns <= IDLE;
-- Stay in this state to capture AWVALID if asserted
-- in next clock cycle.
bram_addr_ld_en_i <= '1';
aw_active_set_i <= '1';
-- Address counter is currently busy.
-- No check on BVALID counter for address pipeline load.
-- Only the BRAM address counter is checked for BID FIFO capacity.
else
-- Check if AWADDR pipeline is not full and can be loaded
if (axi_awaddr_full = '0') then
wr_addr_sm_ns <= LD_AWADDR;
awaddr_pipe_ld_i <= '1';
end if;
end if; -- aw_active
-- Pending operation in pipeline that is waiting
-- until current operation is complete (aw_active = '0')
elsif (axi_awaddr_full = '1') and (aw_active = '0') and
-- Ensure the BVALID counter does not roll over (max = 8 ID values)
(bvalid_cnt_max = '0') then
wr_addr_sm_ns <= IDLE;
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
aw_active_set_i <= '1';
end if; -- AWVALID
---------------------------- LD_AWADDR State ---------------------------
when LD_AWADDR =>
wr_addr_sm_ns <= IDLE;
if (wr_b2b_elgible = '1') and (last_data_ack_mod = '1') and
-- Ensure the BVALID counter does not roll over (max = 8 ID values)
(bvalid_cnt_max = '0') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
aw_active_set_i <= '1';
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
wr_addr_sm_ns <= IDLE;
--coverage on
end case;
end process WR_ADDR_SM_CMB_PROCESS;
---------------------------------------------------------------------------
-- CR # 582705
-- Ensure combinatorial SM output signals do not get set before
-- the end of the reset (and ARREAADY can be set).
bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d2;
aw_active_set <= aw_active_set_i and axi_aresetn_d2;
awaddr_pipe_ld <= awaddr_pipe_ld_i and axi_aresetn_d2;
WR_ADDR_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
-- Ensure that ar_active does not get asserted (from SM) before
-- the end of reset and the ARREADY flag is set.
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
wr_addr_sm_cs <= IDLE;
else
wr_addr_sm_cs <= wr_addr_sm_ns;
end if;
end if;
end process WR_ADDR_SM_REG_PROCESS;
---------------------------------------------------------------------------
-- Asserting awaddr_pipe_sel outside of SM logic
-- The BRAM address counter will get loaded with value in AWADDR pipeline
-- when data is stored in the AWADDR pipeline.
awaddr_pipe_sel <= '1' when (axi_awaddr_full = '1') else '0';
---------------------------------------------------------------------------
-- Register for aw_active
REG_AW_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- CR # 582705
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
aw_active <= '0';
elsif (aw_active_set = '1') then
aw_active <= '1';
elsif (aw_active_clr = '1') then
aw_active <= '0';
else
aw_active <= aw_active;
end if;
end if;
end process REG_AW_ACT;
---------------------------------------------------------------------------
end generate GEN_AW_DUAL;
---------------------------------------------------------------------------
-- *** AXI Write Data Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- AXI WrData Buffer/Register
---------------------------------------------------------------------------
GEN_WRDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate
begin
REG_WRDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (wrdata_reg_ld = '1') then
bram_wrdata_int (i) <= AXI_WDATA (i);
else
bram_wrdata_int (i) <= bram_wrdata_int (i);
end if;
end if;
end process REG_WRDATA;
end generate GEN_WRDATA;
---------------------------------------------------------------------------
-- Generate: GEN_WR_NO_ECC
-- Purpose: Generate BRAM WrData and WE signals based on AXI_WRDATA
-- and AXI_WSTRBs when C_ECC is disabled.
---------------------------------------------------------------------------
GEN_WR_NO_ECC: if C_ECC = 0 generate
begin
---------------------------------------------------------------------------
-- AXI WSTRB Buffer/Register
-- Use AXI write data channel data strobe signals to generate BRAM WE.
---------------------------------------------------------------------------
REG_BRAM_WE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Ensure we don't clear WE when loading subsequent WSTRB value
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(clr_bram_we = '1' and bram_we_ld = '0') then
bram_we_int <= (others => '0');
elsif (bram_we_ld = '1') then
bram_we_int <= AXI_WSTRB;
else
bram_we_int <= bram_we_int;
end if;
end if;
end process REG_BRAM_WE;
----------------------------------------------------------------------------
-- New logic to detect if pending operation in AWADDR pipeline is
-- elgible for back-to-back no "bubble" performance. And BRAM address
-- counter can be loaded upon last BRAM address presented for the current
-- operation.
-- This condition exists when the AWADDR pipeline is full and the pending
-- operation is a burst >= length of two data beats.
-- And not a FIXED burst type (must be INCR or WRAP type).
--
-- Narrow bursts are be neglible
--
-- Add check to complete current single and burst of two data bursts
-- prior to loading BRAM counter
wr_b2b_elgible <= '1' when (axi_awaddr_full = '1') and
-- Replace comparator logic here with register signal (pre pipeline stage
-- on axi_awlen_pipe value
-- Use merge in decode of ONE or TWO
(axi_awlen_pipe_1_or_2 /= '1') and
(axi_awburst_pipe_fixed /= '1') and
-- Use merge in decode of ONE or TWO
(curr_awlen_reg_1_or_2 /= '1')
else '0';
----------------------------------------------------------------------------
end generate GEN_WR_NO_ECC;
---------------------------------------------------------------------------
-- Generate: GEN_WR_ECC
-- Purpose: Generate BRAM WrData and WE signals based on AXI_WRDATA
-- and AXI_WSTRBs when C_ECC is enabled.
---------------------------------------------------------------------------
GEN_WR_ECC: if C_ECC = 1 generate
begin
wr_b2b_elgible <= '0';
---------------------------------------------------------------------------
-- AXI WSTRB Buffer/Register
-- Use AXI write data channel data strobe signals to generate BRAM WE.
---------------------------------------------------------------------------
REG_BRAM_WE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Ensure we don't clear WE when loading subsequent WSTRB value
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(reset_bram_we = '1') then
bram_we_int <= (others => '0');
elsif (set_bram_we = '1') then
bram_we_int <= (others => '1');
else
bram_we_int <= bram_we_int;
end if;
end if;
end process REG_BRAM_WE;
end generate GEN_WR_ECC;
-----------------------------------------------------------------------
-- v1.03a
-----------------------------------------------------------------------
--
-- Implement WREADY to be a registered output. Used by all configurations.
-- This will disable the back-to-back streamlined WDATA
-- for write operations to BRAM.
--
-----------------------------------------------------------------------
REG_WREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_wready_int_mod <= '0';
-- Keep AXI WREADY asserted unless write data register is full
-- Use combinatorial signal from SM.
elsif (axi_wdata_full_cmb = '1') then
axi_wready_int_mod <= '0';
else
axi_wready_int_mod <= '1';
end if;
end if;
end process REG_WREADY;
---------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Generate: GEN_WDATA_SM_ECC
-- Purpose: Create seperate SM for ECC read-modify-write logic.
-- Only used in single port BRAM mode. So, no address
-- pipelining. Must use aw_active from arbitration logic
-- to determine start of write to BRAM.
--
----------------------------------------------------------------------------
-- Test using same write data SM for single or dual port configuration.
-- The difference is the source of aw_active. In a single port configuration,
-- the aw_active is coming from the arbiter SM. In a dual port configuration,
-- the aw_active is coming from the write address SM in this module.
GEN_WDATA_SM_ECC: if C_ECC = 1 generate
begin
-- Unused in this SM configuration
bram_we_ld <= '0';
bram_addr_rst_cmb <= '0';
-- Output only used by ECC register module.
Active_Wr <= active_wr_reg;
---------------------------------------------------------------------------
--
-- WR DATA State Machine
--
-- Description: Central processing unit for AXI write data
-- channel interface handling and AXI write data response
-- handshaking when ECC is enabled. SM will handle
-- each transaction as a read-modify-write to ensure
-- the correct ECC bits are stored in BRAM.
--
-- Dedicated to single port BRAM interface. Transaction
-- is not initiated until valid AWADDR is arbitration,
-- ie. aw_active will be asserted. SM can do early reads
-- while waiting for WVALID to be asserted.
--
-- Valid AWADDR recieve indicator comes from arbitration
-- logic (aw_active will be asserted).
--
-- Outputs: Name Type
--
-- aw_active_clr Not Registered
-- axi_wdata_full_reg Registered
-- wrdata_reg_ld Not Registered
-- bvalid_cnt_inc Not Registered
-- bram_addr_inc Not Registered
-- bram_en_int Registered
-- reset_bram_we Not Registered
-- set_bram_we Not Registered
--
--
-- WR_DATA_ECC_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_DATA_ECC_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
WR_DATA_ECC_SM_CMB_PROCESS: process ( AXI_WVALID,
AXI_WLAST,
aw_active,
wr_busy_reg,
axi_wdata_full_reg,
axi_wr_burst,
AXI_BREADY,
active_wr_reg,
wr_data_ecc_sm_cs )
begin
-- Assign default values for state machine outputs
wr_data_ecc_sm_ns <= wr_data_ecc_sm_cs;
aw_active_clr <= '0';
wr_busy_cmb <= wr_busy_reg;
bvalid_cnt_inc <= '0';
wrdata_reg_ld <= '0';
reset_bram_we <= '0';
set_bram_we_cmb <= '0';
bram_en_cmb <= '0';
bram_addr_inc <= '0';
axi_wdata_full_cmb <= axi_wdata_full_reg;
axi_wr_burst_cmb <= axi_wr_burst;
active_wr_cmb <= active_wr_reg;
case wr_data_ecc_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Prior to AWVALID assertion, WVALID may be asserted
-- and data accepted into WDATA register.
-- Catch this condition and ensure the register full flag is set.
-- Check that data pipeline is not already full.
if (AXI_WVALID = '1') and (axi_wdata_full_reg = '0') then
wrdata_reg_ld <= '1'; -- Load write data register
axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data
-- w/ CR # 609695
--
-- -- Set flag to check if single or not
-- if (AXI_WLAST = '1') then
-- axi_wr_burst_cmb <= '0';
-- else
-- axi_wr_burst_cmb <= '1';
-- end if;
axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not
end if;
-- Check if AWVALID is asserted & wins arbitration
if (aw_active = '1') then
active_wr_cmb <= '1'; -- Set flag that RMW SM is active
-- Controls mux select for BRAM and ECC register module
-- (Set to '1' wr_chnl or '0' for rd_chnl control)
bram_en_cmb <= '1'; -- Initiate BRAM read transfer
reset_bram_we <= '1'; -- Disable Port A write enables
-- Will proceed to read-modify-write if we get a
-- valid write address early (before WVALID)
wr_data_ecc_sm_ns <= RMW_RD_DATA;
end if; -- WVALID
------------------------- RMW_RD_DATA State -------------------------
when RMW_RD_DATA =>
-- Check if data to write is available in data pipeline
if (axi_wdata_full_reg = '1') then
wr_data_ecc_sm_ns <= RMW_CHK_DATA;
-- Else may have address, but not yet data from W channel
elsif (AXI_WVALID = '1') then
-- Ensure that WDATA pipeline is marked as full, so WREADY negates
axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data
wrdata_reg_ld <= '1'; -- Load write data register
-- w/ CR # 609695
--
-- -- Set flag to check if single or not
-- if (AXI_WLAST = '1') then
-- axi_wr_burst_cmb <= '0';
-- else
-- axi_wr_burst_cmb <= '1';
-- end if;
axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not
wr_data_ecc_sm_ns <= RMW_CHK_DATA;
else
-- Hold here and wait for write data
wr_data_ecc_sm_ns <= RMW_RD_DATA;
end if;
------------------------- RMW_CHK_DATA State -------------------------
when RMW_CHK_DATA =>
-- New state here to add register stage on calculating
-- checkbits for read data and then muxing/creating new
-- checkbits for write cycle.
-- Go immediately to MODIFY stage in RMW sequence
wr_data_ecc_sm_ns <= RMW_MOD_DATA;
set_bram_we_cmb <= '1'; -- Enable all WEs to BRAM
------------------------- RMW_MOD_DATA State -------------------------
when RMW_MOD_DATA =>
-- Modify clock cycle in RMW sequence
-- Only reach this state after a read AND we have data
-- in the write data pipeline to modify and subsequently write to BRAM.
bram_en_cmb <= '1'; -- Initiate BRAM write transfer
-- Can clear WDATA pipeline full condition flag
if (axi_wr_burst = '1') then
axi_wdata_full_cmb <= '0';
end if;
wr_data_ecc_sm_ns <= RMW_WR_DATA; -- Go to write data to BRAM
------------------------- RMW_WR_DATA State -------------------------
when RMW_WR_DATA =>
-- Check if last data beat in a burst (or the write is a single)
if (axi_wr_burst = '0') then
-- Can clear WDATA pipeline full condition flag now that
-- write data has gone out to BRAM (for single data transfers)
axi_wdata_full_cmb <= '0';
bvalid_cnt_inc <= '1'; -- Set flag to assert BVALID and increment counter
wr_data_ecc_sm_ns <= IDLE; -- Go back to IDLE, BVALID assertion is seperate
wr_busy_cmb <= '0'; -- Clear flag to arbiter
active_wr_cmb <= '0'; -- Clear flag (wr_chnl is done accessing BRAM)
-- Used for single port arbitration SM
axi_wr_burst_cmb <= '0';
aw_active_clr <= '1'; -- Clear aw_active flag
reset_bram_we <= '1'; -- Disable Port A write enables
else
-- Continue with read-modify-write sequence for write burst
-- If next data beat is available on AXI, capture the data
if (AXI_WVALID = '1') then
wrdata_reg_ld <= '1'; -- Load write data register
axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data
-- w/ CR # 609695
--
-- -- Set flag to check if single or not
-- if (AXI_WLAST = '1') then
-- axi_wr_burst_cmb <= '0';
-- else
-- axi_wr_burst_cmb <= '1';
-- end if;
axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not
end if;
-- After write cycle (in RMW) => Increment BRAM address counter
bram_addr_inc <= '1';
bram_en_cmb <= '1'; -- Initiate BRAM read transfer
reset_bram_we <= '1'; -- Disable Port A write enables
-- Will proceed to read-modify-write if we get a
-- valid write address early (before WVALID)
wr_data_ecc_sm_ns <= RMW_RD_DATA;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
wr_data_ecc_sm_ns <= IDLE;
--coverage on
end case;
end process WR_DATA_ECC_SM_CMB_PROCESS;
---------------------------------------------------------------------------
WR_DATA_ECC_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wr_data_ecc_sm_cs <= IDLE;
bram_en_int <= '0';
axi_wdata_full_reg <= '0';
wr_busy_reg <= '0';
active_wr_reg <= '0';
set_bram_we <= '0';
else
wr_data_ecc_sm_cs <= wr_data_ecc_sm_ns;
bram_en_int <= bram_en_cmb;
axi_wdata_full_reg <= axi_wdata_full_cmb;
wr_busy_reg <= wr_busy_cmb;
active_wr_reg <= active_wr_cmb;
set_bram_we <= set_bram_we_cmb;
end if;
end if;
end process WR_DATA_ECC_SM_REG_PROCESS;
---------------------------------------------------------------------------
end generate GEN_WDATA_SM_ECC;
-- v1.03a
----------------------------------------------------------------------------
--
-- Generate: GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY
-- Purpose: Create seperate SM use case of no ECC (no read-modify-write)
-- and single port BRAM configuration (no back to back operations
-- are supported). Must wait for aw_active from arbiter to indicate
-- control on BRAM interface.
--
----------------------------------------------------------------------------
GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY: if C_ECC = 0 and
C_SINGLE_PORT_BRAM = 1
generate
begin
-- Unused in this SM configuration
wr_busy_cmb <= '0'; -- Unused
wr_busy_reg <= '0'; -- Unused
active_wr_cmb <= '0'; -- Unused
active_wr_reg <= '0'; -- Unused
Active_Wr <= '0'; -- Unused
---------------------------------------------------------------------------
--
-- WR DATA State Machine
--
-- Description: Central processing unit for AXI write data
-- channel interface handling and AXI write data response
-- handshaking.
--
-- Outputs: Name Type
-- aw_active_clr Not Registered
-- bvalid_cnt_inc Not Registered
-- wrdata_reg_ld Not Registered
-- bram_we_ld Not Registered
-- bram_en_int Registered
-- clr_bram_we Registered
-- bram_addr_inc Not Registered
-- wrdata_reg_ld Not Registered
--
-- Note:
--
-- On "narrow burst transfers" BRAM address only
-- gets incremented at BRAM data width.
-- On WRAP bursts, the BRAM address must wrap when
-- the max is reached
--
--
--
-- WR_DATA_SNG_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_DATA_SNG_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
WR_DATA_SNG_SM_CMB_PROCESS: process ( AXI_WVALID,
AXI_WLAST,
aw_active,
axi_wr_burst,
axi_wdata_full_reg,
wr_data_sng_sm_cs )
begin
-- assign default values for state machine outputs
wr_data_sng_sm_ns <= wr_data_sng_sm_cs;
aw_active_clr <= '0';
bvalid_cnt_inc <= '0';
axi_wr_burst_cmb <= axi_wr_burst;
wrdata_reg_ld <= '0';
bram_we_ld <= '0';
bram_en_cmb <= '0';
clr_bram_we_cmb <= '0';
bram_addr_inc <= '0';
bram_addr_rst_cmb <= '0';
axi_wdata_full_cmb <= axi_wdata_full_reg;
case wr_data_sng_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Prior to AWVALID assertion, WVALID may be asserted
-- and data accepted into WDATA register.
-- Catch this condition and ensure the register full flag is set.
-- Check that data pipeline is not already full.
--
-- Modify WE pipeline and mux to BRAM
-- as well. Since WE may be asserted early (when pipeline is loaded),
-- but not yet ready to go out to BRAM.
--
-- Only first data beat will be accepted early into data pipeline.
-- All remaining beats in a burst will only be accepted upon WVALID.
if (AXI_WVALID = '1') and (axi_wdata_full_reg = '0') then
wrdata_reg_ld <= '1'; -- Load write data register
bram_we_ld <= '1'; -- Load WE register
axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data
axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not
end if;
-- Wait for WVALID and aw_active to initiate write transfer
if (aw_active = '1' and
(AXI_WVALID = '1' or axi_wdata_full_reg = '1')) then
-- If operation is a single, then it goes directly out to BRAM
-- WDATA register is never marked as FULL in this case.
-- If data pipeline is not previously loaded, do so now.
if (axi_wdata_full_reg = '0') then
wrdata_reg_ld <= '1'; -- Load write data register
bram_we_ld <= '1'; -- Load WE register
end if;
-- Initiate BRAM write transfer
bram_en_cmb <= '1';
-- If data goes out to BRAM, mark data register as EMPTY
axi_wdata_full_cmb <= '0';
axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not
-- Check for singles, by checking WLAST assertion w/ WVALID
-- Only if write data pipeline is not yet filled, check WLAST
-- Otherwise, if pipeline is already full, use registered value of WLAST
-- to check for single vs. burst write operation.
if (AXI_WLAST = '1' and axi_wdata_full_reg = '0') or
(axi_wdata_full_reg = '1' and axi_wr_burst = '0') then
-- Single data write
wr_data_sng_sm_ns <= SNG_WR_DATA;
-- Set flag to assert BVALID and increment counter
bvalid_cnt_inc <= '1';
-- BRAM WE only asserted for single clock cycle
clr_bram_we_cmb <= '1';
else
-- Burst data write
wr_data_sng_sm_ns <= BRST_WR_DATA;
end if; -- WLAST
end if;
------------------------- SNG_WR_DATA State -------------------------
when SNG_WR_DATA =>
-- If WREADY is registered, then BVALID generation is seperate
-- from write data flow.
-- Go back to IDLE automatically
-- BVALID will get asserted seperately from W channel
wr_data_sng_sm_ns <= IDLE;
bram_addr_rst_cmb <= '1';
aw_active_clr <= '1';
-- Check for capture of next data beat (WREADY will be asserted)
if (AXI_WVALID = '1') then
wrdata_reg_ld <= '1'; -- Load write data register
bram_we_ld <= '1'; -- Load WE register
axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data
axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not
else
axi_wdata_full_cmb <= '0'; -- If no next data, ensure data register is flagged EMPTY.
end if;
------------------------- BRST_WR_DATA State -------------------------
when BRST_WR_DATA =>
-- Reach this state at the 2nd data beat of a burst
-- AWADDR is already accepted
-- Continue to accept data from AXI write channel
-- and wait for assertion of WLAST
-- Check that WVALID remains asserted for burst
-- If negated, indicates throttling from AXI master
if (AXI_WVALID = '1') then
-- If WVALID is asserted for the 2nd and remaining
-- data beats of the transfer
-- Continue w/ BRAM write enable assertion & advance
-- write data register
-- Write data goes directly out to BRAM.
-- WDATA register is never marked as FULL in this case.
wrdata_reg_ld <= '1'; -- Load write data register
bram_we_ld <= '1'; -- Load WE register
-- Initiate BRAM write transfer
bram_en_cmb <= '1';
-- Increment BRAM address counter
bram_addr_inc <= '1';
-- Check for last data beat in burst transfer
if (AXI_WLAST = '1') then
-- Last/single data write
wr_data_sng_sm_ns <= SNG_WR_DATA;
-- Set flag to assert BVALID and increment counter
bvalid_cnt_inc <= '1';
-- BRAM WE only asserted for single clock cycle
clr_bram_we_cmb <= '1';
end if; -- WLAST
-- Throttling
-- Suspend BRAM write & halt write data & WE register load
else
-- Negate write data register load
wrdata_reg_ld <= '0';
-- Negate WE register load
bram_we_ld <= '0';
-- Negate write to BRAM
bram_en_cmb <= '0';
-- Do not increment BRAM address counter
bram_addr_inc <= '0';
end if; -- WVALID
--coverage off
------------------------------ Default ----------------------------
when others =>
wr_data_sng_sm_ns <= IDLE;
--coverage on
end case;
end process WR_DATA_SNG_SM_CMB_PROCESS;
---------------------------------------------------------------------------
WR_DATA_SNG_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wr_data_sng_sm_cs <= IDLE;
bram_en_int <= '0';
clr_bram_we <= '0';
axi_wdata_full_reg <= '0';
else
wr_data_sng_sm_cs <= wr_data_sng_sm_ns;
bram_en_int <= bram_en_cmb;
clr_bram_we <= clr_bram_we_cmb;
axi_wdata_full_reg <= axi_wdata_full_cmb;
end if;
end if;
end process WR_DATA_SNG_SM_REG_PROCESS;
---------------------------------------------------------------------------
end generate GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY;
----------------------------------------------------------------------------
--
-- Generate: GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY
--
-- Purpose: Create seperate SM for new logic to register out WREADY
-- signal. Behavior for back-to-back operations is different
-- than with combinatorial genearted WREADY output to AXI.
--
-- New SM design supports seperate WREADY and BVALID responses.
--
-- New logic here for axi_bvalid_int output register based
-- on counter design of BVALID.
--
----------------------------------------------------------------------------
GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY: if C_ECC = 0 and
C_SINGLE_PORT_BRAM = 0
generate
begin
-- Unused in this SM configuration
active_wr_cmb <= '0'; -- Unused
active_wr_reg <= '0'; -- Unused
Active_Wr <= '0'; -- Unused
wr_busy_cmb <= '0'; -- Unused
wr_busy_reg <= '0'; -- Unused
---------------------------------------------------------------------------
--
-- WR DATA State Machine
--
-- Description: Central processing unit for AXI write data
-- channel interface handling and AXI write data response
-- handshaking.
--
-- Outputs: Name Type
-- bvalid_cnt_inc Not Registered
-- aw_active_clr Not Registered
-- delay_aw_active_clr Registered
-- axi_wdata_full_reg Registered
-- bram_en_int Registered
-- wrdata_reg_ld Not Registered
-- bram_we_ld Not Registered
-- clr_bram_we Registered
-- bram_addr_inc
--
-- Note:
--
-- On "narrow burst transfers" BRAM address only
-- gets incremented at BRAM data width.
-- On WRAP bursts, the BRAM address must wrap when
-- the max is reached
--
-- Add check on BVALID counter max. Check with
-- AWVALID assertions (since AWID is connected to AWVALID).
--
--
-- WR_DATA_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_DATA_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
WR_DATA_SM_CMB_PROCESS: process ( AXI_WVALID,
AXI_WLAST,
bvalid_cnt_max,
bvalid_cnt_amax,
aw_active,
delay_aw_active_clr,
AXI_AWVALID,
axi_awready_int,
bram_addr_ld_en,
axi_awaddr_full,
awaddr_pipe_sel,
axi_wr_burst,
axi_wdata_full_reg,
wr_b2b_elgible,
wr_data_sm_cs )
begin
-- assign default values for state machine outputs
wr_data_sm_ns <= wr_data_sm_cs;
aw_active_clr <= '0';
delay_aw_active_clr_cmb <= delay_aw_active_clr;
bvalid_cnt_inc <= '0';
axi_wr_burst_cmb <= axi_wr_burst;
wrdata_reg_ld <= '0';
bram_we_ld <= '0';
bram_en_cmb <= '0';
clr_bram_we_cmb <= '0';
bram_addr_inc <= '0';
bram_addr_rst_cmb <= '0';
axi_wdata_full_cmb <= axi_wdata_full_reg;
case wr_data_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check valid write data on AXI write data channel
if (AXI_WVALID = '1') then
wrdata_reg_ld <= '1'; -- Load write data register
bram_we_ld <= '1'; -- Load WE register
-- Add condition to check for simultaneous assertion
-- of AWVALID and AWREADY
if ((aw_active = '1') or (AXI_AWVALID = '1' and axi_awready_int = '1')) and
-- Ensure the BVALID counter does not roll over (max = 8 ID values)
(bvalid_cnt_max = '0') then
-- Initiate BRAM write transfer
bram_en_cmb <= '1';
-- Check for singles, by checking WLAST assertion w/ WVALID
if (AXI_WLAST = '1') then
-- Single data write
wr_data_sm_ns <= SNG_WR_DATA;
-- Set flag to assert BVALID and increment counter
bvalid_cnt_inc <= '1';
-- Set flag to delay clear of AW active flag
delay_aw_active_clr_cmb <= '1';
-- BRAM WE only asserted for single clock cycle
clr_bram_we_cmb <= '1';
axi_wr_burst_cmb <= '0';
else
-- Burst data write
wr_data_sm_ns <= BRST_WR_DATA;
axi_wr_burst_cmb <= '1';
end if; -- WLAST
else
-- AWADDR not yet received
-- Go to wait for write address
wr_data_sm_ns <= W8_AWADDR;
-- Set flag that AXI write data pipe is full
-- and can not accept any more data beats
-- WREADY on AXI will negate in this condition.
axi_wdata_full_cmb <= '1';
-- Set flag for single/burst write operation
-- when AWADDR is not yet received
if (AXI_WLAST = '1') then
axi_wr_burst_cmb <= '0';
else
axi_wr_burst_cmb <= '1';
end if; -- WLAST
end if; -- aw_active
end if; -- WVALID
------------------------- W8_AWADDR State -------------------------
when W8_AWADDR =>
-- As we transition into this state, the write data pipeline
-- is already filled. axi_wdata_full_reg should be = '1'.
-- Disable any additional loads into write data register
-- Default value in SM is applied.
-- Wait for write address to be acknowledged
if (((aw_active = '1') or (AXI_AWVALID = '1' and axi_awready_int = '1')) or
-- Detect load of BRAM address counter from value stored in pipeline.
-- No need to wait until aw_active is asserted or address is captured from AXI bus.
-- As BRAM address is loaded from pipe and ready to be presented to BRAM.
-- Assert BRAM WE.
(bram_addr_ld_en = '1' and axi_awaddr_full = '1' and awaddr_pipe_sel = '1')) and
-- Ensure the BVALID counter does not roll over (max = 8 ID values)
(bvalid_cnt_max = '0') then
-- Initiate BRAM write transfer
bram_en_cmb <= '1';
-- Negate write data full condition
axi_wdata_full_cmb <= '0';
-- Check if single or burst operation
if (axi_wr_burst = '1') then
wr_data_sm_ns <= BRST_WR_DATA;
else
wr_data_sm_ns <= SNG_WR_DATA;
-- BRAM WE only asserted for single clock cycle
clr_bram_we_cmb <= '1';
-- Set flag to assert BVALID and increment counter
bvalid_cnt_inc <= '1';
delay_aw_active_clr_cmb <= '1';
end if;
else
-- Set flag that AXI write data pipe is full
-- and can not accept any more data beats
-- WREADY on AXI will negate in this condition.
axi_wdata_full_cmb <= '1';
end if;
------------------------- SNG_WR_DATA State -------------------------
when SNG_WR_DATA =>
-- No need to check for BVALID assertion here.
-- Move here under if clause on write response channel
-- acknowledging completion of write data.
-- If aw_active was not cleared prior to this state, then
-- clear the flag now.
if (delay_aw_active_clr = '1') then
delay_aw_active_clr_cmb <= '0';
aw_active_clr <= '1';
end if;
-- Add check here if while writing single data beat to BRAM,
-- a new AXI data beat is received (prior to the AWVALID assertion).
-- Ensure here that full flag is asserted for data pipeline state.
-- Check valid write data on AXI write data channel
if (AXI_WVALID = '1') then
-- Load write data register
wrdata_reg_ld <= '1';
-- Must also load WE register
bram_we_ld <= '1';
-- Set flag that AXI write data pipe is full
-- and can not accept any more data beats
-- WREADY on AXI will negate in this condition.
-- Ensure that axi_wdata_full_reg is asserted
-- to prevent early captures on next data burst (or single data
-- transfer)
-- This ensures that the data beats do not get skipped.
axi_wdata_full_cmb <= '1';
-- AWADDR not yet received
-- Go to wait for write address
wr_data_sm_ns <= W8_AWADDR;
-- Accept no more new write data after this first data beat
-- Pipeline is already full in this state. No need to assert
-- no_wdata_accept flag to '1'.
-- Set flag for single/burst write operation
-- when AWADDR is not yet received
if (AXI_WLAST = '1') then
axi_wr_burst_cmb <= '0';
else
axi_wr_burst_cmb <= '1';
end if; -- WLAST
else
-- No subsequent pending operation
-- Return to IDLE
wr_data_sm_ns <= IDLE;
bram_addr_rst_cmb <= '1';
end if;
------------------------- BRST_WR_DATA State -------------------------
when BRST_WR_DATA =>
-- Reach this state at the 2nd data beat of a burst
-- AWADDR is already accepted
-- Continue to accept data from AXI write channel
-- and wait for assertion of WLAST
-- Check that WVALID remains asserted for burst
-- If negated, indicates throttling from AXI master
if (AXI_WVALID = '1') then
-- If WVALID is asserted for the 2nd and remaining
-- data beats of the transfer
-- Continue w/ BRAM write enable assertion & advance
-- write data register
wrdata_reg_ld <= '1'; -- Load write data register
bram_we_ld <= '1'; -- Load WE register
bram_en_cmb <= '1'; -- Initiate BRAM write transfer
bram_addr_inc <= '1'; -- Increment BRAM address counter
-- Check for last data beat in burst transfer
if (AXI_WLAST = '1') then
-- Set flag to assert BVALID and increment counter
bvalid_cnt_inc <= '1';
-- The elgible signal will not be asserted for a subsequent
-- single data beat operation. Next operation is a burst.
-- And the AWADDR is loaded in the address pipeline.
-- Only if BVALID counter can handle next transfer,
-- proceed with back-to-back. Otherwise, go to IDLE
-- (after last data write).
if (wr_b2b_elgible = '1' and bvalid_cnt_amax = '0') then
-- Go to next operation and handle as a
-- back-to-back burst. No empty clock cycles.
-- Go to handle new burst for back to back condition
wr_data_sm_ns <= B2B_W8_WR_DATA;
axi_wr_burst_cmb <= '1';
-- No pending subsequent transfer (burst > 2 data beats)
-- to process
else
-- Last/single data write
wr_data_sm_ns <= SNG_WR_DATA;
-- Be sure to clear aw_active flag at end of write burst
-- But delay when the flag is cleared
delay_aw_active_clr_cmb <= '1';
end if;
end if; -- WLAST
-- Throttling
-- Suspend BRAM write & halt write data & WE register load
else
wrdata_reg_ld <= '0'; -- Negate write data register load
bram_we_ld <= '0'; -- Negate WE register load
bram_en_cmb <= '0'; -- Negate write to BRAM
bram_addr_inc <= '0'; -- Do not increment BRAM address counter
end if; -- WVALID
------------------------- B2B_W8_WR_DATA --------------------------
when B2B_W8_WR_DATA =>
-- Reach this state upon a back-to-back condition
-- when BVALID/BREADY handshake is received,
-- but WVALID is not yet asserted for subsequent transfer.
-- Check valid write data on AXI write data channel
if (AXI_WVALID = '1') then
-- Load write data register
wrdata_reg_ld <= '1';
-- Load WE register
bram_we_ld <= '1';
-- Initiate BRAM write transfer
bram_en_cmb <= '1';
-- Burst data write
wr_data_sm_ns <= BRST_WR_DATA;
axi_wr_burst_cmb <= '1';
-- Make modification to last_data_ack_mod signal
-- so that it is asserted when this state is reached
-- and the BRAM address counter gets loaded.
-- WVALID not yet asserted
else
wrdata_reg_ld <= '0'; -- Negate write data register load
bram_we_ld <= '0'; -- Negate WE register load
bram_en_cmb <= '0'; -- Negate write to BRAM
bram_addr_inc <= '0'; -- Do not increment BRAM address counter
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
wr_data_sm_ns <= IDLE;
--coverage on
end case;
end process WR_DATA_SM_CMB_PROCESS;
---------------------------------------------------------------------------
WR_DATA_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wr_data_sm_cs <= IDLE;
bram_en_int <= '0';
clr_bram_we <= '0';
delay_aw_active_clr <= '0';
axi_wdata_full_reg <= '0';
else
wr_data_sm_cs <= wr_data_sm_ns;
bram_en_int <= bram_en_cmb;
clr_bram_we <= clr_bram_we_cmb;
delay_aw_active_clr <= delay_aw_active_clr_cmb;
axi_wdata_full_reg <= axi_wdata_full_cmb;
end if;
end if;
end process WR_DATA_SM_REG_PROCESS;
---------------------------------------------------------------------------
end generate GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY;
---------------------------------------------------------------------------
WR_BURST_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_wr_burst <= '0';
else
axi_wr_burst <= axi_wr_burst_cmb;
end if;
end if;
end process WR_BURST_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Write Response Channel Interface ***
---------------------------------------------------------------------------
-- v1.03a
---------------------------------------------------------------------------
--
--
-- New FIFO storage for BID, so AWID can be stored in
-- a FIFO and B response is seperated from W response.
--
-- Use registered WREADY & BID FIFO in single port configuration.
--
---------------------------------------------------------------------------
-- Instantiate FIFO to store BID values to be asserted back on B channel.
-- Only 8 entries deep, BVALID counter only allows W channel to be 8 ahead of
-- B channel.
--
-- If AWID is a single bit wide, sythesis optimizes the module, srl_fifo,
-- to a single SRL16E library module.
BID_FIFO: entity work.srl_fifo
generic map (
C_DATA_BITS => C_AXI_ID_WIDTH,
C_DEPTH => 8
)
port map (
Clk => S_AXI_AClk,
Reset => bid_fifo_rst,
FIFO_Write => bid_fifo_ld_en,
Data_In => bid_fifo_ld,
FIFO_Read => bid_fifo_rd_en,
Data_Out => bid_fifo_rd,
FIFO_Full => open,
Data_Exists => bid_fifo_not_empty,
Addr => open
);
bid_fifo_rst <= not (S_AXI_AResetn);
bid_fifo_ld_en <= bram_addr_ld_en;
bid_fifo_ld <= AXI_AWID when (awaddr_pipe_sel = '0') else axi_awid_pipe;
-- Read from FIFO when BVALID is to be asserted on bus, or in a back-to-back assertion
-- when a BID value is available in the FIFO.
bid_fifo_rd_en <= bid_fifo_not_empty and -- Only read if data is available.
((bid_gets_fifo_load_d1) or -- a) Do the FIFO read in the clock cycle
-- following the BID value directly
-- aserted on the B channel (from AWID or pipeline).
(first_fifo_bid) or -- b) Read from FIFO when BID is previously stored
-- but BVALID is not yet asserted on AXI.
(bvalid_cnt_dec)); -- c) Or read when next BID value is to be updated
-- on B channel (and exists waiting in FIFO).
-- 1) Special case (1st load in FIFO) (and single clock cycle turnaround needed on BID, from AWID).
-- If loading the FIFO and BVALID is to be asserted in the next clock cycle
-- Then capture this condition to read from FIFO in the subsequent clock cycle
-- (and clear the BID value stored in the FIFO).
bid_gets_fifo_load <= '1' when (bid_fifo_ld_en = '1') and
(first_fifo_bid = '1' or b2b_fifo_bid = '1') else '0';
first_fifo_bid <= '1' when ((bvalid_cnt_inc = '1') and (bvalid_cnt_non_zero = '0')) else '0';
-- 2) An additional special case.
-- When write data register is loaded for single (bvalid_cnt = "001", due to WLAST/WVALID)
-- But, AWID not yet received (FIFO is still empty).
-- If BID FIFO is still empty with the BVALID counter decrement, but simultaneously
-- is increment (same condition as first_fifo_bid).
b2b_fifo_bid <= '1' when (bvalid_cnt_inc = '1' and bvalid_cnt_dec = '1' and
bvalid_cnt = "001" and bid_fifo_not_empty = '0') else '0';
-- Output BID register to B AXI channel
REG_BID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_bid_int <= (others => '0');
-- If loading the FIFO and BVALID is to be asserted in the next clock cycle
-- Then output the AWID or pipelined value (the same BID that gets loaded into FIFO).
elsif (bid_gets_fifo_load = '1') then
axi_bid_int <= bid_fifo_ld;
-- If new value read from FIFO then ensure that value is updated on AXI.
elsif (bid_fifo_rd_en = '1') then
axi_bid_int <= bid_fifo_rd;
else
axi_bid_int <= axi_bid_int;
end if;
end if;
end process REG_BID;
-- Capture condition of BID output updated while the FIFO is also
-- getting updated. Read FIFO in the subsequent clock cycle to
-- clear the value stored in the FIFO.
REG_BID_LD: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bid_gets_fifo_load_d1 <= '0';
else
bid_gets_fifo_load_d1 <= bid_gets_fifo_load;
end if;
end if;
end process REG_BID_LD;
---------------------------------------------------------------------------
-- AXI_BRESP Output Register
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_BRESP
-- Purpose: Generate BRESP output signal when ECC is disabled.
-- Only allowable output is RESP_OKAY.
---------------------------------------------------------------------------
GEN_BRESP: if C_ECC = 0 generate
begin
REG_BRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_bresp_int <= (others => '0');
-- elsif (AXI_WLAST = '1') then
-- CR # 609695
elsif ((AXI_WLAST and AXI_WVALID and axi_wready_int_mod) = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
axi_bresp_int <= RESP_OKAY;
else
axi_bresp_int <= axi_bresp_int;
end if;
end if;
end process REG_BRESP;
end generate GEN_BRESP;
---------------------------------------------------------------------------
-- Generate: GEN_BRESP_ECC
-- Purpose: Generate BRESP output signal when ECC is enabled
-- If no ECC error condition is detected during the RMW
-- sequence, then output will be RESP_OKAY. When an
-- uncorrectable error is detected, the output will RESP_SLVERR.
---------------------------------------------------------------------------
GEN_BRESP_ECC: if C_ECC = 1 generate
signal UE_Q_reg : std_logic := '0';
begin
REG_BRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_bresp_int <= (others => '0');
elsif (bvalid_cnt_inc_d1 = '1') then
--coverage off
-- Exclusive operations not yet supported
-- If no ECC errors occur, respond with OK
if (UE_Q = '1') or (UE_Q_reg = '1') then
axi_bresp_int <= RESP_SLVERR;
--coverage on
else
axi_bresp_int <= RESP_OKAY;
end if;
else
axi_bresp_int <= axi_bresp_int;
end if;
end if;
end process REG_BRESP;
-- Check if any error conditions occured during the write operation.
-- Capture condition for each write transfer.
REG_UE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear at end of current write (and ensure the flag is cleared
-- at the beginning of a write transfer)
if (S_AXI_AResetn = C_RESET_ACTIVE) or (aw_active_re = '1') or
(AXI_BREADY = '1' and axi_bvalid_int = '1') then
UE_Q_reg <= '0';
--coverage off
elsif (UE_Q = '1') then
UE_Q_reg <= '1';
--coverage on
else
UE_Q_reg <= UE_Q_reg;
end if;
end if;
end process REG_UE;
end generate GEN_BRESP_ECC;
-- v1.03a
---------------------------------------------------------------------------
-- Instantiate BVALID counter outside of specific SM generate block.
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- BVALID counter to track the # of required BVALID/BREADY handshakes
-- needed to occur on the AXI interface. Based on early and seperate
-- AWVALID/AWREADY and WVALID/WREADY handshake exchanges.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt <= (others => '0');
-- Ensure we only increment counter wyhen BREADY is not asserted
elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1);
-- Ensure that we only decrement when SM is not incrementing
elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1);
else
bvalid_cnt <= bvalid_cnt;
end if;
end if;
end process REG_BVALID_CNT;
bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and
axi_bvalid_int = '1' and
bvalid_cnt_non_zero = '1') else '0';
bvalid_cnt_non_zero <= '1' when (bvalid_cnt /= "000") else '0';
bvalid_cnt_amax <= '1' when (bvalid_cnt = "110") else '0';
bvalid_cnt_max <= '1' when (bvalid_cnt = "111") else '0';
-- Replace BVALID output register
-- Assert BVALID as long as BVALID counter /= zero
REG_BVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Ensure that if we are also incrementing BVALID counter, the BVALID stays asserted.
(bvalid_cnt = "001" and bvalid_cnt_dec = '1' and bvalid_cnt_inc = '0') then
axi_bvalid_int <= '0';
elsif (bvalid_cnt_non_zero = '1') or (bvalid_cnt_inc = '1') then
axi_bvalid_int <= '1';
else
axi_bvalid_int <= '0';
end if;
end if;
end process REG_BVALID;
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite)
constant null8 : std_logic_vector(0 to 7) := "00000000"; -- Specific to 64-bit data width
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
constant C_USE_LUT6 : boolean := TRUE;
signal RdECC : std_logic_vector(C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Temp
signal WrECC : std_logic_vector(C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal WrECC_i : std_logic_vector(C_ECC_WIDTH-1 downto 0) := (others => '0');
signal AXI_WSTRB_Q : std_logic_vector((C_AXI_DATA_WIDTH/8 - 1) downto 0) := (others => '0');
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC
signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to 64-bit ECC
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence
signal RdModifyWr_Read_i : std_logic := '0';
signal RdModifyWr_Check : std_logic := '0';
signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal UnCorrectedRdData : std_logic_vector(0 to C_AXI_DATA_WIDTH-1) := (others => '0');
signal CE_Q : std_logic := '0';
signal Sl_CE_i : std_logic := '0';
signal Sl_UE_i : std_logic := '0';
subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1);
-- 0:6 for 32-bit ECC
-- 0:7 for 64-bit ECC
type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits;
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
-- v1.03a
constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
begin
-- Generate signal to advance BRAM read address pipeline to
-- capture address for ECC error conditions (in lite_ecc_reg module).
BRAM_Addr_En <= RdModifyWr_Read;
-- v1.03a
RdModifyWr_Read <= '1' when (wr_data_ecc_sm_cs = RMW_RD_DATA) else '0';
RdModifyWr_Modify <= '1' when (wr_data_ecc_sm_cs = RMW_MOD_DATA) else '0';
RdModifyWr_Write <= '1' when (wr_data_ecc_sm_cs = RMW_WR_DATA) else '0';
-----------------------------------------------------------------------
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation.
-- Save WSTRBs here in this register
REG_WSTRB : process (S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
AXI_WSTRB_Q <= (others => '0');
elsif (wrdata_reg_ld = '1') then
AXI_WSTRB_Q <= AXI_WSTRB;
end if;
end if;
end process REG_WSTRB;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_WRDATA_CMB
-- Purpose: Replace manual signal assignment for WrData_cmb with
-- generate funtion.
--
-- Ensure correct byte swapping occurs with
-- CorrectedRdData (0 to C_AXI_DATA_WIDTH-1) assignment
-- to WrData_cmb (C_AXI_DATA_WIDTH-1 downto 0).
--
-- AXI_WSTRB_Q (C_AXI_DATA_WIDTH_BYTES-1 downto 0) matches
-- to WrData_cmb (C_AXI_DATA_WIDTH-1 downto 0).
--
------------------------------------------------------------------------
GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate
begin
WrData_cmb ( (((i+1)*8)-1) downto i*8 ) <= bram_wrdata_int ((((i+1)*8)-1) downto i*8) when
(RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1')
else CorrectedRdData ( (C_AXI_DATA_WIDTH - ((i+1)*8)) to
(C_AXI_DATA_WIDTH - (i*8) - 1) );
end generate GEN_WRDATA_CMB;
REG_WRDATA : process (S_AXI_AClk) is
begin
-- Remove reset value to minimize resources & improve timing
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
WrData <= WrData_cmb;
end if;
end process REG_WRDATA;
------------------------------------------------------------------------
-- New assignment of ECC bits to BRAM write data outside generate
-- blocks. Same signal assignment regardless of ECC type.
BRAM_WrData ((C_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto C_AXI_DATA_WIDTH)
<= WrECC_i xor FaultInjectECC;
------------------------------------------------------------------------
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
begin
---------------------- Hsiao ECC Write Logic ----------------------
-- Instantiate ecc_gen_hsiao module, generated from MIG
ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
-- Merge muxed rd/write data to gen
HSIAO_ECC: process (h_rows, WrData)
constant DQ_WIDTH : integer := CODE_WIDTH;
variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_AXI_DATA_WIDTH);
begin
-- Loop to generate all ECC bits
for k in 0 to ECC_WIDTH - 1 loop
ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_AXI_DATA_WIDTH - 1 downto 0)
and h_rows (k * CODE_WIDTH + C_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH)));
end loop;
WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_AXI_DATA_WIDTH);
end process HSIAO_ECC;
-----------------------------------------------------------------------
-- Generate: GEN_ECC_32
-- Purpose: For 32-bit ECC implementations, assign unused
-- MSB of ECC output to BRAM with '0'.
-----------------------------------------------------------------------
GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
begin
-- Account for 32-bit and MSB '0' of ECC bits
WrECC_i <= '0' & WrECC;
end generate GEN_ECC_32;
-----------------------------------------------------------------------
-- Generate: GEN_ECC_N
-- Purpose: For all non 32-bit ECC implementations, assign ECC
-- bits for BRAM output.
-----------------------------------------------------------------------
GEN_ECC_N: if C_AXI_DATA_WIDTH /= 32 generate
begin
WrECC_i <= WrECC;
end generate GEN_ECC_N;
---------------------- Hsiao ECC Read Logic -----------------------
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( BRAM_RdData (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
end if;
end process REG_SYNDROME;
ecc_rddata_r <= UnCorrectedRdData;
-- Reconstruct H-matrix
H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
CorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_AXI_DATA_WIDTH-1 downto 0);
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
-----------------------------------------------------------------
-- Generate: GEN_ECC_32
-- Purpose: Assign ECC out data vector (N:0) unique for 32-bit BRAM.
-- Add extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 32-bit BRAM data widths.
-- ECC bits are in upper order bits.
-----------------------------------------------------------------
GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
constant correct_data_table_32 : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
begin
--------------------- Hamming 32-bit ECC Write Logic ------------------
-------------------------------------------------------------------------
-- Instance: CHK_HANDLER_WR_32
-- Description: Generate ECC bits for writing into BRAM.
-- WrData (N:0)
-------------------------------------------------------------------------
CHK_HANDLER_WR_32: entity work.checkbit_handler
generic map (
C_ENCODE => true, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => open, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => open, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open ); -- [out std_logic]
-- v1.03a
-- Account for 32-bit and MSB '0' of ECC bits
WrECC_i <= '0' & WrECC;
--------------------- Hamming 32-bit ECC Read Logic -------------------
--------------------------------------------------------------------------
-- Instance: CHK_HANDLER_RD_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
--------------------------------------------------------------------------
CHK_HANDLER_RD_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- DataIn (8:39)
-- CheckIn (1:7)
DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
---------------------------------------------------------------------------
-- Insert register stage for syndrome
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl
-- w/ balanced pipeline stage) before correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
---------------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Generate ECC bits for checking data read from BRAM.
---------------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_32 (i))
port map (
DIn => UnCorrectedRdData (i),
Syndrome => syndrome_reg_i,
DCorr => CorrectedRdData (i));
end generate GEN_CORR_32;
end generate GEN_ECC_32;
-----------------------------------------------------------------
-- Generate: GEN_ECC_64
-- Purpose: Assign ECC out data vector (N:0) unique for 64-bit BRAM.
-- No extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 64-bit BRAM data widths.
-- ECC bits are in upper order bits.
-----------------------------------------------------------------
GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
constant correct_data_table_64 : correct_data_table_type := (
0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001",
4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001",
8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001",
12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001",
16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001",
20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001",
24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101",
28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101",
32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101",
36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101",
40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101",
44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101",
48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101",
52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101",
56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011",
60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011"
);
signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0');
signal syndrome7_a : std_logic := '0';
signal syndrome7_b : std_logic := '0';
begin
--------------------- Hamming 64-bit ECC Write Logic ------------------
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_WR_64
-- Description: Generate ECC bits for writing into BRAM when configured
-- as 64-bit wide BRAM.
-- WrData (N:0)
-- Enable C_REG on encode path.
---------------------------------------------------------------------------
CHK_HANDLER_WR_64: entity work.checkbit_handler_64
generic map (
C_ENCODE => true, -- [boolean]
C_REG => true, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
Clk => S_AXI_AClk, -- [in std_logic]
DataIn => WrData_cmb, -- [in std_logic_vector(0 to 63)]
CheckIn => null8, -- [in std_logic_vector(0 to 7)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 7)]
Syndrome => open, -- [out std_logic_vector(0 to 7)]
Syndrome_7 => open, -- [out std_logic_vector(0 to 11)]
Syndrome_Chk => null8, -- [in std_logic_vector(0 to 7)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open ); -- [out std_logic]
-- Note: (7:0) Old bit lane assignment
-- BRAM_WrData ((C_ECC_WIDTH - 1) downto 0)
-- v1.02a
-- WrECC is assigned to BRAM_WrData (71:64)
-- v1.03a
-- BRAM_WrData (71:64) assignment done outside of this
-- ECC type generate block.
WrECC_i <= WrECC;
--------------------- Hamming 64-bit ECC Read Logic -------------------
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_RD_64
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_RD_64: entity work.checkbit_handler_64
generic map (
C_ENCODE => false, -- [boolean]
C_REG => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
Clk => S_AXI_AClk, -- [in std_logic]
-- DataIn (8:71)
-- CheckIn (0:7)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)]
CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 7)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)]
Syndrome_7 => Syndrome_7, -- [out std_logic_vector(0 to 11)]
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
---------------------------------------------------------------------------
-- Insert register stage for syndrome
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_reg <= Syndrome;
syndrome_7_reg <= Syndrome_7;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Move final XOR to registered side of syndrome bits.
-- Do last XOR on select syndrome bits after pipeline stage
-- before correct_one_bit_64 module.
syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6);
PARITY_CHK7_A: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome7_a ); -- [out std_logic]
PARITY_CHK7_B: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome7_b ); -- [out std_logic]
syndrome_reg_i (7) <= syndrome7_a xor syndrome7_b;
---------------------------------------------------------------------------
-- Generate: GEN_CORRECT_DATA
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
---------------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_64
-- Description: Generate ECC bits for checking data read from BRAM.
---------------------------------------------------------------------------
CORR_ONE_BIT_64: entity work.correct_one_bit_64
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_64 (i))
port map (
DIn => UnCorrectedRdData (i),
Syndrome => syndrome_reg_i,
DCorr => CorrectedRdData (i));
end generate GEN_CORR_64;
end generate GEN_ECC_64;
end generate GEN_HAMMING_ECC;
-- Remember correctable/uncorrectable error from BRAM read
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if RdModifyWr_Modify = '1' then -- Capture error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- ECC register block gets registered UE or CE conditions to update
-- ECC registers/interrupt/flag outputs.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
CE_Failing_We <= CE_Q;
FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0';
-----------------------------------------------------------------------
-- Add register delay on BVALID counter increment
-- Used to clear fault inject register.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt_inc_d1 <= '0';
else
bvalid_cnt_inc_d1 <= bvalid_cnt_inc;
end if;
end if;
end process REG_BVALID_CNT;
-----------------------------------------------------------------------
-- Map BRAM_RdData (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <=
BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- Generate: GEN_ECC_32
-- Purpose: For 32-bit ECC implementations, account for
-- extra bit in read data mapping on registered value.
-----------------------------------------------------------------------
GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
begin
-- Insert register stage for read data to correct
REG_CHK_DATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
UnCorrectedRdData <= bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH);
end if;
end process REG_CHK_DATA;
end generate GEN_ECC_32;
-----------------------------------------------------------------------
-- Generate: GEN_ECC_N
-- Purpose: For all non 32-bit ECC implementations, assign ECC
-- bits for BRAM output.
-----------------------------------------------------------------------
GEN_ECC_N: if C_AXI_DATA_WIDTH /= 32 generate
begin
-- Insert register stage for read data to correct
REG_CHK_DATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
UnCorrectedRdData <= bram_din_a_i(C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1);
end if;
end process REG_CHK_DATA;
end generate GEN_ECC_N;
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Drive default output signals when ECC is diabled.
---------------------------------------------------------------------------
GEN_NO_ECC: if C_ECC = 0 generate
begin
BRAM_Addr_En <= '0';
FaultInjectClr <= '0';
CE_Failing_We <= '0';
Sl_CE <= '0';
Sl_UE <= '0';
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
-- *** BRAM Interface Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WE
-- Purpose: BRAM WE generate process
-- One WE per 8-bits of BRAM data.
---------------------------------------------------------------------------
GEN_BRAM_WE: for i in C_AXI_DATA_WIDTH/8 + (C_ECC*(1+(C_AXI_DATA_WIDTH/128))) - 1 downto 0 generate
begin
BRAM_WE (i) <= bram_we_int (i);
end generate GEN_BRAM_WE;
---------------------------------------------------------------------------
BRAM_En <= bram_en_int;
---------------------------------------------------------------------------
-- BRAM Address Generate
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
--
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WRDATA
-- Purpose: Generate BRAM Write Data.
---------------------------------------------------------------------------
GEN_BRAM_WRDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate
begin
-- Check if ECC is enabled
-- If so, XOR the fault injection vector with the data
-- (post-pipeline) to avoid any timing issues on the data vector
-- from AXI.
-----------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Generate output write data when ECC is disabled.
-----------------------------------------------------------------------
GEN_NO_ECC : if C_ECC = 0 generate
begin
BRAM_WrData (i) <= bram_wrdata_int (i);
end generate GEN_NO_ECC;
-----------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Generate output write data when ECC is enable
-- (use fault vector)
-- (N:0)
-- for 32-bit (31:0) WrData while (ECC = [39:32])
-----------------------------------------------------------------------
GEN_W_ECC : if C_ECC = 1 generate
begin
BRAM_WrData (i) <= WrData (i) xor FaultInjectData (i);
end generate GEN_W_ECC;
end generate GEN_BRAM_WRDATA;
---------------------------------------------------------------------------
end architecture implementation;
-------------------------------------------------------------------------------
-- full_axi.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: full_axi.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller when configured in a full AXI4 mode.
-- The rd_chnl and wr_chnl modules are instantiated.
-- The ECC AXI-Lite register module is instantiated, if enabled.
-- When single port BRAM mode is selected, the arbitration logic
-- is instantiated (and connected to each wr_chnl & rd_chnl).
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen_hsiao.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen_hsiao.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/15/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter and mappings on instantiated modules.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update WE & BRAM data sizes based on 128-bit ECC configuration.
-- Plus XST clean-up.
-- ^^^^^^
-- JLJ 3/31/2011 v1.03a
-- ~~~~~~
-- Add coverage tags.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add signal, AW2Arb_BVALID_Cnt, between wr_chnl and sng_port_arb modules.
-- ^^^^^^
-- JLJ 4/20/2011 v1.03a
-- ~~~~~~
-- Add default values for Arb2AW_Active & Arb2AR_Active when dual port mode.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
use work.lite_ecc_reg;
use work.sng_port_arb;
use work.wr_chnl;
use work.rd_chnl;
------------------------------------------------------------------------------
entity full_axi is
generic (
-- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1;
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- AXI Write Address Channel Signals (AW)
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
-- AXI Write Data Channel Signals (W)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
-- AXI Write Data Response Channel Signals (B)
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
-- AXI Read Address Channel Signals (AR)
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI-Lite ECC Register Interface Signals
-- AXI-Lite Clock and Reset
-- TBD
-- S_AXI_CTRL_ACLK : in std_logic;
-- S_AXI_CTRL_ARESETN : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- BRAM Interface Signals (Port A)
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-- BRAM Interface Signals (Port B)
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0)
);
end entity full_axi;
-------------------------------------------------------------------------------
architecture implementation of full_axi is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH);
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-- Internal AXI Signals
signal S_AXI_AWREADY_i : std_logic := '0';
signal S_AXI_ARREADY_i : std_logic := '0';
-- Internal BRAM Signals
signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_En_A_i : std_logic := '0';
signal BRAM_En_B_i : std_logic := '0';
signal BRAM_WE_A_i : std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal BRAM_RdData_i : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
-- Internal ECC Signals
signal Enable_ECC : std_logic := '0';
signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers
signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Wr_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
--signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
--signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register
signal Wr_Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Wr_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Rd_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal Rd_Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Rd_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal FaultInjectECC : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal FaultInjectECC_i : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal Active_Wr : std_logic := '0';
signal BRAM_Addr_En : std_logic := '0';
signal Wr_BRAM_Addr_En : std_logic := '0';
signal Rd_BRAM_Addr_En : std_logic := '0';
-- Internal Arbitration Signals
signal Arb2AW_Active : std_logic := '0';
signal AW2Arb_Busy : std_logic := '0';
signal AW2Arb_Active_Clr : std_logic := '0';
signal AW2Arb_BVALID_Cnt : std_logic_vector (2 downto 0) := (others => '0');
signal Arb2AR_Active : std_logic := '0';
signal AR2Arb_Active_Clr : std_logic := '0';
signal WrChnl_BRAM_Addr_Rst : std_logic := '0';
signal WrChnl_BRAM_Addr_Ld_En : std_logic := '0';
signal WrChnl_BRAM_Addr_Inc : std_logic := '0';
signal WrChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal RdChnl_BRAM_Addr_Ld_En : std_logic := '0';
signal RdChnl_BRAM_Addr_Inc : std_logic := '0';
signal RdChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal bram_addr_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** BRAM Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: ADDR_SNG_PORT
-- Purpose: OR the BRAM_Addr outputs from each wr_chnl & rd_chnl
-- Only one write or read will be active at a time.
-- Ensure that ecah channel address is driven to '0' when not in use.
---------------------------------------------------------------------------
ADDR_SNG_PORT: if C_SINGLE_PORT_BRAM = 1 generate
signal sng_bram_addr_rst : std_logic := '0';
signal sng_bram_addr_ld_en : std_logic := '0';
signal sng_bram_addr_ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal sng_bram_addr_inc : std_logic := '0';
begin
-- BRAM_Addr_A <= BRAM_Addr_A_i or BRAM_Addr_B_i;
-- BRAM_Addr_A <= BRAM_Addr_A_i when (Arb2AW_Active = '1') else BRAM_Addr_B_i;
-- BRAM_Addr_A <= BRAM_Addr_A_i when (Active_Wr = '1') else BRAM_Addr_B_i;
-- Insert mux on address counter control signals
sng_bram_addr_rst <= WrChnl_BRAM_Addr_Rst;
sng_bram_addr_ld_en <= WrChnl_BRAM_Addr_Ld_En or RdChnl_BRAM_Addr_Ld_En;
sng_bram_addr_ld <= RdChnl_BRAM_Addr_Ld when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Ld;
sng_bram_addr_inc <= RdChnl_BRAM_Addr_Inc when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Inc;
I_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (sng_bram_addr_rst = '1') then
bram_addr_int <= (others => '0');
elsif (sng_bram_addr_ld_en = '1') then
bram_addr_int <= sng_bram_addr_ld;
elsif (sng_bram_addr_inc = '1') then
bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process I_ADDR_CNT;
BRAM_Addr_B <= (others => '0');
BRAM_En_A <= BRAM_En_A_i or BRAM_En_B_i;
-- BRAM_En_A <= BRAM_En_A_i when (Arb2AW_Active = '1') else BRAM_En_B_i;
BRAM_En_B <= '0';
BRAM_RdData_i <= BRAM_RdData_A; -- Assign read data port A
BRAM_WE_A <= BRAM_WE_A_i when (Arb2AW_Active = '1') else (others => '0');
-- v1.03a
-- Early register on WrData and WSTRB in wr_chnl. (Previous value was always cleared).
---------------------------------------------------------------------------
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr_A (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr_A (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
end generate ADDR_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: ADDR_DUAL_PORT
-- Purpose: Assign each BRAM address when in a dual port controller
-- configuration.
---------------------------------------------------------------------------
ADDR_DUAL_PORT: if C_SINGLE_PORT_BRAM = 0 generate
begin
BRAM_Addr_A <= BRAM_Addr_A_i;
BRAM_Addr_B <= BRAM_Addr_B_i;
BRAM_En_A <= BRAM_En_A_i;
BRAM_En_B <= BRAM_En_B_i;
BRAM_WE_A <= BRAM_WE_A_i;
BRAM_RdData_i <= BRAM_RdData_B; -- Assign read data port B
end generate ADDR_DUAL_PORT;
BRAM_WrData_B <= (others => '0');
BRAM_WE_B <= (others => '0');
---------------------------------------------------------------------------
-- *** AXI-Lite ECC Register Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_REGS
-- Purpose: Generate default values if ECC registers are disabled (or when
-- ECC is disabled).
-- Include both AXI-Lite default signal values & internal
-- core signal values.
---------------------------------------------------------------------------
GEN_NO_REGS: if (C_ECC = 0) generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
-- No fault injection
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
-- Interrupt only enabled when ECC status/interrupt registers enabled
ECC_Interrupt <= '0';
ECC_UE <= '0';
Enable_ECC <= '0';
end generate GEN_NO_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_REGS
-- Purpose: Generate ECC register module when ECC is enabled and
-- ECC registers are enabled.
---------------------------------------------------------------------------
-- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate
-- For future implementation.
GEN_REGS: if (C_ECC = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_LITE_ECC_REG : entity work.lite_ecc_reg
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
-- TBD
-- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock
-- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn ,
Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
-- Add AXI-Lite ECC Register Ports
AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
Enable_ECC => Enable_ECC ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => CE_Failing_We ,
CE_CounterReg_Inc => CE_Failing_We ,
Sl_CE => Sl_CE ,
Sl_UE => Sl_UE ,
BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_En => BRAM_Addr_En ,
Active_Wr => Active_Wr ,
-- BRAM_RdData_A => BRAM_RdData_A (C_S_AXI_DATA_WIDTH-1 downto 0) ,
-- BRAM_RdData_B => BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0) ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC_i
);
BRAM_Addr_En <= Wr_BRAM_Addr_En or Rd_BRAM_Addr_En;
-- v1.03a
-- Add coverage tags for Wr_CE_Failing_We.
-- No testing on forcing errors with RMW and AXI write transfers.
--coverage off
CE_Failing_We <= Wr_CE_Failing_We or Rd_CE_Failing_We;
Sl_CE <= Wr_Sl_CE or Rd_Sl_CE;
Sl_UE <= Wr_Sl_UE or Rd_Sl_UE;
--coverage on
-------------------------------------------------------------------
-- Generate: GEN_32
-- Purpose: Add MSB '0' on ECC vector as only 7-bits wide in 32-bit.
-------------------------------------------------------------------
GEN_32: if C_S_AXI_DATA_WIDTH = 32 generate
begin
FaultInjectECC <= '0' & FaultInjectECC_i;
end generate GEN_32;
-------------------------------------------------------------------
-- Generate: GEN_NON_32
-- Purpose: Data widths match at 8-bits for ECC on 64-bit data.
-- And 9-bits for 128-bit data.
-------------------------------------------------------------------
GEN_NON_32: if C_S_AXI_DATA_WIDTH /= 32 generate
begin
FaultInjectECC <= FaultInjectECC_i;
end generate GEN_NON_32;
end generate GEN_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_ARB
-- Purpose: Generate arbitration module when AXI4 is configured in
-- single port mode.
---------------------------------------------------------------------------
GEN_ARB: if (C_SINGLE_PORT_BRAM = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_SNG_PORT : entity work.sng_port_arb
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY ,
AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY ,
Arb2AW_Active => Arb2AW_Active ,
AW2Arb_Busy => AW2Arb_Busy ,
AW2Arb_Active_Clr => AW2Arb_Active_Clr ,
AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt ,
Arb2AR_Active => Arb2AR_Active ,
AR2Arb_Active_Clr => AR2Arb_Active_Clr
);
end generate GEN_ARB;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL
-- Purpose: Dual mode. AWREADY and ARREADY are generated from each
-- wr_chnl and rd_chnl module.
---------------------------------------------------------------------------
GEN_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
S_AXI_AWREADY <= S_AXI_AWREADY_i;
S_AXI_ARREADY <= S_AXI_ARREADY_i;
Arb2AW_Active <= '0';
Arb2AR_Active <= '0';
end generate GEN_DUAL;
---------------------------------------------------------------------------
-- Instance: I_WR_CHNL
--
-- Description:
-- BRAM controller write channel logic. Controls AXI bus handshaking and
-- data flow on the write address (AW), write data (W) and
-- write response (B) channels.
--
-- BRAM signals are marked as output from Wr Chnl for future implementation
-- of merging Wr/Rd channel outputs to a single port of the BRAM module.
--
---------------------------------------------------------------------------
I_WR_CHNL : entity work.wr_chnl
generic map (
-- C_FAMILY => C_FAMILY ,
C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH ,
C_ECC_TYPE => C_ECC_TYPE -- v1.03a
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
AXI_AWID => S_AXI_AWID ,
AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_AWLEN => S_AXI_AWLEN ,
AXI_AWSIZE => S_AXI_AWSIZE ,
AXI_AWBURST => S_AXI_AWBURST ,
AXI_AWLOCK => S_AXI_AWLOCK ,
AXI_AWCACHE => S_AXI_AWCACHE ,
AXI_AWPROT => S_AXI_AWPROT ,
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY_i ,
AXI_WDATA => S_AXI_WDATA ,
AXI_WSTRB => S_AXI_WSTRB ,
AXI_WLAST => S_AXI_WLAST ,
AXI_WVALID => S_AXI_WVALID ,
AXI_WREADY => S_AXI_WREADY ,
AXI_BID => S_AXI_BID ,
AXI_BRESP => S_AXI_BRESP ,
AXI_BVALID => S_AXI_BVALID ,
AXI_BREADY => S_AXI_BREADY ,
-- Arb Ports
Arb2AW_Active => Arb2AW_Active ,
AW2Arb_Busy => AW2Arb_Busy ,
AW2Arb_Active_Clr => AW2Arb_Active_Clr ,
AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt ,
Sng_BRAM_Addr_Rst => WrChnl_BRAM_Addr_Rst ,
Sng_BRAM_Addr_Ld_En => WrChnl_BRAM_Addr_Ld_En ,
Sng_BRAM_Addr_Ld => WrChnl_BRAM_Addr_Ld ,
Sng_BRAM_Addr_Inc => WrChnl_BRAM_Addr_Inc ,
Sng_BRAM_Addr => bram_addr_int ,
-- ECC Ports
Enable_ECC => Enable_ECC ,
BRAM_Addr_En => Wr_BRAM_Addr_En ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => Wr_CE_Failing_We ,
Sl_CE => Wr_Sl_CE ,
Sl_UE => Wr_Sl_UE ,
Active_Wr => Active_Wr ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC ,
BRAM_En => BRAM_En_A_i ,
-- BRAM_WE => BRAM_WE_A ,
-- 4/13
BRAM_WE => BRAM_WE_A_i ,
BRAM_WrData => BRAM_WrData_A ,
BRAM_RdData => BRAM_RdData_A ,
BRAM_Addr => BRAM_Addr_A_i
);
---------------------------------------------------------------------------
-- Instance: I_RD_CHNL
--
-- Description:
-- BRAM controller read channel logic. Controls all handshaking and data
-- flow on read address (AR) and read data (R) AXI channels.
--
-- BRAM signals are marked as Rd Chnl signals for future implementation
-- of merging Rd/Wr BRAM signals to a single BRAM port.
--
---------------------------------------------------------------------------
I_RD_CHNL : entity work.rd_chnl
generic map (
-- C_FAMILY => C_FAMILY ,
C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH ,
C_ECC_TYPE => C_ECC_TYPE -- v1.03a
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
AXI_ARID => S_AXI_ARID ,
AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_ARLEN => S_AXI_ARLEN ,
AXI_ARSIZE => S_AXI_ARSIZE ,
AXI_ARBURST => S_AXI_ARBURST ,
AXI_ARLOCK => S_AXI_ARLOCK ,
AXI_ARCACHE => S_AXI_ARCACHE ,
AXI_ARPROT => S_AXI_ARPROT ,
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY_i ,
AXI_RID => S_AXI_RID ,
AXI_RDATA => S_AXI_RDATA ,
AXI_RRESP => S_AXI_RRESP ,
AXI_RLAST => S_AXI_RLAST ,
AXI_RVALID => S_AXI_RVALID ,
AXI_RREADY => S_AXI_RREADY ,
-- Arb Ports
Arb2AR_Active => Arb2AR_Active ,
AR2Arb_Active_Clr => AR2Arb_Active_Clr ,
Sng_BRAM_Addr_Ld_En => RdChnl_BRAM_Addr_Ld_En ,
Sng_BRAM_Addr_Ld => RdChnl_BRAM_Addr_Ld ,
Sng_BRAM_Addr_Inc => RdChnl_BRAM_Addr_Inc ,
Sng_BRAM_Addr => bram_addr_int ,
-- ECC Ports
Enable_ECC => Enable_ECC ,
BRAM_Addr_En => Rd_BRAM_Addr_En ,
CE_Failing_We => Rd_CE_Failing_We ,
Sl_CE => Rd_Sl_CE ,
Sl_UE => Rd_Sl_UE ,
BRAM_En => BRAM_En_B_i ,
BRAM_Addr => BRAM_Addr_B_i ,
BRAM_RdData => BRAM_RdData_i
);
end architecture implementation;
-------------------------------------------------------------------------------
-- axi_bram_ctrl_top.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_bram_ctrl_top.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller IP core.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl_top.vhd (v4_0)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- ecc_gen.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/9/2011 v1.03a
-- ~~~~~~
-- Update Create_Size_Default function to support 512 & 1024-bit BRAM.
-- Replace usage of Create_Size_Default function.
-- ^^^^^^
-- JLJ 2/15/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter on full_axi module.
-- Update ECC signal sizes for 128-bit support.
-- ^^^^^^
-- JLJ 2/16/2011 v1.03a
-- ~~~~~~
-- Update WE size based on 128-bit ECC configuration.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Add C_ECC_TYPE top level parameter on axi_lite module.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Set C_ECC_TYPE = 1 for Hsiao DV regressions.
-- ^^^^^^
-- JLJ 2/24/2011 v1.03a
-- ~~~~~~
-- Move Find_ECC_Size function to package.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove C_FAMILY from top level.
-- Remove C_FAMILY in axi_lite sub module.
-- ^^^^^^
-- JLJ 6/23/2011 v1.03a
-- ~~~~~~
-- Migrate 9-bit ECC to 16-bit ECC for 128-bit BRAM data width.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
library work;
use work.axi_lite;
use work.full_axi;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity axi_bram_ctrl_top is
generic (
-- AXI Parameters
C_BRAM_ADDR_WIDTH : integer := 12;
-- Width of AXI address bus (in bits)
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1;
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_TYPE : integer := 1;
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE : integer := 1
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
-- Reserved parameters for future implementations.
-- C_ENABLE_AXI_CTRL_REG_IF : integer := 1;
-- By default the ECC AXI-Lite register interface is enabled
-- C_CE_FAILING_REGISTERS : integer := 1;
-- Enable CE (correctable error) failing registers
-- C_UE_FAILING_REGISTERS : integer := 1;
-- Enable UE (uncorrectable error) failing registers
-- C_ECC_STATUS_REGISTERS : integer := 1;
-- Enable ECC status registers
-- C_ECC_ONOFF_REGISTER : integer := 1;
-- Enable ECC on/off control register
-- C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- AXI Write Address Channel Signals (AW)
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
-- AXI Write Data Channel Signals (W)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
-- AXI Write Data Response Channel Signals (B)
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
-- AXI Read Address Channel Signals (AR)
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI-Lite ECC Register Interface Signals
-- AXI-Lite Clock and Reset
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_ACLK : in std_logic;
-- S_AXI_CTRL_ARESETN : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- BRAM Interface Signals (Port A)
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-- BRAM Interface Signals (Port B)
BRAM_Rst_B : out std_logic;
BRAM_Clk_B : out std_logic;
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0)
);
end entity axi_bram_ctrl_top;
-------------------------------------------------------------------------------
architecture implementation of axi_bram_ctrl_top is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Model behavior of AXI Interconnect in simulation for wrapping of ID values.
constant C_SIM_ONLY : std_logic := '1';
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- Create top level constant to assign fixed value to ARSIZE and AWSIZE
-- when narrow bursting is parameterized out of the IP core instantiation.
-- constant AXI_FIXED_SIZE_WO_NARROW : std_logic_vector (2 downto 0) := Create_Size_Default;
-- v1.03a
constant AXI_FIXED_SIZE_WO_NARROW : integer := log2 (C_S_AXI_DATA_WIDTH/8);
-- Only instantiate logic based on C_S_AXI_PROTOCOL.
constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4"));
constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE"));
-- Determine external ECC width.
-- Use function defined in axi_bram_ctrl_funcs package.
constant C_ECC_WIDTH : integer := Find_ECC_Size (C_ECC, C_S_AXI_DATA_WIDTH);
constant C_ECC_FULL_BIT_WIDTH : integer := Find_ECC_Full_Bit_Size (C_ECC, C_S_AXI_DATA_WIDTH);
-- Set internal parameters for ECC register enabling when C_ECC = 1
constant C_ENABLE_AXI_CTRL_REG_IF_I : integer := C_ECC;
constant C_CE_FAILING_REGISTERS_I : integer := C_ECC;
constant C_UE_FAILING_REGISTERS_I : integer := 0; -- Remove all UE registers
-- Catastrophic error indicated with ECC_UE & Interrupt flags.
constant C_ECC_STATUS_REGISTERS_I : integer := C_ECC;
constant C_ECC_ONOFF_REGISTER_I : integer := C_ECC;
constant C_CE_COUNTER_WIDTH : integer := 8 * C_ECC;
-- Counter only sized when C_ECC = 1.
-- Selects CE counter width/threshold to assert ECC_Interrupt
-- Hard coded at 8-bits to capture and count up to 256 correctable errors.
--constant C_ECC_TYPE : integer := 1; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-- Internal BRAM Signals
-- Port A
signal bram_en_a_int : std_logic := '0';
signal bram_we_a_int : std_logic_vector (((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto 0) := (others => '0');
signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
signal bram_rddata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
-- Port B
signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal bram_en_b_int : std_logic := '0';
signal bram_we_b_int : std_logic_vector (((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto 0) := (others => '0');
signal bram_wrdata_b_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
signal bram_rddata_b_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
signal axi_awsize_int : std_logic_vector(2 downto 0) := (others => '0');
signal axi_arsize_int : std_logic_vector(2 downto 0) := (others => '0');
signal S_AXI_ARREADY_int : std_logic := '0';
signal S_AXI_AWREADY_int : std_logic := '0';
signal S_AXI_RID_int : std_logic_vector (C_S_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal S_AXI_BID_int : std_logic_vector (C_S_AXI_ID_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
-- *** BRAM Port A Output Signals ***
BRAM_Rst_A <= not (S_AXI_ARESETN);
BRAM_Clk_A <= S_AXI_ACLK;
BRAM_En_A <= bram_en_a_int;
BRAM_WE_A ((((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH)/8) - 1) downto (C_ECC_FULL_BIT_WIDTH/8)) <= bram_we_a_int((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
BRAM_Addr_A <= bram_addr_a_int;
bram_rddata_a_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH));
BRAM_WrData_A ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Added for 13.3
-- Drive unused upper ECC bits to '0'
-- For bram_block compatibility, must drive unused upper bits to '0' for ECC 128-bit use case.
GEN_128_ECC_WR: if (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1) generate
begin
BRAM_WrData_A ((C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_WIDTH)) <= (others => '0');
BRAM_WrData_A ((C_ECC_WIDTH-1) downto 0) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
BRAM_WE_A ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_a_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8));
bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_A ((C_ECC_WIDTH-1) downto 0);
end generate GEN_128_ECC_WR;
GEN_ECC_WR: if ( not (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1)) generate
begin
BRAM_WrData_A ((C_ECC_WIDTH - 1) downto 0) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
BRAM_WE_A ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_a_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8));
bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_A ((C_ECC_WIDTH-1) downto 0);
end generate GEN_ECC_WR;
-- *** BRAM Port B Output Signals ***
GEN_PORT_B: if (C_SINGLE_PORT_BRAM = 0) generate
begin
BRAM_Rst_B <= not (S_AXI_ARESETN);
BRAM_WE_B ((((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH)/8) - 1) downto (C_ECC_FULL_BIT_WIDTH/8)) <= bram_we_b_int((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
BRAM_Addr_B <= bram_addr_b_int;
BRAM_En_B <= bram_en_b_int;
bram_rddata_b_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH));
BRAM_WrData_B ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH-1 downto 0);
-- 13.3
-- BRAM_WrData_B <= bram_wrdata_b_int;
-- Added for 13.3
-- Drive unused upper ECC bits to '0'
-- For bram_block compatibility, must drive unused upper bits to '0' for ECC 128-bit use case.
GEN_128_ECC_WR: if (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1) generate
begin
BRAM_WrData_B ((C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_WIDTH)) <= (others => '0');
BRAM_WrData_B ((C_ECC_WIDTH-1) downto 0) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
BRAM_WE_B ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_b_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8));
bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_B ((C_ECC_WIDTH-1) downto 0);
end generate GEN_128_ECC_WR;
GEN_ECC_WR: if ( not (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1)) generate
begin
BRAM_WrData_B ((C_ECC_WIDTH - 1) downto 0) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
BRAM_WE_B ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_b_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8));
bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_B ((C_ECC_WIDTH-1) downto 0);
end generate GEN_ECC_WR;
end generate GEN_PORT_B;
GEN_NO_PORT_B: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_Rst_B <= '0';
BRAM_WE_B <= (others => '0');
BRAM_WrData_B <= (others => '0');
BRAM_Addr_B <= (others => '0');
BRAM_En_B <= '0';
end generate GEN_NO_PORT_B;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRAM_CLK_B
-- Purpose: Only drive BRAM_Clk_B when dual port BRAM is enabled.
--
---------------------------------------------------------------------------
GEN_BRAM_CLK_B: if (C_SINGLE_PORT_BRAM = 0) generate
begin
BRAM_Clk_B <= S_AXI_ACLK;
end generate GEN_BRAM_CLK_B;
---------------------------------------------------------------------------
--
-- Generate: GEN_NO_BRAM_CLK_B
-- Purpose: Drive default value for BRAM_Clk_B when single port
-- BRAM is enabled and no clock is necessary on the inactive
-- BRAM port.
--
---------------------------------------------------------------------------
GEN_NO_BRAM_CLK_B: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_Clk_B <= '0';
end generate GEN_NO_BRAM_CLK_B;
---------------------------------------------------------------------------
-- Generate top level ARSIZE and AWSIZE signals for rd_chnl and wr_chnl
-- respectively, based on design parameter setting of generic,
-- C_S_AXI_SUPPORTS_NARROW_BURST.
---------------------------------------------------------------------------
--
-- Generate: GEN_W_NARROW
-- Purpose: Create internal AWSIZE and ARSIZE signal for write and
-- read channel modules based on top level AXI signal inputs.
--
---------------------------------------------------------------------------
GEN_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW_BURST = 1) and (IF_IS_AXI4) generate
begin
axi_awsize_int <= S_AXI_AWSIZE;
axi_arsize_int <= S_AXI_ARSIZE;
end generate GEN_W_NARROW;
---------------------------------------------------------------------------
--
-- Generate: GEN_WO_NARROW
-- Purpose: Create internal AWSIZE and ARSIZE signal for write and
-- read channel modules based on hard coded
-- value that indicates all AXI transfers will be equal in
-- size to the AXI data bus.
--
---------------------------------------------------------------------------
GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW_BURST = 0) or (IF_IS_AXI4LITE) generate
begin
-- axi_awsize_int <= AXI_FIXED_SIZE_WO_NARROW; -- When AXI-LITE (no narrow transfers supported)
-- axi_arsize_int <= AXI_FIXED_SIZE_WO_NARROW;
-- v1.03a
axi_awsize_int <= std_logic_vector (to_unsigned (AXI_FIXED_SIZE_WO_NARROW, 3));
axi_arsize_int <= std_logic_vector (to_unsigned (AXI_FIXED_SIZE_WO_NARROW, 3));
end generate GEN_WO_NARROW;
S_AXI_ARREADY <= S_AXI_ARREADY_int;
S_AXI_AWREADY <= S_AXI_AWREADY_int;
---------------------------------------------------------------------------
--
-- Generate: GEN_AXI_LITE
-- Purpose: Create internal signals for lower level write and read
-- channel modules to discard unused AXI signals when the
-- AXI protocol is set up for AXI-LITE.
--
---------------------------------------------------------------------------
GEN_AXI4LITE: if (IF_IS_AXI4LITE) generate
begin
-- For simulation purposes ONLY
-- AXI Interconnect handles this in real system topologies.
S_AXI_BID <= S_AXI_BID_int;
S_AXI_RID <= S_AXI_RID_int;
-----------------------------------------------------------------------
--
-- Generate: GEN_SIM_ONLY
-- Purpose: Mimic behavior of AXI Interconnect in simulation.
-- In real hardware system, AXI Interconnect stores and
-- wraps value of ARID to RID and AWID to BID.
--
-----------------------------------------------------------------------
GEN_SIM_ONLY: if (C_SIM_ONLY = '1') generate
begin
-------------------------------------------------------------------
-- Must register and wrap the AWID signal
REG_BID: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = C_RESET_ACTIVE) then
S_AXI_BID_int <= (others => '0');
elsif (S_AXI_AWVALID = '1') and (S_AXI_AWREADY_int = '1') then
S_AXI_BID_int <= S_AXI_AWID;
else
S_AXI_BID_int <= S_AXI_BID_int;
end if;
end if;
end process REG_BID;
-------------------------------------------------------------------
-- Must register and wrap the ARID signal
REG_RID: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = C_RESET_ACTIVE) then
S_AXI_RID_int <= (others => '0');
elsif (S_AXI_ARVALID = '1') and (S_AXI_ARREADY_int = '1') then
S_AXI_RID_int <= S_AXI_ARID;
else
S_AXI_RID_int <= S_AXI_RID_int;
end if;
end if;
end process REG_RID;
-------------------------------------------------------------------
end generate GEN_SIM_ONLY;
---------------------------------------------------------------------------
--
-- Generate: GEN_HW
-- Purpose: Drive default values of RID and BID. In real system
-- these are left unconnected and AXI Interconnect is
-- responsible for values.
--
---------------------------------------------------------------------------
GEN_HW: if (C_SIM_ONLY = '0') generate
begin
S_AXI_BID_int <= (others => '0');
S_AXI_RID_int <= (others => '0');
end generate GEN_HW;
---------------------------------------------------------------------------
-- Instance: I_AXI_LITE
--
-- Description:
-- This module is for the AXI-Lite
-- instantiation of the BRAM controller interface.
--
-- Responsible for shared address pipelining between the
-- write address (AW) and read address (AR) channels.
-- Controls (seperately) the data flows for the write data
-- (W), write response (B), and read data (R) channels.
--
-- Creates a shared port to BRAM (for all read and write
-- transactions) or dual BRAM port utilization based on a
-- generic parameter setting.
--
-- Instantiates ECC register block if enabled and
-- generates ECC logic, when enabled.
--
--
---------------------------------------------------------------------------
I_AXI_LITE : entity work.axi_lite
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
-- C_FAMILY => C_FAMILY ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC => C_ECC ,
C_ECC_TYPE => C_ECC_TYPE , -- v1.03a
C_ECC_WIDTH => C_ECC_WIDTH , -- 8-bits for ECC (32 & 64-bit data widths)
C_ENABLE_AXI_CTRL_REG_IF => C_ENABLE_AXI_CTRL_REG_IF_I , -- Use internal constants determined by C_ECC
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS_I ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS_I ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS_I ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER_I ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
ECC_Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
AXI_AWADDR => S_AXI_AWADDR ,
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY_int ,
AXI_WDATA => S_AXI_WDATA ,
AXI_WSTRB => S_AXI_WSTRB ,
AXI_WVALID => S_AXI_WVALID ,
AXI_WREADY => S_AXI_WREADY ,
AXI_BRESP => S_AXI_BRESP ,
AXI_BVALID => S_AXI_BVALID ,
AXI_BREADY => S_AXI_BREADY ,
AXI_ARADDR => S_AXI_ARADDR ,
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY_int ,
AXI_RDATA => S_AXI_RDATA ,
AXI_RRESP => S_AXI_RRESP ,
AXI_RLAST => S_AXI_RLAST ,
AXI_RVALID => S_AXI_RVALID ,
AXI_RREADY => S_AXI_RREADY ,
-- Add AXI-Lite ECC Register Ports
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK ,
-- S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN ,
AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
BRAM_En_A => bram_en_a_int ,
BRAM_WE_A => bram_we_a_int ,
BRAM_Addr_A => bram_addr_a_int ,
BRAM_WrData_A => bram_wrdata_a_int ,
BRAM_RdData_A => bram_rddata_a_int ,
BRAM_En_B => bram_en_b_int ,
BRAM_WE_B => bram_we_b_int ,
BRAM_Addr_B => bram_addr_b_int ,
BRAM_WrData_B => bram_wrdata_b_int ,
BRAM_RdData_B => bram_rddata_b_int
);
end generate GEN_AXI4LITE;
---------------------------------------------------------------------------
--
-- Generate: GEN_AXI
-- Purpose: Only create internal signals for lower level write and read
-- channel modules to assign AXI signals when the
-- AXI protocol is set up for non AXI-LITE IF connections.
-- For AXI4, all AXI signals are assigned to lower level modules.
--
-- For AXI-Lite connections, generate statement above will
-- create default values on these signals (assigned here).
--
---------------------------------------------------------------------------
GEN_AXI4: if (IF_IS_AXI4) generate
begin
---------------------------------------------------------------------------
-- Instance: I_FULL_AXI
--
-- Description:
-- Full AXI BRAM controller logic.
-- Instantiates wr_chnl and rd_chnl modules.
-- If enabled, ECC register interface is included.
--
---------------------------------------------------------------------------
I_FULL_AXI : entity work.full_axi
generic map (
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH , -- 8-bits for ECC (32 & 64-bit data widths)
C_ECC_TYPE => C_ECC_TYPE , -- v1.03a
C_FAULT_INJECT => C_FAULT_INJECT ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_ENABLE_AXI_CTRL_REG_IF => C_ENABLE_AXI_CTRL_REG_IF_I , -- Use internal constants determined by C_ECC
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS_I ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS_I ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS_I ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER_I ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
ECC_Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
S_AXI_AWID => S_AXI_AWID ,
S_AXI_AWADDR => S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH-1 downto 0),
S_AXI_AWLEN => S_AXI_AWLEN ,
S_AXI_AWSIZE => axi_awsize_int ,
S_AXI_AWBURST => S_AXI_AWBURST ,
S_AXI_AWLOCK => S_AXI_AWLOCK ,
S_AXI_AWCACHE => S_AXI_AWCACHE ,
S_AXI_AWPROT => S_AXI_AWPROT ,
S_AXI_AWVALID => S_AXI_AWVALID ,
S_AXI_AWREADY => S_AXI_AWREADY_int ,
S_AXI_WDATA => S_AXI_WDATA ,
S_AXI_WSTRB => S_AXI_WSTRB ,
S_AXI_WLAST => S_AXI_WLAST ,
S_AXI_WVALID => S_AXI_WVALID ,
S_AXI_WREADY => S_AXI_WREADY ,
S_AXI_BID => S_AXI_BID ,
S_AXI_BRESP => S_AXI_BRESP ,
S_AXI_BVALID => S_AXI_BVALID ,
S_AXI_BREADY => S_AXI_BREADY ,
S_AXI_ARID => S_AXI_ARID ,
S_AXI_ARADDR => S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH-1 downto 0),
S_AXI_ARLEN => S_AXI_ARLEN ,
S_AXI_ARSIZE => axi_arsize_int ,
S_AXI_ARBURST => S_AXI_ARBURST ,
S_AXI_ARLOCK => S_AXI_ARLOCK ,
S_AXI_ARCACHE => S_AXI_ARCACHE ,
S_AXI_ARPROT => S_AXI_ARPROT ,
S_AXI_ARVALID => S_AXI_ARVALID ,
S_AXI_ARREADY => S_AXI_ARREADY_int ,
S_AXI_RID => S_AXI_RID ,
S_AXI_RDATA => S_AXI_RDATA ,
S_AXI_RRESP => S_AXI_RRESP ,
S_AXI_RLAST => S_AXI_RLAST ,
S_AXI_RVALID => S_AXI_RVALID ,
S_AXI_RREADY => S_AXI_RREADY ,
-- Add AXI-Lite ECC Register Ports
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK ,
-- S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN ,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
BRAM_En_A => bram_en_a_int ,
BRAM_WE_A => bram_we_a_int ,
BRAM_WrData_A => bram_wrdata_a_int ,
BRAM_Addr_A => bram_addr_a_int ,
BRAM_RdData_A => bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) ,
BRAM_En_B => bram_en_b_int ,
BRAM_WE_B => bram_we_b_int ,
BRAM_Addr_B => bram_addr_b_int ,
BRAM_WrData_B => bram_wrdata_b_int ,
BRAM_RdData_B => bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
);
-- v1.02a
-- Seperate instantiations for wr_chnl and rd_chnl moved to
-- full_axi module.
end generate GEN_AXI4;
end architecture implementation;
-------------------------------------------------------------------------------
-- axi_bram_ctrl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_bram_ctrl_wrapper.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller IP core.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v4_0)
-- |
-- |--axi_bram_ctrl_top.vhd
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- ecc_gen.vhd
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_top;
use work.axi_bram_ctrl_funcs.all;
--use work.coregen_comp_defs.all;
library blk_mem_gen_v8_3_6;
use blk_mem_gen_v8_3_6.all;
------------------------------------------------------------------------------
entity axi_bram_ctrl is
generic (
C_BRAM_INST_MODE : string := "EXTERNAL"; -- external ; internal
--determines whether the bmg is external or internal to axi bram ctrl wrapper
C_MEMORY_DEPTH : integer := 4096;
--Memory depth specified by the user
C_BRAM_ADDR_WIDTH : integer := 12;
-- Width of AXI address bus (in bits)
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1;
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
C_FAMILY : string := "virtex7";
-- Specify the target architecture type
C_SELECT_XPM : integer := 1;
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_TYPE : integer := 1;
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE : integer := 1
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
ecc_interrupt : out std_logic := '0';
ecc_ue : out std_logic := '0';
-- axi write address channel Signals (AW)
s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awlock : in std_logic;
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- axi write data channel Signals (W)
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- axi write data response Channel Signals (B)
s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- axi read address channel Signals (AR)
s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arlock : in std_logic;
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- axi read data channel Signals (R)
s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- axi-lite ecc register Interface Signals
-- axi-lite clock and Reset
-- note: axi-lite control IF and AXI IF share the same clock.
-- s_axi_ctrl_aclk : in std_logic;
-- s_axi_ctrl_aresetn : in std_logic;
-- axi-lite write address Channel Signals (AW)
s_axi_ctrl_awvalid : in std_logic;
s_axi_ctrl_awready : out std_logic;
s_axi_ctrl_awaddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- axi-lite write data Channel Signals (W)
s_axi_ctrl_wdata : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_ctrl_wvalid : in std_logic;
s_axi_ctrl_wready : out std_logic;
-- axi-lite write data Response Channel Signals (B)
s_axi_ctrl_bresp : out std_logic_vector(1 downto 0);
s_axi_ctrl_bvalid : out std_logic;
s_axi_ctrl_bready : in std_logic;
-- axi-lite read address Channel Signals (AR)
s_axi_ctrl_araddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
s_axi_ctrl_arvalid : in std_logic;
s_axi_ctrl_arready : out std_logic;
-- axi-lite read data Channel Signals (R)
s_axi_ctrl_rdata : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_ctrl_rresp : out std_logic_vector(1 downto 0);
s_axi_ctrl_rvalid : out std_logic;
s_axi_ctrl_rready : in std_logic;
-- bram interface signals (Port A)
bram_rst_a : out std_logic;
bram_clk_a : out std_logic;
bram_en_a : out std_logic;
bram_we_a : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_addr_a : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
bram_wrdata_a : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_rddata_a : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-- bram interface signals (Port B)
bram_rst_b : out std_logic;
bram_clk_b : out std_logic;
bram_en_b : out std_logic;
bram_we_b : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_addr_b : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
bram_wrdata_b : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_rddata_b : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0)
);
end entity axi_bram_ctrl;
-------------------------------------------------------------------------------
architecture implementation of axi_bram_ctrl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
component xpm_memory_tdpram
generic (
MEMORY_SIZE : integer := 4096*32;
MEMORY_PRIMITIVE : string := "auto";
CLOCKING_MODE : string := "common_clock";
ECC_MODE : string := "no_ecc";
MEMORY_INIT_FILE : string := "none";
MEMORY_INIT_PARAM : string := "";
WAKEUP_TIME : string := "disable_sleep";
MESSAGE_CONTROL : integer := 0;
WRITE_DATA_WIDTH_A : integer := 32;
READ_DATA_WIDTH_A : integer := 32;
BYTE_WRITE_WIDTH_A : integer := 8;
ADDR_WIDTH_A : integer := 12;
READ_RESET_VALUE_A : string := "0";
READ_LATENCY_A : integer := 1;
WRITE_MODE_A : string := "read_first";
WRITE_DATA_WIDTH_B : integer := 32;
READ_DATA_WIDTH_B : integer := 32;
BYTE_WRITE_WIDTH_B : integer := 8;
ADDR_WIDTH_B : integer := 12;
READ_RESET_VALUE_B : string := "0";
READ_LATENCY_B : integer := 1;
WRITE_MODE_B : string := "read_first"
);
port (
-- Common module ports
sleep : in std_logic;
-- Port A module ports
clka : in std_logic;
rsta : in std_logic;
ena : in std_logic;
regcea : in std_logic;
wea : in std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); -- (WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A)-1:0]
-- addra : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
addra : in std_logic_vector (C_BRAM_ADDR_WIDTH-1 downto 0) := (others => '0');
dina : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); -- [WRITE_DATA_WIDTH_A-1:0]
injectsbiterra : in std_logic;
injectdbiterra : in std_logic;
douta : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- [READ_DATA_WIDTH_A-1:0]
sbiterra : out std_logic;
dbiterra : out std_logic;
-- Port B module ports
clkb : in std_logic;
rstb : in std_logic;
enb : in std_logic;
regceb : in std_logic;
web : in std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
-- addrb : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); -- [ADDR_WIDTH_B-1:0]
addrb : in std_logic_vector (C_BRAM_ADDR_WIDTH-1 downto 0) := (others => '0'); -- [ADDR_WIDTH_B-1:0]
dinb : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
injectsbiterrb : in std_logic;
injectdbiterrb : in std_logic;
doutb : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- [READ_DATA_WIDTH_B-1:0]
sbiterrb : out std_logic;
dbiterrb : out std_logic
);
end component;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------------------------------------------------
-- FUNCTION : log2roundup
---------------------------------------------------------------------------
FUNCTION log2roundup (data_value : integer) RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
CONSTANT lower_limit : integer := 1;
CONSTANT upper_limit : integer := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Only instantiate logic based on C_S_AXI_PROTOCOL.
-- Determine external ECC width.
-- Use function defined in axi_bram_ctrl_funcs package.
-- Set internal parameters for ECC register enabling when C_ECC = 1
-- Catastrophic error indicated with ECC_UE & Interrupt flags.
-- Counter only sized when C_ECC = 1.
-- Selects CE counter width/threshold to assert ECC_Interrupt
-- Hard coded at 8-bits to capture and count up to 256 correctable errors.
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
constant GND : std_logic := '0';
constant VCC : std_logic := '1';
constant ZERO1 : std_logic_vector(0 downto 0) := (others => '0');
constant ZERO2 : std_logic_vector(1 downto 0) := (others => '0');
constant ZERO3 : std_logic_vector(2 downto 0) := (others => '0');
constant ZERO4 : std_logic_vector(3 downto 0) := (others => '0');
constant ZERO8 : std_logic_vector(7 downto 0) := (others => '0');
constant WSTRB_ZERO : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
constant ZERO16 : std_logic_vector(15 downto 0) := (others => '0');
constant ZERO32 : std_logic_vector(31 downto 0) := (others => '0');
constant ZERO64 : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
CONSTANT MEM_TYPE : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,2);
CONSTANT BWE_B : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,1);
CONSTANT BMG_ADDR_WIDTH : INTEGER := log2roundup(C_MEMORY_DEPTH) + log2roundup(C_S_AXI_DATA_WIDTH/8) ;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal clka_bram_clka_i : std_logic := '0';
signal rsta_bram_rsta_i : std_logic := '0';
signal ena_bram_ena_i : std_logic := '0';
signal REGCEA : std_logic := '0';
signal wea_bram_wea_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal addra_bram_addra_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal dina_bram_dina_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal douta_bram_douta_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
signal clkb_bram_clkb_i : std_logic := '0';
signal rstb_bram_rstb_i : std_logic := '0';
signal enb_bram_enb_i : std_logic := '0';
signal REGCEB : std_logic := '0';
signal web_bram_web_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal addrb_bram_addrb_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal dinb_bram_dinb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal doutb_bram_doutb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-----------------------------------------------------------------------
-- Architecture Body
-----------------------------------------------------------------------
begin
gint_inst: IF (C_BRAM_INST_MODE = "INTERNAL" ) GENERATE
constant c_addrb_width : INTEGER := log2roundup(C_MEMORY_DEPTH);
constant C_WEA_WIDTH_I : INTEGER := (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) ;
constant C_WRITE_WIDTH_A_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ;
constant C_READ_WIDTH_A_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128)));
constant C_ADDRA_WIDTH_I : INTEGER := log2roundup(C_MEMORY_DEPTH);
constant C_WEB_WIDTH_I : INTEGER := (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128)));
constant C_WRITE_WIDTH_B_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128)));
constant C_READ_WIDTH_B_I : INTEGER := (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128)));
signal s_axi_rdaddrecc_bmg_int : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal s_axi_dbiterr_bmg_int : STD_LOGIC;
signal s_axi_sbiterr_bmg_int : STD_LOGIC;
signal s_axi_rvalid_bmg_int : STD_LOGIC;
signal s_axi_rlast_bmg_int : STD_LOGIC;
signal s_axi_rresp_bmg_int : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal s_axi_rdata_bmg_int : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
signal s_axi_rid_bmg_int : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal s_axi_arready_bmg_int : STD_LOGIC;
signal s_axi_bvalid_bmg_int : STD_LOGIC;
signal s_axi_bresp_bmg_int : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal s_axi_bid_bmg_int : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal s_axi_wready_bmg_int : STD_LOGIC;
signal s_axi_awready_bmg_int : STD_LOGIC;
signal rdaddrecc_bmg_int : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal dbiterr_bmg_int : STD_LOGIC;
signal sbiterr_bmg_int : STD_LOGIC;
begin
xpm_mem_gen : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_tdpram
generic map (
MEMORY_SIZE => C_WRITE_WIDTH_A_I*C_MEMORY_DEPTH,
MEMORY_PRIMITIVE => "blockram",
CLOCKING_MODE => "common_clock",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "none",
MEMORY_INIT_PARAM => "",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 0,
WRITE_DATA_WIDTH_A => C_WRITE_WIDTH_A_I,
READ_DATA_WIDTH_A => C_READ_WIDTH_A_I,
BYTE_WRITE_WIDTH_A => 8,
ADDR_WIDTH_A => C_ADDRA_WIDTH_I,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1,
WRITE_MODE_A => "write_first", --write_first
WRITE_DATA_WIDTH_B => C_WRITE_WIDTH_B_I,
READ_DATA_WIDTH_B => C_READ_WIDTH_B_I,
BYTE_WRITE_WIDTH_B => 8,
ADDR_WIDTH_B => C_ADDRB_WIDTH,
READ_RESET_VALUE_B => "0",
READ_LATENCY_B => 1,
WRITE_MODE_B => "write_first"
)
port map (
-- Common module ports
sleep => GND,
-- Port A module ports
clka => clka_bram_clka_i,
rsta => rsta_bram_rsta_i,
ena => ena_bram_ena_i,
regcea => GND,
wea => wea_bram_wea_i,
addra => addra_bram_addra_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)),
dina => dina_bram_dina_i,
injectsbiterra => GND,
injectdbiterra => GND,
douta => douta_bram_douta_i,
sbiterra => open,
dbiterra => open,
-- Port B module ports
clkb => clkb_bram_clkb_i,
rstb => rstb_bram_rstb_i,
enb => enb_bram_enb_i,
regceb => GND,
web => web_bram_web_i,
addrb => addrb_bram_addrb_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)),
dinb => dinb_bram_dinb_i,
injectsbiterrb => GND,
injectdbiterrb => GND,
doutb => doutb_bram_doutb_i,
sbiterrb => open,
dbiterrb => open
);
end generate;
blk_mem_gen : if (C_SELECT_XPM = 0) generate
bmgv81_inst : entity blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6
GENERIC MAP(
----------------------------------------------------------------------------
-- Generic Declarations
----------------------------------------------------------------------------
--Device Family & Elaboration Directory Parameters:
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_FAMILY,
---- C_ELABORATION_DIR => "NULL" ,
C_INTERFACE_TYPE => 0 ,
--General Memory Parameters:
----- C_ENABLE_32BIT_ADDRESS => 0 ,
C_MEM_TYPE => MEM_TYPE ,
C_BYTE_SIZE => 8 ,
C_ALGORITHM => 1 ,
C_PRIM_TYPE => 1 ,
--Memory Initialization Parameters:
C_LOAD_INIT_FILE => 0 ,
C_INIT_FILE_NAME => "no_coe_file_loaded" ,
C_USE_DEFAULT_DATA => 0 ,
C_DEFAULT_DATA => "NULL" ,
--Port A Parameters:
--Reset Parameters:
C_HAS_RSTA => 0 ,
--Enable Parameters:
C_HAS_ENA => 1 ,
C_HAS_REGCEA => 0 ,
--Byte Write Enable Parameters:
C_USE_BYTE_WEA => 1 ,
C_WEA_WIDTH => C_WEA_WIDTH_I, --(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) ,
--Write Mode:
C_WRITE_MODE_A => "WRITE_FIRST" ,
--Data-Addr Width Parameters:
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A_I,--(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_READ_WIDTH_A => C_READ_WIDTH_A_I,--(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_WRITE_DEPTH_A => C_MEMORY_DEPTH ,
C_READ_DEPTH_A => C_MEMORY_DEPTH ,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_I,--log2roundup(C_MEMORY_DEPTH) ,
--Port B Parameters:
--Reset Parameters:
C_HAS_RSTB => 0 ,
--Enable Parameters:
C_HAS_ENB => 1 ,
C_HAS_REGCEB => 0 ,
--Byte Write Enable Parameters:
C_USE_BYTE_WEB => BWE_B ,
C_WEB_WIDTH => C_WEB_WIDTH_I,--(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) ,
--Write Mode:
C_WRITE_MODE_B => "WRITE_FIRST" ,
--Data-Addr Width Parameters:
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B_I,--(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_READ_WIDTH_B => C_READ_WIDTH_B_I,--(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_WRITE_DEPTH_B => C_MEMORY_DEPTH ,
C_READ_DEPTH_B => C_MEMORY_DEPTH ,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,--log2roundup(C_MEMORY_DEPTH) ,
--Output Registers/ Pipelining Parameters:
C_HAS_MEM_OUTPUT_REGS_A => 0 ,
C_HAS_MEM_OUTPUT_REGS_B => 0 ,
C_HAS_MUX_OUTPUT_REGS_A => 0 ,
C_HAS_MUX_OUTPUT_REGS_B => 0 ,
C_MUX_PIPELINE_STAGES => 0 ,
--Input/Output Registers for SoftECC :
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B=> 0 ,
--ECC Parameters
C_USE_ECC => 0 ,
C_USE_SOFTECC => 0 ,
C_HAS_INJECTERR => 0 ,
C_EN_ECC_PIPE => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
--Simulation Model Parameters:
C_SIM_COLLISION_CHECK => "NONE" ,
C_COMMON_CLK => 1 ,
C_DISABLE_WARN_BHV_COLL => 1 ,
C_DISABLE_WARN_BHV_RANGE => 1
)
PORT MAP(
----------------------------------------------------------------------------
-- Input and Output Declarations
----------------------------------------------------------------------------
-- Native BMG Input and Output Port Declarations
--Port A:
clka => clka_bram_clka_i ,
rsta => rsta_bram_rsta_i ,
ena => ena_bram_ena_i ,
regcea => GND ,
wea => wea_bram_wea_i ,
addra => addra_bram_addra_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
--addra => addra_bram_addra_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
dina => dina_bram_dina_i ,
douta => douta_bram_douta_i ,
--port b:
clkb => clkb_bram_clkb_i ,
rstb => rstb_bram_rstb_i ,
enb => enb_bram_enb_i ,
regceb => GND ,
web => web_bram_web_i ,
addrb => addrb_bram_addrb_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
--addrb => addrb_bram_addrb_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
dinb => dinb_bram_dinb_i ,
doutb => doutb_bram_doutb_i ,
--ecc:
injectsbiterr => GND ,
injectdbiterr => GND ,
sbiterr => sbiterr_bmg_int,
dbiterr => dbiterr_bmg_int,
rdaddrecc => rdaddrecc_bmg_int,
eccpipece => GND,
sleep => GND,
deepsleep => GND,
shutdown => GND,
-- axi bmg input and output Port Declarations
-- axi global signals
s_aclk => GND ,
s_aresetn => GND ,
-- axi full/lite slave write (write side)
s_axi_awid => ZERO4 ,
s_axi_awaddr => ZERO32 ,
s_axi_awlen => ZERO8 ,
s_axi_awsize => ZERO3 ,
s_axi_awburst => ZERO2 ,
s_axi_awvalid => GND ,
s_axi_awready => s_axi_awready_bmg_int,
s_axi_wdata => ZERO64 ,
s_axi_wstrb => WSTRB_ZERO,
s_axi_wlast => GND ,
s_axi_wvalid => GND ,
s_axi_wready => s_axi_wready_bmg_int,
s_axi_bid => s_axi_bid_bmg_int,
s_axi_bresp => s_axi_bresp_bmg_int,
s_axi_bvalid => s_axi_bvalid_bmg_int,
s_axi_bready => GND ,
-- axi full/lite slave read (Write side)
s_axi_arid => ZERO4,
s_axi_araddr => "00000000000000000000000000000000",
s_axi_arlen => "00000000",
s_axi_arsize => "000",
s_axi_arburst => "00",
s_axi_arvalid => '0',
s_axi_arready => s_axi_arready_bmg_int,
s_axi_rid => s_axi_rid_bmg_int,
s_axi_rdata => s_axi_rdata_bmg_int,
s_axi_rresp => s_axi_rresp_bmg_int,
s_axi_rlast => s_axi_rlast_bmg_int,
s_axi_rvalid => s_axi_rvalid_bmg_int,
s_axi_rready => GND ,
-- axi full/lite sideband Signals
s_axi_injectsbiterr => GND ,
s_axi_injectdbiterr => GND ,
s_axi_sbiterr => s_axi_sbiterr_bmg_int,
s_axi_dbiterr => s_axi_dbiterr_bmg_int,
s_axi_rdaddrecc => s_axi_rdaddrecc_bmg_int
);
end generate;
abcv4_0_int_inst : entity work.axi_bram_ctrl_top
generic map(
-- AXI Parameters
C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
-- AXI ID vector width
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST ,
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
-- Enable single port usage of BRAM
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC => C_ECC ,
-- Enables or disables ECC functionality
C_ECC_TYPE => C_ECC_TYPE ,
C_FAULT_INJECT => C_FAULT_INJECT ,
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
)
port map(
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK => S_AXI_ACLK ,
S_AXI_ARESETN => S_AXI_ARESETN ,
ECC_Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
-- AXI Write Address Channel Signals (AW)
S_AXI_AWID => S_AXI_AWID ,
S_AXI_AWADDR => S_AXI_AWADDR ,
S_AXI_AWLEN => S_AXI_AWLEN ,
S_AXI_AWSIZE => S_AXI_AWSIZE ,
S_AXI_AWBURST => S_AXI_AWBURST ,
S_AXI_AWLOCK => S_AXI_AWLOCK ,
S_AXI_AWCACHE => S_AXI_AWCACHE ,
S_AXI_AWPROT => S_AXI_AWPROT ,
S_AXI_AWVALID => S_AXI_AWVALID ,
S_AXI_AWREADY => S_AXI_AWREADY ,
-- AXI Write Data Channel Signals (W)
S_AXI_WDATA => S_AXI_WDATA ,
S_AXI_WSTRB => S_AXI_WSTRB ,
S_AXI_WLAST => S_AXI_WLAST ,
S_AXI_WVALID => S_AXI_WVALID ,
S_AXI_WREADY => S_AXI_WREADY ,
-- AXI Write Data Response Channel Signals (B)
S_AXI_BID => S_AXI_BID ,
S_AXI_BRESP => S_AXI_BRESP ,
S_AXI_BVALID => S_AXI_BVALID ,
S_AXI_BREADY => S_AXI_BREADY ,
-- AXI Read Address Channel Signals (AR)
S_AXI_ARID => S_AXI_ARID ,
S_AXI_ARADDR => S_AXI_ARADDR ,
S_AXI_ARLEN => S_AXI_ARLEN ,
S_AXI_ARSIZE => S_AXI_ARSIZE ,
S_AXI_ARBURST => S_AXI_ARBURST ,
S_AXI_ARLOCK => S_AXI_ARLOCK ,
S_AXI_ARCACHE => S_AXI_ARCACHE ,
S_AXI_ARPROT => S_AXI_ARPROT ,
S_AXI_ARVALID => S_AXI_ARVALID ,
S_AXI_ARREADY => S_AXI_ARREADY ,
-- AXI Read Data Channel Signals (R)
S_AXI_RID => S_AXI_RID ,
S_AXI_RDATA => S_AXI_RDATA ,
S_AXI_RRESP => S_AXI_RRESP ,
S_AXI_RLAST => S_AXI_RLAST ,
S_AXI_RVALID => S_AXI_RVALID ,
S_AXI_RREADY => S_AXI_RREADY ,
-- AXI-Lite ECC Register Interface Signals
-- AXI-Lite Write Address Channel Signals (AW)
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
-- AXI-Lite Write Data Channel Signals (W)
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
-- AXI-Lite Write Data Response Channel Signals (B)
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
-- AXI-Lite Read Address Channel Signals (AR)
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
-- AXI-Lite Read Data Channel Signals (R)
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
-- BRAM Interface Signals (Port A)
BRAM_Rst_A => rsta_bram_rsta_i ,
BRAM_Clk_A => clka_bram_clka_i ,
BRAM_En_A => ena_bram_ena_i ,
BRAM_WE_A => wea_bram_wea_i ,
BRAM_Addr_A => addra_bram_addra_i,
BRAM_WrData_A => dina_bram_dina_i ,
BRAM_RdData_A => douta_bram_douta_i ,
-- BRAM Interface Signals (Port B)
BRAM_Rst_B => rstb_bram_rstb_i ,
BRAM_Clk_B => clkb_bram_clkb_i ,
BRAM_En_B => enb_bram_enb_i ,
BRAM_WE_B => web_bram_web_i ,
BRAM_Addr_B => addrb_bram_addrb_i ,
BRAM_WrData_B => dinb_bram_dinb_i ,
BRAM_RdData_B => doutb_bram_doutb_i
);
-- The following signals are driven 0's to remove the synthesis warnings
bram_rst_a <= '0';
bram_clk_a <= '0';
bram_en_a <= '0';
bram_we_a <= (others => '0');
bram_addr_a <= (others => '0');
bram_wrdata_a <= (others => '0');
bram_rst_b <= '0';
bram_clk_b <= '0';
bram_en_b <= '0';
bram_we_b <= (others => '0');
bram_addr_b <= (others => '0');
bram_wrdata_b <= (others => '0');
END GENERATE gint_inst; -- End of internal bram instance
gext_inst: IF (C_BRAM_INST_MODE = "EXTERNAL" ) GENERATE
abcv4_0_ext_inst : entity work.axi_bram_ctrl_top
generic map(
-- AXI Parameters
C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
-- AXI ID vector width
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST ,
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
-- Enable single port usage of BRAM
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC => C_ECC ,
-- Enables or disables ECC functionality
C_ECC_TYPE => C_ECC_TYPE ,
C_FAULT_INJECT => C_FAULT_INJECT ,
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
)
port map(
-- AXI Interface Signals
-- AXI Clock and Reset
s_axi_aclk => s_axi_aclk ,
s_axi_aresetn => s_axi_aresetn ,
ecc_interrupt => ecc_interrupt ,
ecc_ue => ecc_ue ,
-- axi write address channel signals (aw)
s_axi_awid => s_axi_awid ,
s_axi_awaddr => s_axi_awaddr ,
s_axi_awlen => s_axi_awlen ,
s_axi_awsize => s_axi_awsize ,
s_axi_awburst => s_axi_awburst ,
s_axi_awlock => s_axi_awlock ,
s_axi_awcache => s_axi_awcache ,
s_axi_awprot => s_axi_awprot ,
s_axi_awvalid => s_axi_awvalid ,
s_axi_awready => s_axi_awready ,
-- axi write data channel signals (w)
s_axi_wdata => s_axi_wdata ,
s_axi_wstrb => s_axi_wstrb ,
s_axi_wlast => s_axi_wlast ,
s_axi_wvalid => s_axi_wvalid ,
s_axi_wready => s_axi_wready ,
-- axi write data response channel signals (b)
s_axi_bid => s_axi_bid ,
s_axi_bresp => s_axi_bresp ,
s_axi_bvalid => s_axi_bvalid ,
s_axi_bready => s_axi_bready ,
-- axi read address channel signals (ar)
s_axi_arid => s_axi_arid ,
s_axi_araddr => s_axi_araddr ,
s_axi_arlen => s_axi_arlen ,
s_axi_arsize => s_axi_arsize ,
s_axi_arburst => s_axi_arburst ,
s_axi_arlock => s_axi_arlock ,
s_axi_arcache => s_axi_arcache ,
s_axi_arprot => s_axi_arprot ,
s_axi_arvalid => s_axi_arvalid ,
s_axi_arready => s_axi_arready ,
-- axi read data channel signals (r)
s_axi_rid => s_axi_rid ,
s_axi_rdata => s_axi_rdata ,
s_axi_rresp => s_axi_rresp ,
s_axi_rlast => s_axi_rlast ,
s_axi_rvalid => s_axi_rvalid ,
s_axi_rready => s_axi_rready ,
-- axi-lite ecc register interface signals
-- axi-lite write address channel signals (aw)
s_axi_ctrl_awvalid => s_axi_ctrl_awvalid ,
s_axi_ctrl_awready => s_axi_ctrl_awready ,
s_axi_ctrl_awaddr => s_axi_ctrl_awaddr ,
-- axi-lite write data channel signals (w)
s_axi_ctrl_wdata => s_axi_ctrl_wdata ,
s_axi_ctrl_wvalid => s_axi_ctrl_wvalid ,
s_axi_ctrl_wready => s_axi_ctrl_wready ,
-- axi-lite write data response channel signals (b)
s_axi_ctrl_bresp => s_axi_ctrl_bresp ,
s_axi_ctrl_bvalid => s_axi_ctrl_bvalid ,
s_axi_ctrl_bready => s_axi_ctrl_bready ,
-- axi-lite read address channel signals (ar)
s_axi_ctrl_araddr => s_axi_ctrl_araddr ,
s_axi_ctrl_arvalid => s_axi_ctrl_arvalid ,
s_axi_ctrl_arready => s_axi_ctrl_arready ,
-- axi-lite read data channel signals (r)
s_axi_ctrl_rdata => s_axi_ctrl_rdata ,
s_axi_ctrl_rresp => s_axi_ctrl_rresp ,
s_axi_ctrl_rvalid => s_axi_ctrl_rvalid ,
s_axi_ctrl_rready => s_axi_ctrl_rready ,
-- bram interface signals (port a)
bram_rst_a => bram_rst_a ,
bram_clk_a => bram_clk_a ,
bram_en_a => bram_en_a ,
bram_we_a => bram_we_a ,
bram_addr_a => bram_addr_a ,
bram_wrdata_a => bram_wrdata_a ,
bram_rddata_a => bram_rddata_a ,
-- bram interface signals (port b)
bram_rst_b => bram_rst_b ,
bram_clk_b => bram_clk_b ,
bram_en_b => bram_en_b ,
bram_we_b => bram_we_b ,
bram_addr_b => bram_addr_b ,
bram_wrdata_b => bram_wrdata_b ,
bram_rddata_b => bram_rddata_b
);
END GENERATE gext_inst; -- End of internal bram instance
end architecture implementation;
| mit | 6514bb0c4e3675cea838fbea3758edcd | 0.439516 | 4.335221 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/sim/zqynq_lab_1_design_axi_bram_ctrl_0_0.vhd | 1 | 16,339 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_11;
USE axi_bram_ctrl_v4_0_11.axi_bram_ctrl;
ENTITY zqynq_lab_1_design_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zqynq_lab_1_design_axi_bram_ctrl_0_0;
ARCHITECTURE zqynq_lab_1_design_axi_bram_ctrl_0_0_arch OF zqynq_lab_1_design_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 0,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rst_b => bram_rst_b,
bram_clk_b => bram_clk_b,
bram_en_b => bram_en_b,
bram_we_b => bram_we_b,
bram_addr_b => bram_addr_b,
bram_wrdata_b => bram_wrdata_b,
bram_rddata_b => bram_rddata_b
);
END zqynq_lab_1_design_axi_bram_ctrl_0_0_arch;
| mit | 291124786d5c3399db914c1a75e2bbc9 | 0.671277 | 3.09041 | false | false | false | false |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/transmitter.vhd | 3 | 11,864 | --input 48.828125 kHz 8 bit audio
--interpolated to 2048 * 8 * 48.828125 = 800 MHz sampling rate 19-bits
--upconverted to lo
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmitter is
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
frequency_stb : in std_logic;
frequency_ack : out std_logic;
control : in std_logic_vector(31 downto 0);
control_stb : in std_logic;
control_ack : out std_logic;
amplitude : in std_logic_vector(31 downto 0);
amplitude_stb : in std_logic;
amplitude_ack : out std_logic;
rf : out std_logic;
tx_rx : out std_logic;
tx_pa : out std_logic
);
end entity transmitter;
architecture rtl of transmitter is
component interpolate is
generic(
interpolation_factor : integer;
output_width : integer;
width : integer
);
port(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(width - 1 downto 0);
input_stb : in std_logic;
input_ack : out std_logic;
output_0 : out std_logic_vector(output_width - 1 downto 0);
output_1 : out std_logic_vector(output_width - 1 downto 0);
output_2 : out std_logic_vector(output_width - 1 downto 0);
output_3 : out std_logic_vector(output_width - 1 downto 0);
output_4 : out std_logic_vector(output_width - 1 downto 0);
output_5 : out std_logic_vector(output_width - 1 downto 0);
output_6 : out std_logic_vector(output_width - 1 downto 0);
output_7 : out std_logic_vector(output_width - 1 downto 0)
);
end component interpolate;
component nco is
generic(
width : integer
);
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
lo_i_0 : out std_logic_vector(width - 1 downto 0);
lo_i_1 : out std_logic_vector(width - 1 downto 0);
lo_i_2 : out std_logic_vector(width - 1 downto 0);
lo_i_3 : out std_logic_vector(width - 1 downto 0);
lo_i_4 : out std_logic_vector(width - 1 downto 0);
lo_i_5 : out std_logic_vector(width - 1 downto 0);
lo_i_6 : out std_logic_vector(width - 1 downto 0);
lo_i_7 : out std_logic_vector(width - 1 downto 0);
lo_q_0 : out std_logic_vector(width - 1 downto 0);
lo_q_1 : out std_logic_vector(width - 1 downto 0);
lo_q_2 : out std_logic_vector(width - 1 downto 0);
lo_q_3 : out std_logic_vector(width - 1 downto 0);
lo_q_4 : out std_logic_vector(width - 1 downto 0);
lo_q_5 : out std_logic_vector(width - 1 downto 0);
lo_q_6 : out std_logic_vector(width - 1 downto 0);
lo_q_7 : out std_logic_vector(width - 1 downto 0)
);
end component nco;
component dac_interface is
generic(
width : integer
);
port(
clk : in std_logic;
rst : in std_logic;
dithering : in std_logic;
input_0 : in std_logic_vector(width - 1 downto 0);
input_1 : in std_logic_vector(width - 1 downto 0);
input_2 : in std_logic_vector(width - 1 downto 0);
input_3 : in std_logic_vector(width - 1 downto 0);
input_4 : in std_logic_vector(width - 1 downto 0);
input_5 : in std_logic_vector(width - 1 downto 0);
input_6 : in std_logic_vector(width - 1 downto 0);
input_7 : in std_logic_vector(width - 1 downto 0);
output : out std_logic
);
end component dac_interface;
signal i_full_rate_0 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_1 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_2 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_3 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_4 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_5 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_6 : std_logic_vector(23 downto 0) := (others => '0');
signal i_full_rate_7 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_0 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_1 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_2 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_3 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_4 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_5 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_6 : std_logic_vector(23 downto 0) := (others => '0');
signal q_full_rate_7 : std_logic_vector(23 downto 0) := (others => '0');
signal lo_i_0 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_1 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_2 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_3 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_4 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_5 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_6 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_i_7 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_0 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_1 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_2 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_3 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_4 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_5 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_6 : std_logic_vector(9 downto 0) := (others => '0');
signal lo_q_7 : std_logic_vector(9 downto 0) := (others => '0');
signal i_out_0 : signed(33 downto 0) := (others => '0');
signal i_out_1 : signed(33 downto 0) := (others => '0');
signal i_out_2 : signed(33 downto 0) := (others => '0');
signal i_out_3 : signed(33 downto 0) := (others => '0');
signal i_out_4 : signed(33 downto 0) := (others => '0');
signal i_out_5 : signed(33 downto 0) := (others => '0');
signal i_out_6 : signed(33 downto 0) := (others => '0');
signal i_out_7 : signed(33 downto 0) := (others => '0');
signal q_out_0 : signed(33 downto 0) := (others => '0');
signal q_out_1 : signed(33 downto 0) := (others => '0');
signal q_out_2 : signed(33 downto 0) := (others => '0');
signal q_out_3 : signed(33 downto 0) := (others => '0');
signal q_out_4 : signed(33 downto 0) := (others => '0');
signal q_out_5 : signed(33 downto 0) := (others => '0');
signal q_out_6 : signed(33 downto 0) := (others => '0');
signal q_out_7 : signed(33 downto 0) := (others => '0');
signal out_0 : std_logic_vector(31 downto 0) := (others => '0');
signal out_1 : std_logic_vector(31 downto 0) := (others => '0');
signal out_2 : std_logic_vector(31 downto 0) := (others => '0');
signal out_3 : std_logic_vector(31 downto 0) := (others => '0');
signal out_4 : std_logic_vector(31 downto 0) := (others => '0');
signal out_5 : std_logic_vector(31 downto 0) := (others => '0');
signal out_6 : std_logic_vector(31 downto 0) := (others => '0');
signal out_7 : std_logic_vector(31 downto 0) := (others => '0');
signal dithering : std_logic := '0';
signal frequency_reg : std_logic_vector(31 downto 0) := (others => '0');
begin
process
begin
wait until rising_edge(clk);
if control_stb = '1' then
dithering <= control(0);
tx_rx <= control(1);
tx_pa <= control(2);
end if;
if frequency_stb = '1' then
frequency_reg <= frequency;
end if;
end process;
control_ack <= '1';
frequency_ack <= '1';
nco_inst_1 : nco generic map(
width => 10
) port map (
clk => clk,
rst => rst,
frequency => frequency_reg,
lo_i_0 => lo_i_0,
lo_i_1 => lo_i_1,
lo_i_2 => lo_i_2,
lo_i_3 => lo_i_3,
lo_i_4 => lo_i_4,
lo_i_5 => lo_i_5,
lo_i_6 => lo_i_6,
lo_i_7 => lo_i_7,
lo_q_0 => lo_q_0,
lo_q_1 => lo_q_1,
lo_q_2 => lo_q_2,
lo_q_3 => lo_q_3,
lo_q_4 => lo_q_4,
lo_q_5 => lo_q_5,
lo_q_6 => lo_q_6,
lo_q_7 => lo_q_7
);
interpolate_inst_1 : interpolate generic map(
interpolation_factor => 8192,
output_width => 13 + 3 + 8,
width => 8
) port map (
clk => clk,
rst => rst,
input => amplitude(23 downto 16),
input_stb => amplitude_stb,
input_ack => amplitude_ack,
output_0 => i_full_rate_0,
output_1 => i_full_rate_1,
output_2 => i_full_rate_2,
output_3 => i_full_rate_3,
output_4 => i_full_rate_4,
output_5 => i_full_rate_5,
output_6 => i_full_rate_6,
output_7 => i_full_rate_7
);
interpolate_inst_2 : interpolate generic map(
interpolation_factor => 8192,
output_width => 13 + 3 + 8,
width => 8
) port map (
clk => clk,
rst => rst,
input => amplitude(7 downto 0),
input_stb => amplitude_stb,
input_ack => open,
output_0 => q_full_rate_0,
output_1 => q_full_rate_1,
output_2 => q_full_rate_2,
output_3 => q_full_rate_3,
output_4 => q_full_rate_4,
output_5 => q_full_rate_5,
output_6 => q_full_rate_6,
output_7 => q_full_rate_7
);
process
variable temp_0 : signed(34 downto 0);
variable temp_1 : signed(34 downto 0);
variable temp_2 : signed(34 downto 0);
variable temp_3 : signed(34 downto 0);
variable temp_4 : signed(34 downto 0);
variable temp_5 : signed(34 downto 0);
variable temp_6 : signed(34 downto 0);
variable temp_7 : signed(34 downto 0);
begin
wait until rising_edge(clk);
i_out_0 <= signed(i_full_rate_0) * signed(lo_i_0);
i_out_1 <= signed(i_full_rate_1) * signed(lo_i_1);
i_out_2 <= signed(i_full_rate_2) * signed(lo_i_2);
i_out_3 <= signed(i_full_rate_3) * signed(lo_i_3);
i_out_4 <= signed(i_full_rate_4) * signed(lo_i_4);
i_out_5 <= signed(i_full_rate_5) * signed(lo_i_5);
i_out_6 <= signed(i_full_rate_6) * signed(lo_i_6);
i_out_7 <= signed(i_full_rate_7) * signed(lo_i_7);
q_out_0 <= signed(q_full_rate_0) * signed(lo_q_0);
q_out_1 <= signed(q_full_rate_1) * signed(lo_q_1);
q_out_2 <= signed(q_full_rate_2) * signed(lo_q_2);
q_out_3 <= signed(q_full_rate_3) * signed(lo_q_3);
q_out_4 <= signed(q_full_rate_4) * signed(lo_q_4);
q_out_5 <= signed(q_full_rate_5) * signed(lo_q_5);
q_out_6 <= signed(q_full_rate_6) * signed(lo_q_6);
q_out_7 <= signed(q_full_rate_7) * signed(lo_q_7);
temp_0 := resize(i_out_0, 35) + q_out_0;
temp_1 := resize(i_out_1, 35) + q_out_1;
temp_2 := resize(i_out_2, 35) + q_out_2;
temp_3 := resize(i_out_3, 35) + q_out_3;
temp_4 := resize(i_out_4, 35) + q_out_4;
temp_5 := resize(i_out_5, 35) + q_out_5;
temp_6 := resize(i_out_6, 35) + q_out_6;
temp_7 := resize(i_out_7, 35) + q_out_7;
out_0 <= std_logic_vector(temp_0(32 downto 1));
out_1 <= std_logic_vector(temp_1(32 downto 1));
out_2 <= std_logic_vector(temp_2(32 downto 1));
out_3 <= std_logic_vector(temp_3(32 downto 1));
out_4 <= std_logic_vector(temp_4(32 downto 1));
out_5 <= std_logic_vector(temp_5(32 downto 1));
out_6 <= std_logic_vector(temp_6(32 downto 1));
out_7 <= std_logic_vector(temp_7(32 downto 1));
end process;
dac_interface_inst_1 : dac_interface generic map(
width => 32
) port map (
clk => clk,
rst => rst,
dithering => dithering,
input_0 => out_0,
input_1 => out_1,
input_2 => out_2,
input_3 => out_3,
input_4 => out_4,
input_5 => out_5,
input_6 => out_6,
input_7 => out_7,
output => rf
);
end rtl;
| mit | e8f5adc928aa29959da644d25b3c04d5 | 0.570297 | 2.870554 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2sgx90-av/leon3mp.vhd | 2 | 22,087 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.ft245.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- RESET, CLK, ERROR
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- combined flash/SSRAM/IO bus (fs_...)
fs_addr : out std_logic_vector(24 downto 0);
fs_data : inout std_logic_vector(31 downto 0);
-- IO chip enable
io_cen : out std_logic;
io_wen : out std_logic;
-- separate flash signals (flash_...)
flash_cen : out std_ulogic;
flash_oen : out std_logic;
flash_wen : out std_logic;
-- separate SSRAM signals (ssram_...)
ssram_cen : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (3 downto 0);
ssram_oen : out std_ulogic;
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
ssram_adspn : out std_ulogic;
ssram_advn : out std_ulogic;
-- DDR2
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
-- ETHERNET PHY
phy_gtx_clk : out std_logic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
-- debug support unit
dsuact : out std_ulogic;
-- console/debug UART
rxd1 : in std_logic;
txd1 : out std_logic;
-- FT245 UART
ft245_data : inout std_logic_vector (7 downto 0);
ft245_rdn : out std_logic;
ft245_wr : out std_logic;
ft245_rxfn : in std_logic;
ft245_txen : in std_logic;
ft245_pwrenn : in std_logic;
-- GPIO
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0)
);
end;
architecture rtl of leon3mp is
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
signal extd : std_logic_vector(31 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector;
signal clkm, rstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal ft245i : ft245_in_type;
signal ft245o : ft245_out_type;
signal ft245_vbdrive : std_logic_vector(7 downto 0);
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clkgen0 : clkgen -- clock generator for main clock
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV,
sdramen => CFG_MCTRL_SDEN, pcien => 0, pcidll => 0,
freq => BOARD_FREQ, clk2xen => 0, clksel => 0, clk_odiv => 0)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => ssram_clkl,
clk2x => open, sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo);
-- ssram_clkl <= not clkm;
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= '0';
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
romaddr => 16#000#, rommask => 16#E00#,
ioaddr => 16#200#, iomask => 16#E00#,
ramaddr => 16#C00#, rammask => 16#F00#,
paddr => 0, pmask => 16#FFF#,
srbanks => 1, wprot => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rom_sel_pad : outpad generic map (tech => padtech)
port map (flash_cen, vcc(0));
ssram_sel_pad : outpad generic map (tech => padtech)
port map (ssram_cen, vcc(0));
io_sel_pad : outpad generic map (tech => padtech)
port map (io_cen, vcc(0));
end generate;
mgpads : if CFG_MCTRL_LEON2 = 1 generate
-- flash/ssram data/address pads
fsaddr_pad : outpadv generic map (width => 25, tech => padtech)
port map (fs_addr, memo.address(25 downto 1));
fsdata_pad : iopadvv generic map (width => 32, tech => padtech)
port map (fs_data, memo.data, memo.vbdrive, memi.data);
-- flash only pads
rom_sel_pad : outpad generic map (tech => padtech)
port map (flash_cen, memo.romsn(0));
rom_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
rom_wri_pad : outpad generic map (tech => padtech)
port map (flash_wen, memo.writen);
-- ssram only pads
ssram_adv_n_pad : outpad generic map (tech => padtech)
port map (ssram_advn, vcc(0));
ssram_adsp_n_pad : outpad generic map (tech => padtech)
port map (ssram_adspn, vcc(0));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, gnd(0));
ssram_sel_pad : outpad generic map ( tech => padtech)
port map (ssram_cen, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.ramoen(0));
ssram_wen_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.wrn(0));
ssram_bw_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.mben);
-- io data
io_sel_pad : outpad generic map (tech => padtech)
port map (io_cen, memo.iosn);
io_wri_pad : outpad generic map (tech => padtech)
port map (io_wen, memo.writen);
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => BOARD_FREQ/10000,
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL,
Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64, readdly => 1,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 3, norefclk => 1, odten => 1, dqsse => 1)
port map ( rst_ddr => resetn, rst_ahb => rstn, clk_ddr => clk, clk_ahb => clkm, clkref200 => gnd(0),
lock => lock, clkddro => clkml, clkddri => clkml, ahbsi => ahbsi, ahbso => ahbso(3),
ddr_clk => ddr_clkv, ddr_clkb => ddr_clkbv, ddr_clk_fb => gnd(0), ddr_cke => ddr_ckev,
ddr_csb => ddr_csbv, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs => ddr_dqs, ddr_dqsn => open, ddr_ad => ddr_ad, ddr_ba => ddr_ba,
ddr_dq => ddr_dq, ddr_odt => ddr_odt);
ddr_clk <= ddr_clkv(2 downto 0); ddr_clkb <= ddr_clkbv(2 downto 0);
ddr_cke <= ddr_ckev(1 downto 0); ddr_csb <= ddr_csbv(1 downto 0);
end generate;
noddr : if (CFG_DDR2SP = 0) generate
ddr_cke <= (others => '0'); ddr_csb <= (others => '1'); lock <= '1';
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 18,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various peripherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE = 1 generate
uart1 : ft245uart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart)
port map (rstn, clkm, apbi, apbo(1), ft245i, ft245o);
ft245_vbdrive <= (others => ft245o.oen);
ft245_data_pad : iopadvv generic map (width => 8, tech => padtech)
port map (ft245_data, ft245o.wrdata, ft245_vbdrive, ft245i.rddata);
ft245_rdn_pad : outpad generic map (tech => padtech)
port map (ft245_rdn, ft245o.rdn);
ft245_wr_pad : outpad generic map (tech => padtech)
port map (ft245_wr, ft245o.wr);
ft245_rxfn_pad : inpad generic map (tech => padtech)
port map (ft245_rxfn, ft245i.rxfn);
ft245_txen_pad : inpad generic map (tech => padtech)
port map (ft245_txen, ft245i.txen);
ft245_pwrenn_pad : inpad generic map (tech => padtech)
port map (ft245_pwrenn, ft245i.pwrenn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2SGX90 SSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 70bef03399b8e5d6823bcd6f8dc1ca70 | 0.552452 | 3.636319 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/spi/spi2ahbx.vhd | 1 | 17,383 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahbx
-- File: spi2ahbx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- This entity is typically wrapped with spi2ahb or spi2ahb_apb.
-------------------------------------------------------------------------------
--
-- Short core documentation, for additional information see the GRLIB IP
-- Library User's Manual (GRIP):
--
-- The core functions as a SPI memory device. To write to the core, issue the
-- following SPI bus sequence:
--
-- 0. Assert chip select
-- 1. Write instruction
-- 2. Send 32-bit address
-- 3. Send data to be written
-- 4. Deassert chip select
--
-- The core will expect 32-bits of data and write these as a word. This can be
-- changed by writing to the core's control register. See documentation further
-- down. If less than HSIZE bytes are transferred the core will drop the data.
-- After HSIZE bytes has been transferred the core will perform the write to
-- memory. If another byte is received before the core has written its data
-- then the core will discard the current and any following bytes. This
-- condition can be detected by checking the MALFUNCTION bit in the core's
-- status register.
--
-- To read to the core, issue the following SPI bus sequence:
--
-- 0. Assert chip select
-- 1. Send read instruction
-- 2. Send 32-bit address to be used
-- 3. Send dummy byte (depending on read instruction used)
-- 4. Read bytes
-- 5. Deassert chip select
--
-- The core will perform 32-bit data accesses to fill its internal buffer. This
-- can be changed by writing to the core's control register (see documentation
-- further down). If the buffer is empty when the core should return the first
-- byte then the core will return invalid data. This condition can be later
-- detected by checking the MALFUNCTION bit in the core's status register.
-- When the core initiates additional data fetches can be configured via the
-- RAHEAD bit in the control/status register.
--
-- The cores control/status register is read via the RDSR instruction and
-- written via the WRSR instruction.
--
-- +--------+-----------------------------------------------------------------+
-- | Bit(s) | Description |
-- +--------+-----------------------------------------------------------------+
-- | 7 | Reserved, always zero (RO) |
-- | 6 | RAHEAD: Read ahead. When this bit is set the core will make a |
-- | | new access to fetch data as soon as the last current data bit |
-- | | has been moved. Otherwise the core will not attempt the new |
-- | | access until the 'change' transition on SCK. See GRIP doc. for |
-- | | details. Default value is '1'. (RW) |
-- | 5 | PROT: Memory protection triggered. Last access was outside |
-- | | range. Updated after each AMBA access (RO) |
-- | 4 | MEXC: Memory exception. Gets set if core receives AMBA ERROR |
-- | | response. Updated after each AMBA access. (RO) |
-- | 3 | DMAACT: Core is currently performing DMA (RO) |
-- | 2 | MALFUNCTION: Set to 1 if DMA is not finished when new byte |
-- | | starts getting shifted |
-- | 1:0 | HSIZE: Controls the access size core will use for AMBA accesses |
-- | | Default is HSIZE = WORD. HSIZE 11 is illegal (RW) |
-- +--------+-----------------------------------------------------------------+
--
-- Documentation of generics:
--
-- [hindex] AHB master index
--
-- [oepol] Output enable polarity
--
-- [filter] Length of filter used on SCK
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.spi.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity spi2ahbx is
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type;
--
spi2ahbi : in spi2ahb_in_type;
spi2ahbo : out spi2ahb_out_type
);
end entity spi2ahbx;
architecture rtl of spi2ahbx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OE : std_ulogic := conv_std_logic(oepol = 1);
constant HIZ : std_ulogic := not OE;
-----------------------------------------------------------------------------
-- Instructions
-----------------------------------------------------------------------------
constant RDSR_INST : std_logic_vector(7 downto 0) := X"05";
constant WRSR_INST : std_logic_vector(7 downto 0) := X"01";
constant READ_INST : std_logic_vector(7 downto 0) := X"03";
constant READD_INST : std_logic_vector(7 downto 0) := X"0B"; -- with dummy
constant WRITE_INST : std_logic_vector(7 downto 0) := X"02";
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type state_type is (decode, rdsr, wrsr, addr, dummy, rd, wr, idle, malfunction);
type spi2ahb_reg_type is record
state : state_type;
--
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hsize : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
--
rahead : std_ulogic;
mexc : std_ulogic;
dodma : std_ulogic;
prot : std_ulogic;
malf : std_ulogic;
--
brec : std_ulogic;
rec : std_ulogic;
dummy : std_ulogic;
cnt : std_logic_vector(2 downto 0);
bcnt : std_logic_vector(1 downto 0);
sreg : std_logic_vector(7 downto 0);
miso : std_ulogic;
rdop : std_logic_vector(1 downto 0);
--
misooen : std_ulogic;
sel : std_logic_vector(1 downto 0);
psck : std_ulogic;
sck : std_logic_vector(filter downto 0);
mosi : std_logic_vector(1 downto 0);
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal ami : ahb_dma_in_type;
signal amo : ahb_dma_out_type;
signal r, rin : spi2ahb_reg_type;
begin
-- Generic AHB master interface
ahbmst0 : ahbmst
generic map (hindex => hindex, hirq => 0, venid => VENDOR_GAISLER,
devid => GAISLER_SPI2AHB, version => 0,
chprot => 3, incaddr => 0)
port map (rstn, clk, ami, amo, ahbi, ahbo);
comb: process (r, rstn, spii, amo, spi2ahbi)
variable v : spi2ahb_reg_type;
variable hrdata : std_logic_vector(31 downto 0);
variable ahbreq : std_ulogic;
variable lb : std_ulogic;
variable sample : std_ulogic;
variable change : std_ulogic;
begin
v := r; ahbreq := '0'; lb := '0'; hrdata := (others => '0');
sample := '0'; change := '0'; v.brec := '0';
---------------------------------------------------------------------------
-- Sync input signals
---------------------------------------------------------------------------
v.sel := r.sel(0) & spii.spisel;
v.sck := r.sck(filter-1 downto 0) & spii.sck;
v.mosi := r.mosi(0) & spii.mosi;
---------------------------------------------------------------------------
-- DMA control
---------------------------------------------------------------------------
if r.dodma = '1' then
if amo.active = '1' then
if amo.ready = '1' then
hrdata := ahbreadword(amo.rdata);
case r.hsize is
when "00" =>
v.haddr := r.haddr + 1;
for i in 1 to 3 loop
if i = conv_integer(r.haddr(1 downto 0)) then
hrdata(31 downto 24) := hrdata(31-8*i downto 24-8*i);
end if;
end loop;
when "01" =>
v.haddr := r.haddr + 2;
if r.haddr(1) = '1' then
hrdata(31 downto 16) := hrdata(15 downto 0);
end if;
when others =>
v.haddr := r.haddr + 4;
end case;
v.sreg := hrdata(31 downto 24);
v.hdata(31 downto 8) := hrdata(23 downto 0);
v.mexc := '0';
v.dodma := '0';
end if;
if amo.mexc = '1' then
v.mexc := '1';
v.dodma := '0';
end if;
else
ahbreq := '1';
end if;
end if;
---------------------------------------------------------------------------
-- SPI communication
---------------------------------------------------------------------------
if andv(r.sck(filter downto 1)) = '1' then v.psck := '1'; end if;
if orv(r.sck(filter downto 1)) = '0' then v.psck := '0'; end if;
if (r.psck xor v.psck) = '1' then
if r.psck = conv_std_logic(cpol = 1) then
sample := not conv_std_logic(cpha = 1);
change := conv_std_logic(cpha = 1);
else
sample := conv_std_logic(cpha = 1);
change := not conv_std_logic(cpha = 1);
end if;
end if;
if sample = '1' then
v.cnt := r.cnt + 1;
if r.cnt = "111" then
v.cnt := (others => '0');
v.brec := '1';
end if;
if r.state /= dummy then
v.sreg := r.sreg(6 downto 0) & r.mosi(1);
end if;
end if;
if change = '1' then
v.miso := r.sreg(7);
end if;
---------------------------------------------------------------------------
-- SPI slave control FSM
---------------------------------------------------------------------------
if ((r.hsize = "00") or ((r.hsize(0) and r.bcnt(0)) = '1') or
(r.bcnt = "11")) then
lb := '1';
end if;
case r.state is
when decode =>
if r.brec = '1' then
case r.sreg is
when RDSR_INST =>
v.state := rdsr;
v.sreg := '0' & r.rahead & r.prot & r.mexc &
r.dodma & r.malf & r.hsize;
when WRSR_INST => v.state := wrsr;
when READ_INST | READD_INST=>
v.state := addr; v.rec := '0';
v.dummy := r.sreg(3);
when WRITE_INST => v.state := addr; v.rec := '1';
when others => null;
end case;
end if;
when rdsr =>
if r.brec = '1' then
v.sreg := '0' & r.rahead & r.prot & r.mexc &
r.dodma & r.malf & r.hsize;
end if;
when wrsr =>
if r.brec = '1' then
v.rahead := r.sreg(6);
v.hsize := r.sreg(1 downto 0);
end if;
when addr =>
-- First we need a 4 byte address, then we handle data.
if r.brec = '1' then
if r.dodma = '1' then
v.state := malfunction;
else
v.haddr := r.haddr(23 downto 0) & r.sreg;
end if;
v.bcnt := r.bcnt + 1;
if r.bcnt = "11" then
if r.rec = '1' then
v.state := wr;
else
if r.dummy = '1' then
v.state := dummy;
else
v.state := rd;
end if;
v.malf := '0';
v.dodma := '1';
v.hwrite := '0';
end if;
end if;
end if;
when dummy =>
if r.brec = '1' then
v.state := rd;
end if;
when rd =>
if r.brec = '1' then
v.bcnt := r.bcnt + 1;
v.hdata(31 downto 8) := r.hdata(23 downto 0);
v.sreg := r.hdata(31 downto 24);
if (lb and r.rahead) = '1' then
v.dodma := '1';
v.bcnt := "00";
end if;
v.rdop(0) := lb and not r.rahead;
end if;
if (change and v.dodma) = '1' then
v.state := malfunction;
end if;
-- Without readahead
if orv(r.rdop) = '1' then
if (sample and v.dodma) = '1' then
-- Case is a little tricky. Master may have sampled bad
-- data but we detect the DMA operation as completed.
v.state := malfunction;
end if;
if (r.rdop(0) and change) = '1' then
v.dodma := '1';
v.rdop := "10";
end if;
if (r.dodma and not v.dodma) = '1' then
v.miso := hrdata(31);
v.rdop := (others => '0');
end if;
end if;
when wr =>
if r.brec = '1' then
v.bcnt := r.bcnt + 1;
if v.dodma = '0' then
if r.bcnt = "00" then v.hdata(31 downto 24) := r.sreg; end if;
if r.bcnt(1) = '0' then v.hdata(23 downto 16) := r.sreg; end if;
if r.bcnt(0) = '0' then v.hdata(15 downto 8) := r.sreg; end if;
v.hdata(7 downto 0) := r.sreg;
if lb = '1' then v.dodma := '1'; v.hwrite := '1'; v.malf := '0'; end if;
else
v.state := malfunction;
end if;
end if;
when idle =>
if r.sel(1) = '0' then
v.state := decode;
v.misooen := OE;
v.cnt := (others => '0');
v.bcnt := (others => '0');
end if;
when malfunction =>
v.malf := '1';
end case;
if r.state /= rd then v.rdop := (others => '0'); end if;
if spi2ahbi.hmask /= zero32 then
if v.dodma = '1' then
if ((spi2ahbi.haddr xor r.haddr) and spi2ahbi.hmask) /= zero32 then
v.dodma := '0';
v.prot := '1';
v.state := idle;
else
v.prot := '0';
end if;
end if;
else
v.prot := '0';
end if;
if spi2ahbi.en = '1' then
if r.sel(1) = '1' then
v.state := idle;
v.misooen := HIZ;
end if;
else
v.state := idle;
v.misooen := HIZ;
end if;
----------------------------------------------------------------------------
-- Reset
----------------------------------------------------------------------------
if rstn = '0' then
v.state := idle;
v.haddr := (others => '0');
v.hdata := (others => '0');
v.hsize := HSIZE_WORD(1 downto 0);
v.rahead := '1';
v.mexc := '0';
v.dodma := '0';
v.prot := '0';
v.malf := '0';
v.psck := conv_std_logic(cpol = 1);
v.miso := '1';
v.misooen := HIZ;
end if;
if spi2ahbi.hmask = zero32 then v.prot := '0'; end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB master control
ami.address <= r.haddr;
ami.wdata <= ahbdrivedata(r.hdata);
ami.start <= ahbreq;
ami.burst <= '0';
ami.write <= r.hwrite;
ami.busy <= '0';
ami.irq <= '0';
ami.size <= '0' & r.hsize;
-- Update outputs
spi2ahbo.dma <= r.dodma;
spi2ahbo.wr <= r.hwrite;
spi2ahbo.prot <= r.prot;
-- Several unused here..
spio.miso <= r.miso;
spio.misooen <= r.misooen;
spio.mosi <= '0';
spio.mosioen <= HIZ;
spio.sck <= '0';
spio.sckoen <= HIZ;
spio.ssn <= (others => '0');
spio.enable <= spi2ahbi.en;
spio.astart <= '0';
end process comb;
reg: process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map ("spi2ahb" & tost(hindex) & ": SPI to AHB bridge");
-- pragma translate_on
end architecture rtl;
| gpl-2.0 | 12dcde432972e15f2b62157aa7c772d3 | 0.46511 | 3.953377 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/usb/grusb.vhd | 1 | 24,317 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Package: grusb
-- File: grusb.vhd
-- Author: Marko Isomaki, Jonas Ekergarn
-- Description: Package for GRUSBHC, GRUSBDC, and GRUSB_DCL
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package grusb is
-----------------------------------------------------------------------------
-- USB in/out types
-----------------------------------------------------------------------------
type grusb_in_type is record
datain : std_logic_vector(15 downto 0);
rxactive : std_ulogic;
rxvalid : std_ulogic;
rxvalidh : std_ulogic;
rxerror : std_ulogic;
txready : std_ulogic;
linestate : std_logic_vector(1 downto 0);
nxt : std_ulogic;
dir : std_ulogic;
vbusvalid : std_ulogic;
hostdisconnect : std_ulogic;
functesten : std_ulogic;
urstdrive : std_ulogic;
end record;
constant grusb_in_none : grusb_in_type :=
((others => '0'), '0', '0', '0', '0', '0', (others => '0'),
'0', '0', '0', '0', '0', '0');
type grusb_out_type is record
dataout : std_logic_vector(15 downto 0);
txvalid : std_ulogic;
txvalidh : std_ulogic;
opmode : std_logic_vector(1 downto 0);
xcvrselect : std_logic_vector(1 downto 0);
termselect : std_ulogic;
suspendm : std_ulogic;
reset : std_ulogic;
stp : std_ulogic;
oen : std_ulogic;
databus16_8 : std_ulogic;
dppulldown : std_ulogic;
dmpulldown : std_ulogic;
idpullup : std_ulogic;
drvvbus : std_ulogic;
dischrgvbus : std_ulogic;
chrgvbus : std_ulogic;
txbitstuffenable : std_ulogic;
txbitstuffenableh : std_ulogic;
fslsserialmode : std_ulogic;
tx_enable_n : std_ulogic;
tx_dat : std_ulogic;
tx_se0 : std_ulogic;
end record;
constant grusb_out_none : grusb_out_type :=
((others => '0'), '0', '0', (others => '0'), (others => '0'),
'0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0');
type grusb_in_vector is array (natural range <>) of grusb_in_type;
type grusb_out_vector is array (natural range <>) of grusb_out_type;
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component grusbhc is
generic (
ehchindex : integer range 0 to NAHBMST-1 := 0;
ehcpindex : integer range 0 to NAPBSLV-1 := 0;
ehcpaddr : integer range 0 to 16#FFF# := 0;
ehcpirq : integer range 0 to NAHBIRQ-1 := 0;
ehcpmask : integer range 0 to 16#FFF# := 16#FFF#;
uhchindex : integer range 0 to NAHBMST-1 := 0;
uhchsindex : integer range 0 to NAHBSLV-1 := 0;
uhchaddr : integer range 0 to 16#FFF# := 0;
uhchmask : integer range 0 to 16#FFF# := 16#FFF#;
uhchirq : integer range 0 to NAHBIRQ-1 := 0;
tech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
netlist : integer range 0 to 1 := 0;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 0;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debugsize : integer := 8192);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
apbi : in apb_slv_in_type;
ehc_apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ehc_ahbmo : out ahb_mst_out_type;
uhc_ahbmo : out ahb_mst_out_vector_type(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso : out ahb_slv_out_vector_type(n_cc*uhcgen downto 1*uhcgen);
o : out grusb_out_vector((nports-1) downto 0);
i : in grusb_in_vector((nports-1) downto 0));
end component;
component grusbdc is
generic (
hsindex : integer range 0 to NAHBSLV-1 := 0;
hirq : integer range 0 to NAHBIRQ-1 := 0;
haddr : integer := 0;
hmask : integer := 16#FFF#;
hmindex : integer range 0 to NAHBMST-1 := 0;
aiface : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
blen : integer range 4 to 128 := 16;
nepi : integer range 1 to 16 := 1;
nepo : integer range 1 to 16 := 1;
i0 : integer range 8 to 3072 := 1024;
i1 : integer range 8 to 3072 := 1024;
i2 : integer range 8 to 3072 := 1024;
i3 : integer range 8 to 3072 := 1024;
i4 : integer range 8 to 3072 := 1024;
i5 : integer range 8 to 3072 := 1024;
i6 : integer range 8 to 3072 := 1024;
i7 : integer range 8 to 3072 := 1024;
i8 : integer range 8 to 3072 := 1024;
i9 : integer range 8 to 3072 := 1024;
i10 : integer range 8 to 3072 := 1024;
i11 : integer range 8 to 3072 := 1024;
i12 : integer range 8 to 3072 := 1024;
i13 : integer range 8 to 3072 := 1024;
i14 : integer range 8 to 3072 := 1024;
i15 : integer range 8 to 3072 := 1024;
o0 : integer range 8 to 3072 := 1024;
o1 : integer range 8 to 3072 := 1024;
o2 : integer range 8 to 3072 := 1024;
o3 : integer range 8 to 3072 := 1024;
o4 : integer range 8 to 3072 := 1024;
o5 : integer range 8 to 3072 := 1024;
o6 : integer range 8 to 3072 := 1024;
o7 : integer range 8 to 3072 := 1024;
o8 : integer range 8 to 3072 := 1024;
o9 : integer range 8 to 3072 := 1024;
o10 : integer range 8 to 3072 := 1024;
o11 : integer range 8 to 3072 := 1024;
o12 : integer range 8 to 3072 := 1024;
o13 : integer range 8 to 3072 := 1024;
o14 : integer range 8 to 3072 := 1024;
o15 : integer range 8 to 3072 := 1024;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
sepirq : integer range 0 to 1 := 0;
irqi : integer range 0 to NAHBIRQ-1 := 1;
irqo : integer range 0 to NAHBIRQ-1 := 2;
functesten : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1);
port (
uclk : in std_ulogic;
usbi : in grusb_in_type;
usbo : out grusb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component grusb_dcl is
generic (
hindex : integer := 0;
memtech : integer := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
functesten : integer range 0 to 1 := 0;
burstlength: integer range 1 to 512 := 8;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1
);
port (
uclk : in std_ulogic;
usbi : in grusb_in_type;
usbo : out grusb_out_type;
hclk : in std_ulogic;
hrst : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component grusb_dcl;
component grusbhc_gen is
generic (
tech : integer := 0;
memtech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer := 3;
netlist : integer range 0 to 1 := 0;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 0;
oepol : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
memsel : integer := 0;
syncprst : integer range 0 to 1 := 0;
sysfreq : integer := 65000;
pcidev : integer range 0 to 1 := 0;
debug : integer := 0;
debugsize : integer := 8192);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
-- EHC APB slave input signals
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
-- EHC APB slave output signals
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_irq : out std_ulogic;
-- EHC/UHC(s) AHB master input signals
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
-- UHC(s) AHB slave input signals
uhc_ahbsi_hsel : in std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
-- EHC AHB master output signals
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC(s) AHB master output signals
uhc_ahbmo_hbusreq : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_hlock : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_htrans : out std_logic_vector(((n_cc*2)-1)*uhcgen downto 0);
uhc_ahbmo_haddr : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
uhc_ahbmo_hwrite : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbmo_hsize : out std_logic_vector(((n_cc*3)-1)*uhcgen downto 0);
uhc_ahbmo_hburst : out std_logic_vector(((n_cc*3)-1)*uhcgen downto 0);
uhc_ahbmo_hprot : out std_logic_vector(((n_cc*4)-1)*uhcgen downto 0);
uhc_ahbmo_hwdata : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
-- UHC(s) AHB slave output signals
uhc_ahbso_hready : out std_logic_vector((n_cc-1)*uhcgen downto 0);
uhc_ahbso_hresp : out std_logic_vector(((n_cc*2)-1)*uhcgen downto 0);
uhc_ahbso_hrdata : out std_logic_vector(((n_cc*32)-1)*uhcgen downto 0);
uhc_ahbso_hsplit : out std_logic_vector(((n_cc*NAHBMST)-1)*uhcgen downto 0);
uhc_irq : out std_logic_vector((n_cc-1)*uhcgen downto 0);
-- ULPI/UTMI+ output signals
xcvrselect : out std_logic_vector(((nports*2)-1) downto 0);
termselect : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataout : out std_logic_vector(((nports*16)-1) downto 0);
txvalidh : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
reset : out std_logic_vector((nports-1) downto 0);
oen : out std_logic_vector((nports-1) downto 0);
suspendm : out std_ulogic;
databus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
tx_enable_n : out std_ulogic;
tx_dat : out std_ulogic;
tx_se0 : out std_ulogic;
-- ULPI/UTMI+ input signals
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datain : in std_logic_vector(((nports*16)-1) downto 0);
rxvalidh : in std_logic_vector((nports-1) downto 0);
hostdisconnect : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
urstdrive : in std_logic_vector((nports-1) downto 0);
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component grusbdc_gen is
generic (
aiface : integer range 0 to 1 := 0;
memtech : integer range 0 to NTECH := DEFMEMTECH;
uiface : integer range 0 to 1 := 0;
dwidth : integer range 8 to 16 := 8;
blen : integer range 4 to 128 := 16;
nepi : integer range 1 to 16 := 1;
nepo : integer range 1 to 16 := 1;
i0 : integer range 8 to 3072 := 1024;
i1 : integer range 8 to 3072 := 1024;
i2 : integer range 8 to 3072 := 1024;
i3 : integer range 8 to 3072 := 1024;
i4 : integer range 8 to 3072 := 1024;
i5 : integer range 8 to 3072 := 1024;
i6 : integer range 8 to 3072 := 1024;
i7 : integer range 8 to 3072 := 1024;
i8 : integer range 8 to 3072 := 1024;
i9 : integer range 8 to 3072 := 1024;
i10 : integer range 8 to 3072 := 1024;
i11 : integer range 8 to 3072 := 1024;
i12 : integer range 8 to 3072 := 1024;
i13 : integer range 8 to 3072 := 1024;
i14 : integer range 8 to 3072 := 1024;
i15 : integer range 8 to 3072 := 1024;
o0 : integer range 8 to 3072 := 1024;
o1 : integer range 8 to 3072 := 1024;
o2 : integer range 8 to 3072 := 1024;
o3 : integer range 8 to 3072 := 1024;
o4 : integer range 8 to 3072 := 1024;
o5 : integer range 8 to 3072 := 1024;
o6 : integer range 8 to 3072 := 1024;
o7 : integer range 8 to 3072 := 1024;
o8 : integer range 8 to 3072 := 1024;
o9 : integer range 8 to 3072 := 1024;
o10 : integer range 8 to 3072 := 1024;
o11 : integer range 8 to 3072 := 1024;
o12 : integer range 8 to 3072 := 1024;
o13 : integer range 8 to 3072 := 1024;
o14 : integer range 8 to 3072 := 1024;
o15 : integer range 8 to 3072 := 1024;
oepol : integer range 0 to 1 := 0;
syncprst : integer range 0 to 1 := 0;
prsttime : integer range 0 to 512 := 0;
sysfreq : integer := 50000;
keepclk : integer range 0 to 1 := 0;
sepirq : integer range 0 to 1 := 0;
functesten : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 1);
port (
-- usb clock
uclk : in std_ulogic;
--usb in signals
datain : in std_logic_vector(15 downto 0);
rxactive : in std_ulogic;
rxvalid : in std_ulogic;
rxvalidh : in std_ulogic;
rxerror : in std_ulogic;
txready : in std_ulogic;
linestate : in std_logic_vector(1 downto 0);
nxt : in std_ulogic;
dir : in std_ulogic;
vbusvalid : in std_ulogic;
urstdrive : in std_ulogic;
--usb out signals
dataout : out std_logic_vector(15 downto 0);
txvalid : out std_ulogic;
txvalidh : out std_ulogic;
opmode : out std_logic_vector(1 downto 0);
xcvrselect : out std_logic_vector(1 downto 0);
termselect : out std_ulogic;
suspendm : out std_ulogic;
reset : out std_ulogic;
stp : out std_ulogic;
oen : out std_ulogic;
databus16_8 : out std_ulogic;
dppulldown : out std_ulogic;
dmpulldown : out std_ulogic;
idpullup : out std_ulogic;
drvvbus : out std_ulogic;
dischrgvbus : out std_ulogic;
chrgvbus : out std_ulogic;
txbitstuffenable : out std_ulogic;
txbitstuffenableh : out std_ulogic;
fslsserialmode : out std_ulogic;
tx_enable_n : out std_ulogic;
tx_dat : out std_ulogic;
tx_se0 : out std_ulogic;
-- amba clock/rst
hclk : in std_ulogic;
hrst : in std_ulogic;
--ahb master in signals
ahbmi_hgrant : in std_ulogic;
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
--ahb master out signals
ahbmo_hbusreq : out std_ulogic;
ahbmo_hlock : out std_ulogic;
ahbmo_htrans : out std_logic_vector(1 downto 0);
ahbmo_haddr : out std_logic_vector(31 downto 0);
ahbmo_hwrite : out std_ulogic;
ahbmo_hsize : out std_logic_vector(2 downto 0);
ahbmo_hburst : out std_logic_vector(2 downto 0);
ahbmo_hprot : out std_logic_vector(3 downto 0);
ahbmo_hwdata : out std_logic_vector(31 downto 0);
--ahb slave in signals
ahbsi_hsel : in std_ulogic;
ahbsi_haddr : in std_logic_vector(31 downto 0);
ahbsi_hwrite : in std_ulogic;
ahbsi_htrans : in std_logic_vector(1 downto 0);
ahbsi_hsize : in std_logic_vector(2 downto 0);
ahbsi_hburst : in std_logic_vector(2 downto 0);
ahbsi_hwdata : in std_logic_vector(31 downto 0);
ahbsi_hprot : in std_logic_vector(3 downto 0);
ahbsi_hready : in std_ulogic;
ahbsi_hmaster : in std_logic_vector(3 downto 0);
ahbsi_hmastlock : in std_ulogic;
--ahb slave out signals
ahbso_hready : out std_ulogic;
ahbso_hresp : out std_logic_vector(1 downto 0);
ahbso_hrdata : out std_logic_vector(31 downto 0);
ahbso_hsplit : out std_logic_vector(NAHBMST-1 downto 0);
-- misc
irq : out std_logic_vector(2*sepirq downto 0);
-- scan signals
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
end grusb;
| gpl-2.0 | 74bc5fac53c396253cac20caf9d5c4f5 | 0.495291 | 3.828846 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_sim_netlist.vhdl | 1 | 719,637 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:59 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_sim_netlist.vhdl
-- Design : zynq_design_1_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
port (
\s_axi_arready[0]\ : out STD_LOGIC;
aa_mi_arvalid : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rlast_i0 : out STD_LOGIC;
\m_axi_arqos[7]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rid_i_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_valid_i_reg_0\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gen_axi.read_cnt_reg[5]\ : in STD_LOGIC;
p_15_in : in STD_LOGIC;
mi_arready_2 : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : in STD_LOGIC;
st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
\s_axi_araddr[30]\ : in STD_LOGIC;
\s_axi_araddr[28]\ : in STD_LOGIC;
\s_axi_araddr[25]\ : in STD_LOGIC;
\m_payload_i_reg[34]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
aresetn_d_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^aa_mi_arvalid\ : STD_LOGIC;
signal \^gen_axi.s_axi_rid_i_reg[11]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.s_axi_rlast_i_i_6_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\ : STD_LOGIC;
signal \^gen_no_arbiter.m_target_hot_i_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_no_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^gen_no_arbiter.m_valid_i_reg_0\ : STD_LOGIC;
signal \^m_axi_arqos[7]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready[0]\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_rid_i[11]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_5\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[10]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[16]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair6";
begin
aa_mi_arvalid <= \^aa_mi_arvalid\;
\gen_axi.s_axi_rid_i_reg[11]\(0) <= \^gen_axi.s_axi_rid_i_reg[11]\(0);
\gen_no_arbiter.m_target_hot_i_reg[0]_0\(0) <= \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0);
\gen_no_arbiter.m_valid_i_reg_0\ <= \^gen_no_arbiter.m_valid_i_reg_0\;
\m_axi_arqos[7]\(68 downto 0) <= \^m_axi_arqos[7]\(68 downto 0);
\s_axi_arready[0]\ <= \^s_axi_arready[0]\;
\gen_axi.s_axi_rid_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => \^gen_axi.s_axi_rid_i_reg[11]\(0),
I2 => mi_arready_2,
I3 => p_15_in,
O => E(0)
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"444444444444444F"
)
port map (
I0 => \gen_axi.read_cnt_reg[5]\,
I1 => p_15_in,
I2 => \gen_axi.s_axi_rlast_i_i_6_n_0\,
I3 => \^m_axi_arqos[7]\(44),
I4 => \^m_axi_arqos[7]\(45),
I5 => \^m_axi_arqos[7]\(47),
O => s_axi_rlast_i0
);
\gen_axi.s_axi_rlast_i_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^m_axi_arqos[7]\(49),
I1 => p_15_in,
I2 => \^m_axi_arqos[7]\(48),
I3 => \^m_axi_arqos[7]\(46),
I4 => \^m_axi_arqos[7]\(51),
I5 => \^m_axi_arqos[7]\(50),
O => \gen_axi.s_axi_rlast_i_i_6_n_0\
);
\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I2 => r_issuing_cnt(1),
O => D(0)
);
\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I1 => r_issuing_cnt(0),
I2 => r_issuing_cnt(1),
I3 => r_issuing_cnt(2),
O => D(1)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666666666662"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\,
I1 => \m_payload_i_reg[34]\,
I2 => r_issuing_cnt(0),
I3 => r_issuing_cnt(1),
I4 => r_issuing_cnt(2),
I5 => r_issuing_cnt(3),
O => \gen_master_slots[0].r_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => r_issuing_cnt(3),
I1 => r_issuing_cnt(2),
I2 => r_issuing_cnt(1),
I3 => r_issuing_cnt(0),
I4 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
O => D(2)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(0),
I1 => aa_mi_artarget_hot(0),
I2 => \^aa_mi_arvalid\,
O => \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\
);
\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
I2 => m_axi_arready(0),
I3 => \m_payload_i_reg[34]\,
O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I1 => r_issuing_cnt(4),
I2 => r_issuing_cnt(5),
I3 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666666666662"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\,
I1 => \m_payload_i_reg[34]_0\,
I2 => r_issuing_cnt(4),
I3 => r_issuing_cnt(5),
I4 => r_issuing_cnt(6),
I5 => r_issuing_cnt(7),
O => \gen_master_slots[1].r_issuing_cnt_reg[8]\(0)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => r_issuing_cnt(7),
I1 => r_issuing_cnt(6),
I2 => r_issuing_cnt(5),
I3 => r_issuing_cnt(4),
I4 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(1),
I1 => aa_mi_artarget_hot(1),
I2 => \^aa_mi_arvalid\,
O => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\
);
\gen_master_slots[1].r_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080808080808080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(1),
I2 => m_axi_arready(1),
I3 => s_axi_rready(0),
I4 => m_valid_i_reg,
I5 => Q(0),
O => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I2 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0)
);
\gen_master_slots[2].r_issuing_cnt[16]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => mi_arready_2,
I1 => \^gen_axi.s_axi_rid_i_reg[11]\(0),
I2 => \^aa_mi_arvalid\,
O => \^gen_no_arbiter.m_valid_i_reg_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => st_aa_artarget_hot(0),
I1 => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\
);
\gen_no_arbiter.m_mesg_i[11]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_mi_arvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(0),
Q => \^m_axi_arqos[7]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(10),
Q => \^m_axi_arqos[7]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(11),
Q => \^m_axi_arqos[7]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(12),
Q => \^m_axi_arqos[7]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(13),
Q => \^m_axi_arqos[7]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(14),
Q => \^m_axi_arqos[7]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(15),
Q => \^m_axi_arqos[7]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(16),
Q => \^m_axi_arqos[7]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(17),
Q => \^m_axi_arqos[7]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(18),
Q => \^m_axi_arqos[7]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(19),
Q => \^m_axi_arqos[7]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(1),
Q => \^m_axi_arqos[7]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(20),
Q => \^m_axi_arqos[7]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(21),
Q => \^m_axi_arqos[7]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(22),
Q => \^m_axi_arqos[7]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(23),
Q => \^m_axi_arqos[7]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(24),
Q => \^m_axi_arqos[7]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(25),
Q => \^m_axi_arqos[7]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(26),
Q => \^m_axi_arqos[7]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(27),
Q => \^m_axi_arqos[7]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(28),
Q => \^m_axi_arqos[7]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(29),
Q => \^m_axi_arqos[7]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(2),
Q => \^m_axi_arqos[7]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(30),
Q => \^m_axi_arqos[7]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(31),
Q => \^m_axi_arqos[7]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(32),
Q => \^m_axi_arqos[7]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(33),
Q => \^m_axi_arqos[7]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(34),
Q => \^m_axi_arqos[7]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(35),
Q => \^m_axi_arqos[7]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(36),
Q => \^m_axi_arqos[7]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(37),
Q => \^m_axi_arqos[7]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(38),
Q => \^m_axi_arqos[7]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(39),
Q => \^m_axi_arqos[7]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(3),
Q => \^m_axi_arqos[7]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(40),
Q => \^m_axi_arqos[7]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(41),
Q => \^m_axi_arqos[7]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(42),
Q => \^m_axi_arqos[7]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(43),
Q => \^m_axi_arqos[7]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(44),
Q => \^m_axi_arqos[7]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(45),
Q => \^m_axi_arqos[7]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(46),
Q => \^m_axi_arqos[7]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(47),
Q => \^m_axi_arqos[7]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(48),
Q => \^m_axi_arqos[7]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(49),
Q => \^m_axi_arqos[7]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(4),
Q => \^m_axi_arqos[7]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(50),
Q => \^m_axi_arqos[7]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(51),
Q => \^m_axi_arqos[7]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(52),
Q => \^m_axi_arqos[7]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(53),
Q => \^m_axi_arqos[7]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(54),
Q => \^m_axi_arqos[7]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(55),
Q => \^m_axi_arqos[7]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(56),
Q => \^m_axi_arqos[7]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(57),
Q => \^m_axi_arqos[7]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(58),
Q => \^m_axi_arqos[7]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(5),
Q => \^m_axi_arqos[7]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(59),
Q => \^m_axi_arqos[7]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(60),
Q => \^m_axi_arqos[7]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(61),
Q => \^m_axi_arqos[7]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(62),
Q => \^m_axi_arqos[7]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(63),
Q => \^m_axi_arqos[7]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(64),
Q => \^m_axi_arqos[7]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(6),
Q => \^m_axi_arqos[7]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(65),
Q => \^m_axi_arqos[7]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(66),
Q => \^m_axi_arqos[7]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(67),
Q => \^m_axi_arqos[7]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(68),
Q => \^m_axi_arqos[7]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(7),
Q => \^m_axi_arqos[7]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(8),
Q => \^m_axi_arqos[7]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(9),
Q => \^m_axi_arqos[7]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => aa_mi_artarget_hot(0),
O => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => \s_axi_arqos[3]\(33),
I1 => \s_axi_arqos[3]\(36),
I2 => \s_axi_araddr[30]\,
I3 => \s_axi_araddr[28]\,
I4 => \s_axi_araddr[25]\,
O => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => st_aa_artarget_hot(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => aa_mi_artarget_hot(1),
O => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\,
Q => aa_mi_artarget_hot(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\,
Q => aa_mi_artarget_hot(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg_0,
Q => \^gen_axi.s_axi_rid_i_reg[11]\(0),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0000002A"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
I2 => m_axi_arready(0),
I3 => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\,
I4 => \^gen_no_arbiter.m_valid_i_reg_0\,
I5 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1__0_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1__0_n_0\,
Q => \^aa_mi_arvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFEFFFEFFFFF"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
I1 => \^aa_mi_arvalid\,
I2 => s_axi_arvalid(0),
I3 => \^s_axi_arready[0]\,
I4 => \chosen_reg[0]\,
I5 => \gen_multi_thread.accept_cnt_reg[3]\,
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg,
Q => \^s_axi_arready[0]\,
R => '0'
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(1),
O => m_axi_arvalid(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
port (
ss_aa_awready : out STD_LOGIC;
aa_sa_awvalid : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
aa_mi_awtarget_hot : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].w_issuing_cnt_reg[9]\ : out STD_LOGIC;
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
st_aa_awtarget_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_target_hot_i_reg[2]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
aresetn_d : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 7 downto 0 );
\chosen_reg[1]\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\chosen_reg[0]\ : in STD_LOGIC;
mi_awready_2 : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[26]\ : in STD_LOGIC;
\s_axi_awaddr[20]\ : in STD_LOGIC;
\s_axi_awqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
signal \^aa_mi_awtarget_hot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^aa_sa_awvalid\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \^gen_master_slots[1].w_issuing_cnt_reg[9]\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
signal \^ss_aa_awready\ : STD_LOGIC;
signal \^st_aa_awtarget_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[10]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_3\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[9]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_4\ : label is "soft_lutpair12";
begin
aa_mi_awtarget_hot(2 downto 0) <= \^aa_mi_awtarget_hot\(2 downto 0);
aa_sa_awvalid <= \^aa_sa_awvalid\;
\gen_master_slots[1].w_issuing_cnt_reg[9]\ <= \^gen_master_slots[1].w_issuing_cnt_reg[9]\;
\m_ready_d_reg[1]\ <= \^m_ready_d_reg[1]\;
ss_aa_awready <= \^ss_aa_awready\;
st_aa_awtarget_hot(0) <= \^st_aa_awtarget_hot\(0);
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_sa_awvalid\,
I2 => \^aa_mi_awtarget_hot\(2),
I3 => mi_awready_2,
O => \gen_master_slots[2].w_issuing_cnt_reg[16]\
);
\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA95555555"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \chosen_reg[0]\,
I2 => m_axi_awready(0),
I3 => \^aa_mi_awtarget_hot\(0),
I4 => \^gen_master_slots[1].w_issuing_cnt_reg[9]\,
I5 => w_issuing_cnt(1),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA55555554"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\,
I1 => w_issuing_cnt(3),
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(2),
I4 => w_issuing_cnt(1),
I5 => \chosen_reg[0]\,
O => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => w_issuing_cnt(3),
I1 => w_issuing_cnt(0),
I2 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I3 => w_issuing_cnt(1),
I4 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_sa_awvalid\,
I2 => \^aa_mi_awtarget_hot\(0),
I3 => m_axi_awready(0),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => \chosen_reg[0]\,
I1 => m_axi_awready(0),
I2 => \^aa_mi_awtarget_hot\(0),
I3 => \^aa_sa_awvalid\,
I4 => m_ready_d(1),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(5),
I3 => w_issuing_cnt(6),
O => D(1)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA55555554"
)
port map (
I0 => \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\,
I1 => w_issuing_cnt(7),
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(6),
I4 => w_issuing_cnt(5),
I5 => \chosen_reg[1]\,
O => E(0)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => w_issuing_cnt(7),
I1 => w_issuing_cnt(4),
I2 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I3 => w_issuing_cnt(5),
I4 => w_issuing_cnt(6),
O => D(2)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_sa_awvalid\,
I2 => \^aa_mi_awtarget_hot\(1),
I3 => m_axi_awready(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000070000000"
)
port map (
I0 => m_valid_i_reg,
I1 => s_axi_bready(0),
I2 => m_axi_awready(1),
I3 => \^aa_mi_awtarget_hot\(1),
I4 => \^aa_sa_awvalid\,
I5 => m_ready_d(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA95555555"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \chosen_reg[1]\,
I2 => m_axi_awready(1),
I3 => \^aa_mi_awtarget_hot\(1),
I4 => \^gen_master_slots[1].w_issuing_cnt_reg[9]\,
I5 => w_issuing_cnt(5),
O => D(0)
);
\gen_master_slots[1].w_issuing_cnt[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => m_ready_d(1),
O => \^gen_master_slots[1].w_issuing_cnt_reg[9]\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\,
I1 => \s_axi_awaddr[26]\,
I2 => \s_axi_awaddr[20]\,
I3 => \s_axi_awqos[3]\(33),
I4 => \s_axi_awqos[3]\(36),
O => \^st_aa_awtarget_hot\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_awqos[3]\(35),
I1 => \s_axi_awqos[3]\(31),
I2 => \s_axi_awqos[3]\(28),
I3 => \s_axi_awqos[3]\(39),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\
);
\gen_no_arbiter.m_mesg_i[11]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_sa_awvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(0),
Q => Q(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(10),
Q => Q(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(11),
Q => Q(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(12),
Q => Q(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(13),
Q => Q(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(14),
Q => Q(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(15),
Q => Q(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(16),
Q => Q(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(17),
Q => Q(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(18),
Q => Q(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(19),
Q => Q(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(1),
Q => Q(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(20),
Q => Q(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(21),
Q => Q(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(22),
Q => Q(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(23),
Q => Q(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(24),
Q => Q(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(25),
Q => Q(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(26),
Q => Q(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(27),
Q => Q(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(28),
Q => Q(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(29),
Q => Q(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(2),
Q => Q(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(30),
Q => Q(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(31),
Q => Q(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(32),
Q => Q(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(33),
Q => Q(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(34),
Q => Q(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(35),
Q => Q(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(36),
Q => Q(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(37),
Q => Q(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(38),
Q => Q(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(39),
Q => Q(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(3),
Q => Q(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(40),
Q => Q(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(41),
Q => Q(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(42),
Q => Q(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(43),
Q => Q(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(44),
Q => Q(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(45),
Q => Q(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(46),
Q => Q(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(47),
Q => Q(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(48),
Q => Q(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(49),
Q => Q(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(4),
Q => Q(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(50),
Q => Q(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(51),
Q => Q(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(52),
Q => Q(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(53),
Q => Q(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(54),
Q => Q(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(55),
Q => Q(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(56),
Q => Q(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(57),
Q => Q(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(58),
Q => Q(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(5),
Q => Q(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(59),
Q => Q(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(60),
Q => Q(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(61),
Q => Q(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(62),
Q => Q(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(63),
Q => Q(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(64),
Q => Q(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(6),
Q => Q(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(65),
Q => Q(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(66),
Q => Q(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(67),
Q => Q(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(68),
Q => Q(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(7),
Q => Q(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(8),
Q => Q(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(9),
Q => Q(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => \^st_aa_awtarget_hot\(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => \^aa_mi_awtarget_hot\(0),
O => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => st_aa_awtarget_enc(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => \^aa_mi_awtarget_hot\(1),
O => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\,
Q => \^aa_mi_awtarget_hot\(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\,
Q => \^aa_mi_awtarget_hot\(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg_0,
Q => \^aa_mi_awtarget_hot\(2),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F2"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
I2 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => \^aa_mi_awtarget_hot\(0),
I1 => \^aa_mi_awtarget_hot\(1),
I2 => \^aa_mi_awtarget_hot\(2),
I3 => m_ready_d(0),
I4 => \^m_ready_d_reg[1]\,
O => \gen_no_arbiter.m_valid_i_i_2_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^aa_sa_awvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^ss_aa_awready\,
I1 => m_ready_d_0(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg,
Q => \^ss_aa_awready\,
R => '0'
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \^aa_mi_awtarget_hot\(0),
I1 => m_ready_d(1),
I2 => \^aa_sa_awvalid\,
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \^aa_mi_awtarget_hot\(1),
I1 => m_ready_d(1),
I2 => \^aa_sa_awvalid\,
O => m_axi_awvalid(1)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555554FFFFFFFF"
)
port map (
I0 => \^m_ready_d_reg[1]\,
I1 => m_ready_d(0),
I2 => \^aa_mi_awtarget_hot\(2),
I3 => \^aa_mi_awtarget_hot\(1),
I4 => \^aa_mi_awtarget_hot\(0),
I5 => aresetn_d,
O => \m_ready_d_reg[0]\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => m_ready_d(0),
I1 => \^aa_mi_awtarget_hot\(2),
I2 => \^aa_mi_awtarget_hot\(1),
I3 => \^aa_mi_awtarget_hot\(0),
O => \m_ready_d_reg[1]_0\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000777"
)
port map (
I0 => m_axi_awready(1),
I1 => \^aa_mi_awtarget_hot\(1),
I2 => mi_awready_2,
I3 => \^aa_mi_awtarget_hot\(2),
I4 => \m_ready_d[1]_i_4_n_0\,
I5 => m_ready_d(1),
O => \^m_ready_d_reg[1]\
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => m_axi_awready(0),
I1 => \^aa_mi_awtarget_hot\(0),
O => \m_ready_d[1]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
port (
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].w_issuing_cnt_reg[1]\ : out STD_LOGIC;
\chosen_reg[0]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]_0\ : out STD_LOGIC;
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ : out STD_LOGIC;
aresetn_d : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
p_80_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[26]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\ : in STD_LOGIC;
\gen_master_slots[1].w_issuing_cnt_reg[10]\ : in STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_0\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ : in STD_LOGIC;
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_3\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_4\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_38_out : in STD_LOGIC;
p_60_out : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
\m_ready_d_reg[1]_5\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \chosen[0]_i_1__0_n_0\ : STD_LOGIC;
signal \chosen[1]_i_1__0_n_0\ : STD_LOGIC;
signal \chosen[2]_i_1__0_n_0\ : STD_LOGIC;
signal \^chosen_reg[0]_0\ : STD_LOGIC;
signal \^chosen_reg[1]_0\ : STD_LOGIC;
signal \^gen_master_slots[0].w_issuing_cnt_reg[1]\ : STD_LOGIC;
signal \^gen_master_slots[2].w_issuing_cnt_reg[16]\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_24_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_25_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_1_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_1_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_1_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_6_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \chosen[0]_i_1__0\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \chosen[2]_i_1__0\ : label is "soft_lutpair112";
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_4\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[2]_i_1\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_6\ : label is "soft_lutpair111";
begin
SR(0) <= \^sr\(0);
\chosen_reg[0]_0\ <= \^chosen_reg[0]_0\;
\chosen_reg[1]_0\ <= \^chosen_reg[1]_0\;
\gen_master_slots[0].w_issuing_cnt_reg[1]\ <= \^gen_master_slots[0].w_issuing_cnt_reg[1]\;
\gen_master_slots[2].w_issuing_cnt_reg[16]\ <= \^gen_master_slots[2].w_issuing_cnt_reg[16]\;
m_valid_i <= \^m_valid_i\;
\chosen[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(0),
I1 => need_arbitration,
I2 => \^chosen_reg[0]_0\,
O => \chosen[0]_i_1__0_n_0\
);
\chosen[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(1),
I1 => need_arbitration,
I2 => \^chosen_reg[1]_0\,
O => \chosen[1]_i_1__0_n_0\
);
\chosen[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(2),
I1 => need_arbitration,
I2 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
O => \chosen[2]_i_1__0_n_0\
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[0]_i_1__0_n_0\,
Q => \^chosen_reg[0]_0\,
R => \^sr\(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[1]_i_1__0_n_0\,
Q => \^chosen_reg[1]_0\,
R => \^sr\(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[2]_i_1__0_n_0\,
Q => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
R => \^sr\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^chosen_reg[0]_0\,
I1 => p_80_out,
I2 => s_axi_bready(0),
O => \^gen_master_slots[0].w_issuing_cnt_reg[1]\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => s_axi_bready(0),
I1 => \^chosen_reg[1]_0\,
I2 => p_60_out,
O => \gen_master_slots[1].w_issuing_cnt_reg[8]\
);
\gen_master_slots[2].w_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"807F7F00"
)
port map (
I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
I1 => p_38_out,
I2 => s_axi_bready(0),
I3 => \m_ready_d_reg[1]_5\,
I4 => w_issuing_cnt(4),
O => \gen_master_slots[2].w_issuing_cnt_reg[16]_0\
);
\gen_multi_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A956"
)
port map (
I0 => Q(0),
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \m_ready_d_reg[1]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFF1100E"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFE00000000FFFF"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => Q(1),
I3 => Q(2),
I4 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AAAAAAAA999A"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => \m_ready_d_reg[1]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I4 => Q(1),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_0,
I1 => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_4\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_3\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_3,
I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_2\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_1\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \m_ready_d_reg[1]_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00AAAA80AA80AA80"
)
port map (
I0 => s_axi_bready(0),
I1 => \^chosen_reg[0]_0\,
I2 => p_80_out,
I3 => m_valid_i_reg,
I4 => p_38_out,
I5 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\
);
\gen_no_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.m_target_hot_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"1FFF1000"
)
port map (
I0 => \s_axi_awaddr[26]\(0),
I1 => st_aa_awtarget_hot(0),
I2 => \^m_valid_i\,
I3 => aresetn_d,
I4 => aa_mi_awtarget_hot(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000F022"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\,
I3 => \s_axi_awaddr[26]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF40FFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I1 => Q(3),
I2 => \gen_multi_thread.accept_cnt_reg[0]\,
I3 => aa_sa_awvalid,
I4 => s_axi_awvalid(0),
I5 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_25\: unisim.vcomponents.LUT5
generic map(
INIT => X"00020000"
)
port map (
I0 => \^gen_master_slots[0].w_issuing_cnt_reg[1]\,
I1 => w_issuing_cnt(2),
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(0),
I4 => w_issuing_cnt(3),
O => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAAEFEFEFAAEAEA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\,
I2 => st_aa_awtarget_hot(0),
I3 => \gen_master_slots[1].w_issuing_cnt_reg[10]\,
I4 => \s_axi_awaddr[26]\(0),
I5 => \gen_master_slots[2].w_issuing_cnt_reg[16]_1\,
O => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\
);
\last_rr_hot[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF57AA00"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[0]_i_1_n_0\
);
\last_rr_hot[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5F7A0A0"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_3_in,
O => \last_rr_hot[1]_i_1_n_0\
);
\last_rr_hot[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDDF8888"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_4_in,
O => \last_rr_hot[2]_i_1_n_0\
);
\last_rr_hot[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEE00000FEE"
)
port map (
I0 => p_60_out,
I1 => p_38_out,
I2 => \^chosen_reg[0]_0\,
I3 => p_80_out,
I4 => \last_rr_hot[2]_i_6_n_0\,
I5 => s_axi_bready(0),
O => need_arbitration
);
\last_rr_hot[2]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA20222020"
)
port map (
I0 => p_38_out,
I1 => p_60_out,
I2 => \last_rr_hot_reg_n_0_[0]\,
I3 => p_80_out,
I4 => p_4_in,
I5 => p_3_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA0A0A0008"
)
port map (
I0 => p_60_out,
I1 => p_3_in,
I2 => p_80_out,
I3 => p_38_out,
I4 => p_4_in,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(1)
);
\last_rr_hot[2]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A8A8A8A88888A88"
)
port map (
I0 => p_80_out,
I1 => p_4_in,
I2 => p_38_out,
I3 => \last_rr_hot_reg_n_0_[0]\,
I4 => p_60_out,
I5 => p_3_in,
O => next_rr_hot(0)
);
\last_rr_hot[2]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
I1 => p_38_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_60_out,
O => \last_rr_hot[2]_i_6_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[0]_i_1_n_0\,
Q => \last_rr_hot_reg_n_0_[0]\,
R => \^sr\(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[1]_i_1_n_0\,
Q => p_3_in,
R => \^sr\(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[2]_i_1_n_0\,
Q => p_4_in,
S => \^sr\(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
I1 => p_38_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_60_out,
I4 => p_80_out,
I5 => \^chosen_reg[0]_0\,
O => s_axi_bvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 is
port (
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.accept_cnt_reg[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]_0\ : out STD_LOGIC;
\m_payload_i_reg[34]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : in STD_LOGIC;
cmd_push_3 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_3\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_4\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_5\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_74_out : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_54_out : in STD_LOGIC;
p_32_out : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\m_payload_i_reg[46]_0\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[46]_1\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 is
signal \chosen[0]_i_1_n_0\ : STD_LOGIC;
signal \chosen[1]_i_1_n_0\ : STD_LOGIC;
signal \chosen[2]_i_1_n_0\ : STD_LOGIC;
signal \^chosen_reg[1]_0\ : STD_LOGIC;
signal \^gen_multi_thread.accept_cnt_reg[2]\ : STD_LOGIC;
signal \i__carry_i_10_n_0\ : STD_LOGIC;
signal \i__carry_i_11_n_0\ : STD_LOGIC;
signal \i__carry_i_12_n_0\ : STD_LOGIC;
signal \i__carry_i_13_n_0\ : STD_LOGIC;
signal \i__carry_i_14_n_0\ : STD_LOGIC;
signal \i__carry_i_15_n_0\ : STD_LOGIC;
signal \i__carry_i_16_n_0\ : STD_LOGIC;
signal \i__carry_i_5_n_0\ : STD_LOGIC;
signal \i__carry_i_6_n_0\ : STD_LOGIC;
signal \i__carry_i_7_n_0\ : STD_LOGIC;
signal \i__carry_i_8_n_0\ : STD_LOGIC;
signal \i__carry_i_9_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_1__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_1__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_1__0_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^m_payload_i_reg[34]\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal \s_axi_rid[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rid[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rid[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \chosen[0]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \chosen[2]_i_1\ : label is "soft_lutpair79";
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1__0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_2\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_3\ : label is "soft_lutpair78";
begin
\chosen_reg[1]_0\ <= \^chosen_reg[1]_0\;
\gen_multi_thread.accept_cnt_reg[2]\ <= \^gen_multi_thread.accept_cnt_reg[2]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i_reg[34]\ <= \^m_payload_i_reg[34]\;
s_axi_rlast(0) <= \^s_axi_rlast\(0);
\chosen[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(0),
I1 => need_arbitration,
I2 => \^m_payload_i_reg[0]_0\,
O => \chosen[0]_i_1_n_0\
);
\chosen[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(1),
I1 => need_arbitration,
I2 => \^chosen_reg[1]_0\,
O => \chosen[1]_i_1_n_0\
);
\chosen[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(2),
I1 => need_arbitration,
I2 => \^m_payload_i_reg[34]\,
O => \chosen[2]_i_1_n_0\
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[0]_i_1_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => SR(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[1]_i_1_n_0\,
Q => \^chosen_reg[1]_0\,
R => SR(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[2]_i_1_n_0\,
Q => \^m_payload_i_reg[34]\,
R => SR(0)
);
\gen_multi_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A659"
)
port map (
I0 => Q(0),
I1 => \gen_no_arbiter.s_ready_i_reg[0]\,
I2 => \^gen_multi_thread.accept_cnt_reg[2]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFF4400B"
)
port map (
I0 => \^gen_multi_thread.accept_cnt_reg[2]\,
I1 => \gen_no_arbiter.s_ready_i_reg[0]\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => Q(1),
I3 => Q(2),
I4 => \^gen_multi_thread.accept_cnt_reg[2]\,
I5 => \gen_no_arbiter.s_ready_i_reg[0]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAAAAAAAAA9A99"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => \^gen_multi_thread.accept_cnt_reg[2]\,
I3 => \gen_no_arbiter.s_ready_i_reg[0]\,
I4 => Q(1),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_0,
I1 => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0),
I3 => \^gen_multi_thread.accept_cnt_reg[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_5\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_4\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_3,
I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\,
I2 => CO(0),
I3 => \^gen_multi_thread.accept_cnt_reg[2]\,
O => E(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_3\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_2\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8880000"
)
port map (
I0 => \^s_axi_rlast\(0),
I1 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I2 => \^m_payload_i_reg[0]_0\,
I3 => p_74_out,
I4 => s_axi_rready(0),
O => \^gen_multi_thread.accept_cnt_reg[2]\
);
\i__carry_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(9),
I2 => \m_payload_i_reg[46]_0\(22),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(22),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_10_n_0\
);
\i__carry_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(5),
I2 => \m_payload_i_reg[46]_0\(18),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(18),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_11_n_0\
);
\i__carry_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(17),
I2 => \m_payload_i_reg[46]_1\(4),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]_0\(17),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => \i__carry_i_12_n_0\
);
\i__carry_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(19),
I2 => \m_payload_i_reg[46]_1\(6),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(19),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_13_n_0\
);
\i__carry_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(2),
I2 => \m_payload_i_reg[46]_0\(15),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(15),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_14_n_0\
);
\i__carry_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(14),
I2 => \m_payload_i_reg[46]_1\(1),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(14),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_15_n_0\
);
\i__carry_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(3),
I2 => \m_payload_i_reg[46]_0\(16),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(16),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_16_n_0\
);
\i__carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(3)
);
\i__carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2)
);
\i__carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1)
);
\i__carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0)
);
\i__carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(11),
I2 => \m_payload_i_reg[46]\(24),
I3 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I4 => \m_payload_i_reg[46]_0\(24),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => \i__carry_i_5_n_0\
);
\i__carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(23),
I2 => \m_payload_i_reg[46]_1\(10),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(23),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_6_n_0\
);
\i__carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(25),
I2 => \m_payload_i_reg[46]_1\(12),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(25),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_7_n_0\
);
\i__carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(8),
I2 => \m_payload_i_reg[46]_0\(21),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(21),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_8_n_0\
);
\i__carry_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(7),
I2 => \m_payload_i_reg[46]_0\(20),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(20),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_9_n_0\
);
\last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF57AA00"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[0]_i_1__0_n_0\
);
\last_rr_hot[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5F7A0A0"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_3_in,
O => \last_rr_hot[1]_i_1__0_n_0\
);
\last_rr_hot[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDDF8888"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_4_in,
O => \last_rr_hot[2]_i_1__0_n_0\
);
\last_rr_hot[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABBBABBBABBBAB88"
)
port map (
I0 => s_axi_rready(0),
I1 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I2 => \^m_payload_i_reg[0]_0\,
I3 => p_74_out,
I4 => p_54_out,
I5 => p_32_out,
O => need_arbitration
);
\last_rr_hot[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA20222020"
)
port map (
I0 => p_32_out,
I1 => p_54_out,
I2 => \last_rr_hot_reg_n_0_[0]\,
I3 => p_74_out,
I4 => p_4_in,
I5 => p_3_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA0A0A0008"
)
port map (
I0 => p_54_out,
I1 => p_3_in,
I2 => p_74_out,
I3 => p_32_out,
I4 => p_4_in,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(1)
);
\last_rr_hot[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A8A8A8A88888A88"
)
port map (
I0 => p_74_out,
I1 => p_4_in,
I2 => p_32_out,
I3 => \last_rr_hot_reg_n_0_[0]\,
I4 => p_54_out,
I5 => p_3_in,
O => next_rr_hot(0)
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[0]_i_1__0_n_0\,
Q => \last_rr_hot_reg_n_0_[0]\,
R => SR(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[1]_i_1__0_n_0\,
Q => p_3_in,
R => SR(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[2]_i_1__0_n_0\,
Q => p_4_in,
S => SR(0)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B3"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_74_out,
I2 => s_axi_rready(0),
O => \m_payload_i_reg[0]\(0)
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => s_axi_rready(0),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
O => \m_payload_i_reg[34]_0\(0)
);
\p_10_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
\p_10_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
\p_10_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
\p_10_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
\p_12_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
\p_12_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
\p_12_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
\p_12_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
\p_14_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \i__carry_i_7_n_0\,
O => S(3)
);
\p_14_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \i__carry_i_10_n_0\,
O => S(2)
);
\p_14_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \i__carry_i_13_n_0\,
O => S(1)
);
\p_14_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \i__carry_i_16_n_0\,
O => S(0)
);
\p_2_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
\p_2_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
\p_2_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
\p_2_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
\p_4_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
\p_4_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
\p_4_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
\p_4_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
\p_6_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
\p_6_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
\p_6_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
\p_6_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
\p_8_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(3)
);
\p_8_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(2)
);
\p_8_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(1)
);
\p_8_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(0),
O => s_axi_rdata(0)
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(5),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(5),
O => s_axi_rdata(5)
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(6),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(6),
O => s_axi_rdata(6)
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(7),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(7),
O => s_axi_rdata(7)
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(8),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(8),
O => s_axi_rdata(8)
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(9),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(9),
O => s_axi_rdata(9)
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(10),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(10),
O => s_axi_rdata(10)
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(11),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(11),
O => s_axi_rdata(11)
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(1),
O => s_axi_rdata(1)
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(2),
O => s_axi_rdata(2)
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(3),
O => s_axi_rdata(3)
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(4),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(4),
O => s_axi_rdata(4)
);
\s_axi_rid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(14),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(1),
I4 => \m_payload_i_reg[46]_0\(14),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(0)
);
\s_axi_rid[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(24),
I2 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I3 => \m_payload_i_reg[46]\(24),
I4 => \m_payload_i_reg[46]_1\(11),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(10)
);
\s_axi_rid[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(25),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(12),
I4 => \m_payload_i_reg[46]_0\(25),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(11)
);
\s_axi_rid[11]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^m_payload_i_reg[34]\,
I1 => p_32_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_54_out,
O => \s_axi_rid[11]_INST_0_i_1_n_0\
);
\s_axi_rid[11]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8FFF"
)
port map (
I0 => \^chosen_reg[1]_0\,
I1 => p_54_out,
I2 => \^m_payload_i_reg[34]\,
I3 => p_32_out,
O => \s_axi_rid[11]_INST_0_i_2_n_0\
);
\s_axi_rid[11]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8FFF"
)
port map (
I0 => \^m_payload_i_reg[34]\,
I1 => p_32_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_54_out,
O => \s_axi_rid[11]_INST_0_i_3_n_0\
);
\s_axi_rid[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(15),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(15),
I4 => \m_payload_i_reg[46]_1\(2),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(1)
);
\s_axi_rid[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(16),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(16),
I4 => \m_payload_i_reg[46]_1\(3),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(2)
);
\s_axi_rid[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(17),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(4),
I4 => \m_payload_i_reg[46]\(17),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => s_axi_rid(3)
);
\s_axi_rid[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(18),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(18),
I4 => \m_payload_i_reg[46]_1\(5),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(4)
);
\s_axi_rid[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(19),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(6),
I4 => \m_payload_i_reg[46]_0\(19),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(5)
);
\s_axi_rid[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(20),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(20),
I4 => \m_payload_i_reg[46]_1\(7),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(6)
);
\s_axi_rid[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(21),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(21),
I4 => \m_payload_i_reg[46]_1\(8),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(7)
);
\s_axi_rid[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(22),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(22),
I4 => \m_payload_i_reg[46]_1\(9),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(8)
);
\s_axi_rid[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(23),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(10),
I4 => \m_payload_i_reg[46]_0\(23),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(9)
);
\s_axi_rlast[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(0),
I2 => \m_payload_i_reg[46]\(13),
I3 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I4 => \m_payload_i_reg[46]_0\(13),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => \^s_axi_rlast\(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FEAEAEA00EAEAEA"
)
port map (
I0 => \m_payload_i_reg[46]\(12),
I1 => p_32_out,
I2 => \^m_payload_i_reg[34]\,
I3 => p_54_out,
I4 => \^chosen_reg[1]_0\,
I5 => \m_payload_i_reg[46]_0\(12),
O => s_axi_rresp(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => p_54_out,
I1 => \^chosen_reg[1]_0\,
I2 => p_32_out,
I3 => \^m_payload_i_reg[34]\,
I4 => \^m_payload_i_reg[0]_0\,
I5 => p_74_out,
O => s_axi_rvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_awready_2 : out STD_LOGIC;
p_14_in : out STD_LOGIC;
p_21_in : out STD_LOGIC;
p_15_in : out STD_LOGIC;
p_17_in : out STD_LOGIC;
\gen_axi.write_cs_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_arready_2 : out STD_LOGIC;
\gen_axi.s_axi_arready_i_reg_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_target_hot_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : in STD_LOGIC;
mi_rready_2 : in STD_LOGIC;
\gen_no_arbiter.m_mesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
\gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC;
mi_bready_2 : in STD_LOGIC;
\m_ready_d_reg[1]\ : in STD_LOGIC;
\storage_data1_reg[0]\ : in STD_LOGIC;
s_axi_rlast_i0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aresetn_d : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave : entity is "axi_crossbar_v2_1_14_decerr_slave";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \^gen_axi.s_axi_arready_i_reg_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bid_i[11]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^gen_axi.write_cs_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^mi_arready_2\ : STD_LOGIC;
signal \^mi_awready_2\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_14_in\ : STD_LOGIC;
signal \^p_15_in\ : STD_LOGIC;
signal \^p_17_in\ : STD_LOGIC;
signal \^p_21_in\ : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_3\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_4\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair15";
begin
\gen_axi.s_axi_arready_i_reg_0\ <= \^gen_axi.s_axi_arready_i_reg_0\;
\gen_axi.write_cs_reg[1]_0\(0) <= \^gen_axi.write_cs_reg[1]_0\(0);
mi_arready_2 <= \^mi_arready_2\;
mi_awready_2 <= \^mi_awready_2\;
p_14_in <= \^p_14_in\;
p_15_in <= \^p_15_in\;
p_17_in <= \^p_17_in\;
p_21_in <= \^p_21_in\;
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg\(0),
I1 => \^p_15_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(12),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \gen_axi.read_cnt_reg\(0),
I1 => \gen_axi.read_cnt_reg__0\(1),
I2 => \^p_15_in\,
I3 => \gen_no_arbiter.m_mesg_i_reg[51]\(13),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A9FFA900"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(2),
I1 => \gen_axi.read_cnt_reg__0\(1),
I2 => \gen_axi.read_cnt_reg\(0),
I3 => \^p_15_in\,
I4 => \gen_no_arbiter.m_mesg_i_reg[51]\(14),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA9FFFFAAA90000"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(3),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg\(0),
I3 => \gen_axi.read_cnt_reg__0\(1),
I4 => \^p_15_in\,
I5 => \gen_no_arbiter.m_mesg_i_reg[51]\(15),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FACAFAFACACACACA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(16),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \^p_15_in\,
I3 => \gen_axi.read_cnt_reg__0\(3),
I4 => \gen_axi.read_cnt[4]_i_2_n_0\,
I5 => \gen_axi.read_cnt_reg__0\(4),
O => p_0_in(4)
);
\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(1),
I1 => \gen_axi.read_cnt_reg\(0),
I2 => \gen_axi.read_cnt_reg__0\(2),
O => \gen_axi.read_cnt[4]_i_2_n_0\
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3CAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(17),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(5),
I3 => \^p_15_in\,
O => p_0_in(5)
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE2E22E2"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(18),
I1 => \^p_15_in\,
I2 => \gen_axi.read_cnt[7]_i_3_n_0\,
I3 => \gen_axi.read_cnt_reg__0\(5),
I4 => \gen_axi.read_cnt_reg__0\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \^mi_arready_2\,
I1 => \gen_no_arbiter.m_target_hot_i_reg[2]\(0),
I2 => aa_mi_arvalid,
I3 => \^p_15_in\,
I4 => mi_rready_2,
I5 => \^gen_axi.s_axi_arready_i_reg_0\,
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B874B8"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(7),
I1 => \^p_15_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(19),
I3 => \gen_axi.read_cnt[7]_i_3_n_0\,
I4 => \gen_axi.read_cnt_reg__0\(5),
I5 => \gen_axi.read_cnt_reg__0\(6),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \gen_axi.read_cnt_reg\(0),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0\(4),
I4 => \gen_axi.read_cnt_reg__0\(3),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg__0\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg__0\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg__0\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg__0\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg__0\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg__0\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg__0\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080FF80FF80FF80"
)
port map (
I0 => \^mi_arready_2\,
I1 => \gen_no_arbiter.m_target_hot_i_reg[2]\(0),
I2 => aa_mi_arvalid,
I3 => \^p_15_in\,
I4 => mi_rready_2,
I5 => \^gen_axi.s_axi_arready_i_reg_0\,
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^p_15_in\,
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FBBB0000"
)
port map (
I0 => \^mi_arready_2\,
I1 => \^p_15_in\,
I2 => mi_rready_2,
I3 => \^gen_axi.s_axi_arready_i_reg_0\,
I4 => aresetn_d,
I5 => E(0),
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \gen_axi.read_cnt[7]_i_3_n_0\,
I1 => \gen_axi.read_cnt_reg__0\(5),
I2 => \gen_axi.read_cnt_reg__0\(6),
I3 => \gen_axi.read_cnt_reg__0\(7),
O => \^gen_axi.s_axi_arready_i_reg_0\
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready_2\,
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7F70F000F0F"
)
port map (
I0 => \gen_no_arbiter.m_valid_i_reg\,
I1 => aa_mi_awtarget_hot(0),
I2 => write_cs(0),
I3 => mi_bready_2,
I4 => \^gen_axi.write_cs_reg[1]_0\(0),
I5 => \^mi_awready_2\,
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready_2\,
R => SR(0)
);
\gen_axi.s_axi_bid_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => write_cs(0),
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => \^mi_awready_2\,
I3 => aa_mi_awtarget_hot(0),
I4 => aa_sa_awvalid,
I5 => m_ready_d(0),
O => \gen_axi.s_axi_bid_i[11]_i_1_n_0\
);
\gen_axi.s_axi_bid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(0),
Q => Q(0),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(10),
Q => Q(10),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(11),
Q => Q(11),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(1),
Q => Q(1),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(2),
Q => Q(2),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(3),
Q => Q(3),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(4),
Q => Q(4),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(5),
Q => Q(5),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(6),
Q => Q(6),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(7),
Q => Q(7),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(8),
Q => Q(8),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(9),
Q => Q(9),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFFA888"
)
port map (
I0 => \storage_data1_reg[0]\,
I1 => write_cs(0),
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => mi_bready_2,
I4 => \^p_21_in\,
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => \^p_21_in\,
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(0),
Q => \skid_buffer_reg[46]\(0),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(10),
Q => \skid_buffer_reg[46]\(10),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(11),
Q => \skid_buffer_reg[46]\(11),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(1),
Q => \skid_buffer_reg[46]\(1),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(2),
Q => \skid_buffer_reg[46]\(2),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(3),
Q => \skid_buffer_reg[46]\(3),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(4),
Q => \skid_buffer_reg[46]\(4),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(5),
Q => \skid_buffer_reg[46]\(5),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(6),
Q => \skid_buffer_reg[46]\(6),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(7),
Q => \skid_buffer_reg[46]\(7),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(8),
Q => \skid_buffer_reg[46]\(8),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(9),
Q => \skid_buffer_reg[46]\(9),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBA8888888A"
)
port map (
I0 => s_axi_rlast_i0,
I1 => E(0),
I2 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
I3 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I4 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
I5 => \^p_17_in\,
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(7),
I1 => \gen_axi.read_cnt_reg__0\(6),
I2 => \gen_axi.read_cnt_reg__0\(5),
O => \gen_axi.s_axi_rlast_i_i_3_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^p_15_in\,
I1 => mi_rready_2,
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(3),
I1 => \gen_axi.read_cnt_reg__0\(4),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0\(2),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => \^p_17_in\,
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFF0202"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => write_cs(0),
I3 => \storage_data1_reg[0]\,
I4 => \^p_14_in\,
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => \^p_14_in\,
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0252"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => write_cs(0),
I3 => \storage_data1_reg[0]\,
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF10FA10"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => mi_bready_2,
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => write_cs(0),
I4 => \storage_data1_reg[0]\,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => \^gen_axi.write_cs_reg[1]_0\(0),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter is
port (
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC;
ss_wr_awvalid : out STD_LOGIC;
ss_aa_awready : in STD_LOGIC;
ss_wr_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter : entity is "axi_crossbar_v2_1_14_splitter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair141";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\FSM_onehot_state[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
O => ss_wr_awvalid
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"111F"
)
port map (
I0 => \^m_ready_d\(1),
I1 => ss_wr_awready,
I2 => \^m_ready_d\(0),
I3 => ss_aa_awready,
O => \gen_multi_thread.accept_cnt_reg[3]\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0302030000000000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
I2 => ss_wr_awready,
I3 => \^m_ready_d\(0),
I4 => ss_aa_awready,
I5 => aresetn_d,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000EC00000000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
I2 => ss_wr_awready,
I3 => \^m_ready_d\(0),
I4 => ss_aa_awready,
I5 => aresetn_d,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => ss_aa_awready,
I1 => \^m_ready_d\(0),
I2 => ss_wr_awready,
I3 => \^m_ready_d\(1),
O => s_axi_awready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 is
port (
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
aa_sa_awvalid : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\m_ready_d_reg[0]_0\ : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[1]\ : in STD_LOGIC;
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[0]_1\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 : entity is "axi_crossbar_v2_1_14_splitter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEEEEEEC"
)
port map (
I0 => aa_sa_awvalid,
I1 => \^m_ready_d\(0),
I2 => aa_mi_awtarget_hot(2),
I3 => aa_mi_awtarget_hot(1),
I4 => aa_mi_awtarget_hot(0),
I5 => \m_ready_d_reg[0]_1\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => aa_sa_awvalid,
I1 => \^m_ready_d\(1),
I2 => aresetn_d,
I3 => \m_ready_d_reg[0]_0\,
I4 => \gen_no_arbiter.m_target_hot_i_reg[1]\,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
push : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => st_aa_awtarget_enc(0),
Q => \storage_data1_reg[0]\,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ is
port (
push : out STD_LOGIC;
\storage_data1_reg[1]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
\gen_rep[0].fifoaddr_reg[0]\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
load_s1 : in STD_LOGIC;
\storage_data1_reg[1]_0\ : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_14_in : in STD_LOGIC;
\storage_data1_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ is
signal \FSM_onehot_state[3]_i_6_n_0\ : STD_LOGIC;
signal \^gen_rep[0].fifoaddr_reg[0]\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal \^push\ : STD_LOGIC;
signal \^s_ready_i_reg\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_rep[0].fifoaddr_reg[0]\ <= \^gen_rep[0].fifoaddr_reg[0]\;
push <= \^push\;
s_ready_i_reg <= \^s_ready_i_reg\;
\FSM_onehot_state[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \FSM_onehot_state[3]_i_6_n_0\,
I1 => s_axi_wlast(0),
I2 => s_axi_wvalid(0),
I3 => m_avalid,
O => \^gen_rep[0].fifoaddr_reg[0]\
);
\FSM_onehot_state[3]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"F035FF35"
)
port map (
I0 => m_axi_wready(0),
I1 => p_14_in,
I2 => \storage_data1_reg[1]_0\,
I3 => \storage_data1_reg[0]\,
I4 => m_axi_wready(1),
O => \FSM_onehot_state[3]_i_6_n_0\
);
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => \^push\,
CLK => aclk,
D => D(0),
Q => p_2_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg\,
O => \^push\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0DFFFFFFDDFFFF"
)
port map (
I0 => out0(1),
I1 => \^gen_rep[0].fifoaddr_reg[0]\,
I2 => s_ready_i_reg_0,
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => out0(0),
O => \^s_ready_i_reg\
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F011FFFFF0110000"
)
port map (
I0 => st_aa_awtarget_enc(0),
I1 => st_aa_awtarget_hot(0),
I2 => p_2_out,
I3 => out0(0),
I4 => load_s1,
I5 => \storage_data1_reg[1]_0\,
O => \storage_data1_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
\m_payload_i_reg[2]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
mi_bready_2 : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 6 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_21_in : in STD_LOGIC;
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[13]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^mi_bready_2\ : STD_LOGIC;
signal \s_axi_bid[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bid[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bid[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_ready_i_i_1__5_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal st_mr_bid : STD_LOGIC_VECTOR ( 35 downto 24 );
begin
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\;
\m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
mi_bready_2 <= \^mi_bready_2\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => '0'
);
\gen_no_arbiter.s_ready_i[0]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => w_issuing_cnt(0),
I1 => s_axi_bready(0),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\i__carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(1),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(8),
Q => st_mr_bid(32),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(9),
Q => st_mr_bid(33),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(10),
Q => Q(4),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(11),
Q => st_mr_bid(35),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(0),
Q => st_mr_bid(24),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(1),
Q => Q(0),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(2),
Q => Q(1),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(3),
Q => Q(2),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(4),
Q => st_mr_bid(28),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(5),
Q => Q(3),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(6),
Q => st_mr_bid(30),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(7),
Q => st_mr_bid(31),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => p_21_in,
I1 => \^mi_bready_2\,
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[2]_0\,
I4 => chosen(0),
O => \m_valid_i_i_1__1_n_0\
);
\m_valid_i_i_1__5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg_0\,
O => \^m_valid_i_reg_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^m_payload_i_reg[2]_0\,
R => \^m_valid_i_reg_0\
);
p_10_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(1),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
p_12_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(1),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
p_14_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(1),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => S(0)
);
p_2_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(1),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
p_4_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(1),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
p_6_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(1),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
p_8_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(1),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\s_axi_bid[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
O => s_axi_bid(0)
);
\s_axi_bid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(0),
I1 => st_mr_bid(24),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(7),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\
);
\s_axi_bid[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
O => s_axi_bid(6)
);
\s_axi_bid[11]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(6),
I1 => st_mr_bid(35),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(13),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\
);
\s_axi_bid[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\,
O => s_axi_bid(1)
);
\s_axi_bid[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(1),
I1 => st_mr_bid(28),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(8),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\
);
\s_axi_bid[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_bid[6]_INST_0_i_1_n_0\,
O => s_axi_bid(2)
);
\s_axi_bid[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(2),
I1 => st_mr_bid(30),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(9),
O => \s_axi_bid[6]_INST_0_i_1_n_0\
);
\s_axi_bid[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
O => s_axi_bid(3)
);
\s_axi_bid[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(3),
I1 => st_mr_bid(31),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(10),
O => \s_axi_bid[7]_INST_0_i_1_n_0\
);
\s_axi_bid[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => s_axi_bid(4)
);
\s_axi_bid[8]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F5303030F53F3F3F"
)
port map (
I0 => st_mr_bid(32),
I1 => \m_payload_i_reg[13]_0\(11),
I2 => m_valid_i_reg_1,
I3 => \^m_payload_i_reg[2]_0\,
I4 => chosen(0),
I5 => \m_payload_i_reg[13]_0\(4),
O => \s_axi_bid[8]_INST_0_i_1_n_0\
);
\s_axi_bid[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
O => s_axi_bid(5)
);
\s_axi_bid[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(5),
I1 => st_mr_bid(33),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(12),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\
);
\s_ready_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
I1 => p_21_in,
I2 => chosen(0),
I3 => s_axi_bready(0),
I4 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__5_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__5_n_0\,
Q => \^mi_bready_2\,
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[12]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_38_out : in STD_LOGIC;
\m_payload_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ is
signal \^gen_multi_thread.accept_cnt_reg[3]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^p_1_in\ : STD_LOGIC;
signal \s_ready_i_i_2__0_n_0\ : STD_LOGIC;
signal st_mr_bid : STD_LOGIC_VECTOR ( 22 downto 13 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 4 downto 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_axi_bid[11]_INST_0_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \s_ready_i_i_2__0\ : label is "soft_lutpair44";
begin
\gen_multi_thread.accept_cnt_reg[3]\ <= \^gen_multi_thread.accept_cnt_reg[3]\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\;
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
p_1_in <= \^p_1_in\;
\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(1),
I1 => aresetn,
O => \aresetn_d_reg[1]\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => p_0_in(1),
R => '0'
);
\gen_no_arbiter.s_ready_i[0]_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000700000000"
)
port map (
I0 => \^gen_multi_thread.accept_cnt_reg[3]\,
I1 => s_axi_bready(0),
I2 => Q(2),
I3 => Q(1),
I4 => Q(0),
I5 => Q(3),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(0),
Q => st_mr_bmesg(3),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(4),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(5),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(12),
Q => st_mr_bid(22),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(6),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(1),
Q => st_mr_bmesg(4),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(0),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(3),
Q => st_mr_bid(13),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(4),
Q => st_mr_bid(14),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(5),
Q => st_mr_bid(15),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(1),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(7),
Q => st_mr_bid(17),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(2),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(3),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => chosen(0),
I4 => \^m_payload_i_reg[0]_0\,
O => \m_valid_i_i_1__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]_0\
);
\s_axi_bid[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\,
O => s_axi_bid(4)
);
\s_axi_bid[10]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0353535FF353535"
)
port map (
I0 => \m_payload_i_reg[12]_0\(4),
I1 => st_mr_bid(22),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(9),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\
);
\s_axi_bid[11]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => chosen(0),
O => \^gen_multi_thread.accept_cnt_reg[3]\
);
\s_axi_bid[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
O => s_axi_bid(0)
);
\s_axi_bid[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0353535FF353535"
)
port map (
I0 => \m_payload_i_reg[12]_0\(0),
I1 => st_mr_bid(13),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(5),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\
);
\s_axi_bid[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\,
O => s_axi_bid(1)
);
\s_axi_bid[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0535353FF535353"
)
port map (
I0 => st_mr_bid(14),
I1 => \m_payload_i_reg[12]_0\(1),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(6),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\
);
\s_axi_bid[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
O => s_axi_bid(2)
);
\s_axi_bid[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0535353FF535353"
)
port map (
I0 => st_mr_bid(15),
I1 => \m_payload_i_reg[12]_0\(2),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(7),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\
);
\s_axi_bid[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
O => s_axi_bid(3)
);
\s_axi_bid[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0353535FF353535"
)
port map (
I0 => \m_payload_i_reg[12]_0\(3),
I1 => st_mr_bid(17),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(8),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FBFBFBF3F808080"
)
port map (
I0 => st_mr_bmesg(3),
I1 => chosen(0),
I2 => \^m_payload_i_reg[0]_0\,
I3 => chosen(1),
I4 => p_38_out,
I5 => \m_payload_i_reg[1]_0\(0),
O => s_axi_bresp(0)
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0CCCFAAAFAAAFAAA"
)
port map (
I0 => \m_payload_i_reg[1]_0\(1),
I1 => st_mr_bmesg(4),
I2 => chosen(1),
I3 => p_38_out,
I4 => \^m_payload_i_reg[0]_0\,
I5 => chosen(0),
O => s_axi_bresp(1)
);
\s_ready_i_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => \^p_1_in\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => chosen(0),
I4 => \aresetn_d_reg[1]_1\,
O => \s_ready_i_i_2__0_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_2__0_n_0\,
Q => \^m_axi_bready\(0),
R => \^p_1_in\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ is
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__4_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(9),
R => '0'
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => chosen(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => s_axi_bready(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_2_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => chosen(0),
I3 => s_axi_bready(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__4_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__4_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\skid_buffer_reg[34]_0\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
p_15_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_17_in : in STD_LOGIC;
\gen_axi.s_axi_arready_i_reg\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 34 );
signal \^skid_buffer_reg[34]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__1\ : label is "soft_lutpair69";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0);
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\skid_buffer_reg[34]_0\ <= \^skid_buffer_reg[34]_0\;
\gen_master_slots[2].r_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"955555552AAAAAAA"
)
port map (
I0 => \gen_axi.s_axi_arready_i_reg\,
I1 => s_axi_rready(0),
I2 => chosen_0(0),
I3 => \^m_valid_i_reg_0\,
I4 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I5 => r_issuing_cnt(0),
O => \gen_master_slots[2].r_issuing_cnt_reg[16]\
);
\gen_no_arbiter.s_ready_i[0]_i_23__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FF2020000F202"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\,
I2 => st_aa_artarget_hot(0),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
I4 => st_aa_artarget_hot(1),
I5 => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_25__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I1 => \^m_valid_i_reg_0\,
I2 => chosen_0(0),
I3 => s_axi_rready(0),
O => \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_17_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(0),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(1),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(2),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(3),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(4),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[40]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(5),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(6),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(7),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(8),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(9),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(10),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(11),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_valid_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF70FFFF"
)
port map (
I0 => s_axi_rready(0),
I1 => chosen_0(0),
I2 => \^m_valid_i_reg_0\,
I3 => p_15_in,
I4 => \^skid_buffer_reg[34]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => p_15_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => s_axi_rready(0),
I3 => chosen_0(0),
I4 => \^m_valid_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[34]_0\,
R => p_1_in
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => p_17_in,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ is
port (
s_ready_i_reg_0 : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 25 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[32]_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 );
p_32_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ is
signal \^gen_master_slots[1].r_issuing_cnt_reg[8]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 25 downto 0 );
signal \^m_axi_rready[1]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in_0 : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 68 downto 35 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_6\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__3\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_valid_i_i_1__3\ : label is "soft_lutpair45";
begin
\gen_master_slots[1].r_issuing_cnt_reg[8]\ <= \^gen_master_slots[1].r_issuing_cnt_reg[8]\;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0);
\m_axi_rready[1]\ <= \^m_axi_rready[1]\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\gen_master_slots[1].r_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
I1 => \^s_ready_i_reg_0\,
I2 => chosen_0(0),
I3 => s_axi_rready(0),
O => \^gen_master_slots[1].r_issuing_cnt_reg[8]\
);
\gen_master_slots[1].r_issuing_cnt[11]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => chosen_0(0),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\
);
\gen_no_arbiter.s_ready_i[0]_i_27__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(0),
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(1),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(2),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3),
I4 => \^gen_master_slots[1].r_issuing_cnt_reg[8]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => s_axi_rready(0),
I2 => chosen_0(0),
O => p_1_in_0
);
\m_payload_i[46]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(12),
Q => st_mr_rmesg(50),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(13),
Q => st_mr_rmesg(51),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(14),
Q => st_mr_rmesg(52),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(15),
Q => st_mr_rmesg(53),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(16),
Q => st_mr_rmesg(54),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(17),
Q => st_mr_rmesg(55),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(18),
Q => st_mr_rmesg(56),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(1),
Q => st_mr_rmesg(39),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(21),
Q => st_mr_rmesg(59),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(23),
Q => st_mr_rmesg(61),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(24),
Q => st_mr_rmesg(62),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(25),
Q => st_mr_rmesg(63),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(26),
Q => st_mr_rmesg(64),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(28),
Q => st_mr_rmesg(66),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(29),
Q => st_mr_rmesg(67),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(2),
Q => st_mr_rmesg(40),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(30),
Q => st_mr_rmesg(68),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(32),
Q => st_mr_rmesg(35),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(3),
Q => st_mr_rmesg(41),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(5),
Q => st_mr_rmesg(43),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(7),
Q => st_mr_rmesg(45),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_valid_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF2AFFFF"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => s_axi_rready(0),
I2 => chosen_0(0),
I3 => m_axi_rvalid(0),
I4 => \^m_axi_rready[1]\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(50),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(5),
O => s_axi_rdata(5)
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(51),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(6),
O => s_axi_rdata(6)
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(52),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(7),
O => s_axi_rdata(7)
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(53),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(8),
O => s_axi_rdata(8)
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(54),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(9),
O => s_axi_rdata(9)
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(55),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(10),
O => s_axi_rdata(10)
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(56),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(11),
O => s_axi_rdata(11)
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(39),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(0),
O => s_axi_rdata(0)
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(59),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(12),
O => s_axi_rdata(12)
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(61),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(13),
O => s_axi_rdata(13)
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(62),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(14),
O => s_axi_rdata(14)
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(63),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(15),
O => s_axi_rdata(15)
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(64),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(16),
O => s_axi_rdata(16)
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(66),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(17),
O => s_axi_rdata(17)
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(67),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(18),
O => s_axi_rdata(18)
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(40),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(1),
O => s_axi_rdata(1)
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(68),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(19),
O => s_axi_rdata(19)
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(41),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(2),
O => s_axi_rdata(2)
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(43),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(3),
O => s_axi_rdata(3)
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(45),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(4),
O => s_axi_rdata(4)
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFFACCCACCCACCC"
)
port map (
I0 => st_mr_rmesg(35),
I1 => \m_payload_i_reg[32]_0\(20),
I2 => \^s_ready_i_reg_0\,
I3 => chosen_0(0),
I4 => p_32_out,
I5 => chosen_0(1),
O => s_axi_rresp(0)
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F4F4F"
)
port map (
I0 => m_axi_rvalid(0),
I1 => \^m_axi_rready[1]\,
I2 => \^s_ready_i_reg_0\,
I3 => s_axi_rready(0),
I4 => chosen_0(0),
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^m_axi_rready[1]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ is
signal \^gen_master_slots[0].r_issuing_cnt_reg[0]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[0]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair39";
begin
\gen_master_slots[0].r_issuing_cnt_reg[0]\ <= \^gen_master_slots[0].r_issuing_cnt_reg[0]\;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[0]\ <= \^m_axi_rready[0]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => s_axi_rready(0),
I2 => \^m_valid_i_reg_0\,
I3 => chosen_0(0),
O => \^gen_master_slots[0].r_issuing_cnt_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_26__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => Q(2),
I3 => Q(3),
I4 => \^gen_master_slots[0].r_issuing_cnt_reg[0]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4CFFFF"
)
port map (
I0 => chosen_0(0),
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_rready(0),
I3 => m_axi_rvalid(0),
I4 => \^m_axi_rready[0]\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FF44FF"
)
port map (
I0 => m_axi_rvalid(0),
I1 => \^m_axi_rready[0]\,
I2 => chosen_0(0),
I3 => \^m_valid_i_reg_0\,
I4 => s_axi_rready(0),
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^m_axi_rready[0]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor is
port (
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[2]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
st_aa_artarget_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
chosen : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\s_axi_araddr[25]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC;
\s_axi_araddr[25]_0\ : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC;
\s_axi_araddr[31]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
p_74_out : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_54_out : in STD_LOGIC;
p_32_out : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\m_payload_i_reg[46]_0\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\m_payload_i_reg[46]_1\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor : entity is "axi_crossbar_v2_1_14_si_transactor";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor is
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 57 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal aid_match_00_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal aid_match_10_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal aid_match_20_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal aid_match_30_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal aid_match_40_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal aid_match_50_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal aid_match_60_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal aid_match_70_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst_n_0\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_1\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_10\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_11\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_12\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_2\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_20\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_21\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_22\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_23\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_24\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_25\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_26\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_27\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_28\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_29\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_30\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_31\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_32\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_33\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_34\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_35\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_36\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_37\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_38\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_39\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_4\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_40\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_41\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_42\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_43\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_44\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_45\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_46\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_47\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_48\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_49\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_50\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_51\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_6\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_7\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_8\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_9\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_13_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9_n_0\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal \^st_aa_artarget_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[2]_i_1__0\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1__0\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_24__0\ : label is "soft_lutpair99";
begin
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\;
m_valid_i <= \^m_valid_i\;
st_aa_artarget_hot(0) <= \^st_aa_artarget_hot\(0);
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_00_carry_i_1_n_0,
S(2) => aid_match_00_carry_i_2_n_0,
S(1) => aid_match_00_carry_i_3_n_0,
S(0) => aid_match_00_carry_i_4_n_0
);
aid_match_00_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
O => aid_match_00_carry_i_1_n_0
);
aid_match_00_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
I1 => \s_axi_araddr[31]\(7),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(6),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
O => aid_match_00_carry_i_2_n_0
);
aid_match_00_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(4),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
I4 => \s_axi_araddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
O => aid_match_00_carry_i_3_n_0
);
aid_match_00_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
I1 => \s_axi_araddr[31]\(0),
I2 => \s_axi_araddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
I4 => \s_axi_araddr[31]\(1),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
O => aid_match_00_carry_i_4_n_0
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_10_carry_i_1_n_0,
S(2) => aid_match_10_carry_i_2_n_0,
S(1) => aid_match_10_carry_i_3_n_0,
S(0) => aid_match_10_carry_i_4_n_0
);
aid_match_10_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
I3 => \s_axi_araddr[31]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
I5 => \s_axi_araddr[31]\(11),
O => aid_match_10_carry_i_1_n_0
);
aid_match_10_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
I3 => \s_axi_araddr[31]\(8),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
I5 => \s_axi_araddr[31]\(6),
O => aid_match_10_carry_i_2_n_0
);
aid_match_10_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(3),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
I3 => \s_axi_araddr[31]\(5),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
I5 => \s_axi_araddr[31]\(4),
O => aid_match_10_carry_i_3_n_0
);
aid_match_10_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(0),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
I3 => \s_axi_araddr[31]\(2),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
I5 => \s_axi_araddr[31]\(1),
O => aid_match_10_carry_i_4_n_0
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_20_carry_i_1_n_0,
S(2) => aid_match_20_carry_i_2_n_0,
S(1) => aid_match_20_carry_i_3_n_0,
S(0) => aid_match_20_carry_i_4_n_0
);
aid_match_20_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
O => aid_match_20_carry_i_1_n_0
);
aid_match_20_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
I1 => \s_axi_araddr[31]\(7),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(6),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
O => aid_match_20_carry_i_2_n_0
);
aid_match_20_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
I4 => \s_axi_araddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
O => aid_match_20_carry_i_3_n_0
);
aid_match_20_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
I4 => \s_axi_araddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
O => aid_match_20_carry_i_4_n_0
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_30_carry_i_1_n_0,
S(2) => aid_match_30_carry_i_2_n_0,
S(1) => aid_match_30_carry_i_3_n_0,
S(0) => aid_match_30_carry_i_4_n_0
);
aid_match_30_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
I1 => \s_axi_araddr[31]\(10),
I2 => \s_axi_araddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
I4 => \s_axi_araddr[31]\(9),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
O => aid_match_30_carry_i_1_n_0
);
aid_match_30_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(7),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
O => aid_match_30_carry_i_2_n_0
);
aid_match_30_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
I4 => \s_axi_araddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
O => aid_match_30_carry_i_3_n_0
);
aid_match_30_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
I1 => \s_axi_araddr[31]\(0),
I2 => \s_axi_araddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
I4 => \s_axi_araddr[31]\(1),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
O => aid_match_30_carry_i_4_n_0
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_40_carry_i_1_n_0,
S(2) => aid_match_40_carry_i_2_n_0,
S(1) => aid_match_40_carry_i_3_n_0,
S(0) => aid_match_40_carry_i_4_n_0
);
aid_match_40_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
O => aid_match_40_carry_i_1_n_0
);
aid_match_40_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(7),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
I4 => \s_axi_araddr[31]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
O => aid_match_40_carry_i_2_n_0
);
aid_match_40_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(5),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
I2 => \s_axi_araddr[31]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
I5 => \s_axi_araddr[31]\(4),
O => aid_match_40_carry_i_3_n_0
);
aid_match_40_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
O => aid_match_40_carry_i_4_n_0
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_50_carry_i_1_n_0,
S(2) => aid_match_50_carry_i_2_n_0,
S(1) => aid_match_50_carry_i_3_n_0,
S(0) => aid_match_50_carry_i_4_n_0
);
aid_match_50_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
O => aid_match_50_carry_i_1_n_0
);
aid_match_50_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(7),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
I4 => \s_axi_araddr[31]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
O => aid_match_50_carry_i_2_n_0
);
aid_match_50_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(4),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
I4 => \s_axi_araddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
O => aid_match_50_carry_i_3_n_0
);
aid_match_50_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
O => aid_match_50_carry_i_4_n_0
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_60_carry_i_1_n_0,
S(2) => aid_match_60_carry_i_2_n_0,
S(1) => aid_match_60_carry_i_3_n_0,
S(0) => aid_match_60_carry_i_4_n_0
);
aid_match_60_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
I4 => \s_axi_araddr[31]\(10),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
O => aid_match_60_carry_i_1_n_0
);
aid_match_60_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(7),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
O => aid_match_60_carry_i_2_n_0
);
aid_match_60_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
I4 => \s_axi_araddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
O => aid_match_60_carry_i_3_n_0
);
aid_match_60_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
I1 => \s_axi_araddr[31]\(0),
I2 => \s_axi_araddr[31]\(1),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
O => aid_match_60_carry_i_4_n_0
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_70_carry_i_1_n_0,
S(2) => aid_match_70_carry_i_2_n_0,
S(1) => aid_match_70_carry_i_3_n_0,
S(0) => aid_match_70_carry_i_4_n_0
);
aid_match_70_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
I1 => \s_axi_araddr[31]\(10),
I2 => \s_axi_araddr[31]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
O => aid_match_70_carry_i_1_n_0
);
aid_match_70_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(7),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
I4 => \s_axi_araddr[31]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
O => aid_match_70_carry_i_2_n_0
);
aid_match_70_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(4),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
I4 => \s_axi_araddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
O => aid_match_70_carry_i_3_n_0
);
aid_match_70_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
O => aid_match_70_carry_i_4_n_0
);
\gen_multi_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.arbiter_resp_inst_n_2\,
Q => \gen_multi_thread.accept_cnt_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.arbiter_resp_inst_n_1\,
Q => \gen_multi_thread.accept_cnt_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.arbiter_resp_inst_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5
port map (
CO(0) => p_8_out,
D(2) => \gen_multi_thread.arbiter_resp_inst_n_0\,
D(1) => \gen_multi_thread.arbiter_resp_inst_n_1\,
D(0) => \gen_multi_thread.arbiter_resp_inst_n_2\,
E(0) => \gen_multi_thread.arbiter_resp_inst_n_4\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg__0\(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_20\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_21\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_22\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_23\,
SR(0) => SR(0),
aclk => aclk,
\chosen_reg[1]_0\ => chosen(1),
cmd_push_0 => cmd_push_0,
cmd_push_3 => cmd_push_3,
\gen_multi_thread.accept_cnt_reg[2]\ => \gen_multi_thread.accept_cnt_reg[2]_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst_n_12\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst_n_11\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0) => p_14_out,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.arbiter_resp_inst_n_10\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_24\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_25\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_26\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_27\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.arbiter_resp_inst_n_9\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_28\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_29\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_30\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_31\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(3) => \gen_multi_thread.arbiter_resp_inst_n_32\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(2) => \gen_multi_thread.arbiter_resp_inst_n_33\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(1) => \gen_multi_thread.arbiter_resp_inst_n_34\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.arbiter_resp_inst_n_35\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.arbiter_resp_inst_n_8\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_36\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_37\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_38\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_39\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\ => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.arbiter_resp_inst_n_7\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_40\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_41\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_42\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_43\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.arbiter_resp_inst_n_6\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_44\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_45\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_46\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_47\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.arbiter_resp_inst_n_5\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_48\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_49\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_50\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_51\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\ => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]_1\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_1\ => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_2\ => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_3\ => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_4\ => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_5\ => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
\m_payload_i_reg[0]\(0) => E(0),
\m_payload_i_reg[0]_0\ => chosen(0),
\m_payload_i_reg[34]\ => chosen(2),
\m_payload_i_reg[34]_0\(0) => \m_payload_i_reg[34]\(0),
\m_payload_i_reg[46]\(25 downto 0) => \m_payload_i_reg[46]\(25 downto 0),
\m_payload_i_reg[46]_0\(25 downto 0) => \m_payload_i_reg[46]_0\(25 downto 0),
\m_payload_i_reg[46]_1\(12 downto 0) => \m_payload_i_reg[46]_1\(12 downto 0),
p_32_out => p_32_out,
p_54_out => p_54_out,
p_74_out => p_74_out,
s_axi_rdata(11 downto 0) => s_axi_rdata(11 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid(0) => s_axi_rvalid(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(0),
I2 => active_cnt(1),
I3 => cmd_push_0,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(3),
I1 => active_cnt(2),
I2 => cmd_push_0,
I3 => active_cnt(1),
I4 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\,
Q => active_cnt(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\,
Q => active_cnt(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\,
Q => active_cnt(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\,
Q => active_cnt(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000F0088888888"
)
port map (
I0 => aid_match_00,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA8FFFFFFFF"
)
port map (
I0 => aid_match_30,
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => active_cnt(27),
I4 => active_cnt(26),
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^st_aa_artarget_hot\(0),
Q => active_target(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(8),
I2 => active_cnt(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(11),
I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF55FF55CF55FF55"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
I1 => active_cnt(8),
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\,
Q => active_cnt(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\,
Q => active_cnt(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\,
Q => active_cnt(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\,
Q => active_cnt(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"3B080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I3 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I4 => aid_match_10,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^st_aa_artarget_hot\(0),
Q => active_target(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
I1 => active_cnt(16),
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(16),
I2 => active_cnt(17),
I3 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(19),
I1 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\,
Q => active_cnt(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\,
Q => active_cnt(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\,
Q => active_cnt(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\,
Q => active_cnt(19),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF77FF77F077FF77"
)
port map (
I0 => aid_match_20,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^st_aa_artarget_hot\(0),
Q => active_target(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => cmd_push_3,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(27),
I1 => active_cnt(26),
I2 => cmd_push_3,
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\,
Q => active_cnt(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\,
Q => active_cnt(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\,
Q => active_cnt(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\,
Q => active_cnt(27),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
I4 => aid_match_00,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_60,
I1 => active_cnt(49),
I2 => active_cnt(48),
I3 => active_cnt(50),
I4 => active_cnt(51),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => aid_match_20,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0A0A0A3A0A0A0A"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\,
I1 => active_cnt(26),
I2 => active_cnt(27),
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
I4 => aid_match_30,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => aid_match_10,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_70,
I1 => active_cnt(57),
I2 => active_cnt(56),
I3 => active_cnt(58),
I4 => active_cnt(59),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF0001"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_40,
I1 => active_cnt(33),
I2 => active_cnt(32),
I3 => active_cnt(34),
I4 => active_cnt(35),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => aid_match_50,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^st_aa_artarget_hot\(0),
Q => active_target(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
I1 => active_cnt(32),
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(32),
I2 => active_cnt(33),
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(35),
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
I2 => active_cnt(33),
I3 => active_cnt(32),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(35),
I1 => active_cnt(34),
I2 => active_cnt(32),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\,
Q => active_cnt(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\,
Q => active_cnt(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\,
Q => active_cnt(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\,
Q => active_cnt(35),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5545FFFFFFEFFFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I5 => aid_match_40,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^st_aa_artarget_hot\(0),
Q => active_target(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
I1 => active_cnt(40),
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(40),
I2 => active_cnt(41),
I3 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(43),
I1 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\,
Q => active_cnt(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\,
Q => active_cnt(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\,
Q => active_cnt(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\,
Q => active_cnt(43),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF77FF77F077FF77"
)
port map (
I0 => aid_match_50,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAABFFFFFFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\,
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => active_cnt(27),
I4 => active_cnt(26),
I5 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^st_aa_artarget_hot\(0),
Q => active_target(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
I1 => active_cnt(48),
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(48),
I2 => active_cnt(49),
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(51),
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
I2 => active_cnt(49),
I3 => active_cnt(48),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(51),
I1 => active_cnt(50),
I2 => active_cnt(48),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\,
Q => active_cnt(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\,
Q => active_cnt(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\,
Q => active_cnt(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\,
Q => active_cnt(51),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555545555555"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA800000000"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => active_cnt(51),
I2 => active_cnt(50),
I3 => active_cnt(48),
I4 => active_cnt(49),
I5 => aid_match_60,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\,
I1 => active_cnt(51),
I2 => active_cnt(50),
I3 => active_cnt(48),
I4 => active_cnt(49),
I5 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^st_aa_artarget_hot\(0),
Q => active_target(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
I1 => active_cnt(56),
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(56),
I2 => active_cnt(57),
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(59),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(59),
I1 => active_cnt(58),
I2 => active_cnt(56),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\,
Q => active_cnt(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\,
Q => active_cnt(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\,
Q => active_cnt(58),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\,
Q => active_cnt(59),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => \s_axi_araddr[31]\(17),
I1 => \s_axi_araddr[31]\(20),
I2 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\,
I3 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\,
I4 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\,
O => \^st_aa_artarget_hot\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_araddr[31]\(13),
I1 => \s_axi_araddr[31]\(22),
I2 => \s_axi_araddr[31]\(15),
I3 => \s_axi_araddr[31]\(12),
I4 => \s_axi_araddr[31]\(14),
I5 => \s_axi_araddr[31]\(26),
O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_araddr[31]\(25),
I1 => \s_axi_araddr[31]\(27),
I2 => \s_axi_araddr[31]\(23),
I3 => \s_axi_araddr[31]\(24),
O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_araddr[31]\(18),
I1 => \s_axi_araddr[31]\(19),
I2 => \s_axi_araddr[31]\(16),
I3 => \s_axi_araddr[31]\(21),
O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_araddr[25]_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF5555CFFF5555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^st_aa_artarget_hot\(0),
Q => active_target(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(57),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F40"
)
port map (
I0 => \s_axi_araddr[25]_0\,
I1 => \^m_valid_i\,
I2 => aresetn_d,
I3 => \gen_no_arbiter.m_target_hot_i_reg[2]_0\(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\gen_no_arbiter.s_ready_i[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDDDFFFD"
)
port map (
I0 => aid_match_30,
I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
I2 => \s_axi_araddr[25]\(0),
I3 => active_target(25),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"88880008"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I2 => \s_axi_araddr[25]\(0),
I3 => active_target(49),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"22220002"
)
port map (
I0 => aid_match_50,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I2 => \s_axi_araddr[25]\(0),
I3 => active_target(41),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"40FF404040404040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I1 => aid_match_10,
I2 => active_target(8),
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I4 => aid_match_00,
I5 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_13_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_14__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0404040404FF0404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I1 => aid_match_50,
I2 => active_target(40),
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I4 => aid_match_10,
I5 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010101010FF1010"
)
port map (
I0 => active_target(16),
I1 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I2 => aid_match_20,
I3 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
I4 => aid_match_30,
I5 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAAAA8"
)
port map (
I0 => aid_match_00,
I1 => active_cnt(0),
I2 => active_cnt(1),
I3 => active_cnt(3),
I4 => active_cnt(2),
I5 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_17__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FF080808"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I2 => active_target(48),
I3 => aid_match_40,
I4 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I5 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F1000000"
)
port map (
I0 => active_target(33),
I1 => \s_axi_araddr[25]\(0),
I2 => active_target(32),
I3 => aid_match_40,
I4 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I5 => \^st_aa_artarget_hot\(0),
O => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I2 => active_target(49),
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I4 => aid_match_20,
I5 => active_target(17),
O => \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_20__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F007F7F7F7F7F7F"
)
port map (
I0 => active_target(33),
I1 => aid_match_40,
I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I4 => aid_match_50,
I5 => active_target(41),
O => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => aid_match_70,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
I2 => active_target(57),
I3 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
I4 => aid_match_30,
I5 => active_target(25),
O => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"40FF404040404040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I1 => aid_match_10,
I2 => active_target(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I4 => aid_match_00,
I5 => active_target(1),
O => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_24__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(3),
I1 => \gen_multi_thread.accept_cnt_reg__0\(2),
I2 => \gen_multi_thread.accept_cnt_reg__0\(1),
I3 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000002F2"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\,
I2 => \^st_aa_artarget_hot\(0),
I3 => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\,
I5 => \gen_no_arbiter.m_valid_i_reg\,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000E00"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\,
I1 => \s_axi_araddr[25]\(0),
I2 => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0000111F"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I1 => active_target(9),
I2 => active_target(1),
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\,
I4 => \s_axi_araddr[25]\(0),
I5 => \gen_no_arbiter.s_ready_i[0]_i_13_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEEEF"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I3 => active_target(56),
I4 => \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFAAAAAAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\,
I5 => \s_axi_araddr[25]_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7F7F700F7F7F7F7"
)
port map (
I0 => aid_match_70,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
I2 => active_target(57),
I3 => active_target(17),
I4 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I5 => aid_match_20,
O => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => aid_match_70,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
I2 => active_target(56),
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I4 => aid_match_20,
I5 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_48\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_49\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_50\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_51\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_28\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_29\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_30\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_31\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_24\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_25\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_26\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_27\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_20\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_21\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_22\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_23\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_44\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_45\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_46\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_47\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_40\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_41\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_42\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_43\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_36\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_37\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_38\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_39\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_32\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_33\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_34\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_35\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
port (
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
\gen_master_slots[0].w_issuing_cnt_reg[1]\ : out STD_LOGIC;
chosen : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
st_aa_awtarget_enc : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
p_80_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].w_issuing_cnt_reg[10]\ : in STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ : in STD_LOGIC;
\s_axi_awaddr[31]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[2]\ : in STD_LOGIC;
\m_payload_i_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[5]\ : in STD_LOGIC;
\m_payload_i_reg[7]\ : in STD_LOGIC;
\m_payload_i_reg[12]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC;
\m_payload_i_reg[13]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_38_out : in STD_LOGIC;
p_60_out : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
\m_ready_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_14_si_transactor";
end \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 57 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal \aid_match_00_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal \aid_match_10_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal \aid_match_20_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal \aid_match_30_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal \aid_match_40_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal \aid_match_50_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal \aid_match_60_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal \aid_match_70_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal \gen_multi_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst_n_10\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_11\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_12\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_13\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_14\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_15\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_16\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_17\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_2\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_3\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_4\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_9\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_10_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_16_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_19_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_i_1_n_0 : STD_LOGIC;
signal p_10_out_carry_i_3_n_0 : STD_LOGIC;
signal p_10_out_carry_i_4_n_0 : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_i_1_n_0 : STD_LOGIC;
signal p_12_out_carry_i_3_n_0 : STD_LOGIC;
signal p_12_out_carry_i_4_n_0 : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_i_1_n_0 : STD_LOGIC;
signal p_14_out_carry_i_3_n_0 : STD_LOGIC;
signal p_14_out_carry_i_4_n_0 : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_i_1_n_0 : STD_LOGIC;
signal p_2_out_carry_i_3_n_0 : STD_LOGIC;
signal p_2_out_carry_i_4_n_0 : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_i_1_n_0 : STD_LOGIC;
signal p_4_out_carry_i_3_n_0 : STD_LOGIC;
signal p_4_out_carry_i_4_n_0 : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_i_1_n_0 : STD_LOGIC;
signal p_6_out_carry_i_3_n_0 : STD_LOGIC;
signal p_6_out_carry_i_4_n_0 : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_i_1_n_0 : STD_LOGIC;
signal p_8_out_carry_i_3_n_0 : STD_LOGIC;
signal p_8_out_carry_i_4_n_0 : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal \^st_aa_awtarget_enc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_12\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_28\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_8__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_9__0\ : label is "soft_lutpair140";
begin
D(0) <= \^d\(0);
Q(2 downto 0) <= \^q\(2 downto 0);
SR(0) <= \^sr\(0);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ <= \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ <= \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\;
st_aa_awtarget_enc(0) <= \^st_aa_awtarget_enc\(0);
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_00_carry_i_1__0_n_0\,
S(2) => \aid_match_00_carry_i_2__0_n_0\,
S(1) => \aid_match_00_carry_i_3__0_n_0\,
S(0) => \aid_match_00_carry_i_4__0_n_0\
);
\aid_match_00_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
I4 => \s_axi_awaddr[31]\(10),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
O => \aid_match_00_carry_i_1__0_n_0\
);
\aid_match_00_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(0),
I1 => \s_axi_awaddr[31]\(6),
I2 => \s_axi_awaddr[31]\(7),
I3 => \^q\(1),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^q\(2),
O => \aid_match_00_carry_i_2__0_n_0\
);
\aid_match_00_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I4 => \s_axi_awaddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
O => \aid_match_00_carry_i_3__0_n_0\
);
\aid_match_00_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I1 => \s_axi_awaddr[31]\(0),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(1),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
O => \aid_match_00_carry_i_4__0_n_0\
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_10_carry_i_1__0_n_0\,
S(2) => \aid_match_10_carry_i_2__0_n_0\,
S(1) => \aid_match_10_carry_i_3__0_n_0\,
S(0) => \aid_match_10_carry_i_4__0_n_0\
);
\aid_match_10_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(9),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I3 => \s_axi_awaddr[31]\(10),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \s_axi_awaddr[31]\(11),
O => \aid_match_10_carry_i_1__0_n_0\
);
\aid_match_10_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(6),
I1 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(0),
I2 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2),
I3 => \s_axi_awaddr[31]\(8),
I4 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(1),
I5 => \s_axi_awaddr[31]\(7),
O => \aid_match_10_carry_i_2__0_n_0\
);
\aid_match_10_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(3),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I3 => \s_axi_awaddr[31]\(4),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \s_axi_awaddr[31]\(5),
O => \aid_match_10_carry_i_3__0_n_0\
);
\aid_match_10_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(0),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I3 => \s_axi_awaddr[31]\(2),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I5 => \s_axi_awaddr[31]\(1),
O => \aid_match_10_carry_i_4__0_n_0\
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_20_carry_i_1__0_n_0\,
S(2) => \aid_match_20_carry_i_2__0_n_0\,
S(1) => \aid_match_20_carry_i_3__0_n_0\,
S(0) => \aid_match_20_carry_i_4__0_n_0\
);
\aid_match_20_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
O => \aid_match_20_carry_i_1__0_n_0\
);
\aid_match_20_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(8),
I3 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2),
I4 => \s_axi_awaddr[31]\(6),
I5 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0),
O => \aid_match_20_carry_i_2__0_n_0\
);
\aid_match_20_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(3),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
O => \aid_match_20_carry_i_3__0_n_0\
);
\aid_match_20_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I4 => \s_axi_awaddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
O => \aid_match_20_carry_i_4__0_n_0\
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_30_carry_i_1__0_n_0\,
S(2) => \aid_match_30_carry_i_2__0_n_0\,
S(1) => \aid_match_30_carry_i_3__0_n_0\,
S(0) => \aid_match_30_carry_i_4__0_n_0\
);
\aid_match_30_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I1 => \s_axi_awaddr[31]\(10),
I2 => \s_axi_awaddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
I4 => \s_axi_awaddr[31]\(9),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
O => \aid_match_30_carry_i_1__0_n_0\
);
\aid_match_30_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(0),
I1 => \s_axi_awaddr[31]\(6),
I2 => \s_axi_awaddr[31]\(7),
I3 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(1),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2),
O => \aid_match_30_carry_i_2__0_n_0\
);
\aid_match_30_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I1 => \s_axi_awaddr[31]\(3),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
O => \aid_match_30_carry_i_3__0_n_0\
);
\aid_match_30_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
O => \aid_match_30_carry_i_4__0_n_0\
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_40_carry_i_1__0_n_0\,
S(2) => \aid_match_40_carry_i_2__0_n_0\,
S(1) => \aid_match_40_carry_i_3__0_n_0\,
S(0) => \aid_match_40_carry_i_4__0_n_0\
);
\aid_match_40_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
O => \aid_match_40_carry_i_1__0_n_0\
);
\aid_match_40_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(6),
I3 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2),
O => \aid_match_40_carry_i_2__0_n_0\
);
\aid_match_40_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I4 => \s_axi_awaddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
O => \aid_match_40_carry_i_3__0_n_0\
);
\aid_match_40_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
O => \aid_match_40_carry_i_4__0_n_0\
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_50_carry_i_1__0_n_0\,
S(2) => \aid_match_50_carry_i_2__0_n_0\,
S(1) => \aid_match_50_carry_i_3__0_n_0\,
S(0) => \aid_match_50_carry_i_4__0_n_0\
);
\aid_match_50_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I1 => \s_axi_awaddr[31]\(10),
I2 => \s_axi_awaddr[31]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
O => \aid_match_50_carry_i_1__0_n_0\
);
\aid_match_50_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(8),
I3 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2),
I4 => \s_axi_awaddr[31]\(6),
I5 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0),
O => \aid_match_50_carry_i_2__0_n_0\
);
\aid_match_50_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(3),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
O => \aid_match_50_carry_i_3__0_n_0\
);
\aid_match_50_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I1 => \s_axi_awaddr[31]\(0),
I2 => \s_axi_awaddr[31]\(1),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I4 => \s_axi_awaddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
O => \aid_match_50_carry_i_4__0_n_0\
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_60_carry_i_1__0_n_0\,
S(2) => \aid_match_60_carry_i_2__0_n_0\,
S(1) => \aid_match_60_carry_i_3__0_n_0\,
S(0) => \aid_match_60_carry_i_4__0_n_0\
);
\aid_match_60_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
I4 => \s_axi_awaddr[31]\(10),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
O => \aid_match_60_carry_i_1__0_n_0\
);
\aid_match_60_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0),
I1 => \s_axi_awaddr[31]\(6),
I2 => \s_axi_awaddr[31]\(8),
I3 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2),
I4 => \s_axi_awaddr[31]\(7),
I5 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1),
O => \aid_match_60_carry_i_2__0_n_0\
);
\aid_match_60_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I1 => \s_axi_awaddr[31]\(3),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
O => \aid_match_60_carry_i_3__0_n_0\
);
\aid_match_60_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I1 => \s_axi_awaddr[31]\(0),
I2 => \s_axi_awaddr[31]\(1),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I4 => \s_axi_awaddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
O => \aid_match_60_carry_i_4__0_n_0\
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_70_carry_i_1__0_n_0\,
S(2) => \aid_match_70_carry_i_2__0_n_0\,
S(1) => \aid_match_70_carry_i_3__0_n_0\,
S(0) => \aid_match_70_carry_i_4__0_n_0\
);
\aid_match_70_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
O => \aid_match_70_carry_i_1__0_n_0\
);
\aid_match_70_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(6),
I3 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2),
O => \aid_match_70_carry_i_2__0_n_0\
);
\aid_match_70_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(3),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
O => \aid_match_70_carry_i_3__0_n_0\
);
\aid_match_70_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
O => \aid_match_70_carry_i_4__0_n_0\
);
\gen_multi_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.accept_cnt[0]_i_1_n_0\,
Q => \gen_multi_thread.accept_cnt_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.arbiter_resp_inst_n_4\,
Q => \gen_multi_thread.accept_cnt_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.arbiter_resp_inst_n_3\,
Q => \gen_multi_thread.accept_cnt_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.arbiter_resp_inst_n_2\,
Q => \gen_multi_thread.accept_cnt_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp
port map (
CO(0) => p_0_out,
D(2) => \gen_multi_thread.arbiter_resp_inst_n_2\,
D(1) => \gen_multi_thread.arbiter_resp_inst_n_3\,
D(0) => \gen_multi_thread.arbiter_resp_inst_n_4\,
E(0) => \gen_multi_thread.arbiter_resp_inst_n_9\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg\(3 downto 0),
SR(0) => \^sr\(0),
aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\chosen_reg[0]_0\ => chosen(0),
\chosen_reg[1]_0\ => chosen(1),
cmd_push_0 => cmd_push_0,
cmd_push_3 => cmd_push_3,
\gen_master_slots[0].w_issuing_cnt_reg[1]\ => \gen_master_slots[0].w_issuing_cnt_reg[1]\,
\gen_master_slots[1].w_issuing_cnt_reg[10]\ => \gen_master_slots[1].w_issuing_cnt_reg[10]\,
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_master_slots[1].w_issuing_cnt_reg[8]\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\ => chosen(2),
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ => \gen_master_slots[2].w_issuing_cnt_reg[16]\,
\gen_master_slots[2].w_issuing_cnt_reg[16]_1\ => \gen_master_slots[2].w_issuing_cnt_reg[16]_0\,
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst_n_17\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst_n_16\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0) => p_14_out,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.arbiter_resp_inst_n_15\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.arbiter_resp_inst_n_14\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\ => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.arbiter_resp_inst_n_13\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\ => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.arbiter_resp_inst_n_12\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\ => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.arbiter_resp_inst_n_11\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.arbiter_resp_inst_n_10\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\ => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\,
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_no_arbiter.s_ready_i_reg[0]_0\,
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
\m_ready_d_reg[1]_0\ => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
\m_ready_d_reg[1]_1\ => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
\m_ready_d_reg[1]_2\ => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
\m_ready_d_reg[1]_3\ => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
\m_ready_d_reg[1]_4\ => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
\m_ready_d_reg[1]_5\ => \m_ready_d_reg[1]_0\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
p_38_out => p_38_out,
p_60_out => p_60_out,
p_80_out => p_80_out,
\s_axi_awaddr[26]\(0) => \^st_aa_awtarget_enc\(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
w_issuing_cnt(4 downto 0) => w_issuing_cnt(4 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(0),
I2 => active_cnt(1),
I3 => cmd_push_0,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(3),
I1 => active_cnt(2),
I2 => cmd_push_0,
I3 => active_cnt(1),
I4 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\,
Q => active_cnt(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\,
Q => active_cnt(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\,
Q => active_cnt(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\,
Q => active_cnt(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(6),
Q => \^q\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(7),
Q => \^q\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(8),
Q => \^q\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0500050035300500"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I3 => aid_match_00,
I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_40,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => aid_match_50,
O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(8),
I2 => active_cnt(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(11),
I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBBFFBBF0BBFFBB"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => aid_match_10,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
I1 => active_cnt(8),
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\,
Q => active_cnt(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\,
Q => active_cnt(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\,
Q => active_cnt(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\,
Q => active_cnt(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08083B08"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I3 => aid_match_10,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
I1 => active_cnt(16),
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(16),
I2 => active_cnt(17),
I3 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(19),
I1 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\,
Q => active_cnt(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\,
Q => active_cnt(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\,
Q => active_cnt(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\,
Q => active_cnt(19),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDDFFDDF0DDFFDD"
)
port map (
I0 => aid_match_20,
I1 => \m_ready_d_reg[1]\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => cmd_push_3,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(27),
I1 => active_cnt(26),
I2 => cmd_push_3,
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\,
Q => active_cnt(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\,
Q => active_cnt(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\,
Q => active_cnt(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\,
Q => active_cnt(27),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"004400440F440044"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => aid_match_30,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF0001"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEFFF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => aid_match_20,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_10,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_30,
I1 => active_cnt(26),
I2 => active_cnt(27),
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
I1 => active_cnt(32),
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(32),
I2 => active_cnt(33),
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(35),
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
I2 => active_cnt(33),
I3 => active_cnt(32),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\,
Q => active_cnt(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\,
Q => active_cnt(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\,
Q => active_cnt(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\,
Q => active_cnt(35),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFAFAFAFAFACAFAF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_00,
I1 => active_cnt(2),
I2 => active_cnt(3),
I3 => active_cnt(1),
I4 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
I1 => active_cnt(40),
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(40),
I2 => active_cnt(41),
I3 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(43),
I1 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\,
Q => active_cnt(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\,
Q => active_cnt(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\,
Q => active_cnt(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\,
Q => active_cnt(43),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAFFFFFACAFFCF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\,
I4 => aid_match_50,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
I1 => active_cnt(48),
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(48),
I2 => active_cnt(49),
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(51),
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
I2 => active_cnt(49),
I3 => active_cnt(48),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(51),
I1 => active_cnt(50),
I2 => active_cnt(48),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\,
Q => active_cnt(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\,
Q => active_cnt(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\,
Q => active_cnt(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\,
Q => active_cnt(51),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEE0EEEE"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_60,
I1 => active_cnt(49),
I2 => active_cnt(48),
I3 => active_cnt(50),
I4 => active_cnt(51),
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => active_cnt(48),
I5 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
I1 => active_cnt(56),
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(56),
I2 => active_cnt(57),
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(59),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\,
Q => active_cnt(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\,
Q => active_cnt(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\,
Q => active_cnt(58),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\,
Q => active_cnt(59),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\,
I1 => \s_axi_awaddr[31]\(17),
I2 => \s_axi_awaddr[31]\(20),
O => \^st_aa_awtarget_enc\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\,
I1 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\,
I2 => \s_axi_awaddr[31]\(19),
I3 => \s_axi_awaddr[31]\(15),
I4 => \s_axi_awaddr[31]\(12),
I5 => \s_axi_awaddr[31]\(23),
O => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_awaddr[31]\(14),
I1 => \s_axi_awaddr[31]\(25),
I2 => \s_axi_awaddr[31]\(21),
I3 => \s_axi_awaddr[31]\(22),
O => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \s_axi_awaddr[31]\(24),
I1 => \s_axi_awaddr[31]\(27),
I2 => \s_axi_awaddr[31]\(13),
I3 => \s_axi_awaddr[31]\(26),
I4 => \s_axi_awaddr[31]\(18),
I5 => \s_axi_awaddr[31]\(16),
O => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^st_aa_awtarget_enc\(0),
I1 => st_aa_awtarget_hot(0),
O => \^d\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0000FFEF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF0001"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFD"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I2 => active_cnt(58),
I3 => active_cnt(59),
I4 => active_cnt(57),
I5 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_70,
I1 => active_cnt(58),
I2 => active_cnt(59),
I3 => active_cnt(57),
I4 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(57),
R => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000F100"
)
port map (
I0 => active_target(41),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(40),
I3 => aid_match_50,
I4 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_10_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"22220002"
)
port map (
I0 => aid_match_20,
I1 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I2 => active_target(17),
I3 => st_aa_awtarget_hot(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(56),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(57),
O => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(8),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(9),
O => \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44440004"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I1 => aid_match_00,
I2 => active_target(1),
I3 => st_aa_awtarget_hot(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44440004"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
I1 => aid_match_30,
I2 => active_target(25),
I3 => st_aa_awtarget_hot(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0404040404FF0404"
)
port map (
I0 => active_target(32),
I1 => aid_match_40,
I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\,
I3 => active_target(8),
I4 => aid_match_10,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_16_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFB00FBFB"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I1 => aid_match_50,
I2 => active_target(40),
I3 => active_target(24),
I4 => aid_match_30,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0404040404FF0404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I1 => aid_match_20,
I2 => active_target(16),
I3 => active_target(0),
I4 => aid_match_00,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
I5 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_19_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040FF4040404040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I1 => aid_match_20,
I2 => active_target(17),
I3 => aid_match_00,
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I5 => active_target(1),
O => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"2020FF2020202020"
)
port map (
I0 => aid_match_40,
I1 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\,
I2 => active_target(33),
I3 => aid_match_70,
I4 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\,
I5 => active_target(57),
O => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDF00DFDFDFDFDF"
)
port map (
I0 => active_target(41),
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I2 => aid_match_50,
I3 => aid_match_10,
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
I5 => active_target(9),
O => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080FF8080808080"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\,
I2 => active_target(49),
I3 => aid_match_30,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
I5 => active_target(25),
O => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
I1 => \gen_multi_thread.accept_cnt_reg\(1),
I2 => \gen_multi_thread.accept_cnt_reg\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000DDD0"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_10_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF22F2"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004040400"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_16_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I4 => active_target(48),
I5 => \gen_no_arbiter.s_ready_i[0]_i_19_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEE0EEEE"
)
port map (
I0 => st_aa_awtarget_hot(0),
I1 => \^st_aa_awtarget_enc\(0),
I2 => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(32),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(33),
O => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(48),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(49),
O => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => \i__carry_i_1_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => \i__carry_i_4_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry_i_1_n_0\,
S(2) => \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\(0),
S(1) => \i__carry_i_3_n_0\,
S(0) => \i__carry_i_4_n_0\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_10_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\(0),
S(1) => p_10_out_carry_i_3_n_0,
S(0) => p_10_out_carry_i_4_n_0
);
p_10_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_10_out_carry_i_1_n_0
);
p_10_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_10_out_carry_i_3_n_0
);
p_10_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_10_out_carry_i_4_n_0
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_12_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\(0),
S(1) => p_12_out_carry_i_3_n_0,
S(0) => p_12_out_carry_i_4_n_0
);
p_12_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_12_out_carry_i_1_n_0
);
p_12_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_12_out_carry_i_3_n_0
);
p_12_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_12_out_carry_i_4_n_0
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_14_out_carry_i_1_n_0,
S(2) => S(0),
S(1) => p_14_out_carry_i_3_n_0,
S(0) => p_14_out_carry_i_4_n_0
);
p_14_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_14_out_carry_i_1_n_0
);
p_14_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_14_out_carry_i_3_n_0
);
p_14_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_14_out_carry_i_4_n_0
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_2_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\(0),
S(1) => p_2_out_carry_i_3_n_0,
S(0) => p_2_out_carry_i_4_n_0
);
p_2_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_2_out_carry_i_1_n_0
);
p_2_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_2_out_carry_i_3_n_0
);
p_2_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_2_out_carry_i_4_n_0
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_4_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\(0),
S(1) => p_4_out_carry_i_3_n_0,
S(0) => p_4_out_carry_i_4_n_0
);
p_4_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_4_out_carry_i_1_n_0
);
p_4_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_4_out_carry_i_3_n_0
);
p_4_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_4_out_carry_i_4_n_0
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_6_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\(0),
S(1) => p_6_out_carry_i_3_n_0,
S(0) => p_6_out_carry_i_4_n_0
);
p_6_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_6_out_carry_i_1_n_0
);
p_6_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_6_out_carry_i_3_n_0
);
p_6_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_6_out_carry_i_4_n_0
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_8_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\(0),
S(1) => p_8_out_carry_i_3_n_0,
S(0) => p_8_out_carry_i_4_n_0
);
p_8_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_8_out_carry_i_1_n_0
);
p_8_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_8_out_carry_i_3_n_0
);
p_8_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_8_out_carry_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
port (
s_ready_i_reg_0 : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_axi.write_cs_reg[1]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.write_cs_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_14_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo : entity is "axi_data_fifo_v2_1_12_axic_reg_srl_fifo";
end zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
signal \/FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal areset_d1 : STD_LOGIC;
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_1\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_2\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_3\ : STD_LOGIC;
signal load_s1 : STD_LOGIC;
signal m_avalid : STD_LOGIC;
signal m_valid_i : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal p_0_in5_out : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal s_ready_i_i_2_n_0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \storage_data1[0]_i_1_n_0\ : STD_LOGIC;
signal \storage_data1_reg_n_0_[0]\ : STD_LOGIC;
signal \storage_data1_reg_n_0_[1]\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair142";
begin
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\/FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40440000"
)
port map (
I0 => p_9_in,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => m_ready_d(0),
I3 => s_axi_awvalid(0),
I4 => p_0_in8_in,
O => \/FSM_onehot_state[0]_i_1_n_0\
);
\/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20202F20"
)
port map (
I0 => s_axi_awvalid(0),
I1 => m_ready_d(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[1]_i_1_n_0\
);
\/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0B0B0BF"
)
port map (
I0 => m_ready_d(0),
I1 => s_axi_awvalid(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[2]_i_1_n_0\
);
\/FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002A22"
)
port map (
I0 => p_0_in8_in,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => m_ready_d(0),
I3 => s_axi_awvalid(0),
I4 => p_9_in,
O => \/FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF488F488F488"
)
port map (
I0 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i
);
\FSM_onehot_state[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => fifoaddr(1),
I1 => fifoaddr(0),
I2 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I5 => fifoaddr(2),
O => p_0_in5_out
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => areset_d1
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => areset_d1
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => areset_d1
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => areset_d1
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => SR(0),
Q => areset_d1,
R => '0'
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \storage_data1_reg_n_0_[0]\,
I1 => \storage_data1_reg_n_0_[1]\,
I2 => \gen_axi.write_cs_reg[1]_0\(0),
I3 => s_axi_wlast(0),
I4 => s_axi_wvalid(0),
I5 => m_avalid,
O => \gen_axi.write_cs_reg[1]\
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C133DDFF3ECC2200"
)
port map (
I0 => p_0_in8_in,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => \^s_ready_i_reg_0\,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFD5402A"
)
port map (
I0 => fifoaddr(0),
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
I3 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFFF77710000888"
)
port map (
I0 => fifoaddr(0),
I1 => fifoaddr(1),
I2 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I5 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\
port map (
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
push => push,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[1].srl_nx1\: entity work.\zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\
port map (
D(0) => D(0),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
\gen_rep[0].fifoaddr_reg[0]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
load_s1 => load_s1,
m_avalid => m_avalid,
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_ready_d(0) => m_ready_d(0),
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
p_14_in => p_14_in,
push => push,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
s_ready_i_reg_0 => \^s_ready_i_reg_0\,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
\storage_data1_reg[0]\ => \storage_data1_reg_n_0_[0]\,
\storage_data1_reg[1]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_1\,
\storage_data1_reg[1]_0\ => \storage_data1_reg_n_0_[1]\
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \storage_data1_reg_n_0_[0]\,
I1 => \storage_data1_reg_n_0_[1]\,
I2 => m_avalid,
I3 => s_axi_wvalid(0),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \storage_data1_reg_n_0_[0]\,
I1 => \storage_data1_reg_n_0_[1]\,
I2 => m_avalid,
I3 => s_axi_wvalid(0),
O => m_axi_wvalid(1)
);
m_valid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF400F400F400"
)
port map (
I0 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => m_valid_i_i_1_n_0,
Q => m_avalid,
R => areset_d1
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A8A008A0A800080"
)
port map (
I0 => m_avalid,
I1 => m_axi_wready(1),
I2 => \storage_data1_reg_n_0_[0]\,
I3 => \storage_data1_reg_n_0_[1]\,
I4 => p_14_in,
I5 => m_axi_wready(0),
O => s_axi_wready(0)
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFFAAAAAAAA"
)
port map (
I0 => s_ready_i_i_2_n_0,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I2 => fifoaddr(0),
I3 => fifoaddr(1),
I4 => fifoaddr(2),
I5 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => areset_d1,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
O => s_ready_i_i_2_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^s_ready_i_reg_0\,
R => SR(0)
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => st_aa_awtarget_enc(0),
I3 => load_s1,
I4 => \storage_data1_reg_n_0_[0]\,
O => \storage_data1[0]_i_1_n_0\
);
\storage_data1[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"88888888FFC88888"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => p_0_in8_in,
I3 => p_9_in,
I4 => s_axi_awvalid(0),
I5 => m_ready_d(0),
O => load_s1
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \storage_data1[0]_i_1_n_0\,
Q => \storage_data1_reg_n_0_[0]\,
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[1].srl_nx1_n_1\,
Q => \storage_data1_reg_n_0_[1]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
port (
p_80_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_74_out : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
begin
b_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\
port map (
D(13 downto 0) => D(13 downto 0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
chosen(0) => chosen(0),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_80_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\
port map (
E(0) => E(0),
Q(3 downto 0) => Q(3 downto 0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
chosen_0(0) => chosen_0(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_74_out,
p_1_in => p_1_in,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
port (
p_60_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
p_54_out : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 25 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[12]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_38_out : in STD_LOGIC;
\m_payload_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[32]\ : in STD_LOGIC_VECTOR ( 20 downto 0 );
p_32_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
signal \^p_1_in\ : STD_LOGIC;
begin
p_1_in <= \^p_1_in\;
b_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\
port map (
D(13 downto 0) => D(13 downto 0),
Q(3 downto 0) => Q(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\aresetn_d_reg[1]_1\ => \aresetn_d_reg[1]_1\,
chosen(1 downto 0) => chosen(1 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_multi_thread.accept_cnt_reg[3]\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(6 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(6 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_60_out,
\m_payload_i_reg[12]_0\(9 downto 0) => \m_payload_i_reg[12]\(9 downto 0),
\m_payload_i_reg[1]_0\(1 downto 0) => \m_payload_i_reg[1]\(1 downto 0),
p_1_in => \^p_1_in\,
p_38_out => p_38_out,
s_axi_bid(4 downto 0) => s_axi_bid(4 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0)
);
r_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\
port map (
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]_0\,
chosen_0(1 downto 0) => chosen_0(1 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[11]\ => \gen_master_slots[1].r_issuing_cnt_reg[11]\,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0) => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[1]\ => \m_axi_rready[1]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
\m_payload_i_reg[32]_0\(20 downto 0) => \m_payload_i_reg[32]\(20 downto 0),
p_1_in => \^p_1_in\,
p_32_out => p_32_out,
s_axi_rdata(19 downto 0) => s_axi_rdata(19 downto 0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(0),
s_ready_i_reg_0 => p_54_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
port (
p_38_out : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
mi_bready_2 : out STD_LOGIC;
p_32_out : out STD_LOGIC;
mi_rready_2 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 6 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : out STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_21_in : in STD_LOGIC;
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[13]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_valid_i_reg_0 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
p_15_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_17_in : in STD_LOGIC;
\gen_axi.s_axi_arready_i_reg\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
signal \^m_valid_i_reg\ : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
b_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
D(11 downto 0) => D(11 downto 0),
Q(4 downto 0) => Q(4 downto 0),
S(0) => S(0),
aclk => aclk,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
chosen(0) => chosen(0),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0),
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0),
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0),
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0),
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0),
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0),
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\,
\m_payload_i_reg[13]_0\(13 downto 0) => \m_payload_i_reg[13]\(13 downto 0),
\m_payload_i_reg[2]_0\ => p_38_out,
m_valid_i_reg_0 => \^m_valid_i_reg\,
m_valid_i_reg_1 => m_valid_i_reg_0,
mi_bready_2 => mi_bready_2,
p_1_in => p_1_in,
p_21_in => p_21_in,
s_axi_bid(6 downto 0) => s_axi_bid(6 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_ready_i_reg_0 => s_ready_i_reg,
w_issuing_cnt(0) => w_issuing_cnt(0)
);
r_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \^m_valid_i_reg\,
chosen_0(0) => chosen_0(0),
\gen_axi.s_axi_arready_i_reg\ => \gen_axi.s_axi_arready_i_reg\,
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(12 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_valid_i_reg_0 => p_32_out,
p_15_in => p_15_in,
p_17_in => p_17_in,
p_1_in => p_1_in,
r_issuing_cnt(0) => r_issuing_cnt(0),
s_axi_rready(0) => s_axi_rready(0),
\skid_buffer_reg[34]_0\ => mi_rready_2,
st_aa_artarget_hot(1 downto 0) => st_aa_artarget_hot(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_axi.write_cs_reg[1]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.write_cs_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_14_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router : entity is "axi_crossbar_v2_1_14_wdata_router";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router is
begin
wrouter_aw_fifo: entity work.zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
port map (
D(0) => D(0),
SR(0) => SR(0),
aclk => aclk,
\gen_axi.write_cs_reg[1]\ => \gen_axi.write_cs_reg[1]\,
\gen_axi.write_cs_reg[1]_0\(0) => \gen_axi.write_cs_reg[1]_0\(0),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
m_ready_d(0) => m_ready_d(0),
p_14_in => p_14_in,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg_0 => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar is
port (
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
\m_axi_arqos[7]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_RREADY : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
aresetn : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 56 downto 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 56 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar : entity is "axi_crossbar_v2_1_14_crossbar";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar is
signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 2 to 2 );
signal aa_mi_arvalid : STD_LOGIC;
signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal aa_sa_awvalid : STD_LOGIC;
signal addr_arbiter_ar_n_2 : STD_LOGIC;
signal addr_arbiter_ar_n_3 : STD_LOGIC;
signal addr_arbiter_ar_n_4 : STD_LOGIC;
signal addr_arbiter_ar_n_5 : STD_LOGIC;
signal addr_arbiter_ar_n_6 : STD_LOGIC;
signal addr_arbiter_ar_n_7 : STD_LOGIC;
signal addr_arbiter_ar_n_80 : STD_LOGIC;
signal addr_arbiter_ar_n_81 : STD_LOGIC;
signal addr_arbiter_ar_n_82 : STD_LOGIC;
signal addr_arbiter_ar_n_84 : STD_LOGIC;
signal addr_arbiter_ar_n_85 : STD_LOGIC;
signal addr_arbiter_aw_n_10 : STD_LOGIC;
signal addr_arbiter_aw_n_11 : STD_LOGIC;
signal addr_arbiter_aw_n_12 : STD_LOGIC;
signal addr_arbiter_aw_n_13 : STD_LOGIC;
signal addr_arbiter_aw_n_14 : STD_LOGIC;
signal addr_arbiter_aw_n_15 : STD_LOGIC;
signal addr_arbiter_aw_n_16 : STD_LOGIC;
signal addr_arbiter_aw_n_2 : STD_LOGIC;
signal addr_arbiter_aw_n_20 : STD_LOGIC;
signal addr_arbiter_aw_n_21 : STD_LOGIC;
signal addr_arbiter_aw_n_3 : STD_LOGIC;
signal addr_arbiter_aw_n_7 : STD_LOGIC;
signal addr_arbiter_aw_n_8 : STD_LOGIC;
signal addr_arbiter_aw_n_9 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_decerr_slave.decerr_slave_inst_n_7\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_12\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_20\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_21\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_22\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_23\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_26\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_27\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_75\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_76\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_1\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_13\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_19\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_20\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_21\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_22\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_23\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_24\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_25\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_26\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_27\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_28\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_29\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_30\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_31\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_45\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst/chosen\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst/chosen_1\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\ : STD_LOGIC;
signal \^m_axi_arqos[7]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_3 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_valid_i : STD_LOGIC;
signal m_valid_i_2 : STD_LOGIC;
signal mi_arready_2 : STD_LOGIC;
signal mi_awready_2 : STD_LOGIC;
signal mi_bready_2 : STD_LOGIC;
signal mi_rready_2 : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_21_in : STD_LOGIC;
signal p_24_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_32_out : STD_LOGIC;
signal p_34_out : STD_LOGIC;
signal p_38_out : STD_LOGIC;
signal p_54_out : STD_LOGIC;
signal p_56_out : STD_LOGIC;
signal p_60_out : STD_LOGIC;
signal p_74_out : STD_LOGIC;
signal p_76_out : STD_LOGIC;
signal p_80_out : STD_LOGIC;
signal r_issuing_cnt : STD_LOGIC_VECTOR ( 16 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal \r_pipe/p_1_in_0\ : STD_LOGIC;
signal reset : STD_LOGIC;
signal s_axi_rlast_i0 : STD_LOGIC;
signal s_axi_rvalid_i : STD_LOGIC;
signal ss_aa_awready : STD_LOGIC;
signal ss_wr_awready : STD_LOGIC;
signal ss_wr_awvalid : STD_LOGIC;
signal st_aa_artarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_aa_awtarget_enc : STD_LOGIC_VECTOR ( 0 to 0 );
signal st_aa_awtarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
signal st_mr_bid : STD_LOGIC_VECTOR ( 34 downto 0 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_rid : STD_LOGIC_VECTOR ( 35 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 69 downto 0 );
signal w_issuing_cnt : STD_LOGIC_VECTOR ( 16 downto 0 );
signal write_cs : STD_LOGIC_VECTOR ( 1 to 1 );
begin
Q(68 downto 0) <= \^q\(68 downto 0);
S_AXI_ARREADY(0) <= \^s_axi_arready\(0);
\m_axi_arqos[7]\(68 downto 0) <= \^m_axi_arqos[7]\(68 downto 0);
addr_arbiter_ar: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter
port map (
D(2) => addr_arbiter_ar_n_2,
D(1) => addr_arbiter_ar_n_3,
D(0) => addr_arbiter_ar_n_4,
E(0) => s_axi_rvalid_i,
Q(0) => p_56_out,
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\,
aresetn_d_reg_0 => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\,
\chosen_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\,
\gen_axi.read_cnt_reg[5]\ => \gen_decerr_slave.decerr_slave_inst_n_7\,
\gen_axi.s_axi_rid_i_reg[11]\(0) => aa_mi_artarget_hot(2),
\gen_master_slots[0].r_issuing_cnt_reg[0]\(0) => addr_arbiter_ar_n_84,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(2) => addr_arbiter_ar_n_5,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(1) => addr_arbiter_ar_n_6,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(0) => addr_arbiter_ar_n_7,
\gen_master_slots[1].r_issuing_cnt_reg[8]\(0) => addr_arbiter_ar_n_85,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_31\,
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ => addr_arbiter_ar_n_82,
\gen_no_arbiter.m_target_hot_i_reg[0]_0\(0) => st_aa_artarget_hot(0),
\gen_no_arbiter.m_valid_i_reg_0\ => addr_arbiter_ar_n_80,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_ar_n_81,
\m_axi_arqos[7]\(68 downto 0) => \^m_axi_arqos[7]\(68 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
\m_payload_i_reg[34]\ => \gen_master_slots[0].reg_slice_mi_n_5\,
\m_payload_i_reg[34]_0\ => \gen_master_slots[1].reg_slice_mi_n_27\,
m_valid_i => m_valid_i,
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_75\,
mi_arready_2 => mi_arready_2,
p_15_in => p_15_in,
r_issuing_cnt(7 downto 4) => r_issuing_cnt(11 downto 8),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0),
\s_axi_araddr[25]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\,
\s_axi_araddr[28]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\,
\s_axi_araddr[30]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
\s_axi_arqos[3]\(68 downto 12) => \s_axi_arqos[3]\(56 downto 0),
\s_axi_arqos[3]\(11 downto 0) => s_axi_arid(11 downto 0),
\s_axi_arready[0]\ => \^s_axi_arready\(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rlast_i0 => s_axi_rlast_i0,
s_axi_rready(0) => s_axi_rready(0),
st_aa_artarget_hot(0) => st_aa_artarget_hot(1)
);
addr_arbiter_aw: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0
port map (
D(2) => addr_arbiter_aw_n_7,
D(1) => addr_arbiter_aw_n_8,
D(0) => addr_arbiter_aw_n_9,
E(0) => addr_arbiter_aw_n_15,
Q(68 downto 0) => \^q\(68 downto 0),
SR(0) => reset,
aa_mi_awtarget_hot(2 downto 0) => aa_mi_awtarget_hot(2 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\,
aresetn_d_reg_0 => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\,
\chosen_reg[0]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\,
\chosen_reg[1]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\,
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => addr_arbiter_aw_n_16,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(2) => addr_arbiter_aw_n_11,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(1) => addr_arbiter_aw_n_12,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(0) => addr_arbiter_aw_n_13,
\gen_master_slots[1].w_issuing_cnt_reg[9]\ => addr_arbiter_aw_n_10,
\gen_master_slots[2].w_issuing_cnt_reg[16]\ => addr_arbiter_aw_n_14,
\gen_no_arbiter.m_target_hot_i_reg[2]_0\ => addr_arbiter_aw_n_20,
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
m_ready_d(1 downto 0) => m_ready_d_3(1 downto 0),
m_ready_d_0(0) => m_ready_d(0),
\m_ready_d_reg[0]\ => addr_arbiter_aw_n_2,
\m_ready_d_reg[1]\ => addr_arbiter_aw_n_3,
\m_ready_d_reg[1]_0\ => addr_arbiter_aw_n_21,
m_valid_i => m_valid_i_2,
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_6\,
mi_awready_2 => mi_awready_2,
\s_axi_awaddr[20]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\,
\s_axi_awaddr[26]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\,
\s_axi_awqos[3]\(68 downto 12) => D(56 downto 0),
\s_axi_awqos[3]\(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
ss_aa_awready => ss_aa_awready,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr_slave.decerr_slave_inst\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave
port map (
E(0) => s_axi_rvalid_i,
Q(11 downto 0) => p_24_in(11 downto 0),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(2),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axi.s_axi_arready_i_reg_0\ => \gen_decerr_slave.decerr_slave_inst_n_7\,
\gen_axi.write_cs_reg[1]_0\(0) => write_cs(1),
\gen_no_arbiter.m_mesg_i_reg[11]\(11 downto 0) => \^q\(11 downto 0),
\gen_no_arbiter.m_mesg_i_reg[51]\(19 downto 12) => \^m_axi_arqos[7]\(51 downto 44),
\gen_no_arbiter.m_mesg_i_reg[51]\(11 downto 0) => \^m_axi_arqos[7]\(11 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[2]\(0) => aa_mi_artarget_hot(2),
\gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_aw_n_10,
m_ready_d(0) => m_ready_d_3(1),
\m_ready_d_reg[1]\ => addr_arbiter_aw_n_14,
mi_arready_2 => mi_arready_2,
mi_awready_2 => mi_awready_2,
mi_bready_2 => mi_bready_2,
mi_rready_2 => mi_rready_2,
p_14_in => p_14_in,
p_15_in => p_15_in,
p_17_in => p_17_in,
p_21_in => p_21_in,
s_axi_rlast_i0 => s_axi_rlast_i0,
\skid_buffer_reg[46]\(11 downto 0) => p_20_in(11 downto 0),
\storage_data1_reg[0]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\
);
\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(0),
O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\,
Q => r_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => addr_arbiter_ar_n_4,
Q => r_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => addr_arbiter_ar_n_3,
Q => r_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => addr_arbiter_ar_n_2,
Q => r_issuing_cnt(3),
R => reset
);
\gen_master_slots[0].reg_slice_mi\: entity work.zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice
port map (
D(13 downto 2) => m_axi_bid(11 downto 0),
D(1 downto 0) => m_axi_bresp(1 downto 0),
E(0) => \r_pipe/p_1_in_0\,
Q(3 downto 0) => r_issuing_cnt(3 downto 0),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[2].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[2].reg_slice_mi_n_5\,
chosen(0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(0),
chosen_0(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_5\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 2) => st_mr_bid(11 downto 0),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1 downto 0) => st_mr_bmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_76_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(34 downto 3),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_4\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => M_AXI_RREADY(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
p_1_in => p_1_in,
p_74_out => p_74_out,
p_80_out => p_80_out,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(0),
O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\,
Q => w_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => addr_arbiter_aw_n_13,
Q => w_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => addr_arbiter_aw_n_12,
Q => w_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => addr_arbiter_aw_n_11,
Q => w_issuing_cnt(3),
R => reset
);
\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(8),
O => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].r_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => addr_arbiter_ar_n_6,
Q => r_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => addr_arbiter_ar_n_5,
Q => r_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\,
Q => r_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => addr_arbiter_ar_n_7,
Q => r_issuing_cnt(9),
R => reset
);
\gen_master_slots[1].reg_slice_mi\: entity work.zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1
port map (
D(13 downto 2) => m_axi_bid(23 downto 12),
D(1 downto 0) => m_axi_bresp(3 downto 2),
Q(3 downto 0) => w_issuing_cnt(11 downto 8),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \gen_master_slots[1].reg_slice_mi_n_76\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[2].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_1\ => \gen_master_slots[2].reg_slice_mi_n_5\,
chosen(1 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2 downto 1),
chosen_0(1 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2 downto 1),
\gen_master_slots[1].r_issuing_cnt_reg[11]\ => \gen_master_slots[1].reg_slice_mi_n_75\,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0) => r_issuing_cnt(11 downto 8),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_27\,
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_6\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_master_slots[1].reg_slice_mi_n_12\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(6) => st_mr_bid(23),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(5 downto 2) => st_mr_bid(21 downto 18),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(1) => st_mr_bid(16),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(0) => st_mr_bid(12),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_master_slots[1].reg_slice_mi_n_20\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_master_slots[1].reg_slice_mi_n_21\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ => \gen_master_slots[1].reg_slice_mi_n_22\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ => \gen_master_slots[1].reg_slice_mi_n_23\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 14) => st_mr_rid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13) => p_56_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12) => st_mr_rmesg(36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11) => st_mr_rmesg(69),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10) => st_mr_rmesg(65),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9) => st_mr_rmesg(60),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8 downto 7) => st_mr_rmesg(58 downto 57),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6 downto 3) => st_mr_rmesg(49 downto 46),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2) => st_mr_rmesg(44),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1) => st_mr_rmesg(42),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => st_mr_rmesg(38),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_master_slots[1].reg_slice_mi_n_5\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_26\,
m_axi_bready(0) => m_axi_bready(1),
m_axi_bvalid(0) => m_axi_bvalid(1),
m_axi_rdata(31 downto 0) => m_axi_rdata(63 downto 32),
m_axi_rid(11 downto 0) => m_axi_rid(23 downto 12),
m_axi_rlast(0) => m_axi_rlast(1),
\m_axi_rready[1]\ => M_AXI_RREADY(1),
m_axi_rresp(1 downto 0) => m_axi_rresp(3 downto 2),
m_axi_rvalid(0) => m_axi_rvalid(1),
\m_payload_i_reg[12]\(9) => st_mr_bid(34),
\m_payload_i_reg[12]\(8) => st_mr_bid(29),
\m_payload_i_reg[12]\(7 downto 5) => st_mr_bid(27 downto 25),
\m_payload_i_reg[12]\(4) => st_mr_bid(10),
\m_payload_i_reg[12]\(3) => st_mr_bid(5),
\m_payload_i_reg[12]\(2 downto 0) => st_mr_bid(3 downto 1),
\m_payload_i_reg[1]\(1 downto 0) => st_mr_bmesg(1 downto 0),
\m_payload_i_reg[32]\(20) => st_mr_rmesg(0),
\m_payload_i_reg[32]\(19 downto 17) => st_mr_rmesg(33 downto 31),
\m_payload_i_reg[32]\(16 downto 13) => st_mr_rmesg(29 downto 26),
\m_payload_i_reg[32]\(12) => st_mr_rmesg(24),
\m_payload_i_reg[32]\(11 downto 5) => st_mr_rmesg(21 downto 15),
\m_payload_i_reg[32]\(4) => st_mr_rmesg(10),
\m_payload_i_reg[32]\(3) => st_mr_rmesg(8),
\m_payload_i_reg[32]\(2 downto 0) => st_mr_rmesg(6 downto 4),
p_1_in => p_1_in,
p_32_out => p_32_out,
p_38_out => p_38_out,
p_54_out => p_54_out,
p_60_out => p_60_out,
s_axi_bid(4) => s_axi_bid(10),
s_axi_bid(3) => s_axi_bid(5),
s_axi_bid(2 downto 0) => s_axi_bid(3 downto 1),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_rdata(19 downto 17) => s_axi_rdata(30 downto 28),
s_axi_rdata(16 downto 13) => s_axi_rdata(26 downto 23),
s_axi_rdata(12) => s_axi_rdata(21),
s_axi_rdata(11 downto 5) => s_axi_rdata(18 downto 12),
s_axi_rdata(4) => s_axi_rdata(7),
s_axi_rdata(3) => s_axi_rdata(5),
s_axi_rdata(2 downto 0) => s_axi_rdata(3 downto 1),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(0)
);
\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(8),
O => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].w_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => addr_arbiter_aw_n_8,
Q => w_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => addr_arbiter_aw_n_7,
Q => w_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\,
Q => w_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => addr_arbiter_aw_n_9,
Q => w_issuing_cnt(9),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_master_slots[2].reg_slice_mi_n_45\,
Q => r_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].reg_slice_mi\: entity work.zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2
port map (
D(11 downto 0) => p_24_in(11 downto 0),
E(0) => \r_pipe/p_1_in\,
Q(4) => st_mr_bid(34),
Q(3) => st_mr_bid(29),
Q(2 downto 0) => st_mr_bid(27 downto 25),
S(0) => \gen_master_slots[2].reg_slice_mi_n_20\,
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_76\,
chosen(0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2),
chosen_0(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2),
\gen_axi.s_axi_arready_i_reg\ => addr_arbiter_ar_n_80,
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => p_20_in(11 downto 0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_4\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_26\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_45\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_13\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_master_slots[2].reg_slice_mi_n_19\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_master_slots[2].reg_slice_mi_n_28\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_master_slots[2].reg_slice_mi_n_29\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_master_slots[2].reg_slice_mi_n_21\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_master_slots[2].reg_slice_mi_n_22\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_master_slots[2].reg_slice_mi_n_23\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_master_slots[2].reg_slice_mi_n_24\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_master_slots[2].reg_slice_mi_n_25\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_master_slots[2].reg_slice_mi_n_26\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_master_slots[2].reg_slice_mi_n_27\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(12 downto 1) => st_mr_rid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0) => p_34_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8 downto 6),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_30\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[2].reg_slice_mi_n_31\,
\m_payload_i_reg[13]\(13) => st_mr_bid(23),
\m_payload_i_reg[13]\(12 downto 9) => st_mr_bid(21 downto 18),
\m_payload_i_reg[13]\(8) => st_mr_bid(16),
\m_payload_i_reg[13]\(7 downto 6) => st_mr_bid(12 downto 11),
\m_payload_i_reg[13]\(5 downto 2) => st_mr_bid(9 downto 6),
\m_payload_i_reg[13]\(1) => st_mr_bid(4),
\m_payload_i_reg[13]\(0) => st_mr_bid(0),
m_valid_i_reg => \gen_master_slots[2].reg_slice_mi_n_1\,
m_valid_i_reg_0 => \gen_master_slots[1].reg_slice_mi_n_6\,
mi_bready_2 => mi_bready_2,
mi_rready_2 => mi_rready_2,
p_15_in => p_15_in,
p_17_in => p_17_in,
p_1_in => p_1_in,
p_21_in => p_21_in,
p_32_out => p_32_out,
p_38_out => p_38_out,
r_issuing_cnt(0) => r_issuing_cnt(16),
s_axi_bid(6) => s_axi_bid(11),
s_axi_bid(5 downto 2) => s_axi_bid(9 downto 6),
s_axi_bid(1) => s_axi_bid(4),
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0),
s_ready_i_reg => \gen_master_slots[2].reg_slice_mi_n_5\,
st_aa_artarget_hot(1 downto 0) => st_aa_artarget_hot(1 downto 0),
w_issuing_cnt(0) => w_issuing_cnt(16)
);
\gen_master_slots[2].w_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\,
Q => w_issuing_cnt(16),
R => reset
);
\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor
port map (
E(0) => \r_pipe/p_1_in_0\,
SR(0) => reset,
aclk => aclk,
aresetn_d => aresetn_d,
chosen(2 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2 downto 0),
\gen_multi_thread.accept_cnt_reg[2]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\,
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\,
\gen_no_arbiter.m_target_hot_i_reg[2]_0\(0) => aa_mi_artarget_hot(2),
\gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_ar_n_81,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\,
\gen_no_arbiter.s_ready_i_reg[0]_1\ => \^s_axi_arready\(0),
\m_payload_i_reg[34]\(0) => \r_pipe/p_1_in\,
\m_payload_i_reg[46]\(25 downto 14) => st_mr_rid(11 downto 0),
\m_payload_i_reg[46]\(13) => p_76_out,
\m_payload_i_reg[46]\(12) => st_mr_rmesg(1),
\m_payload_i_reg[46]\(11) => st_mr_rmesg(34),
\m_payload_i_reg[46]\(10) => st_mr_rmesg(30),
\m_payload_i_reg[46]\(9) => st_mr_rmesg(25),
\m_payload_i_reg[46]\(8 downto 7) => st_mr_rmesg(23 downto 22),
\m_payload_i_reg[46]\(6 downto 3) => st_mr_rmesg(14 downto 11),
\m_payload_i_reg[46]\(2) => st_mr_rmesg(9),
\m_payload_i_reg[46]\(1) => st_mr_rmesg(7),
\m_payload_i_reg[46]\(0) => st_mr_rmesg(3),
\m_payload_i_reg[46]_0\(25 downto 14) => st_mr_rid(23 downto 12),
\m_payload_i_reg[46]_0\(13) => p_56_out,
\m_payload_i_reg[46]_0\(12) => st_mr_rmesg(36),
\m_payload_i_reg[46]_0\(11) => st_mr_rmesg(69),
\m_payload_i_reg[46]_0\(10) => st_mr_rmesg(65),
\m_payload_i_reg[46]_0\(9) => st_mr_rmesg(60),
\m_payload_i_reg[46]_0\(8 downto 7) => st_mr_rmesg(58 downto 57),
\m_payload_i_reg[46]_0\(6 downto 3) => st_mr_rmesg(49 downto 46),
\m_payload_i_reg[46]_0\(2) => st_mr_rmesg(44),
\m_payload_i_reg[46]_0\(1) => st_mr_rmesg(42),
\m_payload_i_reg[46]_0\(0) => st_mr_rmesg(38),
\m_payload_i_reg[46]_1\(12 downto 1) => st_mr_rid(35 downto 24),
\m_payload_i_reg[46]_1\(0) => p_34_out,
m_valid_i => m_valid_i,
p_32_out => p_32_out,
p_54_out => p_54_out,
p_74_out => p_74_out,
\s_axi_araddr[25]\(0) => st_aa_artarget_hot(0),
\s_axi_araddr[25]_0\ => addr_arbiter_ar_n_82,
\s_axi_araddr[31]\(27 downto 12) => \s_axi_arqos[3]\(31 downto 16),
\s_axi_araddr[31]\(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_rdata(11) => s_axi_rdata(31),
s_axi_rdata(10) => s_axi_rdata(27),
s_axi_rdata(9) => s_axi_rdata(22),
s_axi_rdata(8 downto 7) => s_axi_rdata(20 downto 19),
s_axi_rdata(6 downto 3) => s_axi_rdata(11 downto 8),
s_axi_rdata(2) => s_axi_rdata(6),
s_axi_rdata(1) => s_axi_rdata(4),
s_axi_rdata(0) => s_axi_rdata(0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(1),
s_axi_rvalid(0) => s_axi_rvalid(0),
st_aa_artarget_hot(0) => st_aa_artarget_hot(1)
);
\gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\
port map (
D(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\,
Q(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8 downto 6),
S(0) => \gen_master_slots[2].reg_slice_mi_n_20\,
SR(0) => reset,
aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(2),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
chosen(2 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2 downto 0),
\gen_master_slots[0].w_issuing_cnt_reg[1]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\,
\gen_master_slots[1].w_issuing_cnt_reg[10]\ => \gen_master_slots[1].reg_slice_mi_n_5\,
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\,
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ => \gen_master_slots[2].reg_slice_mi_n_30\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_21\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_22\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_23\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_24\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_25\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_26\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_27\,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\,
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_20,
\m_payload_i_reg[11]\ => \gen_master_slots[2].reg_slice_mi_n_28\,
\m_payload_i_reg[12]\ => \gen_master_slots[1].reg_slice_mi_n_23\,
\m_payload_i_reg[13]\ => \gen_master_slots[2].reg_slice_mi_n_29\,
\m_payload_i_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_13\,
\m_payload_i_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_12\,
\m_payload_i_reg[4]\ => \gen_master_slots[1].reg_slice_mi_n_20\,
\m_payload_i_reg[5]\ => \gen_master_slots[1].reg_slice_mi_n_21\,
\m_payload_i_reg[6]\ => \gen_master_slots[2].reg_slice_mi_n_19\,
\m_payload_i_reg[7]\ => \gen_master_slots[1].reg_slice_mi_n_22\,
\m_ready_d_reg[1]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\,
\m_ready_d_reg[1]_0\ => addr_arbiter_aw_n_14,
m_valid_i => m_valid_i_2,
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_6\,
p_38_out => p_38_out,
p_60_out => p_60_out,
p_80_out => p_80_out,
\s_axi_awaddr[31]\(27 downto 12) => D(31 downto 16),
\s_axi_awaddr[31]\(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
w_issuing_cnt(4) => w_issuing_cnt(16),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
\gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
ss_aa_awready => ss_aa_awready,
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid
);
\gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router
port map (
D(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\,
SR(0) => reset,
aclk => aclk,
\gen_axi.write_cs_reg[1]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\,
\gen_axi.write_cs_reg[1]_0\(0) => write_cs(1),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
m_ready_d(0) => m_ready_d(1),
p_14_in => p_14_in,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0)
);
splitter_aw_mi: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3
port map (
aa_mi_awtarget_hot(2 downto 0) => aa_mi_awtarget_hot(2 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_no_arbiter.m_target_hot_i_reg[1]\ => addr_arbiter_aw_n_3,
m_ready_d(1 downto 0) => m_ready_d_3(1 downto 0),
\m_ready_d_reg[0]_0\ => addr_arbiter_aw_n_21,
\m_ready_d_reg[0]_1\ => addr_arbiter_aw_n_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "axi_crossbar_v2_1_14_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b11";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b11";
attribute P_ONES : string;
attribute P_ONES of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 63 downto 32 );
signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 63 downto 32 );
signal \^m_axi_awburst\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \^m_axi_awcache\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^m_axi_awprot\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^m_axi_awqos\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\(0) <= s_axi_wlast(0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(63 downto 32) <= \^m_axi_araddr\(63 downto 32);
m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(63 downto 32);
m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(3 downto 2);
m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(3 downto 2);
m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(7 downto 4);
m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(7 downto 4);
m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_arlen(15 downto 8) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlock(1) <= \^m_axi_arlock\(1);
m_axi_arlock(0) <= \^m_axi_arlock\(1);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(5 downto 3);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(5 downto 3);
m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(7 downto 4);
m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(7 downto 4);
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(5 downto 3);
m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(5 downto 3);
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(63 downto 32) <= \^m_axi_awaddr\(63 downto 32);
m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(63 downto 32);
m_axi_awburst(3 downto 2) <= \^m_axi_awburst\(3 downto 2);
m_axi_awburst(1 downto 0) <= \^m_axi_awburst\(3 downto 2);
m_axi_awcache(7 downto 4) <= \^m_axi_awcache\(7 downto 4);
m_axi_awcache(3 downto 0) <= \^m_axi_awcache\(7 downto 4);
m_axi_awid(23 downto 12) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(11 downto 0) <= \^m_axi_awid\(11 downto 0);
m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(15 downto 8);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(15 downto 8);
m_axi_awlock(1) <= \^m_axi_awlock\(1);
m_axi_awlock(0) <= \^m_axi_awlock\(1);
m_axi_awprot(5 downto 3) <= \^m_axi_awprot\(5 downto 3);
m_axi_awprot(2 downto 0) <= \^m_axi_awprot\(5 downto 3);
m_axi_awqos(7 downto 4) <= \^m_axi_awqos\(7 downto 4);
m_axi_awqos(3 downto 0) <= \^m_axi_awqos\(7 downto 4);
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(5 downto 3) <= \^m_axi_awsize\(5 downto 3);
m_axi_awsize(2 downto 0) <= \^m_axi_awsize\(5 downto 3);
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(23) <= \<const0>\;
m_axi_wid(22) <= \<const0>\;
m_axi_wid(21) <= \<const0>\;
m_axi_wid(20) <= \<const0>\;
m_axi_wid(19) <= \<const0>\;
m_axi_wid(18) <= \<const0>\;
m_axi_wid(17) <= \<const0>\;
m_axi_wid(16) <= \<const0>\;
m_axi_wid(15) <= \<const0>\;
m_axi_wid(14) <= \<const0>\;
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(1) <= \^s_axi_wlast\(0);
m_axi_wlast(0) <= \^s_axi_wlast\(0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_samd.crossbar_samd\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar
port map (
D(56 downto 53) => s_axi_awqos(3 downto 0),
D(52 downto 49) => s_axi_awcache(3 downto 0),
D(48 downto 47) => s_axi_awburst(1 downto 0),
D(46 downto 44) => s_axi_awprot(2 downto 0),
D(43) => s_axi_awlock(0),
D(42 downto 40) => s_axi_awsize(2 downto 0),
D(39 downto 32) => s_axi_awlen(7 downto 0),
D(31 downto 0) => s_axi_awaddr(31 downto 0),
M_AXI_RREADY(1 downto 0) => m_axi_rready(1 downto 0),
Q(68 downto 65) => \^m_axi_awqos\(7 downto 4),
Q(64 downto 61) => \^m_axi_awcache\(7 downto 4),
Q(60 downto 59) => \^m_axi_awburst\(3 downto 2),
Q(58 downto 56) => \^m_axi_awprot\(5 downto 3),
Q(55) => \^m_axi_awlock\(1),
Q(54 downto 52) => \^m_axi_awsize\(5 downto 3),
Q(51 downto 44) => \^m_axi_awlen\(15 downto 8),
Q(43 downto 12) => \^m_axi_awaddr\(63 downto 32),
Q(11 downto 0) => \^m_axi_awid\(11 downto 0),
S_AXI_ARREADY(0) => s_axi_arready(0),
aclk => aclk,
aresetn => aresetn,
\m_axi_arqos[7]\(68 downto 65) => \^m_axi_arqos\(7 downto 4),
\m_axi_arqos[7]\(64 downto 61) => \^m_axi_arcache\(7 downto 4),
\m_axi_arqos[7]\(60 downto 59) => \^m_axi_arburst\(3 downto 2),
\m_axi_arqos[7]\(58 downto 56) => \^m_axi_arprot\(5 downto 3),
\m_axi_arqos[7]\(55) => \^m_axi_arlock\(1),
\m_axi_arqos[7]\(54 downto 52) => \^m_axi_arsize\(5 downto 3),
\m_axi_arqos[7]\(51 downto 44) => \^m_axi_arlen\(7 downto 0),
\m_axi_arqos[7]\(43 downto 12) => \^m_axi_araddr\(63 downto 32),
\m_axi_arqos[7]\(11 downto 0) => \^m_axi_arid\(11 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
m_axi_bid(23 downto 0) => m_axi_bid(23 downto 0),
m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0),
m_axi_bresp(3 downto 0) => m_axi_bresp(3 downto 0),
m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(23 downto 0) => m_axi_rid(23 downto 0),
m_axi_rlast(1 downto 0) => m_axi_rlast(1 downto 0),
m_axi_rresp(3 downto 0) => m_axi_rresp(3 downto 0),
m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
\s_axi_arqos[3]\(56 downto 53) => s_axi_arqos(3 downto 0),
\s_axi_arqos[3]\(52 downto 49) => s_axi_arcache(3 downto 0),
\s_axi_arqos[3]\(48 downto 47) => s_axi_arburst(1 downto 0),
\s_axi_arqos[3]\(46 downto 44) => s_axi_arprot(2 downto 0),
\s_axi_arqos[3]\(43) => s_axi_arlock(0),
\s_axi_arqos[3]\(42 downto 40) => s_axi_arsize(2 downto 0),
\s_axi_arqos[3]\(39 downto 32) => s_axi_arlen(7 downto 0),
\s_axi_arqos[3]\(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wlast(0) => \^s_axi_wlast\(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_xbar_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_xbar_0 : entity is "zynq_design_1_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_xbar_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_xbar_0 : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2";
end zynq_design_1_xbar_0;
architecture STRUCTURE of zynq_design_1_xbar_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "64'b0000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 2;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 8;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "2'b11";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "2'b11";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(63 downto 0) => m_axi_araddr(63 downto 0),
m_axi_arburst(3 downto 0) => m_axi_arburst(3 downto 0),
m_axi_arcache(7 downto 0) => m_axi_arcache(7 downto 0),
m_axi_arid(23 downto 0) => m_axi_arid(23 downto 0),
m_axi_arlen(15 downto 0) => m_axi_arlen(15 downto 0),
m_axi_arlock(1 downto 0) => m_axi_arlock(1 downto 0),
m_axi_arprot(5 downto 0) => m_axi_arprot(5 downto 0),
m_axi_arqos(7 downto 0) => m_axi_arqos(7 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_arregion(7 downto 0) => m_axi_arregion(7 downto 0),
m_axi_arsize(5 downto 0) => m_axi_arsize(5 downto 0),
m_axi_aruser(1 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(1 downto 0),
m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
m_axi_awaddr(63 downto 0) => m_axi_awaddr(63 downto 0),
m_axi_awburst(3 downto 0) => m_axi_awburst(3 downto 0),
m_axi_awcache(7 downto 0) => m_axi_awcache(7 downto 0),
m_axi_awid(23 downto 0) => m_axi_awid(23 downto 0),
m_axi_awlen(15 downto 0) => m_axi_awlen(15 downto 0),
m_axi_awlock(1 downto 0) => m_axi_awlock(1 downto 0),
m_axi_awprot(5 downto 0) => m_axi_awprot(5 downto 0),
m_axi_awqos(7 downto 0) => m_axi_awqos(7 downto 0),
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_awregion(7 downto 0) => m_axi_awregion(7 downto 0),
m_axi_awsize(5 downto 0) => m_axi_awsize(5 downto 0),
m_axi_awuser(1 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(1 downto 0),
m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
m_axi_bid(23 downto 0) => m_axi_bid(23 downto 0),
m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0),
m_axi_bresp(3 downto 0) => m_axi_bresp(3 downto 0),
m_axi_buser(1 downto 0) => B"00",
m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(23 downto 0) => m_axi_rid(23 downto 0),
m_axi_rlast(1 downto 0) => m_axi_rlast(1 downto 0),
m_axi_rready(1 downto 0) => m_axi_rready(1 downto 0),
m_axi_rresp(3 downto 0) => m_axi_rresp(3 downto 0),
m_axi_ruser(1 downto 0) => B"00",
m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wid(23 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(23 downto 0),
m_axi_wlast(1 downto 0) => m_axi_wlast(1 downto 0),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wuser(1 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
| mit | bea811a7e45606fd9691c97a64514a90 | 0.562699 | 2.590374 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/tmp.srcs/sources_1/ip/convolve_kernel_ap_fmul_2_max_dsp_32/hdl/xbip_utils_v3_0_vh_rfs.vhd | 16 | 168,945 | `protect begin_protected
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`protect end_protected
| mit | cd737bc6d75472cc702664755308089d | 0.954683 | 1.81116 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Accum/src/DPATH.vhd | 1 | 1,565 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library accum;
use accum.OneHotAccum.all;
entity DPATH is
port(
EN: in std_logic;
-- operation type
OT: in operation;
-- operand
OP1: in operand;
RES: out operand;
-- zero flag
ZF: out std_logic
);
end DPATH;
architecture Beh of DPATH is
signal ACCUM: operand;
signal res_add: operand;
signal res_sub: operand;
signal res_shift: operand;
signal t_zf: std_logic;
Begin
res_add <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(ACCUM) + CONV_INTEGER(OP1), 16);
res_sub <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(ACCUM) - CONV_INTEGER(OP1), 16);
REGA: process (EN, OT, OP1, res_add, res_sub, res_shift)
begin
if rising_edge(EN) then
case OT is
when LOAD => ACCUM <= OP1;
when ADD => ACCUM <= res_add;
when SUBT => ACCUM <= res_sub;
when SHIFT => ACCUM <= res_shift;
when others => null;
end case;
end if;
end process;
FLAGS: process(ACCUM)
begin
if ACCUM = (ACCUM'range => '0') then
t_zf <= '1';
else
t_zf <= '0';
end if;
end process;
GRAY: process(ACCUM)
begin
for i in 0 to 14 loop
res_shift(i) <= ACCUM(i) xor ACCUM(i+1);
end loop;
res_shift(15) <= ACCUM(15);
end process;
RES <= ACCUM;
ZF <= t_zf;
End Beh; | mit | 2a068bbdba8700f01d85c13d888c9c00 | 0.531629 | 3.372845 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/apbps2.vhd | 1 | 13,596 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbps2
-- File: apbps2.vhd
-- Author: Marcus Hellqvist, Jiri Gaisler
-- Modified by: Jan Andersson
-- Description: PS/2 keyboard interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity apbps2 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 0;
oepol : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end;
architecture rtl of apbps2 is
constant fifosize : integer := 16;
type rxstates is (idle,start,data,parity,stop);
type txstates is (idle,waitrequest,start,data,parity,stop,ack);
type fifotype is array(0 to fifosize-1) of std_logic_vector(7 downto 0);
type ps2_regs is record
-- status reg
data_ready : std_ulogic; -- data ready
parity_error : std_ulogic; -- parity carry out/ error bit
frame_error : std_ulogic; -- frame error when receiving
kb_inh : std_ulogic; -- keyboard inhibit
rbf : std_ulogic; -- receiver buffer full
tbf : std_ulogic; -- transmitter buffer full
rcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
tcnt : std_logic_vector(log2x(fifosize) downto 0); -- fifo counter
-- control reg
rx_en : std_ulogic; -- receive enable
tx_en : std_ulogic; -- transmit enable
rx_irq_en : std_ulogic; -- keyboard interrupt enable
tx_irq_en : std_ulogic; -- transmit interrupt enable
-- others
tx_act : std_ulogic; -- tx active
rxdf : std_logic_vector(4 downto 0); -- rx data filter
rxcf : std_logic_vector(4 downto 0); -- rx clock filter
rx_irq : std_ulogic; -- keyboard interrupt
tx_irq : std_ulogic; -- transmit interrupt
rxfifo : fifotype; -- fifo with 16 bytes
rraddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
rwaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
rxstate : rxstates;
txfifo : fifotype; -- fifo with 16 bytes
traddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo read address
twaddr : std_logic_vector(log2x(fifosize)-1 downto 0); -- fifo write address
txstate : txstates;
ps2_clk_syn : std_ulogic; -- ps2 clock synchronized
ps2_data_syn : std_ulogic; -- ps2 data synchronized
ps2_clk_fall : std_ulogic; -- ps2 clock falling edge detector
rshift : std_logic_vector(7 downto 0); -- shift register
rpar : std_ulogic; -- parity check bit
tshift : std_logic_vector(9 downto 0); -- shift register
tpar : std_ulogic; -- transmit parity bit
ps2clk : std_ulogic; -- ps2 clock
ps2data : std_ulogic; -- ps2 data
ps2clkoe : std_ulogic; -- ps2 clock output enable
ps2dataoe : std_ulogic; -- ps2 data output enable
timer : std_logic_vector(16 downto 0); -- timer
reload : std_logic_vector(16 downto 0); -- reload register
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
constant REVISION : integer := 2;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBPS2, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant OUTPUT : std_ulogic := conv_std_logic(oepol = 1);
constant INPUT : std_ulogic := conv_std_logic(oepol = 0);
signal r, rin : ps2_regs;
signal ps2_clk, ps2_data : std_ulogic;
begin
ps2_op : process(r, rst, ps2_clk, ps2_data,apbi)
variable v : ps2_regs;
variable rdata : std_logic_vector(31 downto 0);
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r;
rdata := (others => '0'); v.data_ready := '0'; irq := (others => '0'); irq(pirq) := r.rx_irq or r.tx_irq;
v.rx_irq := '0'; v.tx_irq := '0'; v.rbf := r.rcnt(log2x(fifosize)); v.tbf := r.tcnt(log2x(fifosize));
if r.rcnt /= rcntzero then v.data_ready := '1'; end if;
-- Synchronize and filter ps2 input
v.rxdf(0) := ps2_data; v.rxdf(4 downto 1) := r.rxdf(3 downto 0);
v.rxcf(0) := ps2_clk; v.rxcf(4 downto 1) := r.rxcf(3 downto 0);
if (r.rxdf(4) & r.rxdf(4) & r.rxdf(4) & r.rxdf(4)) = r.rxdf(3 downto 0) then
v.ps2_data_syn := r.rxdf(4);
end if;
if (r.rxcf(4) & r.rxcf(4) & r.rxcf(4) & r.rxcf(4)) = r.rxcf(3 downto 0) then
v.ps2_clk_syn := r.rxcf(4);
end if;
if (v.ps2_clk_syn /= r.ps2_clk_syn) and (v.ps2_clk_syn = '0') then
v.ps2_clk_fall := '1';
else
v.ps2_clk_fall := '0';
end if;
-- read registers
case apbi.paddr(3 downto 2) is
when "00" =>
rdata(7 downto 0) := r.rxfifo(conv_integer(r.rraddr));
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
if r.rcnt /= rcntzero then
v.rxfifo(conv_integer(r.rraddr)) := (others => '0');
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "01" =>
rdata(27 + log2x(fifosize) downto 27) := r.rcnt;
rdata(22 + log2x(fifosize) downto 22) := r.tcnt;
rdata(5 downto 0) := r.tbf & r.rbf & r.kb_inh & r.frame_error & r.parity_error & r.data_ready;
when "10" =>
rdata(3 downto 0) := r.tx_irq_en & r.rx_irq_en & r.tx_en & r.rx_en;
when others =>
if fixed = 0 then rdata(r.reload'range) := r.reload; end if;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
if r.tcnt(log2x(fifosize)) = '0' then
v.txfifo(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
v.twaddr := r.twaddr + 1; v.tcnt := r.tcnt + 1;
end if;
when "01" =>
v.kb_inh := apbi.pwdata(3);
v.frame_error := apbi.pwdata(2);
v.parity_error := apbi.pwdata(1);
when "10" =>
v.tx_irq_en := apbi.pwdata(3);
v.rx_irq_en := apbi.pwdata(2);
v.tx_en := apbi.pwdata(1);
v.rx_en := apbi.pwdata(0);
when "11" =>
if fixed = 0 then
v.reload := apbi.pwdata(r.reload'range);
end if;
when others =>
null;
end case;
end if;
case r.txstate is
when idle =>
if r.tx_en = '1' and r.tcnt /= rcntzero then
v.ps2clk := '0'; v.ps2clkoe := OUTPUT; v.tx_act := '1';
v.ps2data := '1'; v.ps2dataoe := OUTPUT; v.txstate := waitrequest;
if fixed = 1 then v.timer := conv_std_logic_vector(fKHz/10,r.timer'length);
else v.timer := r.reload; end if;
end if;
when waitrequest =>
v.timer := r.timer - 1;
if (v.timer(r.timer'left) and not r.timer(r.timer'left)) = '1' then
v.ps2data := '0'; v.txstate := start;
end if;
when start =>
v.ps2clkoe := INPUT; v.ps2clk := '1';
v.tshift := "10" & r.txfifo(conv_integer(r.traddr));
v.traddr := r.traddr + 1; v.tcnt := r.tcnt - 1;
v.tpar := '1';
v.txstate := data;
when data =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tshift(0);
v.tpar := r.tpar xor r.tshift(0);
v.tshift := '1' & r.tshift(9 downto 1);
if v.tshift = "1111111110" then v.txstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.ps2data := r.tpar; v.txstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
v.ps2data := '1'; v.txstate := ack;
end if;
when ack =>
v.ps2dataoe := INPUT;
if r.ps2_clk_fall = '1' and r.ps2_data_syn = '0'then
v.ps2data := '1'; v.ps2dataoe := OUTPUT; v.tx_irq := r.tx_irq_en;
v.txstate := idle; v.tx_act := '0';
end if;
end case;
-- receiver state machine
case r.rxstate is
when idle =>
if (r.rx_en and not r.tx_act) = '1' then
v.rshift := (others => '1'); v.rxstate := start;
end if;
when start =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '0' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rxstate := data; v.rpar := '0';
v.parity_error := '0'; v.frame_error := '0';
else v.rxstate := idle; end if;
end if;
when data =>
if r.ps2_clk_fall = '1' then
v.rshift := r.ps2_data_syn & r.rshift(7 downto 1);
v.rpar := r.rpar xor r.ps2_data_syn;
if r.rshift(0) = '0' then v.rxstate := parity; end if;
end if;
when parity =>
if r.ps2_clk_fall = '1' then
v.parity_error := r.rpar xor (not r.ps2_data_syn);
v.rxstate := stop;
end if;
when stop =>
if r.ps2_clk_fall = '1' then
if r.ps2_data_syn = '1' then
v.rx_irq := r.rx_irq_en; v.rxstate := idle;
if (r.rbf or r.parity_error) = '0' then
v.rxfifo(conv_integer(r.rwaddr)) := r.rshift(7 downto 0);
v.rwaddr := r.rwaddr + 1; v.rcnt := r.rcnt + 1;
end if;
else v.frame_error := '1'; v.rxstate := idle; end if;
end if;
end case;
-- keyboard inhibit / high impedance
if v.tx_act = '0' then
if r.rbf = '1' then
v.kb_inh := '1'; v.ps2clk := '0'; v.ps2data := '1';
v.ps2dataoe := OUTPUT; v.ps2clkoe := OUTPUT;
else
v.ps2clk := '1'; v.ps2data := '1'; v.ps2dataoe := INPUT;
v.ps2clkoe := INPUT;
end if;
end if;
if r.tx_act = '1' then
v.rxstate := idle;
end if;
-- reset operations
if rst = '0' then
v.data_ready := '0'; v.kb_inh := '0'; v.parity_error := '0';
v.frame_error := '0'; v.rx_en := '0'; v.tx_act := '0';
v.tx_en := '0'; v.rx_irq := '0'; v.tx_irq := '0';
v.ps2_clk_fall := '0'; v.ps2_clk_syn := '0'; v.ps2_data_syn := '0';
v.rshift := (others => '0'); v.rxstate := idle; v.txstate := idle;
v.rraddr := (others => '0'); v.rwaddr := (others => '0');
v.rcnt := (others => '0'); v.traddr := (others => '0');
v.twaddr := (others => '0'); v.tcnt := (others => '0');
v.tshift := (others => '0'); v.tpar := '0';
if fixed = 0 then
v.reload := conv_std_logic_vector(fKHz/10,r.reload'length);
end if;
end if;
if fixed = 1 then v.reload := (others => '0'); end if;
-- update registers
rin <= v;
-- drive outputs
apbo.prdata <= rdata;
apbo.pirq <= irq;
apbo.pindex <= pindex;
ps2o.ps2_clk_o <= r.ps2clk;
ps2o.ps2_clk_oe <= r.ps2clkoe;
ps2o.ps2_data_o <= r.ps2data;
ps2o.ps2_data_oe <= r.ps2dataoe;
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
ps2_data <= to_x01(ps2i.ps2_data_i);
ps2_clk <= to_x01(ps2i.ps2_clk_i);
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbps2_" & tost(pindex) & ": APB PS2 interface rev " &
tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
| gpl-2.0 | 62b0f5bb0792765fd5514aa9278865c2 | 0.510003 | 3.349593 | false | false | false | false |
juskojan/Bc.FIT | 3BIT/IMP/fpga/top_level.vhd | 1 | 6,288 | -- top_level.vhd : keyboard + lcd
-- Copyright (C) 2009 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek vasicek AT fit.vutbr.cz
--
-- LICENSE TERMS
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. All advertising materials mentioning features or use of this software
-- or firmware must display the following acknowledgement:
--
-- This product includes software developed by the University of
-- Technology, Faculty of Information Technology, Brno and its
-- contributors.
--
-- 4. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software or firmware is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id$
--
--
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_ARITH.ALL;
use ieee.std_logic_UNSIGNED.ALL;
architecture main of tlv_bare_ifc is
-----------------------------------------------------------------------------
-- Signaly
-- Keyboard 4x4
signal key_data_in : std_logic_vector (15 downto 0);
-- displej
signal dis_addr : std_logic_vector(0 downto 0);
signal dis_data_out : std_logic_vector(15 downto 0);
signal dis_write_en : std_logic;
signal led : std_logic;
-----------------------------------------------------------------------------
-- POUZITE KOMPONENTY
component SPI_adc
generic (
ADDR_WIDTH : integer;
DATA_WIDTH : integer;
ADDR_OUT_WIDTH : integer;
BASE_ADDR : integer
);
port (
CLK : in std_logic;
CS : in std_logic;
DO : in std_logic;
DO_VLD : in std_logic;
DI : out std_logic;
DI_REQ : in std_logic;
ADDR : out std_logic_vector (ADDR_OUT_WIDTH-1 downto 0);
DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0);
DATA_IN : in std_logic_vector (DATA_WIDTH-1 downto 0);
WRITE_EN : out std_logic;
READ_EN : out std_logic
);
end component;
-- Keyboard 4x4
component keyboard_controller
port(
CLK : in std_logic;
RST : in std_logic;
DATA_OUT : out std_logic_vector(15 downto 0);
DATA_VLD : out std_logic;
KB_KIN : out std_logic_vector(3 downto 0);
KB_KOUT : in std_logic_vector(3 downto 0)
);
end component;
component lcd_raw_controller
port (
RST : in std_logic;
CLK : in std_logic;
DATA_IN : in std_logic_vector (15 downto 0);
WRITE_EN : in std_logic;
DISPLAY_RS : out std_logic;
DISPLAY_DATA : inout std_logic_vector(7 downto 0);
DISPLAY_RW : out std_logic;
DISPLAY_EN : out std_logic
);
end component;
begin
LEDF <= '0';
-- Adresovy dekoder
SPI_adc_keybrd: SPI_adc
generic map(
ADDR_WIDTH => 8, -- sirka adresy 8 bitu
DATA_WIDTH => 16, -- sirka dat 16 bitu
ADDR_OUT_WIDTH => 1, -- sirka adresy na vystupu min. 1 bit
BASE_ADDR => 16#0002# -- adresovy prostor od 0x0002
)
port map(
CLK => CLK,
CS => SPI_CS,
DO => SPI_DO,
DO_VLD => SPI_DO_VLD,
DI => SPI_DI,
DI_REQ => SPI_DI_REQ,
ADDR => open,
DATA_OUT => open,
DATA_IN => key_data_in,
WRITE_EN => open,
READ_EN => open
);
-- Radic klavesnice
keybrd: keyboard_controller
port map(
CLK => CLK,
RST => RESET, -- reset
DATA_OUT => key_data_in,
DATA_VLD => open,
-- Keyboart
KB_KIN => KIN,
KB_KOUT => KOUT
);
-- SPI dekoder pro displej
spidecd: SPI_adc
generic map (
ADDR_WIDTH => 8, -- sirka adresy 8 bitu
DATA_WIDTH => 16, -- sirka dat 16 bitu
ADDR_OUT_WIDTH => 1, -- sirka adresy na vystupu 1 bit
BASE_ADDR => 16#00# -- adresovy prostor od 0x00-0x01
)
port map (
CLK => CLK,
CS => SPI_CS,
DO => SPI_DO,
DO_VLD => SPI_DO_VLD,
DI => SPI_DI,
DI_REQ => SPI_DI_REQ,
ADDR => dis_addr,
DATA_OUT => dis_data_out,
DATA_IN => "0000000000000000",
WRITE_EN => dis_write_en,
READ_EN => open
);
-- radic LCD displeje
lcdctrl: lcd_raw_controller
port map (
RST => RESET,
CLK => CLK,
-- ridici signaly
DATA_IN => dis_data_out,
WRITE_EN => dis_write_en,
--- signaly displeje
DISPLAY_RS => LRS,
DISPLAY_DATA => LD,
DISPLAY_RW => LRW,
DISPLAY_EN => LE
);
end main;
| gpl-3.0 | e66f937d206c76c99d7ae86ce289b3ca | 0.547551 | 3.984791 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/eth/core/greth_pkg.vhd | 1 | 23,863 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
package grethpkg is
--gigabit sync types
type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0);
type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0);
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1500, 16);
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
type ahb_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(4 downto 0);
write : std_ulogic;
data : std_logic_vector(31 downto 0);
waddress : std_logic_vector(4 downto 0);
end record;
type ahb_fifo_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type nchar_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(5 downto 0);
write : std_ulogic;
data : std_logic_vector(8 downto 0);
waddress : std_logic_vector(5 downto 0);
end record;
type nchar_fifo_out_type is record
data : std_logic_vector(8 downto 0);
end record;
type rmapbuf_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(7 downto 0);
write : std_ulogic;
data : std_logic_vector(7 downto 0);
waddress : std_logic_vector(7 downto 0);
end record;
type rmapbuf_out_type is record
data : std_logic_vector(7 downto 0);
end record;
type ahbc_mst_in_type is record
hgrant : std_ulogic; -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type ahbc_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_in_type is record
psel : std_ulogic; -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type gbit_host_tx_type is record
full_duplex : std_ulogic;
start : std_ulogic;
read_ack : std_ulogic;
data : std_logic_vector(31 downto 0);
datavalid : std_ulogic;
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type gbit_rx_host_type is record
sync_start : std_ulogic;
done : std_ulogic;
write : std_logic_vector(3 downto 0);
dataout : data_sync_type;
byte_count : std_logic_vector(10 downto 0);
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
end record;
type gbit_host_rx_type is record
full_duplex : std_ulogic;
gbit : std_ulogic;
doneack : std_ulogic;
writeack : std_logic_vector(3 downto 0);
speed : std_ulogic;
writeok : std_logic_vector(3 downto 0);
rxenable : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
rx_en : std_ulogic;
end record;
type gbit_gtx_host_type is record
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
read : std_logic_vector(3 downto 0);
status : std_logic_vector(2 downto 0);
end record;
type gbit_host_gtx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
burstmode : std_ulogic;
txen : std_ulogic;
start_sync : std_ulogic;
readack : std_logic_vector(3 downto 0);
valid : std_logic_vector(3 downto 0);
data : data_sync_type;
len : std_logic_vector(10 downto 0);
end record;
type host_tx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
start : std_ulogic;
readack : std_ulogic;
speed : std_ulogic;
data : std_logic_vector(31 downto 0);
datavalid : std_ulogic;
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
end record;
type tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type rx_host_type is record
dataout : std_logic_vector(31 downto 0);
start : std_ulogic;
done : std_ulogic;
write : std_ulogic;
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
lentype : std_logic_vector(15 downto 0);
mcasthash : std_logic_vector(5 downto 0);
end record;
type host_rx_type is record
writeack : std_ulogic;
doneack : std_ulogic;
speed : std_ulogic;
writeok : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_crs : std_ulogic;
rx_er : std_ulogic;
enable : std_ulogic;
rx_en : std_ulogic;
end record;
component greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end component;
component greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end component;
component eth_rstgen is
generic(acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end component;
component greth_gbit_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in gbit_host_tx_type;
txo : out gbit_tx_host_type);
end component;
component greth_gbit_gtx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2);
port(
rst : in std_ulogic;
clk : in std_ulogic;
gtxi : in gbit_host_gtx_type;
gtxo : out gbit_gtx_host_type
);
end component;
component greth_gbit_rx is
generic(
multicast : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in gbit_host_rx_type;
rxo : out gbit_rx_host_type);
end component;
component eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type);
end component;
component eth_edcl_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type
);
end component;
function mirror(din : in std_logic_vector) return std_logic_vector;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector;
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer;
function setburstlength(fifosize : in integer) return integer;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector;
end package;
package body grethpkg is
function mirror(din : in std_logic_vector)
return std_logic_vector is
variable do : std_logic_vector(din'range);
begin
for i in 0 to din'length-1 loop
do(din'high-i) := din(i+din'low);
end loop;
return do;
end function;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(16 downto 0);
variable vd2 : std_logic_vector(16 downto 0);
variable sum : std_logic_vector(16 downto 0);
begin
vd1 := '0' & d1; vd2 := '0' & d2;
sum := vd1 + vd2;
sum(15 downto 0) := sum(15 downto 0) + sum(16);
return sum(15 downto 0);
end function;
--16-bit one's complement adder for ip/tcp checksum detection
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(25 downto 0);
variable vd2 : std_logic_vector(25 downto 0);
variable sum : std_logic_vector(25 downto 0);
begin
vd1 := "0000000000" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic is
variable valid : std_ulogic;
begin
valid := '1';
if usesz = '1' then
if len > minpload then
if bcnt /= len then
valid := '0';
end if;
else
if bcnt /= minpload then
valid := '0';
end if;
end if;
end if;
return valid;
end function;
function setburstlength(fifosize : in integer) return integer is
begin
if fifosize <= 64 then
return fifosize/2;
else
return 32;
end if;
end function;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
function calccrc_8(data : in std_logic_vector( 7 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable d : std_logic_vector(7 downto 0);
begin
d(7) := data(0); d(6) := data(1); d(5) := data(2); d(4) := data(3);
d(3) := data(4); d(2) := data(5); d(1) := data(6); d(0) := data(7);
ncrc(0) := d(6) xor d(0) xor crc(24) xor crc(30);
ncrc(1) := d(7) xor d(6) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(30) xor crc(31);
ncrc(2) := d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(26) xor crc(30) xor crc(31);
ncrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(27) xor crc(31);
ncrc(4) := d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(28) xor crc(30);
ncrc(5) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28) xor crc(29) xor crc(30) xor crc(31);
ncrc(6) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30) xor crc(31);
ncrc(7) := d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(29) xor crc(31);
ncrc(8) := d(4) xor d(3) xor d(1) xor d(0) xor crc(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28);
ncrc(9) := d(5) xor d(4) xor d(2) xor d(1) xor crc(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29);
ncrc(10) := d(5) xor d(3) xor d(2) xor d(0) xor crc(2) xor crc(24) xor crc(26) xor crc(27) xor crc(29);
ncrc(11) := d(4) xor d(3) xor d(1) xor d(0) xor crc(3) xor crc(24) xor crc(25) xor crc(27) xor crc(28);
ncrc(12) := d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor crc(4) xor crc(24) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30);
ncrc(13) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor crc(5) xor crc(25) xor crc(26) xor crc(27) xor crc(29) xor crc(30) xor crc(31);
ncrc(14) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor crc(6) xor crc(26) xor crc(27) xor crc(28) xor crc(30) xor crc(31);
ncrc(15) := d(7) xor d(5) xor d(4) xor d(3) xor crc(7) xor crc(27) xor crc(28) xor crc(29) xor crc(31);
ncrc(16) := d(5) xor d(4) xor d(0) xor crc(8) xor crc(24) xor crc(28) xor crc(29);
ncrc(17) := d(6) xor d(5) xor d(1) xor crc(9) xor crc(25) xor crc(29) xor crc(30);
ncrc(18) := d(7) xor d(6) xor d(2) xor crc(10) xor crc(26) xor crc(30) xor crc(31);
ncrc(19) := d(7) xor d(3) xor crc(11) xor crc(27) xor crc(31);
ncrc(20) := d(4) xor crc(12) xor crc(28);
ncrc(21) := d(5) xor crc(13) xor crc(29);
ncrc(22) := d(0) xor crc(14) xor crc(24);
ncrc(23) := d(6) xor d(1) xor d(0) xor crc(15) xor crc(24) xor crc(25) xor crc(30);
ncrc(24) := d(7) xor d(2) xor d(1) xor crc(16) xor crc(25) xor crc(26) xor crc(31);
ncrc(25) := d(3) xor d(2) xor crc(17) xor crc(26) xor crc(27);
ncrc(26) := d(6) xor d(4) xor d(3) xor d(0) xor crc(18) xor crc(24) xor crc(27) xor crc(28) xor crc(30);
ncrc(27) := d(7) xor d(5) xor d(4) xor d(1) xor crc(19) xor crc(25) xor crc(28) xor crc(29) xor crc(31);
ncrc(28) := d(6) xor d(5) xor d(2) xor crc(20) xor crc(26) xor crc(29) xor crc(30);
ncrc(29) := d(7) xor d(6) xor d(3) xor crc(21) xor crc(27) xor crc(30) xor crc(31);
ncrc(30) := d(7) xor d(4) xor crc(22) xor crc(28) xor crc(31);
ncrc(31) := d(5) xor crc(23) xor crc(29);
return ncrc;
end function;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(17 downto 0);
variable vd2 : std_logic_vector(17 downto 0);
variable sum : std_logic_vector(17 downto 0);
begin
vd1 := "00" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
end package body;
| gpl-2.0 | 320cb29faab71a0acd4552acd4748b4f | 0.55211 | 3.070776 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-gr-cpci-xc4v/testbench.vhd | 1 | 15,895 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
port (
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic := '1';
pci_int : inout std_logic_vector(3 downto 0);
pci_66 : in std_logic := '0'
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_logic;
signal oen : std_logic;
signal read : std_logic;
signal writen : std_logic;
signal brdyn : std_logic;
signal bexcn : std_logic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal test : std_logic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_logic := '0';
signal VCC : std_logic := '1';
signal NC : std_logic := 'Z';
signal clk2 : std_logic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic;
signal gtx_clk : std_logic := '0';
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
signal led_cfg: std_logic_vector(2 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_stb : std_logic;
signal spw_clk : std_logic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after 10 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
led_cfg<="000"; --put the phy in base10h mode
can_rxd <= (others => 'H'); bexcn <= '1'; wdogn <= 'H';
gpio(2 downto 0) <= "LHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
pci_arb_req <= "HHHH";
-- spacewire loop-back
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, sdclk, error, wdogn, address(27 downto 0), data,
sa, sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1,
txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_int, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd,
spw_clk, spw_rxdp, spw_rxdn, spw_rxsp, spw_rxsn, spw_txdp,
spw_txdn, spw_txsp, spw_txsn
);
-- optional sdram
sd0 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
sd1 : if ((CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1)) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
sd64 : if (CFG_MCTRL_SD64 = 1) generate
u4: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u5: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u6: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u7: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
-- data <= buskeep(data), (others => 'H') after 250 ns;
data <= buskeep(data) after 5 ns;
-- sd <= buskeep(sd), (others => 'H') after 250 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | a331d033f4b2d6fa39a933871b802085 | 0.573073 | 3.049108 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-arrow-bemicro-sdk/config.vhd | 1 | 6,490 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2011 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (10);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (0);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0b#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 1;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (2);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#50000#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (4);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0#;
constant CFG_GRGPIO_WIDTH : integer := (6);
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (2);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 1;
constant CFG_SPICTRL_TWEN : integer := 1;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 65c494c8f4b84fbc8241aad4c1bdd729 | 0.647612 | 3.666667 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-sp605/config.vhd | 1 | 7,546 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (3);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020605#;
constant CFG_ETH_ENL : integer := 16#000987#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- PCIEXP interface
constant CFG_PCIEXP : integer := 0;
constant CFG_PCIE_TYPE : integer := 0;
constant CFG_PCIE_SIM_MAS : integer := 0;
constant CFG_PCIEXPVID : integer := 16#0#;
constant CFG_PCIEXPDID : integer := 16#0#;
constant CFG_NO_OF_LANES : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 3beeed3e1ce1ff8e63148a51c3b538db | 0.653459 | 3.640135 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/inferred/ddrphy_datapath.vhd | 1 | 9,238 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy_datapath
-- File: ddrphy_datapath.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR/DDR2 PHY data path (digital part of phy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ddrphy_datapath is
generic (
regtech: integer := 0;
dbits: integer;
abits: integer;
bankbits: integer range 2 to 3 := 2;
ncs: integer;
nclk: integer;
-- Enable extra resync stage clocked by clkresync
resync: integer range 0 to 2 := 0
);
port (
clk0: in std_ulogic;
clk90: in std_ulogic;
clk180: in std_ulogic;
clk270: in std_ulogic;
clkresync: in std_ulogic;
ddr_clk: out std_logic_vector(nclk-1 downto 0);
ddr_clkb: out std_logic_vector(nclk-1 downto 0);
ddr_dq_in: in std_logic_vector(dbits-1 downto 0);
ddr_dq_out: out std_logic_vector(dbits-1 downto 0);
ddr_dq_oen: out std_logic_vector(dbits-1 downto 0);
ddr_dqs_in90: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_in90n: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_out: out std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_oen: out std_logic_vector(dbits/8-1 downto 0);
ddr_cke: out std_logic_vector(ncs-1 downto 0);
ddr_csb: out std_logic_vector(ncs-1 downto 0);
ddr_web: out std_ulogic;
ddr_rasb: out std_ulogic;
ddr_casb: out std_ulogic;
ddr_ad: out std_logic_vector(abits-1 downto 0);
ddr_ba: out std_logic_vector(bankbits-1 downto 0);
ddr_dm: out std_logic_vector(dbits/8-1 downto 0);
ddr_odt: out std_logic_vector(ncs-1 downto 0);
-- Control signals synchronous to clk0
dqin: out std_logic_vector(dbits*2-1 downto 0);
dqout: in std_logic_vector(dbits*2-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (bankbits-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0); -- Clk enable control signal to memory
odt : in std_logic_vector(ncs-1 downto 0);
dqs_en : in std_ulogic; -- Run dqs strobe (active low)
dqs_oen : in std_ulogic; -- DQS output enable (active low)
ddrclk_en : in std_logic_vector(nclk-1 downto 0) -- Enable/stop ddr_clk
);
end;
architecture rtl of ddrphy_datapath is
signal vcc,gnd: std_ulogic;
signal dqs_en_inv,dqs_en_inv180: std_ulogic;
signal dqcaptr,dqcaptf: std_logic_vector(dbits-1 downto 0);
signal dqsyncr,dqsyncf: std_logic_vector(dbits-1 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- DDR interface clock signal
-----------------------------------------------------------------------------
-- 90 degree shifted relative to master clock, gated by ddrclk_en
genclk: for x in 0 to nclk-1 generate
clkreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => ddrclk_en(x), d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clk(x));
clkbreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => gnd, d2 => ddrclk_en(x), ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clkb(x));
end generate;
-----------------------------------------------------------------------------
-- Control signals RAS,CAS,WE,BA,ADDR,CS,ODT,CKE
-----------------------------------------------------------------------------
rasreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => rasn, q => ddr_rasb);
casreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => casn, q => ddr_casb);
wereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => wen, q => ddr_web);
genba: for x in 0 to bankbits-1 generate
bareg: grdff generic map (tech => regtech)
port map (clk => clk0, d => ba(x), q => ddr_ba(x));
end generate;
gencs: for x in 0 to ncs-1 generate
csreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => csn(x), q => ddr_csb(x));
ckereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => cke(x), q => ddr_cke(x));
odtreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => odt(x), q => ddr_odt(x));
end generate;
genaddr: for x in 0 to abits-1 generate
addrreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => addr(x), q => ddr_ad(x));
end generate;
-----------------------------------------------------------------------------
-- Outgoing data, output enable, DQS, DQSOEN, DM
-----------------------------------------------------------------------------
gendqout: for x in 0 to dbits-1 generate
dqoutreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqout(x+dbits), d2 => dqout(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dq_out(x));
dqoenreg: grdff
generic map (tech => regtech)
port map (clk => clk0, d => oen, q => ddr_dq_oen(x));
end generate;
-- dqs_en -> invert -> delay -> +90-deg DDR-regs -> dqs_out
-- In total oen is delayed 5/4 cycles. We use 1/2 cycle delay
-- instead of 1 cycle delay to get better timing margin to DDR regs.
-- DQSOEN is delayed one cycle just like ctrl sigs
dqs_en_inv <= not dqs_en;
dqseninv180reg: grdff
generic map (tech => regtech)
port map (clk => clk180, d => dqs_en_inv, q => dqs_en_inv180);
gendqsout: for x in 0 to dbits/8-1 generate
dqsreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqs_en_inv180, d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_dqs_out(x));
dqsoenreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqs_oen, q => ddr_dqs_oen(x));
end generate;
gendm: for x in 0 to dbits/8-1 generate
dmreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dm(x+dbits/8), d2 => dm(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dm(x));
end generate;
-----------------------------------------------------------------------------
-- Incoming data
-----------------------------------------------------------------------------
gendqin: for x in 0 to dbits-1 generate
-- capture using dqs+90
-- Note: The ddr_ireg delivers both edges on c1 rising edge, therefore c1
-- is connected to inverted clock (c1 rising edge == dqs falling edge)
dqcaptreg: ddr_ireg generic map (tech => regtech)
port map (d => ddr_dq_in(x),
c1 => ddr_dqs_in90n(x/8), c2 => ddr_dqs_in90(x/8), ce => vcc, r => gnd, s => gnd,
q1 => dqcaptf(x), q2 => dqcaptr(x));
-- optional extra resync stage
ifresync: if resync=1 generate
genresync: for x in 0 to dbits-1 generate
dqsyncrreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptr(x), q => dqsyncr(x));
dqsyncfreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptf(x), q => dqsyncf(x));
end generate;
end generate;
noresync: if resync/=1 generate
dqsyncr <= dqcaptr;
dqsyncf <= dqcaptf;
end generate;
-- sample in clk0 domain
gensamp: if resync/=2 generate
dqinregr: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncr(x), q => dqin(x+dbits));
dqinregf: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncf(x), q => dqin(x));
end generate;
nosamp: if resync=2 generate
dqin(x+dbits) <= dqsyncr(x);
dqin(x) <= dqsyncf(x);
end generate;
end generate;
end;
| gpl-2.0 | 85c2b3340a56f63ace20caf7dc48a02e | 0.545573 | 3.627012 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/altera_mf/tap_altera_mf.vhd | 1 | 4,934 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_altera
-- File: tap_altera_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Altera TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altera_mf_components.all;
use altera_mf.sld_virtual_jtag;
-- pragma translate_on
entity altera_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of altera_tap is
signal ir0 : std_logic_vector(7 downto 0);
component sld_virtual_jtag
generic (
--lpm_hint : string := "UNUSED";
--lpm_type : string := "sld_virtual_jtag";
sld_auto_instance_index : string := "NO";
sld_instance_index : natural := 0;
sld_ir_width : natural := 1;
sld_sim_action : string := "UNUSED"
--sld_sim_n_scan : natural := 0;
--sld_sim_total_length : natural := 0
);
port(
ir_in : out std_logic_vector(sld_ir_width-1 downto 0);
ir_out : in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_cdr : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_uir : out std_logic;
tck : out std_logic;
tdi : out std_logic;
tdo : in std_logic;
tms : out std_logic;
virtual_state_cdr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_uir : out std_logic
);
end component;
begin
tapo_rst <= '0';
tapo_xsel1 <= '0'; tapo_xsel2 <= '0';
u0 : sld_virtual_jtag
generic map (sld_ir_width => 8,
sld_auto_instance_index => "NO",
sld_instance_index => 0)
port map (ir_in => tapo_inst,
ir_out => ir0,
jtag_state_cdr => open,
jtag_state_cir => open,
jtag_state_e1dr => open,
jtag_state_e1ir => open,
jtag_state_e2dr => open,
jtag_state_e2ir => open,
jtag_state_pdr => open,
jtag_state_pir => open,
jtag_state_rti => open,
jtag_state_sdr => open,
jtag_state_sdrs => open,
jtag_state_sir => open,
jtag_state_sirs => open,
jtag_state_tlr => open,
jtag_state_udr => open,
jtag_state_uir => open,
tck => tapo_tck,
tdi => tapo_tdi,
tdo => tapi_tdo1,
tms => open,
virtual_state_cdr => tapo_capt,
virtual_state_cir => open,
virtual_state_e1dr => open,
virtual_state_e2dr => open,
virtual_state_pdr => open,
virtual_state_sdr => tapo_shft,
virtual_state_udr => tapo_upd,
virtual_state_uir => open);
end;
| gpl-2.0 | 794a015ae104c0798ac6b4a42818fb49 | 0.55756 | 3.31586 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/pci/grpci1/dmactrl.vhd | 1 | 19,010 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dmactrl
-- File: dmactrl.vhd
-- Author: Alf Vaerneus - Gaisler Research
-- Modified: Nils-Johan Wessman - Gaisler Research
-- Description: Simple DMA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
entity dmactrl is
generic (
hindex : integer := 0;
slvindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
blength : integer := 4
);
port (
rst : in std_logic;
clk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi0 : in ahb_slv_in_type;
ahbso0 : out ahb_slv_out_type;
ahbsi1 : out ahb_slv_in_type;
ahbso1 : in ahb_slv_out_type
);
end;
architecture rtl of dmactrl is
constant BURST_LENGTH : integer := blength;
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DMACTRL, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type state_type is(idle, read1, read2, read3, read4, read5, write1, write2, writeb, write3, write4, turn);
type rbuf_type is array (0 to 2) of std_logic_vector(31 downto 0);
type dmactrl_reg_type is record
state : state_type;
addr0 : std_logic_vector(31 downto 2);
addr1 : std_logic_vector(31 downto 2);
hmbsel : std_logic_vector(0 to NAHBAMR-1);
htrans : std_logic_vector(1 downto 0);
rbuf : rbuf_type;
write : std_logic;
start_req : std_logic;
start : std_logic;
ready : std_logic;
err : std_logic;
first0 : std_logic;
first1 : std_logic;
no_ws : std_logic; -- no wait states
blimit : std_logic; -- 1k limit
dmao_start: std_logic;
dmao_ready: std_logic; -- sets if ready responce in read4, not set two_in_buf if retry on second access in buf
two_in_buf: std_logic; -- two words in rbuf to be stored
burstl_p : std_logic_vector(BURST_LENGTH - 1 downto 0); -- pci access counter
burstl_a : std_logic_vector(BURST_LENGTH - 1 downto 0); -- amba access counter
ahb0_htrans : std_logic_vector(1 downto 0);
ahb0_hresp : std_logic_vector(1 downto 0);
ahb0_hready : std_logic;
ahb0_retry : std_logic;
ahb0_hsel : std_logic;
start_del : std_logic;
end record;
signal r,rin : dmactrl_reg_type;
signal dmai : pci_ahb_dma_in_type;
signal dmao : pci_ahb_dma_out_type;
begin
comb : process(rst,r,dmao,apbi,ahbsi0,ahbso1)
variable v : dmactrl_reg_type;
variable vdmai : pci_ahb_dma_in_type;
variable pdata : std_logic_vector(31 downto 0);
variable slvbusy : ahb_slv_out_type;
variable dma_done, pci_done : std_logic;
variable bufloc : integer range 0 to 2;
begin
slvbusy := ahbso1; v := r;
vdmai.burst := '1'; vdmai.address := r.addr0 & "00";
vdmai.write := not r.write; vdmai.start := '0'; vdmai.size := "10";
vdmai.wdata := r.rbuf(0); pdata := (others => '0');
vdmai.busy := '0'; vdmai.irq := '0';
bufloc := 0;
v.start_del := r.start;
--slvbusy.hready := '1'; slvbusy.hindex := hindex; --slvbusy.hresp := "00";
--v.ahb0_htrans := ahbsi0.htrans; v.ahb0_retry := '0';
--v.ahb0_hsel := ahbsi0.hsel(slvindex); v.ahb0_hready := ahbsi0.hready;
v.ahb0_hready := '1'; v.ahb0_hresp := HRESP_OKAY; v.ahb0_retry := '0';
slvbusy.hready := r.ahb0_hready; slvbusy.hresp := r.ahb0_hresp;
-- AMBA busy response when dma is running
--if r.ahb0_retry = '1' then slvbusy.hresp := "10";
--else slvbusy.hresp := "00"; end if;
if r.ahb0_retry = '1' then v.ahb0_hresp := HRESP_RETRY; end if;
--if r.ahb0_htrans = "10" and (r.start = '1') and r.ahb0_hsel = '1' and r.ahb0_hready = '1' then
-- slvbusy.hready := '0';
-- slvbusy.hresp := "10";
-- v.ahb0_retry := '1';
--end if;
if ahbsi0.htrans = "10" and (r.start = '1') and ahbsi0.hsel(slvindex) = '1' and ahbsi0.hready = '1' then
v.ahb0_hready := '0';
v.ahb0_hresp := HRESP_RETRY;
v.ahb0_retry := '1';
end if;
-- Done signals
if (r.burstl_a(BURST_LENGTH - 1 downto 1) = zero32(BURST_LENGTH - 1 downto 1)) then -- AMBA access done
dma_done := '1'; else dma_done := '0'; end if;
if (r.burstl_p(BURST_LENGTH - 1 downto 1) = zero32(BURST_LENGTH - 1 downto 1)) then -- PCI access done
pci_done := '1'; else pci_done := '0'; end if;
-- APB interface
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if apbi.pwrite = '1' then
v.start_req := apbi.pwdata(0);
v.write := apbi.pwdata(1);
v.ready := r.ready and not apbi.pwdata(2);
v.err := r.err and not apbi.pwdata(3);
v.hmbsel := apbi.pwdata(7 downto 4);
end if;
pdata := zero32(31 downto 8) & r.hmbsel & r.err & r.ready & r.write & r.start_req;
when "001" =>
if apbi.pwrite = '1' then v.addr0 := apbi.pwdata(31 downto 2); end if;
pdata := r.addr0 & "00";
when "010" =>
if apbi.pwrite = '1' then v.addr1 := apbi.pwdata(31 downto 2); end if;
pdata := r.addr1 & "00";
when "011" =>
if apbi.pwrite = '1' then
v.burstl_p := apbi.pwdata(BURST_LENGTH - 1 downto 0);
v.burstl_a := apbi.pwdata(BURST_LENGTH - 1 downto 0);
end if;
pdata := zero32(31 downto BURST_LENGTH) & r.burstl_p;
when others =>
end case;
end if;
-- can't start dma until AMBA slave is idle
if r.start_req = '1' and (ahbsi0.hready = '1' and (ahbsi0.htrans = "00" or ahbsi0.hsel(slvindex) = '0')) then
v.start := '1';
end if;
case r.state is
when idle =>
v.htrans := "00";
v.first0 := '1'; v.first1 := '1';
v.no_ws := '0'; v.dmao_start := '0'; v.blimit := '0';
if r.start = '1' then
if r.write = '0' then v.state := read1;
else v.state := write1; end if;
end if;
when read1 => -- Start PCI read
bufloc := 0;
v.htrans := "10";
if ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY then
if r.htrans(1) = '1' then
if pci_done = '1' then
v.htrans := "00";
v.state := read5;
else
v.htrans := "11";
v.state := read2;
end if;
end if;
elsif ahbso1.hready = '0' then
v.htrans := "11";
else
v.htrans := "00";
end if;
when read2 => -- fill rbuf (3 words)
if r.first1 = '1' then bufloc := 1; -- store 3 words
else bufloc := 2; end if;
if ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY then
--if r.htrans = "11" then
if r.htrans(1) = '1' then
v.first1 := '0';
if pci_done = '1' then
v.htrans := "00";
v.state := read5;
elsif r.first1 = '0' then
v.htrans := "01";
v.state := read3;
v.first0 := '1';
end if;
end if;
elsif ahbso1.hready = '0' and ahbso1.hresp = HRESP_RETRY then
v.htrans := "00";
else
if ahbso1.hresp = HRESP_RETRY then
v.htrans := "10";
else
v.htrans := "11";
end if;
end if;
when read3 => -- write to AMBA and read from PCI
vdmai.start := '1';
bufloc := 1;
if (dmao.ready and dmao.start) = '1' then bufloc := 1; v.no_ws := '1'; -- no wait state on AMBA ?
else
bufloc := 2;
if dmao.active = '1' then v.no_ws := '0'; end if;
end if;
if dmao.active = '0' then v.blimit := '1';
else v.blimit := '0'; end if;
if dmao.ready = '1' then
v.first0 := '0';
v.htrans := "11";
else
v.htrans := "01";
end if;
if r.htrans(1) = '1' and ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY and pci_done = '1' then
v.state := read5;
v.htrans := "00";
elsif r.htrans(1) = '1' and ahbso1.hready = '0' and ahbso1.hresp = HRESP_RETRY then
if dmao.active = '0' then v.two_in_buf := '1'; end if; -- two words in rbuf to store
v.state := read4;
v.htrans := "01";
if bufloc = 2 then v.dmao_ready := '0'; end if;
end if;
when read4 => -- PCI retry
bufloc := 1;
--if dmao.ready = '1' then v.two_in_buf := '0'; end if;
if dmao.ready = '1' then v.two_in_buf := '0'; v.dmao_ready := '1'; end if;
if dmao.retry = '1' and r.dmao_ready = '0' then v.two_in_buf := '1'; end if; -- two words in rbuf if retry/split
if dmao.retry = '1' then v.dmao_start := '0'; end if; -- retry last word
if dmao.start = '1' and r.two_in_buf = '0' then v.dmao_start := '1'; end if;
if r.no_ws = '1' and r.dmao_start = '1' then vdmai.start := '0';
elsif dmao.start = '1' and r.two_in_buf = '0' then v.no_ws := '1'; vdmai.start := '0';
else vdmai.start := '1'; end if;
--if dmao.ready = '1' and r.no_ws = '1' and r.two_in_buf = '0' then -- handle change of waitstates (sdram refresh)
if (dmao.ready = '1' or (dmao.active = '0' and r.dmao_start = '1')) and r.no_ws = '1' and r.two_in_buf = '0' then
v.first0 := '1';
v.first1 := '1';
v.no_ws := '0';
v.dmao_start := '0';
v.state := read1;
end if;
when read5 => -- PCI read done
if dmao.start = '1' then v.first0 := '0'; -- first amba access
elsif dmao.active = '0' then v.first0 := '1'; end if; -- 1k limit
if dma_done = '0' or (r.first0 = '1' and dmao.start = '0') then vdmai.start := '1'; end if;
if (dmao.ready and dmao.start) = '1' then bufloc := 1; v.no_ws := '1'; -- no wait state on AMBA ?
else bufloc := 2; end if;
if dmao.ready = '1' and dma_done = '1' then
v.state := turn;
end if;
when write1 => -- Read first from AMBA
bufloc := 0;
v.first1 := '1'; v.no_ws := '0';
if dmao.start = '1' then v.first0 := '0'; -- first amba access
elsif dmao.active = '0' then v.first0 := '1'; end if; -- 1k limit
if dma_done = '1' and (r.first0 = '0' or dmao.start = '1') then vdmai.start := '0';
else vdmai.start := '1'; end if;
if dmao.ready = '1' then
if dma_done = '1' then v.state := write4;
else v.state := write2; end if;
v.htrans := "10"; -- start access to PCI
end if;
when write2 => -- Read from AMBA and write to PCI
bufloc := 0;
if (dmao.ready and dmao.start) = '1' then v.no_ws := '1'; end if; -- no wait state on AMBA ?
if dmao.start = '1' then v.first0 := '0'; -- first amba access
elsif dmao.active = '0' then v.first0 := '1'; end if; -- 1k limit
if dmao.ready = '1' then -- Data ready write to PCI
v.htrans := "11";
if dma_done = '1' then
v.state := write4;
end if;
else v.htrans := "01"; end if;
if ahbso1.hready = '0' then
vdmai.start := '0';
if v.no_ws = '1' then bufloc := 1; end if;
if dmao.active = '0' then v.state := writeb; -- AMBA 1k limit
else v.state := write3; v.dmao_ready := '1'; end if; -- assume ready responce, change later of retry/split
elsif dma_done = '0' or (r.first0 = '1' and dmao.start = '0') then
vdmai.start := '1';
end if;
when writeb => -- AMBA 1k limit and PCI retry
bufloc := 1;
if dmao.active = '1' then vdmai.start := '0';
else vdmai.start := '1'; end if;
if dmao.ready = '1' then v.state := write3; v.dmao_ready := '1'; end if;
when write3 => -- Retry from PCI
bufloc := 1;
--if ahbso1.hready = '1' then v.htrans := "10"; -- wait for AMBA access to be done before retry
--if (ahbso1.hready and (dmao.ready or not dmao.active)) = '1' then v.htrans := "10";
if (ahbso1.hready and (dmao.ready or (not dmao.active and r.dmao_ready))) = '1' then v.htrans := "10"; -- handle retry (don't start until ready)
else v.htrans := "01"; end if;
-- handle retry/split (restart access)
if dmao.retry = '1' then v.dmao_ready := '0';
elsif dmao.ready = '1' then v.dmao_ready := '1'; end if;
if r.dmao_ready = '0' and dmao.active = '0' then vdmai.start := '1';
else vdmai.start := '0'; end if;
if r.htrans(1) = '1' and ahbso1.hready = '1' and ahbso1.hresp = HRESP_OKAY then
if pci_done = '1' then
v.htrans := "00";
v.state := turn;
elsif dma_done = '1' and r.burstl_a(0) = '0' then
v.htrans := "01";
v.state := write4;
else
v.htrans := "11";
v.first0 := '1';
v.state := write2;
end if;
end if;
when write4 => -- Done read AMBA
v.htrans := "11";
if pci_done = '1' and ahbso1.hready = '1' and r.htrans(1) = '1' then
v.htrans := "00";
v.state := turn;
elsif ahbso1.hready = '0' then
v.state := write3;
v.htrans := "01";
v.dmao_ready := '1';
end if;
when turn =>
v.htrans := "00";
-- can't switch off dma until AMBA slave is idle
if (ahbsi0.hsel(slvindex) = '0' and r.ahb0_retry = '0' and ahbsi0.hready = '1')
or (ahbsi0.htrans = "00" and ahbsi0.hready = '1') or r.ahb0_retry = '1' then
v.ready := '1'; v.first1 := '1'; v.start_req := '0';
v.start := '0'; v.state := idle;
end if;
end case;
if ((r.htrans(1) and ahbso1.hready) = '1' and ahbso1.hresp = HRESP_OKAY) then -- PCI access done
v.burstl_p := r.burstl_p - '1'; -- dec counter
v.addr1 := r.addr1 + '1'; -- inc address (PCI)
if (r.write = '0' or r.state = write4 or r.state = write3) then
if r.state /= read1 and r.state /= read2 and (v.no_ws = '1' or r.state = write3) and v.blimit = '0' then
v.rbuf(0) := r.rbuf(1); -- dont update if wait states
v.rbuf(1) := r.rbuf(2); --
end if;
if r.write = '0' then v.rbuf(bufloc) := ahbreadword(ahbso1.hrdata); end if; -- PCI to AMBA
end if; -- if wait states store in buf(2) else
end if; -- in buf(1). Frist word in buf(0)
if dmao.ready = '1' then -- AMBA access done
v.burstl_a := r.burstl_a - '1'; -- dec counter
v.addr0 := r.addr0 + 1; -- inc address (AMBA master)
if r.write = '1' then
if r.state /= write3 and bufloc = 0 then -- dont update if retry from PCI
v.rbuf(0) := r.rbuf(1);
v.rbuf(1) := r.rbuf(2);
end if;
v.rbuf(bufloc) := dmao.rdata; -- AMBA to PCI
elsif r.write = '0' and (r.first0 = '1' or v.state = read4 or r.state = read5 or (v.no_ws = '0' or r.blimit = '1')) then
v.rbuf(0) := r.rbuf(1); -- update when data is written if wait states or PCI retry or PCI done
v.rbuf(1) := r.rbuf(2);
end if;
end if;
--if (ahbso1.hresp = HRESP_ERROR or (dmao.mexc or dmao.retry) = '1') then
if (ahbso1.hresp = HRESP_ERROR or dmao.mexc = '1') then
v.err := '1'; v.state := turn; v.htrans := HTRANS_IDLE;
end if;
--cancel dma
if r.start = '1' and r.start_req = '0' then
v.state := turn;
end if;
if rst = '0' then
v.state := idle;
v.start := '0';
v.start_req := '0';
v.write := '0';
v.err := '0';
v.ready := '0';
v.first1 := '1';
v.two_in_buf := '0';
v.hmbsel := (others => '0');
v.addr1 := (others => '0');
end if;
if r.start = '1' then
ahbsi1.hsel <= (others => '1');
ahbsi1.hmbsel(0 to 3) <= r.hmbsel;
ahbsi1.hsize <= "010";
ahbsi1.hwrite <= r.write;
ahbsi1.htrans <= v.htrans;
-- ahbsi1.haddr <= r.addr1 & "00";
ahbsi1.haddr <= v.addr1 & "00";
ahbsi1.hburst <= "001";
ahbsi1.hwdata <= ahbdrivedata(r.rbuf(0));
ahbsi1.hready <= ahbso1.hready;
ahbsi1.hmaster <= conv_std_logic_vector(hindex,4);
ahbso0 <= slvbusy;
else
ahbsi1.hsel <= ahbsi0.hsel;
ahbsi1.hmbsel(0 to 3) <= ahbsi0.hmbsel(0 to 3);
ahbsi1.hsize <= ahbsi0.hsize;
ahbsi1.hwrite <= ahbsi0.hwrite;
ahbsi1.htrans <= ahbsi0.htrans;
ahbsi1.haddr <= ahbsi0.haddr;
ahbsi1.hburst <= ahbsi0.hburst;
ahbsi1.hwdata <= ahbsi0.hwdata;
ahbsi1.hready <= ahbsi0.hready;
ahbsi1.hmaster <= ahbsi0.hmaster;
ahbso0 <= ahbso1;
if r.ahb0_hresp = HRESP_RETRY then
ahbso0.hready <= r.ahb0_hready; ahbso0.hresp <= r.ahb0_hresp;
end if;
v.state := idle;
end if;
dmai <= vdmai;
rin <= v;
apbo.pconfig <= pconfig;
apbo.prdata <= pdata;
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= v.ready and not r.ready;
apbo.pindex <= pindex;
ahbsi1.hirq <= (others => '0');
ahbsi1.hprot <= (others => '0');
ahbsi1.hmastlock <= '0';
ahbsi1.testen <= '0';
ahbsi1.testrst <= '0';
ahbsi1.scanen <= '0';
ahbsi1.testoen <= '0';
ahbsi1.testin <= ahbsi0.testin;
end process;
cpur : process (clk)
begin
if rising_edge (clk) then
r <= rin;
end if;
end process;
ahbmst0 : pciahbmst generic map (hindex => hindex, devid => GAISLER_DMACTRL, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("dmactrl" & tost(pindex) &
": 32-bit DMA controller & AHB/AHB bridge rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 | 3220a66a54d4953c3c2bfcdb688fa611 | 0.536086 | 3.190133 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-avnet-eval-xc4vlx60/testbench.vhd | 1 | 9,246 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '1'; -- Reset
signal rstn: std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal clk50 : std_ulogic := '1';
signal clk_200p : std_ulogic := '0';
signal clk_200n : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd1, rxd1 : std_logic;
signal eth_macclk, etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal erxdt, etxdt : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
clk50 <= not clk50 after 10 ns;
clk_200p <= not clk_200p after 2.5 ns;
clk_200n <= not clk_200n after 2.5 ns;
rst <= '1', '0' after 1000 ns;
rstn <= not rst;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
resetn => rst,
resoutn => resoutn,
clk_100mhz => clk,
clk_50mhz => clk50,
clk_200p => clk_200p,
clk_200n => clk_200n,
errorn => error,
address => address(22 downto 1),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
sertx => dsutx,
serrx => dsurx,
rtsn => rtsn,
ctsn => ctsn,
dsuen => dsuen,
dsubre => dsubre,
dsuact => dsuactn,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
ddr0: ddrram
generic map (width => 16, abits => 13, colbits => 9, rowbits => 12, implbanks => 1,
fname => sdramfile, lddelay => (300 us)*CFG_MIG_DDR2)
port map (
ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 3)
port map(resoutn, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, eth_macclk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rstn, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 | 87badcc210f3280e3a1fcf75ea45c903 | 0.541856 | 3.41055 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/uart/ahbuart.vhd | 1 | 2,654 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbuart
-- File: ahbuart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UART with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
use gaisler.uart.all;
use gaisler.libdcom.all;
entity ahbuart is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
uarti : in uart_in_type;
uarto : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type );
end;
architecture struct of ahbuart is
constant REVISION : integer := 0;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal duarti : dcom_uart_in_type;
signal duarto : dcom_uart_out_type;
begin
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER, devid => GAISLER_AHBUART)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
dcom_uart0 : dcom_uart generic map (pindex, paddr, pmask)
port map (rst, clk, uarti, uarto, apbi, apbo, duarti, duarto);
dcom0 : dcom port map (rst, clk, dmai, dmao, duarti, duarto, ahbi);
-- pragma translate_off
bootmsg : report_version
generic map ("ahbuart" & tost(pindex) &
": AHB Debug UART rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 | 72a53903531d3723b9e387ba82dd837b | 0.613791 | 3.796853 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-digilent-xc3s1000/vga_clkgen.vhd | 1 | 1,999 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity vga_clkgen is
port (
resetn : in std_logic;
sel : in std_logic_vector(1 downto 0);
clk25 : in std_logic;
clk50 : in std_logic;
clkout : out std_logic
);
end;
architecture struct of vga_clkgen is
component BUFG port ( O : out std_logic; I : in std_logic); end component;
signal clk65, clksel : std_logic;
begin
-- 65 MHz clock generator
clkgen65 : clkmul_virtex2 generic map (13, 5) port map (resetn, clk25, clk65);
clk_select : process (clk25, clk50, clk65, sel)
begin
case sel is
when "00" => clksel <= clk25;
when "01" => clksel <= clk50;
when "10" => clksel <= clk65;
when others => clksel <= '0';
end case;
end process;
bufg1 : BUFG port map (I => clksel, O => clkout);
end;
| gpl-2.0 | 43b05e39cf44578502a3a9b98de2bd19 | 0.630815 | 3.829502 | false | false | false | false |
vtfr/somador-4bits-com-acumulador | src/vhdl/somador_4bits_acc.vhdl | 1 | 2,512 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Somador de 4 bits
entity somador_4bits_acc is
port (
a : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
sel0 : in std_logic;
sel1 : in std_logic;
cout : out std_logic;
vdd : in std_logic;
vss : in std_logic;
clk : in std_logic
);
end somador_4bits_acc;
-- Implementacao do Somador de 4 bits usando quatro somadores
-- de 1 bit
architecture structural of somador_4bits_acc is
-- Define o componente do somador de 4 bits
component somador_4bits
port (
a, b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
cin : in std_logic;
cout : out std_logic;
vdd : in std_logic;
vss : in std_logic
);
end component;
-- Define o componente do mux de 4 bits
component mux_4bits
port (
ctrl : in std_logic;
a, b : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
vdd : in std_logic;
vss : in std_logic
);
end component;
-- Define o componente do inversor de 4 bits
component inv_4bits
port (
a : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
vdd : in std_logic;
vss : in std_logic
);
end component;
-- Define o componente do inversor de 4 bits
component acc_4bits
port (
a : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
clk : in std_logic;
vdd : in std_logic;
vss : in std_logic
);
end component;
signal inv_a : std_logic_vector(3 downto 0);
signal mux0_value : std_logic_vector(3 downto 0);
signal mux1_value : std_logic_vector(3 downto 0);
signal acc_value : std_logic_vector(3 downto 0);
signal somador_value : std_logic_vector(3 downto 0);
begin
-- Começa invertendo o A, dependendo do valor de sel0
inv0: inv_4bits port map (
a => a,
s => inv_a,
vdd => vdd,
vss => vss);
-- Liga ao mux0
mux0: mux_4bits port map (
a => a,
b => inv_a,
ctrl => sel0,
s => mux0_value,
vdd => vdd,
vss => vss);
-- Liga ao somador
somador: somador_4bits port map (
a => mux0_value,
b => acc_value,
cin => sel0,
cout => cout,
s => somador_value,
vdd => vdd,
vss => vss);
mux1: mux_4bits port map (
a => mux0_value,
b => somador_value,
ctrl => sel1,
s => mux1_value,
vdd => vdd,
vss => vss);
acc: acc_4bits port map (
a => mux1_value,
clk => clk,
s => acc_value,
vdd => vdd,
vss => vss);
s <= mux1_value;
end structural;
| gpl-3.0 | bb2483b8b50b5e9d1afbddf0d1c7e1bc | 0.610514 | 2.618352 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/cycloneiii/cycloneiii_clkgen.vhd | 1 | 7,921 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of cyclone3_pll is
component altpll
generic (
intended_device_family : string := "CycloneIII" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "clock0";
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
port_clkena0 : string := "PORT_CONNECTIVITY";
port_clkena1 : string := "PORT_CONNECTIVITY";
port_clkena2 : string := "PORT_CONNECTIVITY";
port_clkena3 : string := "PORT_CONNECTIVITY";
port_clkena4 : string := "PORT_CONNECTIVITY";
port_clkena5 : string := "PORT_CONNECTIVITY"
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (4 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 3) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1' when sdramen = 1 else '0';
clkena(2) <= '1' when clk2xen = 1 else '0';
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(2); e0 <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
width_clock => 5, compensate_clock => "CLK1",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
-- Must use operation_mode other than "ZERO_DELAY_BUFFER" due to
-- tool issues with ZERO_DELAY_BUFFER and non-existent output clock
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 5,
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_cycloneiii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
tech : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_cycloneiii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
component cyclone3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : cyclone3_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_cycloneiii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_cycloneiii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-2.0 | 49343bb6b24b38b4ecc1e8a46578b19c | 0.586921 | 3.51888 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/ahb2mig_series7_pkg.vhd | 1 | 28,030 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ah2mig_series7_pkg
-- File: ah2mig_series7_pkg.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: Components, types and functions for AHB2MIG Series 7 controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library gaisler;
use gaisler.all;
package ahb2mig_series7_pkg is
-------------------------------------------------------------------------------
-- AHB2MIG configuration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AHB2MIG interface type declarations and constant
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AHB2MIG Subprograms
-------------------------------------------------------------------------------
function nbrmaxmigcmds (
datawidth : integer)
return integer;
function nbrmigcmds (
hwrite : std_logic;
hsize : std_logic_vector;
htrans : std_logic_vector;
step : unsigned;
datawidth : integer)
return integer;
function reversebyte (
data : std_logic_vector)
return std_logic_vector;
function reversebytemig (
data : std_logic_vector)
return std_logic_vector;
function ahbselectdatanoreplicastep (
haddr : std_logic_vector(7 downto 2);
hsize : std_logic_vector(2 downto 0)
)
return unsigned;
function ahbselectdatanoreplicaoutput (
haddr : std_logic_vector(7 downto 0);
counter : unsigned(31 downto 0);
hsize : std_logic_vector(2 downto 0);
rdbuffer : unsigned;
wr_count : unsigned;
replica : boolean)
return std_logic_vector;
function ahbselectdatanoreplicamask (
haddr : std_logic_vector(6 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbselectdatanoreplica (hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 0); hsize : std_logic_vector(2 downto 0))
return std_logic_vector;
function ahbdrivedatanoreplica (hdata : std_logic_vector) return std_logic_vector;
-------------------------------------------------------------------------------
-- AHB2MIG Components
-------------------------------------------------------------------------------
end;
package body ahb2mig_series7_pkg is
-- Number of Max MIG commands
function nbrmaxmigcmds(
datawidth : integer)
return integer is
variable ret : integer;
begin
case datawidth is
when 128 =>
ret:= 4;
when 64 =>
ret := 2;
when others =>
ret := 2;
end case;
return ret;
end function nbrmaxmigcmds;
-- Number of MIG commands
function nbrmigcmds(
hwrite : std_logic;
hsize : std_logic_vector;
htrans : std_logic_vector;
step : unsigned;
datawidth : integer)
return integer is
variable ret : integer;
begin
if (hwrite = '0') then
case datawidth is
when 128 =>
if (hsize = HSIZE_4WORD) then
ret:= 4;
elsif (hsize = HSIZE_DWORD) then
ret := 2;
elsif (hsize = HSIZE_WORD) then
ret := 1;
else
ret := 1;
end if;
when 64 =>
if (hsize = HSIZE_DWORD) then
ret := 2;
elsif (hsize = HSIZE_WORD) then
ret := 2;
else
ret := 1;
end if;
-- 32
when others =>
if (hsize = HSIZE_WORD) then
ret := 2;
else
ret := 1;
end if;
end case;
if (htrans /= HTRANS_SEQ) then
ret := 1;
end if;
else
ret := to_integer(shift_right(step,4)) + 1;
end if;
return ret;
end function nbrmigcmds;
-- Reverses byte order.
function reversebyte(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/8-1) loop
rdata(i*8+8-1 downto i*8) := data(data'length-i*8-1 downto data'length-i*8-8);
end loop;
return rdata;
end function reversebyte;
-- Reverses byte order.
function reversebytemig(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/8-1) loop
rdata(i*8+8-1 downto i*8) := data(data'left-i*8 downto data'left-i*8-7);
end loop;
return rdata;
end function reversebytemig;
-- Takes in AHB data vector 'hdata' and returns valid data on the full
-- data vector output based on 'haddr' and 'hsize' inputs together with
-- GRLIB AHB bus width. The function works down to word granularity.
function ahbselectdatanoreplica (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbselectdatanoreplica
ret := (others => '0');
case hsize is
when HSIZE_4WORD =>
ret(AHBDW-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto 0));
when HSIZE_DWORD =>
if AHBDW = 128 then
case haddr(3) is
when '0' => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto AHBDW/2));
when others => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW/2-1 downto 0));
end case;
elsif AHBDW = 64 then
ret(AHBDW-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto 0));
end if;
when HSIZE_WORD =>
if AHBDW = 128 then
case haddr(3 downto 2) is
when "00" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 64 then
case haddr(2) is
when '0' => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto AHBDW/2));
when others => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW/2-1 downto 0));
end case;
elsif AHBDW = 32 then
ret(AHBDW-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto 0));
end if;
when HSIZE_HWORD =>
if AHBDW = 128 then
case haddr(3 downto 1) is
when "000" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := reversebytemig(hdata(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := reversebytemig(hdata(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
elsif AHBDW = 64 then
case haddr(2 downto 1) is
when "00" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)) := reversebytemig(hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := reversebytemig(hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)) := reversebytemig(hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 32 then
case haddr(1) is
when '0' => ret(AHBDW/2-1 downto 0) := reversebytemig(hdata(AHBDW-1 downto AHBDW/2));
when others => ret(AHBDW-1 downto AHBDW/2) := reversebytemig(hdata(AHBDW/2-1 downto 0));
end case;
end if;
-- HSIZE_BYTE
when others =>
if AHBDW = 128 then
case haddr(3 downto 0) is
when "0000" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata(16*(AHBDW/16)-1 downto 15*(AHBDW/16));
when "0001" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata(15*(AHBDW/16)-1 downto 14*(AHBDW/16));
when "0010" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata(14*(AHBDW/16)-1 downto 13*(AHBDW/16));
when "0011" => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata(13*(AHBDW/16)-1 downto 12*(AHBDW/16));
when "0100" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata(12*(AHBDW/16)-1 downto 11*(AHBDW/16));
when "0101" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata(11*(AHBDW/16)-1 downto 10*(AHBDW/16));
when "0110" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata(10*(AHBDW/16)-1 downto 9*(AHBDW/16));
when "0111" => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata( 9*(AHBDW/16)-1 downto 8*(AHBDW/16));
when "1000" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata( 8*(AHBDW/16)-1 downto 7*(AHBDW/16));
when "1001" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata( 7*(AHBDW/16)-1 downto 6*(AHBDW/16));
when "1010" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata( 6*(AHBDW/16)-1 downto 5*(AHBDW/16));
when "1011" => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata( 5*(AHBDW/16)-1 downto 4*(AHBDW/16));
when "1100" => ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)) := hdata( 4*(AHBDW/16)-1 downto 3*(AHBDW/16));
when "1101" => ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)) := hdata( 3*(AHBDW/16)-1 downto 2*(AHBDW/16));
when "1110" => ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)) := hdata( 2*(AHBDW/16)-1 downto 1*(AHBDW/16));
when others => ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)) := hdata( 1*(AHBDW/16)-1 downto 0*(AHBDW/16));
end case;
elsif AHBDW = 64 then
case haddr(2 downto 0) is
when "000" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := hdata(8*(AHBDW/8)-1 downto 7*(AHBDW/8));
when "001" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := hdata(7*(AHBDW/8)-1 downto 6*(AHBDW/8));
when "010" => ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)) := hdata(6*(AHBDW/8)-1 downto 5*(AHBDW/8));
when "011" => ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)) := hdata(5*(AHBDW/8)-1 downto 4*(AHBDW/8));
when "100" => ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)) := hdata(4*(AHBDW/8)-1 downto 3*(AHBDW/8));
when "101" => ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)) := hdata(3*(AHBDW/8)-1 downto 2*(AHBDW/8));
when "110" => ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)) := hdata(2*(AHBDW/8)-1 downto 1*(AHBDW/8));
when others => ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)) := hdata(1*(AHBDW/8)-1 downto 0*(AHBDW/8));
end case;
elsif AHBDW = 32 then
case haddr(1 downto 0) is
when "00" => ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)) := hdata(4*(AHBDW/4)-1 downto 3*(AHBDW/4));
when "01" => ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)) := hdata(3*(AHBDW/4)-1 downto 2*(AHBDW/4));
when "10" => ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)) := hdata(2*(AHBDW/4)-1 downto 1*(AHBDW/4));
when others => ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)) := hdata(1*(AHBDW/4)-1 downto 0*(AHBDW/4));
end case;
end if;
end case;
return ret;
end ahbselectdatanoreplica;
function ahbselectdatanoreplicastep (
haddr : std_logic_vector(7 downto 2);
hsize : std_logic_vector(2 downto 0))
return unsigned is
variable ret : unsigned(31 downto 0);
begin -- ahbselectdatanoreplicastep
ret := (others => '0');
case AHBDW is
when 128 =>
if (hsize = HSIZE_4WORD) then
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
elsif (hsize = HSIZE_DWORD) then
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
else
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
end if;
when 64 =>
if (hsize = HSIZE_DWORD) then
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
else
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
end if;
-- 32
when others =>
ret := resize(unsigned(haddr(5 downto 2)),ret'length);
end case;
return ret;
end ahbselectdatanoreplicastep;
function ahbselectdatanoreplicamask (
haddr : std_logic_vector(6 downto 0);
hsize : std_logic_vector(2 downto 0))
return std_logic_vector is
variable ret : std_logic_vector(AHBDW/4-1 downto 0);
variable ret128 : std_logic_vector(128/4-1 downto 0);
begin -- ahbselectdatanoreplicamask
ret := (others => '0');
ret128 := (others => '0');
case hsize is
when HSIZE_4WORD =>
ret(AHBDW/8-1 downto 0) := (others => '1');
when HSIZE_DWORD =>
if AHBDW = 128 then
case haddr(3) is
when '0' => ret(AHBDW/8/2-1 downto 0) := (others => '1');
when others => ret(AHBDW/8/2-1 downto 0) := (others => '1');
end case;
else
ret(AHBDW/8-1 downto 0) := (others => '1');
end if;
when HSIZE_WORD =>
if AHBDW = 128 then
case haddr(3 downto 2) is
when "00" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when "01" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when "10" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when others => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
end case;
elsif AHBDW = 64 then
case haddr(2) is
when '0' => ret(AHBDW/8/2-1 downto 0) := (others => '1');
when others => ret(AHBDW/8/2-1 downto 0) := (others => '1');
end case;
elsif AHBDW = 32 then
ret(AHBDW/8-1 downto 0) := (others => '1');
end if;
when HSIZE_HWORD =>
if AHBDW = 128 then
case haddr(3 downto 1) is
when "000" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when "001" => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
when "010" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when "011" => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
when "100" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when "101" => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
when "110" => ret128(1*(128/8/8)-1 downto 0*(128/8/8)) := (others => '1');
when others => ret128(2*(128/8/8)-1 downto 1*(128/8/8)) := (others => '1');
end case;
ret := std_logic_vector(resize(unsigned(ret128),ret'length));
elsif AHBDW = 64 then
case haddr(2 downto 1) is
when "00" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when "01" => ret(2*(AHBDW/8/4)-1 downto 1*(AHBDW/8/4)) := (others => '1');
when "10" => ret(1*(AHBDW/8/4)-1 downto 0*(AHBDW/8/4)) := (others => '1');
when others => ret(2*(AHBDW/8/4)-1 downto 1*(AHBDW/8/4)) := (others => '1');
end case;
elsif AHBDW = 32 then
case haddr(1) is
when '0' => ret(AHBDW/8/2-1 downto 0) := (others => '1');
when others => ret(AHBDW/8-1 downto AHBDW/8/2) := (others => '1');
end case;
end if;
-- HSIZE_BYTE
when others =>
if AHBDW = 128 then
case haddr(3 downto 0) is
when "0000" => ret( 0) := '1';
when "0001" => ret( 1) := '1';
when "0010" => ret( 2) := '1';
when "0011" => ret( 3) := '1';
when "0100" => ret( 0) := '1';
when "0101" => ret( 1) := '1';
when "0110" => ret( 2) := '1';
when "0111" => ret( 3) := '1';
when "1000" => ret( 0) := '1';
when "1001" => ret( 1) := '1';
when "1010" => ret( 2) := '1';
when "1011" => ret( 3) := '1';
when "1100" => ret( 0) := '1';
when "1101" => ret( 1) := '1';
when "1110" => ret( 2) := '1';
when others => ret( 3) := '1';
end case;
elsif AHBDW = 64 then
case haddr(2 downto 0) is
when "000" => ret(0) := '1';
when "001" => ret(1) := '1';
when "010" => ret(2) := '1';
when "011" => ret(3) := '1';
when "100" => ret(0) := '1';
when "101" => ret(1) := '1';
when "110" => ret(2) := '1';
when others => ret(3) := '1';
end case;
elsif AHBDW = 32 then
case haddr(1 downto 0) is
when "00" => ret(0) := '1';
when "01" => ret(1) := '1';
when "10" => ret(2) := '1';
when others => ret(3) := '1';
end case;
end if;
end case;
return ret;
end ahbselectdatanoreplicamask;
function ahbselectdatanoreplicaoutput (
haddr : std_logic_vector(7 downto 0);
counter : unsigned(31 downto 0);
hsize : std_logic_vector(2 downto 0);
rdbuffer : unsigned;
wr_count : unsigned;
replica : boolean)
return std_logic_vector is
variable ret : std_logic_vector(AHBDW-1 downto 0);
variable retrep : std_logic_vector(AHBDW-1 downto 0);
variable rdbuffer_int : unsigned(AHBDW-1 downto 0);
variable hdata : std_logic_vector(AHBDW-1 downto 0);
variable offset : unsigned(31 downto 0);
variable steps : unsigned(31 downto 0);
variable stepsint : natural;
begin -- ahbselectdatanoreplicaoutput
ret := (others => '0');
case hsize is
when HSIZE_4WORD =>
offset := resize((unsigned(haddr(5 downto 4))&"0000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"0000000"),steps'length) + offset;
when HSIZE_DWORD =>
if AHBDW = 128 then
offset := resize((unsigned(haddr(5 downto 4))&"0000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 1)&"0000000"),steps'length) + offset;
elsif AHBDW = 64 then
offset := resize((unsigned(haddr(5 downto 3))&"000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"000000"),steps'length) + offset;
end if;
when others =>
if AHBDW = 128 then
offset := resize((unsigned(haddr(5 downto 4))&"0000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 2)&"0000000"),steps'length) + offset;
elsif AHBDW = 64 then
offset := resize((unsigned(haddr(5 downto 3))&"000000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 1)&"000000"),steps'length) + offset;
elsif AHBDW = 32 then
offset := resize((unsigned(haddr(5 downto 2))&"00000"),offset'length);
steps := resize(unsigned(wr_count(wr_count'length-1 downto 0)&"00000"),steps'length) + offset;
end if;
end case;
stepsint := to_integer(steps);
rdbuffer_int := resize(shift_right(rdbuffer,stepsint),rdbuffer_int'length);
hdata := std_logic_vector(rdbuffer_int(AHBDW-1 downto 0));
ret(AHBDW-1 downto 0) := reversebyte(hdata);
case hsize is
when HSIZE_4WORD =>
offset := resize(unsigned(haddr) + unsigned(counter&"0000"),offset'length);
when HSIZE_DWORD =>
offset := resize(unsigned(haddr) + unsigned(counter&"000"),offset'length);
when others =>
offset := resize(unsigned(haddr) + unsigned(counter&"00"),offset'length);
end case;
if (replica = true) then
case hsize is
when HSIZE_4WORD =>
retrep := ahbdrivedata(ret(AHBDW-1 downto 0));
when HSIZE_DWORD =>
if AHBDW = 128 then
if offset(3) = '0' then retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else retrep := ahbdrivedata(ret(AHBDW/2-1 downto 0)); end if;
else
retrep := ahbdrivedata(ret(AHBDW-1 downto 0));
end if;
when HSIZE_WORD =>
if AHBDW = 128 then
case offset(3 downto 2) is
when "00" => retrep := ahbdrivedata(ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => retrep := ahbdrivedata(ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => retrep := ahbdrivedata(ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
elsif AHBDW = 64 then
if offset(2) = '0' then retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else retrep := ahbdrivedata(ret(AHBDW/2-1 downto 0)); end if;
else
retrep := ahbdrivedata(ret(AHBDW-1 downto 0));
end if;
when HSIZE_HWORD =>
if AHBDW = 128 then
case offset(3 downto 1) is
when "000" => retrep := ahbdrivedata(ret(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => retrep := ahbdrivedata(ret(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => retrep := ahbdrivedata(ret(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => retrep := ahbdrivedata(ret(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => retrep := ahbdrivedata(ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => retrep := ahbdrivedata(ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => retrep := ahbdrivedata(ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
elsif AHBDW = 64 then
case offset(2 downto 1) is
when "00" => retrep := ahbdrivedata(ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => retrep := ahbdrivedata(ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => retrep := ahbdrivedata(ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
else
if offset(1) = '0' then retrep := ahbdrivedata(ret(AHBDW-1 downto AHBDW/2));
else retrep := ahbdrivedata(ret(AHBDW/2-1 downto 0)); end if;
end if;
-- HSIZE_BYTE
when others =>
if AHBDW = 128 then
case offset(3 downto 0) is
when "0000" => retrep := ahbdrivedata(ret(16*(AHBDW/16)-1 downto 15*(AHBDW/16)));
when "0001" => retrep := ahbdrivedata(ret(15*(AHBDW/16)-1 downto 14*(AHBDW/16)));
when "0010" => retrep := ahbdrivedata(ret(14*(AHBDW/16)-1 downto 13*(AHBDW/16)));
when "0011" => retrep := ahbdrivedata(ret(13*(AHBDW/16)-1 downto 12*(AHBDW/16)));
when "0100" => retrep := ahbdrivedata(ret(12*(AHBDW/16)-1 downto 11*(AHBDW/16)));
when "0101" => retrep := ahbdrivedata(ret(11*(AHBDW/16)-1 downto 10*(AHBDW/16)));
when "0110" => retrep := ahbdrivedata(ret(10*(AHBDW/16)-1 downto 9*(AHBDW/16)));
when "0111" => retrep := ahbdrivedata(ret( 9*(AHBDW/16)-1 downto 8*(AHBDW/16)));
when "1000" => retrep := ahbdrivedata(ret( 8*(AHBDW/16)-1 downto 7*(AHBDW/16)));
when "1001" => retrep := ahbdrivedata(ret( 7*(AHBDW/16)-1 downto 6*(AHBDW/16)));
when "1010" => retrep := ahbdrivedata(ret( 6*(AHBDW/16)-1 downto 5*(AHBDW/16)));
when "1011" => retrep := ahbdrivedata(ret( 5*(AHBDW/16)-1 downto 4*(AHBDW/16)));
when "1100" => retrep := ahbdrivedata(ret( 4*(AHBDW/16)-1 downto 3*(AHBDW/16)));
when "1101" => retrep := ahbdrivedata(ret( 3*(AHBDW/16)-1 downto 2*(AHBDW/16)));
when "1110" => retrep := ahbdrivedata(ret( 2*(AHBDW/16)-1 downto 1*(AHBDW/16)));
when others => retrep := ahbdrivedata(ret( 1*(AHBDW/16)-1 downto 0*(AHBDW/16)));
end case;
elsif AHBDW = 64 then
case offset(2 downto 0) is
when "000" => retrep := ahbdrivedata(ret(8*(AHBDW/8)-1 downto 7*(AHBDW/8)));
when "001" => retrep := ahbdrivedata(ret(7*(AHBDW/8)-1 downto 6*(AHBDW/8)));
when "010" => retrep := ahbdrivedata(ret(6*(AHBDW/8)-1 downto 5*(AHBDW/8)));
when "011" => retrep := ahbdrivedata(ret(5*(AHBDW/8)-1 downto 4*(AHBDW/8)));
when "100" => retrep := ahbdrivedata(ret(4*(AHBDW/8)-1 downto 3*(AHBDW/8)));
when "101" => retrep := ahbdrivedata(ret(3*(AHBDW/8)-1 downto 2*(AHBDW/8)));
when "110" => retrep := ahbdrivedata(ret(2*(AHBDW/8)-1 downto 1*(AHBDW/8)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/8)-1 downto 0*(AHBDW/8)));
end case;
else
case offset(1 downto 0) is
when "00" => retrep := ahbdrivedata(ret(4*(AHBDW/4)-1 downto 3*(AHBDW/4)));
when "01" => retrep := ahbdrivedata(ret(3*(AHBDW/4)-1 downto 2*(AHBDW/4)));
when "10" => retrep := ahbdrivedata(ret(2*(AHBDW/4)-1 downto 1*(AHBDW/4)));
when others => retrep := ahbdrivedata(ret(1*(AHBDW/4)-1 downto 0*(AHBDW/4)));
end case;
end if;
end case;
--ret := ahbdrivedatamig(retrep);
ret :=retrep;
end if;
return ret;
end ahbselectdatanoreplicaoutput;
-- purpose: extends 'hdata' to suite AHB data width. If the input vector's
-- length exceeds AHBDW the low part is returned.
function ahbdrivedatanoreplica (
hdata : std_logic_vector)
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin -- ahbdrivedatanoreplica
if AHBDW < hdata'length then
data := hdata(AHBDW+hdata'low-1 downto hdata'low);
else
data := (others => '0');
data(hdata'length-1 downto 0) := hdata;
end if;
return data;
end ahbdrivedatanoreplica;
end; | gpl-2.0 | 4835c55555ba1d8474c1d1d6a876fb4b | 0.545665 | 3.53557 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.cache/ip/2017.3/8c616458fc878cb7/led_controller_design_processing_system7_0_0_sim_netlist.vhdl | 1 | 206,174 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:47 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_processing_system7_0_0_sim_netlist.vhdl
-- Design : led_controller_design_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "led_controller_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "led_controller_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "led_controller_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT";
attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 2438d076db1b2e7f4146b3b5f04c28f3 | 0.639605 | 2.766211 | false | false | false | false |
cesar-avalos3/C8VHDL | sources/vhdl/mem_mod.vhd | 1 | 3,341 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mem_mod is
Port ( address : in STD_LOGIC_VECTOR (12 downto 0);
clock : in STD_LOGIC;
we : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0));
end mem_mod;
architecture Behavioral of mem_mod is
type RAM is array ( ( 2 * 4096 ) - 1 downto 0 ) of std_logic_vector( 7 downto 0 );
signal sys_RAM : RAM := (
0 => x"00", 1 => x"00", -- set DT and ST to 0
511 => "10101010", -- memory mapped port
2 => "11110000", 22 => "10010000", 42 => "11110000", 62 => "11110000",
3 => "10010000", 23 => "10010000", 43 => "10010000", 63 => "10000000",
4 => "10010000", 24 => "11110000", 44 => "11110000", 64 => "10000000",
5 => "10010000", 25 => "00010000", 45 => "10010000", 65 => "10000000",
6 => "11110000", 26 => "00010000", 46 => "11110000", 66 => "11110000",
7 => "00100000", 27 => "11110000", 47 => "11110000", 67 => "11100000",
8 => "01100000", 28 => "10000000", 48 => "10010000", 68 => "10010000",
9 => "00100000", 29 => "11110000", 49 => "11110000", 69 => "10010000",
10 => "00100000", 30 => "00010000", 50 => "00010000", 70 => "10010000",
11 => "01110000", 31 => "11110000", 51 => "11110000", 71 => "11100000",
12 => "11110000", 32 => "11110000", 52 => "11110000", 72 => "11110000",
13 => "00010000", 33 => "10000000", 53 => "10010000", 73 => "10000000",
14 => "11110000", 34 => "11110000", 54 => "11110000", 74 => "11110000",
15 => "10000000", 35 => "10010000", 55 => "10010000", 75 => "10000000",
16 => "11110000", 36 => "11110000", 56 => "10010000", 76 => "11110000",
17 => "11110000", 37 => "11110000", 57 => "11100000", 77 => "11110000",
18 => "00010000", 38 => "00010000", 58 => "10010000", 78 => "10000000",
19 => "11110000", 39 => "00100000", 59 => "11100000", 79 => "11110000",
20 => "00010000", 40 => "01000000", 60 => "10010000", 80 => "10000000",
21 => "11110000", 41 => "01000000", 61 => "11100000", 81 => "10000000",
others => ( others => '0')
);
signal read_address : std_logic_vector( 12 downto 0 );
begin
process ( clock )
begin
if ( rising_edge( clock ) ) then
if( we = '1' ) then
sys_RAM( to_integer( unsigned( address ))) <= dataIn;
end if;
read_address <= address;
end if;
end process;
dataOut <= sys_RAM( to_integer( unsigned( read_address )));
end Behavioral; | mit | 6397f2e7ec43aadfcdee18f1592bfc39 | 0.410655 | 4.355932 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/jtag/jtagcom.vhd | 1 | 7,818 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: jtagcom
-- File: jtagcom.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Modified: J. Gaisler, K. Glembo, J. Andersson - Aeroflex Gaisler
-- Description: JTAG Debug Interface with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libjtagcom.all;
use gaisler.misc.all;
entity jtagcom is
generic (
isel : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
reread : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tck : in std_ulogic;
trst : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of jtagcom is
constant ADDBITS : integer := 10;
constant NOCMP : boolean := (isel /= 0);
type state_type is (shft, ahb, nxt_shft);
type reg_type is record
addr : std_logic_vector(34 downto 0);
data : std_logic_vector(32 downto 0);
state : state_type;
tcktog: std_logic_vector(nsync-1 downto 0);
tcktog2: std_ulogic;
tdishft: std_ulogic;
trst : std_logic_vector(nsync-1 downto 0);
tdi : std_logic_vector(nsync-1 downto 0);
shift : std_logic_vector(nsync-1 downto 0);
shift2: std_ulogic;
upd : std_logic_vector(nsync-1 downto 0);
upd2 : std_ulogic;
asel : std_logic_vector(nsync-1 downto 0);
dsel : std_logic_vector(nsync-1 downto 0);
seq : std_ulogic;
holdn : std_ulogic;
end record;
type tckreg_type is record
tcktog: std_ulogic;
tdi: std_ulogic;
tdor: std_ulogic;
end record;
signal nexttdo: std_ulogic;
signal r, rin : reg_type;
signal tr: tckreg_type;
begin
comb : process (rst, r, tapo, dmao, tr)
variable v : reg_type;
variable redge0 : std_ulogic;
variable vdmai : ahb_dma_in_type;
variable asel, dsel : std_ulogic;
variable vtapi : tap_in_type;
variable write, seq : std_ulogic;
variable vnexttdo: std_ulogic;
begin
v := r;
if NOCMP then
asel := tapo.asel; dsel := tapo.dsel;
else
if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if;
if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if;
end if;
vtapi.en := asel or dsel;
vnexttdo := '0';
if asel='1' then
if tapo.shift='1' then
vnexttdo := r.addr(1);
else
vnexttdo := r.addr(0);
end if;
else
if tapo.shift='1' then
vnexttdo := r.data(1);
else
vnexttdo := r.data(0);
end if;
if reread /= 0 then vnexttdo := vnexttdo and r.holdn; end if;
end if;
nexttdo <= vnexttdo;
vtapi.tdo := tr.tdor;
write := r.addr(34); seq := r.seq;
v.tcktog(0) := r.tcktog(nsync-1); v.tcktog(nsync-1) := tr.tcktog;
v.tcktog2 := r.tcktog(0); v.shift2 := r.shift(0);
v.trst(0) := r.trst(nsync-1); v.trst(nsync-1) := tapo.reset;
v.tdi(0) := r.tdi(nsync-1); v.tdi(nsync-1) := tr.tdi;
v.shift(0) := r.shift(nsync-1); v.shift(nsync-1) := tapo.shift;
v.upd(0) := r.upd(nsync-1); v.upd(nsync-1) := tapo.upd;
v.upd2 := r.upd(0);
v.asel(0) := r.asel(nsync-1); v.asel(nsync-1) := asel;
v.dsel(0) := r.dsel(nsync-1); v.dsel(nsync-1) := dsel;
redge0 := r.tcktog2 xor r.tcktog(0);
v.tdishft := '0';
vdmai.address := r.addr(31 downto 0); vdmai.wdata := ahbdrivedata(r.data(31 downto 0));
vdmai.start := '0'; vdmai.burst := '0'; vdmai.write := write;
vdmai.busy := '0'; vdmai.irq := '0'; vdmai.size := '0' & r.addr(33 downto 32);
case r.state is
when shft =>
if (r.asel(0) or r.dsel(0)) = '1' then
if r.shift2 = '1' then
if redge0 = '1' then
if r.asel(0) = '1' then v.addr(33 downto 0) := r.addr(34 downto 1); end if;
if r.dsel(0) = '1' then v.data(31 downto 0) := r.data(32 downto 1); end if;
v.tdishft := '1'; -- Shift in TDI next AHB cycle
end if;
elsif r.upd2 = '1' then
if reread /= 0 then
v.data(32) := '0'; -- Transfer not done
end if;
if (r.asel(0) and not write) = '1' then v.state := ahb; end if;
if (r.dsel(0) and (write or (not write and seq))) = '1' then -- data register
v.state := ahb;
if (seq and not write) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
end if;
end if;
if r.tdishft='1' then
if r.asel(0)='1' then v.addr(34):=r.tdi(0); end if;
if r.dsel(0)='1' then v.data(32):=r.tdi(0); v.seq:=r.tdi(0); end if;
end if;
if reread /= 0 then v.holdn := '1'; end if;
vdmai.size := "000";
when ahb =>
if reread /= 0 and r.shift2 = '1' then v.holdn := '0'; end if;
if dmao.active = '1' then
if dmao.ready = '1' then
v.data(31 downto 0) := ahbreadword(dmao.rdata);
v.state := nxt_shft;
if reread /= 0 then
v.data(32) := '1'; -- Transfer done
end if;
if (write and seq) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
else
vdmai.start := '1';
end if;
when nxt_shft =>
if reread /= 0 then
v.holdn := (r.holdn or r.upd2) and not r.shift2;
if r.upd2 = '0' and r.shift2 = '0' and r.holdn = '1' then v.state := shft; end if;
else
if r.upd2 = '0' then v.state := shft; end if;
end if;
when others =>
v.state := shft; v.addr := (others => '0'); v.seq := '0';
end case;
if (rst = '0') or (r.trst(0) = '1') then
v.state := shft; v.addr := (others => '0'); v.seq := '0';
end if;
if reread = 0 then v.holdn := '0'; end if;
rin <= v; dmai <= vdmai; tapi <= vtapi;
end process;
reg : process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
tckreg: process (tck,trst)
begin
if rising_edge(tck) then
tr.tcktog <= not tr.tcktog;
tr.tdi <= tapo.tdi;
tr.tdor <= nexttdo;
end if;
if trst='0' then
tr.tcktog <= '0';
tr.tdi <= '0';
tr.tdor <= '0';
end if;
end process;
end;
| gpl-2.0 | 35f0542f2ade11971b323b5775377032 | 0.545536 | 3.282116 | false | false | false | false |
khaledhassan/vhdl-examples | clock_divider/clk_div.vhd | 1 | 2,407 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Simple parameterized clock divider that uses a counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all; -- don't use for synthesis, but OK for static numbers
entity clk_div is
generic (
clk_in_freq : natural;
clk_out_freq : natural
);
port (
rst : in std_logic;
clk_in : in std_logic;
clk_out : out std_logic
);
end clk_div;
architecture BHV of clk_div is
constant OUT_PERIOD_COUNT : integer := (clk_in_freq/clk_out_freq)-1;
begin
process(clk_in, rst)
variable count : integer range 0 to OUT_PERIOD_COUNT; -- note: integer type defaults to 32-bits wide unless you specify the range yourself
begin
if(rst = '1') then
count := 0;
clk_out <= '0';
elsif(rising_edge(clk_in)) then
if(count = OUT_PERIOD_COUNT) then
count := 0;
else
count := count + 1;
end if;
if(count > OUT_PERIOD_COUNT/2) then
clk_out <= '1';
else
clk_out <= '0';
end if;
end if;
end process;
end BHV;
| mit | d381ce86a9b7ca72d1c58ae351c28e16 | 0.655588 | 4.045378 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/inferred/sim_pll.vhd | 1 | 6,451 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: sim_pll
-- File: sim_pll.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulated PLL with input frequency checking
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity sim_pll is
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
-- Frequency limits in kHz, for checking only
minfreq: integer := 0;
maxfreq: integer := 10000000;
-- Lock tolerance in ps
locktol: integer := 2
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end;
architecture sim of sim_pll is
signal clkout1,clkout2,clkout3,clkout4: std_logic;
signal tp: time := 1 ns;
signal timeset: boolean := false;
signal fb: std_ulogic;
signal comp: time := 0 ns;
signal llock: std_logic;
begin
o1 <= transport clkout1 after tp + (tp*clkdiv1*(clkphase1 mod 360)) / (clkmul*360);
o2 <= transport clkout2 after tp + (tp*clkdiv2*(clkphase2 mod 360)) / (clkmul*360);
o3 <= transport clkout3 after tp + (tp*clkdiv3*(clkphase3 mod 360)) / (clkmul*360);
o4 <= transport clkout4 after tp + (tp*clkdiv4*(clkphase4 mod 360)) / (clkmul*360);
lock <= llock after tp*20; -- 20 cycle inertia on lock signal
freqmeas: process(i)
variable ts,te: time;
variable mf: integer;
variable warned: boolean := false;
variable first: boolean := true;
begin
if rising_edge(i) and (now /= (0 ps)) then
ts := te;
te := now;
if first then
first := false;
else
mf := (1 ms) / (te-ts);
assert (mf >= minfreq and mf <= maxfreq) or warned or rst='0' or llock/='1'
report "Input frequency out of range, " &
"measured: " & tost(mf) & ", min:" & tost(minfreq) & ", max:" & tost(maxfreq)
severity warning;
if (mf < minfreq or mf > maxfreq) and rst/='0' and llock='1' then warned := true; end if;
if llock='0' or te-ts-tp > locktol*(1 ps) or te-ts-tp < -locktol*(1 ps) then
tp <= te-ts;
timeset <= true;
end if;
end if;
end if;
end process;
genclk: process
variable divcount1,divcount2,divcount3,divcount4: integer;
variable compen: boolean;
variable t: time;
variable compps: integer;
begin
compen := false;
clkout1 <= '0';
clkout2 <= '0';
clkout3 <= '0';
clkout4 <= '0';
if not timeset or rst='0' then
wait until timeset and rst/='0';
end if;
divcount1 := 0;
divcount2 := 0;
divcount3 := 0;
divcount4 := 0;
fb <= '1';
clkout1 <= '1';
clkout2 <= '1';
clkout3 <= '1';
clkout4 <= '1';
oloop: loop
for x in 0 to 2*clkmul-1 loop
if x=0 then fb <= '1'; end if;
if x=clkmul then fb <= '0'; end if;
t := tp/(2*clkmul);
if compen and comp /= (0 ns) then
-- Handle compensation below resolution limit (1 ps assumed)
if comp < 2*clkmul*(1 ps) and comp > -2*clkmul*(1 ps) then
compps := abs(comp / (1 ps));
if x > 0 and x <= compps then
if comp > 0 ps then
t := t + 1 ps;
else
t := t - 1 ps;
end if;
end if;
else
t:=t+comp/(2*clkmul);
end if;
end if;
if t > (0 ns) then
wait on rst for t;
else
wait for 1 ns;
end if;
exit oloop when rst='0';
divcount1 := divcount1+1;
if divcount1 >= clkdiv1 then
clkout1 <= not clkout1;
divcount1 := 0;
end if;
divcount2 := divcount2+1;
if divcount2 >= clkdiv2 then
clkout2 <= not clkout2;
divcount2 := 0;
end if;
divcount3 := divcount3+1;
if divcount3 >= clkdiv3 then
clkout3 <= not clkout3;
divcount3 := 0;
end if;
divcount4 := divcount4+1;
if divcount4 >= clkdiv4 then
clkout4 <= not clkout4;
divcount4 := 0;
end if;
end loop;
compen := true;
end loop oloop;
end process;
fbchk: process(fb,i)
variable last_i,prev_i: time;
variable last_fb,prev_fb: time;
variable vlock: std_logic := '0';
begin
if falling_edge(i) then
prev_i := last_i;
last_i := now;
end if;
if falling_edge(fb) then
-- Update phase compensation
if last_i < last_fb+tp/2 then
comp <= (last_i - last_fb);
else
comp <= last_i - now;
end if;
prev_fb := last_fb;
last_fb := now;
end if;
if (last_i<=(last_fb+locktol*(1 ps)) and last_i>=(last_fb-locktol*(1 ps)) and
prev_i<=(prev_fb+locktol*(1 ps)) and prev_i>=(prev_fb-locktol*(1 ps))) then
vlock := '1';
end if;
if prev_fb > last_i+locktol*(1 ps) or prev_i>last_fb+locktol*(1 ps) then
vlock := '0';
end if;
llock <= vlock;
end process;
end;
| gpl-2.0 | 35ac5f7d089681066a8a23f9a655b8dc | 0.541156 | 3.690503 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_sim_netlist.vhdl | 1 | 533,674 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:39:16 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_sim_netlist.vhdl
-- Design : zynq_design_1_auto_pc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm : entity is "axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm : entity is "axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel : entity is "axi_protocol_converter_v2_1_13_b2s_b_channel";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel : entity is "axi_protocol_converter_v2_1_13_b2s_r_channel";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel : entity is "axi_protocol_converter_v2_1_13_b2s_ar_channel";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel : entity is "axi_protocol_converter_v2_1_13_b2s_aw_channel";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s : entity is "axi_protocol_converter_v2_1_13_b2s";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter";
attribute P_AXI3 : integer;
attribute P_AXI3 of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_auto_pc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_auto_pc_0 : entity is "zynq_design_1_auto_pc_0,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_auto_pc_0 : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end zynq_design_1_auto_pc_0;
architecture STRUCTURE of zynq_design_1_auto_pc_0 is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | a8b7e0cdc45b76f773dbbb56f71f3152 | 0.531581 | 2.538331 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/gr1553b/gr1553b_pkg.vhd | 1 | 15,843 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: gr1553b_pkg
-- File: gr1553b_pkg.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Package for GR1553B top-level component and user-visible types
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.ahb_mst_in_type;
use grlib.amba.ahb_mst_out_type;
use grlib.amba.apb_slv_in_type;
use grlib.amba.apb_slv_out_type;
library techmap;
use techmap.gencomp.all;
package gr1553b_pkg is
constant gr1553b_version: integer := 0;
constant gr1553b_cfgver: integer := 0;
-----------------------------------------------------------------------------
-- Types and top level component
type gr1553b_txout_type is record
busA_txP: std_logic;
busA_txN: std_logic;
busA_txen: std_logic;
busA_rxen: std_logic;
busB_txP: std_logic;
busB_txN: std_logic;
busB_txen: std_logic;
busB_rxen: std_logic;
-- For convenience, inverted versions of txen
busA_txin: std_logic;
busB_txin: std_logic;
end record;
type gr1553b_rxin_type is record
busA_rxP: std_logic;
busA_rxN: std_logic;
busB_rxP: std_logic;
busB_rxN: std_logic;
end record;
type gr1553b_auxin_type is record
extsync: std_logic;
rtaddr: std_logic_vector(4 downto 0);
rtpar: std_logic;
end record;
type gr1553b_auxout_type is record
rtsync: std_logic;
busreset: std_logic;
validcmdA: std_logic;
validcmdB: std_logic;
timedoutA: std_logic;
timedoutB: std_logic;
badreg: std_logic;
irqvec: std_logic_vector(7 downto 0);
end record;
constant gr1553b_rxin_zero: gr1553b_rxin_type :=
(busA_rxP=>'0', busA_rxN=>'0', busB_rxP=>'0', busB_rxN=>'0');
constant gr1553b_txout_zero: gr1553b_txout_type :=
('0','0','0','0','0','0','0','0','1','1');
constant gr1553b_auxin_zero: gr1553b_auxin_type :=
(extsync => '0', rtaddr => "00000", rtpar => '0');
constant gr1553b_auxout_zero: gr1553b_auxout_type :=
('0','0','0','0','0','0','0',x"00");
constant gr1553b_rxin_none: gr1553b_rxin_type := gr1553b_rxin_zero;
constant gr1553b_txout_none: gr1553b_txout_type := gr1553b_txout_zero;
constant gr1553b_auxin_none: gr1553b_auxin_type := gr1553b_auxin_zero;
constant gr1553b_auxout_none: gr1553b_auxout_type := gr1553b_auxout_zero;
component gr1553b is
generic(
hindex: integer := 0;
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer range 0 to 1 := 0;
bm_filters: integer range 0 to 1 := 1;
codecfreq: integer := 20;
sameclk: integer range 0 to 1 := 0
);
port(
clk: in std_logic;
rst: in std_logic;
ahbmi: in ahb_mst_in_type;
ahbmo: out ahb_mst_out_type;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
auxin: in gr1553b_auxin_type;
auxout: out gr1553b_auxout_type;
codec_clk: in std_logic;
codec_rst: in std_logic;
txout: out gr1553b_txout_type;
txout_fb: in gr1553b_txout_type;
rxin: in gr1553b_rxin_type
);
end component;
-----------------------------------------------------------------------------
-- Pads convenience component
component gr1553b_pads is
generic (
padtech: integer;
outen_pol: integer range 0 to 1;
level: integer := ttl;
slew: integer := 0;
voltage: integer := x33v;
strength: integer := 12;
filter: integer := 0
);
port (
txout: in gr1553b_txout_type;
rxin: out gr1553b_rxin_type;
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaoutenin : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busboutenin : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Wrappers for netlists etc.
component gr1553b_stdlogic is
generic (
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1;
ahbendian: integer range 0 to 1 := 0
);
port (
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
-- AHB interface
mi_hgrant : in std_logic; -- bus grant
mi_hready : in std_ulogic; -- transfer done
mi_hresp : in std_logic_vector(1 downto 0); -- response type
mi_hrdata : in std_logic_vector(31 downto 0); -- read data bus
mo_hbusreq: out std_ulogic; -- bus request
mo_htrans : out std_logic_vector(1 downto 0); -- transfer type
mo_haddr : out std_logic_vector(31 downto 0); -- address bus (byte)
mo_hwrite : out std_ulogic; -- read/write
mo_hsize : out std_logic_vector(2 downto 0); -- transfer size
mo_hburst : out std_logic_vector(2 downto 0); -- burst type
mo_hwdata : out std_logic_vector(31 downto 0); -- write data bus
-- APB interface
si_psel : in std_logic; -- slave select
si_penable: in std_ulogic; -- strobe
si_paddr : in std_logic_vector(7 downto 0); -- address bus (byte addr)
si_pwrite : in std_ulogic; -- write
si_pwdata : in std_logic_vector(31 downto 0); -- write data bus
so_prdata : out std_logic_vector(31 downto 0); -- read data bus
so_pirq : out std_logic; -- interrupt bus
-- Aux signals
bcsync : in std_logic;
rtsync : out std_logic;
busreset : out std_logic;
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_logic;
-- 1553 transceiver interface
busainen : out std_logic;
busainp : in std_logic;
busainn : in std_logic;
busaouten : out std_logic;
busaoutp : out std_logic;
busaoutn : out std_logic;
busbinen : out std_logic;
busbinp : in std_logic;
busbinn : in std_logic;
busbouten : out std_logic;
busboutp : out std_logic;
busboutn : out std_logic
);
end component;
component gr1553b_nlw is
generic(
tech: integer := 0;
hindex: integer := 0;
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
bc_enable: integer range 0 to 1 := 1;
rt_enable: integer range 0 to 1 := 1;
bm_enable: integer range 0 to 1 := 1;
bc_timer: integer range 0 to 2 := 1;
bc_rtbusmask: integer range 0 to 1 := 1;
extra_regkeys: integer range 0 to 1 := 0;
syncrst: integer range 0 to 2 := 1
);
port(
clk: in std_logic;
rst: in std_logic;
ahbmi: in ahb_mst_in_type;
ahbmo: out ahb_mst_out_type;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
auxin: in gr1553b_auxin_type;
auxout: out gr1553b_auxout_type;
codec_clk: in std_logic;
codec_rst: in std_logic;
txout: out gr1553b_txout_type;
txout_fb: in gr1553b_txout_type;
rxin: in gr1553b_rxin_type
);
end component;
-----------------------------------------------------------------------------
-- APB Register definitions
constant REG_IRQSTATUS: std_logic_vector := x"00";
constant REG_IRQENABLE: std_logic_vector := x"04";
constant REG_BCSTATUS: std_logic_vector := x"40";
constant REG_BCACTION: std_logic_vector := x"44";
constant REG_BCSCHEMADDR: std_logic_vector := x"48";
constant REG_BCASYNCADDR: std_logic_vector := x"4C";
constant REG_BCTIME: std_logic_vector := x"50";
constant REG_BCWAKEUP: std_logic_vector := x"54";
constant REG_BCIRQSRC: std_logic_vector := x"58";
constant REG_BCRTBUSMASK: std_logic_vector := x"5C";
constant REG_BCSCHEMSLOT: std_logic_vector := x"68";
constant REG_BCASYNCSLOT: std_logic_vector := x"6C";
constant REG_RTSTATUS: std_logic_vector := x"80";
constant REG_RTCONFIG: std_logic_vector := x"84";
constant REG_RTBUSSTAT: std_logic_vector := x"88";
constant REG_RTBUSWORDS: std_logic_vector := x"8C";
constant REG_RTSYNC: std_logic_vector := x"90";
constant REG_RTTABLEADDR: std_logic_vector := x"94";
constant REG_RTMODECONFIG: std_logic_vector := x"98";
constant REG_RTTIMETAG: std_logic_vector := x"A4";
constant REG_RTLOGMASK: std_logic_vector := x"AC";
constant REG_RTLOGPOS: std_logic_vector := x"B0";
constant REG_RTIRQSRC: std_logic_vector := x"B4";
constant REG_BMSTATUS: std_logic_vector := x"C0";
constant REG_BMCONFIG: std_logic_vector := x"C4";
constant REG_BMADDRFILT: std_logic_vector := x"C8";
constant REG_BMSAFILT: std_logic_vector := x"CC";
constant REG_BMMCFILT: std_logic_vector := x"D0";
constant REG_BMBUFSTART: std_logic_vector := x"D4";
constant REG_BMBUFEND: std_logic_vector := x"D8";
constant REG_BMBUFPOS: std_logic_vector := x"DC";
constant REG_BMTIMETAG: std_logic_vector := x"E0";
-----------------------------------------------------------------------------
-- Embedded RT core
component grrt is
generic (
codecfreq: integer := 20;
sameclk : integer := 1;
syncrst : integer range 0 to 1 := 1
);
port (
-- Clock and reset
clk : in std_ulogic;
rst : in std_ulogic;
clk1553 : in std_ulogic;
rst1553 : in std_ulogic;
-- Control signals
rtaddr : in std_logic_vector(4 downto 0);
rtaddrp : in std_ulogic;
rtstat : in std_logic_vector(3 downto 0); -- 3=SR, 2=busy 1=SSF 0=TF
ad31en : in std_ulogic; -- 1=RT31 is normal addr, 0=RT31 is broadcast
rtsync : out std_ulogic;
rtreset : out std_ulogic;
stamp : out std_ulogic;
-- Front-end interface
phase : out std_logic_vector(1 downto 0);
transfer : out std_logic_vector(11 downto 0);
resp : in std_logic_vector(1 downto 0);
tfrerror : out std_ulogic;
txdata : in std_logic_vector(15 downto 0);
rxdata : out std_logic_vector(15 downto 0);
datardy : in std_ulogic;
datarw : out std_ulogic;
-- 1553 transceiver interface
aoutin : out std_ulogic;
aoutp : out std_ulogic;
aoutn : out std_ulogic;
ainen : out std_ulogic;
ainp : in std_ulogic;
ainn : in std_ulogic;
boutin : out std_ulogic;
boutp : out std_ulogic;
boutn : out std_ulogic;
binen : out std_ulogic;
binp : in std_ulogic;
binn : in std_ulogic;
-- Fail-safe timer feedback
aoutp_fb : in std_logic;
aoutn_fb : in std_logic;
boutp_fb : in std_logic;
boutn_fb : in std_logic
);
end component;
-----------------------------------------------------------------------------
-- Test signal generators
component gr1553b_tgapb is
generic(
pindex : integer := 0;
paddr: integer := 0;
pmask : integer := 16#fff#;
codecfreq: integer := 20;
extmodeen: integer range 0 to 1 := 0;
rawmodeen: integer range 0 to 1 := 0;
rawmemtech: integer := 0
);
port(
clk: in std_logic;
rst: in std_logic;
codec_clk: in std_logic;
codec_rst: in std_logic;
apbsi: in apb_slv_in_type;
apbso: out apb_slv_out_type;
txout_core: in gr1553b_txout_type;
rxin_core: out gr1553b_rxin_type;
txout_bus: out gr1553b_txout_type;
rxin_bus: in gr1553b_rxin_type;
testing: out std_logic
);
end component;
-----------------------------------------------------------------------------
-- Simulation types and components for test bench
-- U=Undefined, X=Unknown, 0=Zero, +=High, -=Low
type uwire1553 is ('U','X','0','+','-');
type uwire1553_array is array(natural range <>) of uwire1553;
function resolved (a: uwire1553_array) return uwire1553;
subtype wire1553 is resolved uwire1553;
component simtrans1553_single is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
buswire: inout wire1553;
rxen: in std_logic;
txin: in std_logic;
txP: in std_logic;
txN: in std_logic;
rxP: out std_logic;
rxN: out std_logic
);
end component;
component simtrans1553 is
generic (
txdelay: time := 200 ns;
rxdelay: time := 450 ns
);
port (
busA: inout wire1553;
busB: inout wire1553;
rxenA: in std_logic;
txinA: in std_logic;
txAP: in std_logic;
txAN: in std_logic;
rxAP: out std_logic;
rxAN: out std_logic;
rxenB: in std_logic;
txinB: in std_logic;
txBP: in std_logic;
txBN: in std_logic;
rxBP: out std_logic;
rxBN: out std_logic
);
end component;
component combine1553 is
port (
clk: in std_ulogic;
txin1,rxen1: in std_ulogic;
tx1P,tx1N: in std_ulogic;
rx1P,rx1N: out std_ulogic;
txin2,rxen2: in std_ulogic;
tx2P,tx2N: in std_ulogic;
rx2P,rx2N: out std_ulogic;
txin,rxen: out std_ulogic;
txP,txN: out std_ulogic;
rxP,rxN: in std_ulogic
);
end component;
end package;
package body gr1553b_pkg is
function resolved (a: uwire1553_array) return uwire1553 is
variable w,w2: uwire1553;
begin
w := a(a'left);
for q in a'range loop
w2 := a(q);
if w /= w2 then
case w is
when 'U' => w := 'X';
when 'X' => null;
when '0' => w := w2;
when '+' | '-' => if w2 /= '0' then w:='X'; end if;
end case;
end if;
end loop;
return w;
end;
end package body;
| gpl-2.0 | dd67b8dd8cf6870053461ecc5f6fa104 | 0.560689 | 3.491186 | false | false | false | false |
eamadio/fpgaMSP430 | sync_debouncer_10ms.vhd | 1 | 2,981 | ------------------------------------------------------------------------------
-- Copyright (C) 2001 Authors
--
-- This source file may be used and distributed without restriction provided
-- that this copyright statement is not removed from the file and that any
-- derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
-- License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this source; if not, write to the Free Software Foundation,
-- Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
--
------------------------------------------------------------------------------
--
-- *File Name: sync_debouncer_10ms.vhd
--
-- *Module Description:
-- Super basic 10ms debouncer.
--
-- *Author(s):
-- - Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
-- $Rev$
-- $LastChangedBy$
-- $LastChangedDate$
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; -- standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; -- for the signed, unsigned types and arithmetic ops
entity sync_debouncer_10ms is
port (
-- INPUTs
clk_50mhz : in std_logic; -- 50MHz clock
rst : in std_logic; -- reset
signal_async : in std_logic; -- Asynchonous signal
-- OUTPUTs
signal_debounced : out std_logic -- Synchronized and 10ms debounced signal
);
end entity sync_debouncer_10ms;
architecture RTL of sync_debouncer_10ms is
signal sync_stage : std_logic_vector(1 downto 0);
signal debounce_counter : unsigned(18 downto 0);
begin
REGS : process (clk_50mhz, rst)
begin
if (rst = '1') then
sync_stage <= "00";
debounce_counter <= TO_UNSIGNED( 0, 19);
signal_debounced <= '0';
elsif rising_edge(clk_50mhz) then
-- Synchronize signal
sync_stage <= sync_stage(0) & signal_async;
-- Debouncer (10.48ms = 0x7ffff x 50MHz clock cycles)
if (signal_debounced = sync_stage(1)) then
debounce_counter <= TO_UNSIGNED(0,19);
else
debounce_counter <= debounce_counter+1;
end if;
-- Output signal
if (debounce_counter = TO_UNSIGNED( ((2**19)-1), 19)) then
signal_debounced <= not(signal_debounced);
end if;
end if;
end process REGS;
end RTL; -- sync_debouncer_10ms | bsd-3-clause | 55c2551eaf26a8409f9cfa6e40ede375 | 0.621939 | 3.782995 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/iodpad.vhd | 1 | 5,110 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iodpad
-- File: iodpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Open-drain I/O pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iodpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iodpad is
signal gnd, oen : std_ulogic;
begin
oen <= not i when oepol /= padoen_polarity(tech) else i;
gnd <= '0';
gen0 : if has_pads(tech) = 0 generate
pad <= '0'
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(i)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(pad)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa : if (tech = proasic) or (tech = apa3) generate
x0 : apa3_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atc : if (tech = atc18s) generate
x0 : atc18_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
atcrh : if (tech = atc18rha) generate
x0 : atc18rha_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
um : if (tech = umc) generate
x0 : umc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rhu : if (tech = rhumc) generate
x0 : rhumc_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
ihp : if (tech = ihp25) generate
x0 : ihp25_iopad generic map (level, slew, voltage, strength)
port map (pad, gnd, oen, o);
end generate;
rh18t : if (tech = rhlib18t) generate
x0 : rh_lib18t_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut025 : if (tech = ut25) generate
x0 : ut025crh_iopad generic map (strength)
port map (pad, gnd, oen, o);
end generate;
ut13 : if (tech = ut130) generate
x0 : ut130hbd_iopad generic map (strength) port map (pad, gnd, oen, o);
end generate;
pere : if (tech = peregrine) generate
x0 : peregrine_iopad generic map (level, slew, voltage, strength)
port map(pad, gnd, oen, o);
end generate;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iodpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iodpadv is
begin
v : for j in width-1 downto 0 generate
x0 : iodpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), o(j));
end generate;
end;
| gpl-2.0 | 3f41560b7bf3f74fb77e5a78c5dce08e | 0.627789 | 3.502399 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2sgx90-av/sram32.vhd | 1 | 2,686 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram32
-- File: sram32.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 32-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram32 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1Kx32)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(31 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram32 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+3, abits, tacc, fname)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index+2, abits, tacc, fname)
port map (a, d(15 downto 8), cex(1), we, oe);
sr2 : sram generic map (index+1, abits, tacc, fname)
port map (a, d(23 downto 16), cex(1), we, oe);
sr3 : sram generic map (index, abits, tacc, fname)
port map (a, d(31 downto 24), cex(1), we, oe);
end sim;
-- pragma translate_on
| gpl-2.0 | dc4b337c2a639c02156e086edd9ee507 | 0.592703 | 3.709945 | false | false | false | false |
kloboves/sicxe | vhdl/seg7.vhd | 1 | 6,838 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Data bit connections on display:
--
-- --0--
-- | |
-- 1 2
-- | |
-- --3--
-- | |
-- 4 5
-- | |
-- --6-- [7] (dot)
entity seg7 is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
-- special display modes
error_i : in std_logic;
stop_i : in std_logic;
-- register access
data_i : in std_logic_vector(7 downto 0);
write_mode_i : in std_logic;
write_raw_i : std_logic_vector(3 downto 0);
write_hex_i : std_logic_vector(1 downto 0);
-- display output
cathode_o : out std_logic_vector(7 downto 0);
anode_o : out std_logic_vector(3 downto 0)
);
end seg7;
architecture behavioral of seg7 is
-- registers
signal reg_mode : std_logic_vector(1 downto 0);
signal reg_raw : std_logic_vector(31 downto 0);
signal reg_hex : std_logic_vector(15 downto 0);
-- delay counter
signal delay_counter : std_logic_vector(14 downto 0);
signal delay_counter_done : std_logic;
-- current digit
signal digit_counter : std_logic_vector(1 downto 0);
signal digit_raw : std_logic_vector(7 downto 0);
signal digit_hex : std_logic_vector(3 downto 0);
-- output
signal cathode : std_logic_vector(7 downto 0);
signal anode : std_logic_vector(3 downto 0);
signal cathode_delay1 : std_logic_vector(7 downto 0);
signal anode_delay1 : std_logic_vector(3 downto 0);
begin
-- registers
reg_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_mode <= (others => '0');
reg_raw <= (others => '0');
reg_hex <= (others => '0');
else
reg_mode <= reg_mode;
reg_raw <= reg_raw;
reg_hex <= reg_hex;
if (write_mode_i = '1') then
reg_mode <= data_i(1 downto 0);
end if;
if (write_raw_i(3) = '1') then
reg_raw(31 downto 24) <= data_i;
end if;
if (write_raw_i(2) = '1') then
reg_raw(23 downto 16) <= data_i;
end if;
if (write_raw_i(1) = '1') then
reg_raw(15 downto 8) <= data_i;
end if;
if (write_raw_i(0) = '1') then
reg_raw(7 downto 0) <= data_i;
end if;
if (write_hex_i(1) = '1') then
reg_hex(15 downto 8) <= data_i;
end if;
if (write_hex_i(0) = '1') then
reg_hex(7 downto 0) <= data_i;
end if;
end if;
end if;
end process;
-- delay counter
delay_counter_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
delay_counter <= (others => '0');
else
if (delay_counter = "111111111111111") then
delay_counter <= (others => '0');
else
delay_counter <= delay_counter + 1;
end if;
end if;
end if;
end process;
delay_counter_done_proc : process(delay_counter)
begin
if (delay_counter = "111111111111111") then
delay_counter_done <= '1';
else
delay_counter_done <= '0';
end if;
end process;
-- current digit
digit_counter_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
digit_counter <= (others => '0');
else
if (delay_counter_done = '1') then
digit_counter <= digit_counter + 1;
else
digit_counter <= digit_counter;
end if;
end if;
end if;
end process;
digit_proc : process(digit_counter, reg_raw, reg_hex)
begin
case (digit_counter) is
when "00" =>
digit_raw <= reg_raw(7 downto 0);
digit_hex <= reg_hex(3 downto 0);
when "01" =>
digit_raw <= reg_raw(15 downto 8);
digit_hex <= reg_hex(7 downto 4);
when "10" =>
digit_raw <= reg_raw(23 downto 16);
digit_hex <= reg_hex(11 downto 8);
when "11" =>
digit_raw <= reg_raw(31 downto 24);
digit_hex <= reg_hex(15 downto 12);
when others =>
digit_raw <= (others => '0');
digit_hex <= (others => '0');
end case;
end process;
-- output
cathode_o <= cathode_delay1;
anode_o <= anode_delay1;
delay_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
cathode_delay1 <= (others => '0');
anode_delay1 <= (others => '1');
else
cathode_delay1 <= cathode;
anode_delay1 <= anode;
end if;
end if;
end process;
anode_proc : process(digit_counter)
begin
case (digit_counter) is
when "00" => anode <= "1110";
when "01" => anode <= "1101";
when "10" => anode <= "1011";
when "11" => anode <= "0111";
when others => anode <= (others => '1');
end case;
end process;
cathode_proc : process(error_i, stop_i, digit_counter, reg_mode, digit_raw, digit_hex)
begin
if (error_i = '1') then
case (digit_counter) is
when "00" => cathode <= "11111111"; -- blank
when "01" => cathode <= "11100111"; -- r
when "10" => cathode <= "11100111"; -- r
when "11" => cathode <= "10100100"; -- E
when others => cathode <= (others => '1');
end case;
elsif (stop_i = '1') then
case (digit_counter) is
when "00" => cathode <= "11100000"; -- P
when "01" => cathode <= "10001000"; -- O
when "10" => cathode <= "10100101"; -- t
when "11" => cathode <= "10010100"; -- S
when others => cathode <= (others => '1');
end case;
else
if (reg_mode = "00") then
cathode <= not digit_raw;
else
if ((reg_mode = "01" and (digit_counter = "10" or digit_counter = "11")) or
(reg_mode = "10" and (digit_counter = "00" or digit_counter = "01"))) then
cathode <= not digit_raw;
else
case digit_hex is
when "0000" => cathode <= "10001000";
when "0001" => cathode <= "11011011";
when "0010" => cathode <= "10100010";
when "0011" => cathode <= "10010010";
when "0100" => cathode <= "11010001";
when "0101" => cathode <= "10010100";
when "0110" => cathode <= "10000100";
when "0111" => cathode <= "11011010";
when "1000" => cathode <= "10000000";
when "1001" => cathode <= "10010000";
when "1010" => cathode <= "11000000";
when "1011" => cathode <= "10000101";
when "1100" => cathode <= "10101100";
when "1101" => cathode <= "10000011";
when "1110" => cathode <= "10100100";
when "1111" => cathode <= "11100100";
when others => cathode <= (others => '1');
end case;
end if;
end if;
end if;
end process;
end behavioral;
| mit | ca58afaa31fb5c6fb4fa1e72910a36f3 | 0.524569 | 3.429288 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_processing_system7_0_2/zqynq_lab_1_design_processing_system7_0_2_sim_netlist.vhdl | 1 | 197,463 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:29:07 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top zqynq_lab_1_design_processing_system7_0_2 -prefix
-- zqynq_lab_1_design_processing_system7_0_2_ zqynq_lab_1_design_processing_system7_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "zqynq_lab_1_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
end zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 2) => B"00000000000000",
IRQF2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_processing_system7_0_2 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_processing_system7_0_2 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_processing_system7_0_2 : entity is "zqynq_lab_1_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_processing_system7_0_2 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zqynq_lab_1_design_processing_system7_0_2 : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.2";
end zqynq_lab_1_design_processing_system7_0_2;
architecture STRUCTURE of zqynq_lab_1_design_processing_system7_0_2 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "zqynq_lab_1_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.zqynq_lab_1_design_processing_system7_0_2_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 6dc2fc353a3a59826f32fc6ea316d5a4 | 0.634499 | 2.750947 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/ddrphy.vhd | 1 | 54,817 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy
-- File: ddrphy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
------------------------------------------------------------------
-- DDR PHY with tech mapping ------------------------------------
------------------------------------------------------------------
entity ddrphy is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest: integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- return clock
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy is
signal lddr_clk,lddr_clkb: std_logic_vector(nclk-1 downto 0);
signal lddr_clk_fb_out,lddr_clk_fb: std_logic;
signal lddr_cke, lddr_csb: std_logic_vector(ncs-1 downto 0);
signal lddr_web,lddr_rasb,lddr_casb: std_logic;
signal lddr_dm, lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen: std_logic_vector(dbits/8-1 downto 0);
signal lddr_ad: std_logic_vector(abits-1 downto 0);
signal lddr_ba: std_logic_vector(1 downto 0);
signal lddr_dq_in,lddr_dq_out,lddr_dq_oen: std_logic_vector(dbits-1 downto 0);
begin
strat2 : if (tech = stratix2) generate
ddr_phy0 : stratixii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
clkread <= '0';
dqvalid <= '1';
end generate;
cyc3 : if (tech = cyclone3) generate
ddr_phy0 : cycloneiii_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
clkread <= '0';
dqvalid <= '1';
end generate;
xc2v : if (tech = virtex2) or (tech = spartan3) generate
ddr_phy0 : virtex2_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
clkread <= '0';
dqvalid <= '1';
end generate;
xc4v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate
ddr_phy0 : virtex4_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew,
phyiconf => phyiconf
)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, ck);
clkread <= '0';
dqvalid <= '1';
end generate;
xc3se : if (tech = spartan3e) or (tech = spartan6) generate
ddr_phy0 : spartan3e_ddr_phy
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew
)
port map (
rst, clk, clkout, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke);
dqvalid <= '1';
end generate;
-----------------------------------------------------------------------------
-- For technologies where the PHY does not have pads,
-- instantiate ddrphy_wo_pads + pads
-----------------------------------------------------------------------------
seppads: if ddrphy_builtin_pads(tech)=0 generate
phywop: ddrphy_wo_pads
generic map (tech,MHz,rstdelay,dbits,clk_mul,clk_div,
rskew,mobile,abits,nclk,ncs,scantest,phyiconf)
port map (
rst,clk,clkout,clkoutret,clkread,lock,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,lddr_cke,lddr_csb,
lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,
lddr_dq_in,lddr_dq_out,lddr_dq_oen,
addr,ba,dqin,dqout,dm,oen,dqs,dqsoen,rasn,casn,wen,csn,cke,ck,
moben,dqvalid,testen,testrst,scanen,testoen);
pads: ddrpads
generic map (tech,dbits,abits,nclk,ncs,0)
port map (ddr_clk,ddr_clkb,ddr_clk_fb_out,ddr_clk_fb,
ddr_cke,ddr_csb,ddr_web,ddr_rasb,ddr_casb,ddr_dm,ddr_dqs,
ddr_ad,ddr_ba,ddr_dq,
open,open,open,open,open,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,lddr_dq_in,lddr_dq_out,lddr_dq_oen);
end generate;
nseppads: if ddrphy_builtin_pads(tech)/=0 generate
lddr_clk <= (others => '0');
lddr_clkb <= (others => '0');
lddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
lddr_cke <= (others => '0');
lddr_csb <= (others => '0');
lddr_web <= '0';
lddr_rasb <= '0';
lddr_casb <= '0';
lddr_dm <= (others => '0');
lddr_dqs_in <= (others => '0');
lddr_dqs_out <= (others => '0');
lddr_dqs_oen <= (others => '0');
lddr_ad <= (others => '0');
lddr_ba <= (others => '0');
lddr_dq_in <= (others => '0');
lddr_dq_out <= (others => '0');
lddr_dq_oen <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddrphy_wo_pads is
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
rskew : integer := 0; mobile: integer := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (1 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddrphy_wo_pads is
begin
gut90: if (tech = ut90) generate
ddr_phy0: ut90nhbd_ddr_phy_wo_pads
generic map (
MHz => MHz, abits => abits, dbits => dbits,
nclk => nclk, ncs => ncs)
port map (
rst, clk, clkout, clkoutret, lock,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen, ddr_ad, ddr_ba, ddr_dq_in, ddr_dq_out, ddr_dq_oen,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen, rasn, casn, wen, csn, cke, ck,
moben, dqvalid, testen, testrst, scanen, testoen
);
ddr_clk_fb_out <= '0';
clkread <= '0';
end generate;
inf : if (tech = inferred) generate
ddr_phy0 : generic_ddr_phy_wo_pads
generic map (MHz => MHz, rstdelay => rstdelay
-- reduce 200 us start-up delay during simulation
-- pragma translate_off
/ 200
-- pragma translate_on
, clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew, mobile => mobile,
abits => abits, nclk => nclk, ncs => ncs
)
port map (
rst, clk, clkout, clkoutret, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen, ddr_ad, ddr_ba, ddr_dq_in, ddr_dq_out, ddr_dq_oen,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, ck, moben);
clkread <= '0';
dqvalid <= '1';
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddrpads is
generic (tech: integer := virtex5;
dbits: integer := 16;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1 downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1 downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0) -- ddr data
);
end;
architecture rtl of ddrpads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- DDR clock feedback
fbclkpadgen: if ddrphy_has_fbclk(tech)/=0 generate
fbclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk_fb_out, lddr_clk_fb_out);
fbclk_in_pad : inpad generic map (tech => tech)
port map (ddr_clk_fb, lddr_clk_fb);
end generate;
nfbclkpadgen: if ddrphy_has_fbclk(tech)=0 generate
ddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
end generate;
-- External DDR clock
ddrclocks : for i in 0 to nclk-1 generate
-- DDR_CLK/B
xc456v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate
ddrclk_pad : outpad_ds generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), ddr_clkb(i), lddr_clk(i), vcc);
end generate;
noxc456v : if not ((tech = virtex4) or (tech = virtex5) or (tech = virtex6)) generate
-- DDR_CLK
ddrclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), lddr_clk(i));
-- DDR_CLKB
ddrclkb_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clkb(i), lddr_clkb(i));
end generate;
end generate;
-- DDR single-edge control signals
-- RAS
rasn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb, lddr_rasb);
-- CAS
casn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb, lddr_casb);
-- WEN
wen_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web, lddr_web);
-- BA
bagen : for i in 0 to 1 generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba(i), lddr_ba(i));
end generate;
-- ADDRESS
dagen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad(i), lddr_ad(i));
end generate;
-- CSN and CKE
ddrbanks : for i in 0 to ncs-1 generate
csn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_csb(i), lddr_csb(i));
cke_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_cke(i), lddr_cke(i));
end generate;
-- DQS pads
dqsgen : for i in 0 to dbits/8-1 generate
dqspn_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (pad => ddr_dqs(i), i=> lddr_dqs_out(i), en => lddr_dqs_oen(i),
o => lddr_dqs_in(i));
end generate;
-- DQM pads
dmgen : for i in 0 to dbits/8-1 generate
ddr_bm_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_dm(i), lddr_dm(i));
end generate;
-- Data bus pads
ddgen : for i in 0 to dbits-1 generate
dq_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_ii)
port map (pad => ddr_dq(i), i => lddr_dq_out(i), en => lddr_dq_oen(i),
o => lddr_dq_in(i));
end generate;
-- Second copy of address/data lines
ctrl2gen: if ctrl2en/=0 generate
rasn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb2, lddr_rasb);
casn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb2, lddr_casb);
wen2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web2, lddr_web);
ba2gen : for i in 0 to 1 generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba2(i), lddr_ba(i));
da2gen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad2(i), lddr_ad(i));
end generate;
end generate;
end generate;
ctrl2ngen: if ctrl2en=0 generate
ddr_rasb2 <= '0';
ddr_casb2 <= '0';
ddr_web2 <= '0';
ddr_ba2 <= (others => '0');
ddr_ad2 <= (others => '0');
end generate;
end;
------------------------------------------------------------------
-- DDR2 PHY with tech mapping ------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr2pads is
generic (tech: integer := virtex5;
dbits: integer := 16;
eightbanks: integer := 0;
dqsse: integer range 0 to 1 := 0;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_odt : in std_logic_vector(ncs-1 downto 0)
);
end;
architecture rtl of ddr2pads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- DDR clock feedback
fbclkpadgen: if ddr2phy_has_fbclk(tech)/=0 generate
fbclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk_fb_out, lddr_clk_fb_out);
fbclk_in_pad : inpad generic map (tech => tech)
port map (ddr_clk_fb, lddr_clk_fb);
end generate;
nfbclkpadgen: if ddr2phy_has_fbclk(tech)=0 generate
ddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
end generate;
-- External DDR clock
ddrclocks : for i in 0 to nclk-1 generate
-- DDR_CLK/B
xc456v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = spartan6) generate
ddrclk_pad : outpad_ds generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), ddr_clkb(i), lddr_clk(i), vcc);
end generate;
noxc456v : if not ((tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = spartan6)) generate
-- DDR_CLK
ddrclk_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clk(i), lddr_clk(i));
-- DDR_CLKB
ddrclkb_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_clkb(i), lddr_clkb(i));
end generate;
end generate;
-- DDR single-edge control signals
-- RAS
rasn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb, lddr_rasb);
-- CAS
casn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb, lddr_casb);
-- WEN
wen_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web, lddr_web);
-- BA
bagen : for i in 0 to 1+eightbanks generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba(i), lddr_ba(i));
end generate;
-- ODT
odtgen : for i in 0 to ncs-1 generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_odt(i), lddr_odt(i));
end generate;
-- ADDRESS
dagen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad(i), lddr_ad(i));
end generate;
-- CSN and CKE
ddrbanks : for i in 0 to ncs-1 generate
csn_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_csb(i), lddr_csb(i));
cke_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_cke(i), lddr_cke(i));
end generate;
-- DQS pads
dqsse0 : if dqsse = 0 generate
dqsgen : for i in 0 to dbits/8-1 generate
dqspn_pad : iopad_ds generic map (tech => tech, slew => 1, level => sstl18_ii)
port map (padp => ddr_dqs(i), padn => ddr_dqsn(i), i=> lddr_dqs_out(i), en => lddr_dqs_oen(i),
o => lddr_dqs_in(i));
end generate;
end generate;
dqsse1 : if dqsse = 1 generate
dqsgen : for i in 0 to dbits/8-1 generate
dqspn_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (pad => ddr_dqs(i), i=> lddr_dqs_out(i), en => lddr_dqs_oen(i),
o => lddr_dqs_in(i));
end generate;
end generate;
-- DQM pads
dmgen : for i in 0 to dbits/8-1 generate
ddr_bm_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_dm(i), lddr_dm(i));
end generate;
-- Data bus pads
ddgen : for i in 0 to dbits-1 generate
dq_pad : iopad generic map (tech => tech, slew => 1, level => sstl18_ii)
port map (pad => ddr_dq(i), i => lddr_dq_out(i), en => lddr_dq_oen(i),
o => lddr_dq_in(i));
end generate;
-- Second copy of address/data lines
ctrl2gen: if ctrl2en/=0 generate
rasn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_rasb2, lddr_rasb);
casn2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_casb2, lddr_casb);
wen2_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_web2, lddr_web);
ba2gen : for i in 0 to 1+eightbanks generate
ddr_ba_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ba2(i), lddr_ba(i));
da2gen : for i in 0 to abits-1 generate
ddr_ad_pad : outpad generic map (tech => tech, slew => 1, level => sstl18_i)
port map (ddr_ad2(i), lddr_ad(i));
end generate;
end generate;
end generate;
ctrl2ngen: if ctrl2en=0 generate
ddr_rasb2 <= '0';
ddr_casb2 <= '0';
ddr_web2 <= '0';
ddr_ba2 <= (others => '0');
ddr_ad2 <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
use techmap.allpads.n2x_padcontrol_none;
-- With built-in pads
entity ddr2phy is
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8: integer := 0;
ddelayb9: integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
ctrl2en: integer := 0;
resync: integer := 0; custombits: integer := 8; extraio: integer := 0;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
-- Copy of control signals for 2nd DIMM
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddr2phy is
signal lddr_clk,lddr_clkb: std_logic_vector(nclk-1 downto 0);
signal lddr_clk_fb_out,lddr_clk_fb: std_logic;
signal lddr_cke, lddr_csb: std_logic_vector(ncs-1 downto 0);
signal lddr_web,lddr_rasb,lddr_casb: std_logic;
signal lddr_dm, lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen: std_logic_vector(dbits/8-1 downto 0);
signal lddr_dqsn_in,lddr_dqsn_out,lddr_dqsn_oen: std_logic_vector(dbits/8-1 downto 0);
signal lddr_ad: std_logic_vector(abits-1 downto 0);
signal lddr_ba: std_logic_vector(1+eightbanks downto 0);
signal lddr_dq_in,lddr_dq_out,lddr_dq_oen: std_logic_vector(dbits-1 downto 0);
signal lddr_odt: std_logic_vector(ncs-1 downto 0);
signal customdin_exp: std_logic_vector(132 downto 0);
begin
customdin_exp(custombits-1 downto 0) <= customdin;
customdin_exp(customdin_exp'high downto custombits) <= (others => '0');
-- For technologies without PHY-specific registers
nreggen: if ddr2phy_has_reg(tech)=0 and ddr2phy_builtin_pads(tech)/=0 generate
regrdata <= x"0000000000000000";
end generate;
ncustgen: if ddr2phy_has_custom(tech)=0 and ddr2phy_builtin_pads(tech)/=0 generate
customdout <= (others => '0');
end generate;
stra2 : if (tech = stratix2) generate
ddr_phy0 : stratixii_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits
)
port map (
rst, clk, clkout, lock, ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
dqin_valid <= '1';
end generate;
stra3 : if (tech = stratix3) generate
ddr_phy0 : stratixiii_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7,
numidelctrl => numidelctrl, norefclk => norefclk,
tech => tech, rskew => rskew, eightbanks => eightbanks
)
port map (
rst, clk, clkref, clkout, lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_pll, cal_rst, odt, oct);
dqin_valid <= '1';
end generate;
sp3a : if (tech = spartan3) generate
ddr_phy0 : spartan3a_ddr2_phy
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, tech => tech, rskew => rskew,
eightbanks => eightbanks)
port map ( rst, clk, clkout, lock, ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_pll, odt);
dqin_valid <= '1';
end generate;
nextreme : if (tech = easic90) generate
ddr_phy0 : easic90_ddr2_phy
generic map (
tech => tech,
MHz => MHz,
clk_mul => clk_mul,
clk_div => clk_div,
dbits => dbits,
rstdelay => rstdelay,
eightbanks => eightbanks)
port map (
rst, clk, clkout, lock, ddr_clk, ddr_clkb, ddr_clk_fb_out,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, odt, '1');
dqin_valid <= '1';
end generate;
nextreme2 : if (tech = easic45) generate
-- This requires dbits/8 extra bidir I/O that are suppliedd on the ddr_dqs port
ddr_phy0 : n2x_ddr2_phy
generic map (
MHz => MHz, rstdelay => rstdelay,
dbits => dbits, clk_mul => clk_mul, clk_div => clk_div, norefclk => norefclk,
eightbanks => eightbanks, dqsse => dqsse, abits => abits,
nclk => nclk, ncs => ncs, ctrl2en => ctrl2en)
port map (
rst => rst, clk => clk, clk270d => clkref,
clkout => clkout, clkoutret => clkoutret, lock => lock,
ddr_clk => ddr_clk, ddr_clkb => ddr_clkb, ddr_cke => ddr_cke,
ddr_csb => ddr_csb, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs => ddr_dqs(dbits/8-1 downto 0), ddr_dqsn => ddr_dqsn, ddr_ad => ddr_ad, ddr_ba => ddr_ba,
ddr_dq => ddr_dq, ddr_odt => ddr_odt, rden_pad => ddr_dqs(dbits/4-1 downto dbits/8),
addr => addr, ba => ba, dqin => dqin, dqout => dqout, dm => dm,
noen => noen,
rasn => rasn, casn => casn, wen => wen, csn => csn, cke => cke,
odt => odt, read_pend => read_pend, dqin_valid => dqin_valid,
regwdata => regwdata, regwrite => regwrite, regrdata => regrdata,
ddr_web2 => ddr_web2, ddr_rasb2 => ddr_rasb2, ddr_casb2 => ddr_casb2,
ddr_ad2 => ddr_ad2, ddr_ba2 => ddr_ba2,
dq_control => customdin_exp(73 downto 56),
dqs_control => customdin_exp(55 downto 38),
ck_control => customdin_exp(37 downto 20),
cmd_control => customdin_exp(19 downto 2),
compen => customdin_exp(0),
compupd => customdin_exp(1)
);
ddr_clk_fb_out <= '0';
customdout <= (others => '0');
end generate;
-----------------------------------------------------------------------------
-- For technologies where the PHY does not have pads,
-- instantiate ddr2phy_wo_pads + pads
-----------------------------------------------------------------------------
seppads: if ddr2phy_builtin_pads(tech)=0 generate
phywop: ddr2phy_wo_pads
generic map (tech,MHz,rstdelay,dbits,clk_mul,clk_div,
ddelayb0,ddelayb1,ddelayb2,ddelayb3,
ddelayb4,ddelayb5,ddelayb6,ddelayb7,
ddelayb8,ddelayb9,ddelayb10,ddelayb11,
numidelctrl,norefclk,rskew,eightbanks,dqsse,abits,nclk,ncs,
resync,custombits,scantest)
port map (
rst,clk,clkref,clkout,clkoutret,clkresync,lock,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,lddr_cke,lddr_csb,
lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,
lddr_dq_in,lddr_dq_out,lddr_dq_oen,lddr_odt,
addr,ba,dqin,dqout,dm,oen,noen,dqs,dqsoen,rasn,casn,wen,csn,cke,
cal_en,cal_inc,cal_pll,cal_rst,odt,oct,
read_pend,regwdata,regwrite,regrdata,dqin_valid,customclk,customdin,customdout,
testen,testrst,scanen,testoen);
pads: ddr2pads
generic map (tech,dbits,eightbanks,dqsse,abits,nclk,ncs,ctrl2en)
port map (ddr_clk,ddr_clkb,ddr_clk_fb_out,ddr_clk_fb,
ddr_cke,ddr_csb,ddr_web,ddr_rasb,ddr_casb,ddr_dm,ddr_dqs,ddr_dqsn,
ddr_ad,ddr_ba,ddr_dq,ddr_odt,
ddr_web2,ddr_rasb2,ddr_casb2,ddr_ad2,ddr_ba2,
lddr_clk,lddr_clkb,lddr_clk_fb_out,lddr_clk_fb,
lddr_cke,lddr_csb,lddr_web,lddr_rasb,lddr_casb,lddr_dm,
lddr_dqs_in,lddr_dqs_out,lddr_dqs_oen,
lddr_ad,lddr_ba,lddr_dq_in,lddr_dq_out,lddr_dq_oen,lddr_odt);
end generate;
nseppads: if ddr2phy_builtin_pads(tech)/=0 generate
lddr_clk <= (others => '0');
lddr_clkb <= (others => '0');
lddr_clk_fb_out <= '0';
lddr_clk_fb <= '0';
lddr_cke <= (others => '0');
lddr_csb <= (others => '0');
lddr_web <= '0';
lddr_rasb <= '0';
lddr_casb <= '0';
lddr_dm <= (others => '0');
lddr_dqs_in <= (others => '0');
lddr_dqs_out <= (others => '0');
lddr_dqs_oen <= (others => '0');
lddr_dqsn_in <= (others => '0');
lddr_dqsn_out <= (others => '0');
lddr_dqsn_oen <= (others => '0');
lddr_ad <= (others => '0');
lddr_ba <= (others => '0');
lddr_dq_in <= (others => '0');
lddr_dq_out <= (others => '0');
lddr_dq_oen <= (others => '0');
lddr_odt <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
-- without pads (typically used for ASIC technologies)
entity ddr2phy_wo_pads is
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8: integer := 0;
ddelayb9: integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
resync : integer := 0; custombits: integer := 8; scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture rtl of ddr2phy_wo_pads is
begin
-- For technologies without PHY-specific registers
nreggen: if ddr2phy_has_reg(tech)=0 generate
regrdata <= x"0000000000000000";
end generate;
ncustgen: if ddr2phy_has_custom(tech)=0 generate
customdout <= (others => '0');
end generate;
xc4v : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate
ddr_phy0 : virtex5_ddr2_phy_wo_pads
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
ddelayb0 => ddelayb0, ddelayb1 => ddelayb1, ddelayb2 => ddelayb2,
ddelayb3 => ddelayb3, ddelayb4 => ddelayb4, ddelayb5 => ddelayb5,
ddelayb6 => ddelayb6, ddelayb7 => ddelayb7, ddelayb8 => ddelayb8,
ddelayb9 => ddelayb9, ddelayb10 => ddelayb10, ddelayb11 => ddelayb11,
numidelctrl => numidelctrl, norefclk => norefclk,
tech => tech, eightbanks => eightbanks, dqsse => dqsse,
abits => abits, nclk => nclk, ncs => ncs
)
port map (
rst, clk, clkref, clkout, clkoutret, lock,
ddr_clk, ddr_clkb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen,
ddr_ad, ddr_ba,
ddr_dq_in, ddr_dq_out, ddr_dq_oen,ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
ddr_clk_fb_out <= '0';
dqin_valid <= '1';
end generate;
sp6 : if (tech = spartan6) generate
ddr_phy0 : spartan6_ddr2_phy_wo_pads
generic map (
MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits,
tech => tech, rskew => rskew,
eightbanks => eightbanks,
abits => abits, nclk => nclk, ncs => ncs)
port map (
rst, clk, clkout, lock,
ddr_clk, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen,
ddr_ad, ddr_ba, ddr_dq_in, ddr_dq_out, ddr_dq_oen, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, cal_en, cal_inc, cal_rst, odt);
ddr_clkb <= (others => '0');
ddr_clk_fb_out <= '0';
dqin_valid <= '1';
end generate;
inf : if (has_ddr2phy(tech) = 0) generate
ddr_phy0 : generic_ddr2_phy_wo_pads
generic map (MHz => MHz, rstdelay => rstdelay,
clk_mul => clk_mul, clk_div => clk_div, dbits => dbits, rskew => rskew,
eightbanks => eightbanks, abits => abits, nclk => nclk, ncs => ncs
)
port map (
rst, clk, clkout, clkoutret, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs_in, ddr_dqs_out, ddr_dqs_oen,
ddr_ad, ddr_ba,
ddr_dq_in, ddr_dq_out, ddr_dq_oen, ddr_odt,
addr, ba, dqin, dqout, dm, oen, dqs, dqsoen,
rasn, casn, wen, csn, cke, "111", odt
);
dqin_valid <= '1';
end generate;
end;
-------------------------------------------------------------------------------
-- LPDDR2 phy
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity lpddr2phy_wo_pads is
generic (
tech : integer := virtex5;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- ckkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end;
architecture tmap of lpddr2phy_wo_pads is
begin
inf: if true generate
phy0: generic_lpddr2phy_wo_pads
generic map (
tech => tech,
dbits => dbits,
nclk => nclk,
ncs => ncs,
clkratio => clkratio,
scantest => scantest)
port map (
rst => rst,
clkin => clkin,
clkin2 => clkin2,
clkout => clkout,
clkoutret => clkoutret,
clkout2 => clkout2,
lock => lock,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_ca => ddr_ca,
ddr_dm => ddr_dm,
ddr_dqs_in => ddr_dqs_in,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ca => ca,
cke => cke,
csn => csn,
dqin => dqin,
dqout => dqout,
dm => dm,
ckstop => ckstop,
boot => boot,
wrpend => wrpend,
rdpend => rdpend,
wrreq => wrreq,
rdvalid => rdvalid,
refcal => refcal,
refcalwu => refcalwu,
refcaldone => refcaldone,
phycmd => phycmd,
phycmden => phycmden,
phycmdin => phycmdin,
phycmdout => phycmdout,
testen => testen,
testrst => testrst,
scanen => scanen,
testoen => testoen);
end generate;
end;
| gpl-2.0 | 692e599a82225283f004b768a49aa64e | 0.556561 | 3.286588 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_auto_pc_1/zqynq_lab_1_design_auto_pc_1_sim_netlist.vhdl | 1 | 531,562 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:12:07 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top zqynq_lab_1_design_auto_pc_1 -prefix
-- zqynq_lab_1_design_auto_pc_1_ zqynq_lab_1_design_auto_pc_2_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_auto_pc_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_auto_pc_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_auto_pc_1 : entity is "zqynq_lab_1_design_auto_pc_2,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_auto_pc_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zqynq_lab_1_design_auto_pc_1 : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end zqynq_lab_1_design_auto_pc_1;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1 is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | ebbdabf861a3cce2bf31a88fc23a318d | 0.530745 | 2.536163 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ipshared/4575/hdl/axi_utils_v2_0_vh_rfs.vhd | 7 | 292,628 | `protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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`protect end_protected
| mit | b188911de1e2299d4cb4a502c4893e34 | 0.954704 | 1.810694 | false | false | false | false |
Subsets and Splits